coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

New patch to review for coreboot: smaug: Set LDO2 voltage to 1.8V
by Patrick Georgi 13 Jul '15

13 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10900 -gerrit commit 2479813deeab5919b167f2595ed964a8a4637f78 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 10 17:36:49 2015 -0700 smaug: Set LDO2 voltage to 1.8V LDO2 regulator is used as an always-on reference for the droop alert circuit. Set output voltage to match kernel settings. CQ-DEPEND=CL:284649 BUG=chrome-os-partner:42305 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5ef4e266d8ec278dadffa846af8dc49b6d18c37e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 611465f6248cba0ddce0083b431cb7ee17bc4b4c Original-Change-Id: I58cc473452b871392d813387707a0b8288e46561 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284879 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/smaug/pmic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 73aa0de..b10e67b 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -95,6 +95,13 @@ void pmic_init(unsigned bus) pmic_write_reg_77620(bus, MAX77620_CNFG2SD_REG, 0x04, 1); pmic_write_reg_77620(bus, MAX77620_SD1_REG, 0x2a, 1); + /* + * MAX77620: Set LDO2 output to 1.8V. LDO2 is used as always-on + * reference for the droop alert circuit. Match this setting with what + * the kernel expects. + */ + pmic_write_reg_77620(bus, MAX77620_CNFG1_L2_REG, 0x14, 1); + /* MAX77621: Set VOUT_REG to 1.0V - CPU VREG */ pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0xBF, 1);

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New patch to review for coreboot: t210: Apply A57 hardware issue workaround during cpu startup
by Patrick Georgi 13 Jul '15

13 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10899 -gerrit commit b845fe9ddcaa9e2557ddd2cfe1b831c878155b2a Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 10 15:29:13 2015 -0700 t210: Apply A57 hardware issue workaround during cpu startup Define custom stage_entry to apply workaround for A57 hardware issue for power on reset. It is observed that BTB contains stale data after power on reset. This could lead to unexpected branching and crashes at random intervals during the boot flow. Thus, invalidate the BTB immediately after power on reset. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test does not crash in firmware for 10K iterations. Change-Id: Ifbc9667bc5556112374f35733192b67b64a345d2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: bc7c2fec3c6b29e291235669ba9f22ff611064a7 Original-Change-Id: I1f5714074afdfee64b88cea8a394936ca848634b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284869 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/Makefile.inc | 3 +- src/soc/nvidia/tegra210/reset_handler.S | 75 -------------------------- src/soc/nvidia/tegra210/stage_entry.S | 95 +++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 76 deletions(-) diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 3b2dc7c..8d7e1fc 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -101,13 +101,14 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += ../tegra/usb.c ramstage-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon.c ramstage-$(CONFIG_HAVE_MTC) += mtc.c +ramstage-y += stage_entry.S secmon-y += cpu.c secmon-y += cpu_lib.S secmon-y += flow_ctrl.c secmon-y += power.c secmon-y += psci.c -secmon-y += reset_handler.S +secmon-y += stage_entry.S secmon-y += uart.c secmon-y += gic.c diff --git a/src/soc/nvidia/tegra210/reset_handler.S b/src/soc/nvidia/tegra210/reset_handler.S deleted file mode 100644 index 53622b1..0000000 --- a/src/soc/nvidia/tegra210/reset_handler.S +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/asm.h> - -#define CPUACTLR_EL1 s3_1_c15_c2_0 - -CPU_RESET_ENTRY(tegra210_reset_handler) - /* - * Invalidate BTB along with I$ to remove any stale entries - * from the branch predictor array. - */ - mrs x0, CPUACTLR_EL1 - orr x0, x0, #1 - msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ - dsb sy - isb - ic iallu /* invalidate */ - dsb sy - isb - - bic x0, x0, #1 - msr CPUACTLR_EL1, x0 /* restore original CPUACTLR_EL1 */ - dsb sy - isb - - .rept 7 - nop /* wait */ - .endr - - /* - * Extract OSLK bit and check if it is '1'. This bit remains '0' - * for A53. If '1', turn off regional clock gating and request - * warm reset. - */ - mrs x0, oslsr_el1 - and x0, x0, #2 /* extract oslk bit */ - mrs x1, mpidr_el1 - bics xzr, x0, x1, lsr #7 /* 0 if slow cluster */ - b.eq __restore_oslock - mov x0, xzr - msr oslar_el1, x0 /* os lock stays 0 across warm reset */ - mov x3, #3 - movz x4, #0x8000, lsl #48 - msr CPUACTLR_EL1, x4 /* turn off RCG */ - isb - msr rmr_el3, x3 /* request warm reset */ - isb - dsb sy - wfi - - /* - * These nops are here so that speculative execution won't harm us - * before we are done warm reset. - */ - .rept 65 - nop - .endr - -__restore_oslock: - mov x0, #1 - msr oslar_el1, x0 - - b arm64_cpu_startup_resume -ENDPROC(tegra210_reset_handler) diff --git a/src/soc/nvidia/tegra210/stage_entry.S b/src/soc/nvidia/tegra210/stage_entry.S new file mode 100644 index 0000000..ee0265f --- /dev/null +++ b/src/soc/nvidia/tegra210/stage_entry.S @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/asm.h> +#include <cpu/cortex_a57.h> + +/* + * It is observed that BTB contains stale data after power on reset. This could + * lead to unexpected branching and crashes at random intervals during the boot + * flow. Thus, invalidate the BTB immediately after power on reset. + */ +.macro t210_a57_fixup + /* + * Invalidate BTB along with I$ to remove any stale entries + * from the branch predictor array. + */ + mrs x0, CPUACTLR_EL1 + orr x0, x0, #BTB_INVALIDATE + msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ + dsb sy + isb + ic iallu /* invalidate */ + dsb sy + isb + + bic x0, x0, #BTB_INVALIDATE + msr CPUACTLR_EL1, x0 /* restore original CPUACTLR_EL1 */ + dsb sy + isb + + .rept 7 + nop /* wait */ + .endr + + /* + * Extract OSLK bit and check if it is '1'. This bit remains '0' + * for A53. If '1', turn off regional clock gating and request + * warm reset. + */ + mrs x0, oslsr_el1 + and x0, x0, #2 /* extract oslk bit */ + mrs x1, mpidr_el1 + bics xzr, x0, x1, lsr #7 /* 0 if slow cluster */ + b.eq 1000f + mov x0, xzr + msr oslar_el1, x0 /* os lock stays 0 across warm reset */ + mov x3, #3 + movz x4, #0x8000, lsl #48 + msr CPUACTLR_EL1, x4 /* turn off RCG */ + isb + msr rmr_el3, x3 /* request warm reset */ + isb + dsb sy + wfi + + /* + * These nops are here so that speculative execution won't harm us + * before we are done warm reset. + */ + .rept 65 + nop + .endr + +1000: + /* Restore os lock */ + mov x0, #1 + msr oslar_el1, x0 +.endm + +ENTRY(stage_entry) + t210_a57_fixup + b arm64_cpu_startup +ENDPROC(stage_entry) + +ENTRY(tegra210_reset_handler) + t210_a57_fixup + b arm64_cpu_startup_resume +ENDPROC(tegra210_reset_handler)

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New patch to review for coreboot: arm64/a57: Move cortex_a57.h under include directory
by Patrick Georgi 13 Jul '15

13 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10898 -gerrit commit b509965c6f5bdc2eb5a5f790ec93d46ff187f070 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 10 15:27:02 2015 -0700 arm64/a57: Move cortex_a57.h under include directory BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully Change-Id: I8a94176a3faacb25ae5e9eaeaac4011ddf5af6a1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 802cba6f28a4e683256e8ce9fb6395acecdc9397 Original-Change-Id: I3a5983d4a40466bc0aa8ab3bd8430ab6cdd093cc Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284868 Original-Reviewed-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/cpu/cortex_a57.S | 2 +- src/arch/arm64/cpu/cortex_a57.h | 32 ------------------------------ src/arch/arm64/include/cpu/cortex_a57.h | 35 +++++++++++++++++++++++++++++++++ 3 files changed, 36 insertions(+), 33 deletions(-) diff --git a/src/arch/arm64/cpu/cortex_a57.S b/src/arch/arm64/cpu/cortex_a57.S index ce8534b..4535d2b 100644 --- a/src/arch/arm64/cpu/cortex_a57.S +++ b/src/arch/arm64/cpu/cortex_a57.S @@ -19,7 +19,7 @@ #include <arch/asm.h> #include <arch/cache_helpers.h> -#include "cortex_a57.h" +#include <cpu/cortex_a57.h> ENTRY(arm64_cpu_early_setup) mrs x0, CPUECTLR_EL1 diff --git a/src/arch/arm64/cpu/cortex_a57.h b/src/arch/arm64/cpu/cortex_a57.h deleted file mode 100644 index 5bd6160..0000000 --- a/src/arch/arm64/cpu/cortex_a57.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef __ARCH_ARM64_CORTEX_A57_H__ -#define __ARCH_ARM64_CORTEX_A57_H__ - -#define CPUECTLR_EL1 S3_1_c15_c2_1 -#define SMPEN_SHIFT 6 - -/* Cortex MIDR[15:4] PN */ -#define CORTEX_A53_PN 0xd03 - -/* Double lock control bit */ -#define OSDLR_DBL_LOCK_BIT 1 - -#endif /* __ARCH_ARM64_CORTEX_A57_H__ */ diff --git a/src/arch/arm64/include/cpu/cortex_a57.h b/src/arch/arm64/include/cpu/cortex_a57.h new file mode 100644 index 0000000..113a6ff --- /dev/null +++ b/src/arch/arm64/include/cpu/cortex_a57.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_ARM64_CORTEX_A57_H__ +#define __ARCH_ARM64_CORTEX_A57_H__ + +#define CPUACTLR_EL1 s3_1_c15_c2_0 +#define BTB_INVALIDATE (1 << 0) + +#define CPUECTLR_EL1 S3_1_c15_c2_1 +#define SMPEN_SHIFT 6 + +/* Cortex MIDR[15:4] PN */ +#define CORTEX_A53_PN 0xd03 + +/* Double lock control bit */ +#define OSDLR_DBL_LOCK_BIT 1 + +#endif /* __ARCH_ARM64_CORTEX_A57_H__ */

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New patch to review for coreboot: arm64: Define stage_entry as weak symbol
by Patrick Georgi 13 Jul '15

13 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10897 -gerrit commit 7c9eba16a7da49de650905e43a81c4f761086b7a Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 10 15:25:26 2015 -0700 arm64: Define stage_entry as weak symbol This allows SoCs/CPUs to have custom stage_entry in order to apply any fixups that need to run before standard cpu reset procedure. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully Change-Id: Iaae7636349140664b19e81b0082017b63b13f45b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 498d04b0e9a3394943f03cad603c30ae8b3805d4 Original-Change-Id: I9a005502d4cfcb76017dcae3a655efc0c8814a93 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284867 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/include/arch/asm.h | 4 ++++ src/arch/arm64/stage_entry.S | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index 0dc2974..851f3f9 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -41,4 +41,8 @@ */ #define CPU_RESET_ENTRY(name) ENTRY_WITH_ALIGN(name, 6) +#define ENTRY_WEAK(name) \ + ENTRY(name) \ + .weak name \ + #endif /* __ARM_ARM64_ASM_H */ diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 5ff2c4e..4e15dbb 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -228,6 +228,12 @@ CPU_RESET_ENTRY(arm64_cpu_startup_resume) b arm64_c_environment ENDPROC(arm64_cpu_startup_resume) -ENTRY(stage_entry) +/* + * stage_entry is defined as a weak symbol to allow SoCs/CPUs to define a custom + * entry point to perform any fixups that need to be done immediately after + * power on reset. In case SoC/CPU does not need any custom-defined entrypoint, + * this weak symbol can be used to jump directly to arm64_cpu_startup. + */ +ENTRY_WEAK(stage_entry) b arm64_cpu_startup ENDPROC(stage_entry)

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Patch merged into coreboot/master: libpayload: Fix arithmetic precedence in div_round_up()
by gerrit＠coreboot.org 13 Jul '15

13 Jul '15

the following patch was just integrated into master: commit 6df355da879797899eb6337eb21868163c1ee07d Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jul 9 15:47:07 2015 -0700 libpayload: Fix arithmetic precedence in div_round_up() Well, this is just embarrassing... BRANCH=None BUG=None TEST=None Change-Id: I7c443d2100b6861d736320ac14c1bd9965937a66 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 455e3784882ea1b76bcf8e17724869e37d9c629d Original-Change-Id: Ia33e98aeaa8e78e3e3d2c7547e673a623ea86ce2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284596 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/10879 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Martin Roth <gaumless(a)gmail.com> See http://review.coreboot.org/10879 for details. -gerrit

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Patch merged into coreboot/master: t210: Add TZDRAM_BASE param to BL31_MAKEARGS
by gerrit＠coreboot.org 13 Jul '15

13 Jul '15

the following patch was just integrated into master: commit 3ae5044b7330ea4af0214b7db29749eed17f2e66 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 7 21:35:56 2015 -0700 t210: Add TZDRAM_BASE param to BL31_MAKEARGS 1. Make TTB_SIZE Kconfig option 2. Add Kconfig option for maximum secure component size 3. Add check in Makefile to ensure that Trustzone area is big enough to hold TTB and secure components 4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE BUG=chrome-os-partner:42319 BRANCH=None Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284074 Original-Reviewed-by: Varun Wadekar <vwadekar(a)nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10878 for details. -gerrit

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Patch set updated for coreboot: coreinfo: Fix build output (cosmetical)
by Stefan Reinauer 13 Jul '15

13 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10744 -gerrit commit 4ebc2550f22a61d562300ecd7d4eb5642531b35f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jun 30 15:22:12 2015 -0700 coreinfo: Fix build output (cosmetical) This patch aligns the output of coreinfo with the output of libpayload, and switches from using $(Q) to .SILENT Change-Id: I6c3cdda7febc02bab9195fc98f46490c0d478a9a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/Makefile | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 3cc0fc9..d63f515 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -43,7 +43,7 @@ MAKEFLAGS += -rR --no-print-directory # Make is silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) -Q := @ +.SILENT: endif HOSTCC ?= gcc @@ -72,19 +72,19 @@ include $(src)/.config all: $(TARGET) $(TARGET): $(src)/.config $(obj)/config.h $(OBJS) libpayload - $(Q)printf " LPCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LPCC) -o $@ $(OBJS) - $(Q)$(OBJCOPY) --only-keep-debug $@ $(TARGET).debug - $(Q)$(OBJCOPY) --strip-debug $@ - $(Q)$(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ + printf " LPCC $(subst $(shell pwd)/,,$(@)) (LINK)\n" + $(LPCC) -o $@ $(OBJS) + $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug + $(OBJCOPY) --strip-debug $@ + $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ $(obj)/%.S.o: $(src)/%.S libpayload - $(Q)printf " LPAS $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LPAS) -o $@ $< + printf " LPAS $(subst $(shell pwd)/,,$(@))\n" + $(LPAS) -o $@ $< $(obj)/%.o: $(src)/%.c libpayload - $(Q)printf " LPCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LPCC) $(CFLAGS) -c -o $@ $< + printf " LPCC $(subst $(shell pwd)/,,$(@))\n" + $(LPCC) $(CFLAGS) -c -o $@ $< else all: config @@ -92,13 +92,13 @@ endif ifneq ($(strip $(HAVE_LIBPAYLOAD)),) libpayload: - $(Q)printf "Found Libpayload $(LIBPAYLOAD_DIR).\n" + printf "Found Libpayload $(LIBPAYLOAD_DIR).\n" else libpayload: - $(Q)printf "Building libpayload @ $(LIBCONFIG_PATH).\n" - $(Q)make -C $(LIBCONFIG_PATH) distclean - $(Q)make -C $(LIBCONFIG_PATH) $(LIB_CONFIG) - $(Q)make -C $(LIBCONFIG_PATH) DESTDIR=$(shell pwd)/$(LIBPAYLOAD_DIR) install + printf "Building libpayload @ $(LIBCONFIG_PATH).\n" + make -C $(LIBCONFIG_PATH) distclean + make -C $(LIBCONFIG_PATH) $(LIB_CONFIG) + make -C $(LIBCONFIG_PATH) DESTDIR=$(shell pwd)/$(LIBPAYLOAD_DIR) install endif $(obj)/config.h: @@ -107,11 +107,11 @@ $(obj)/config.h: $(shell mkdir -p $(obj) $(objk)/lxdialog $(KCONFIG_SPLITCONFIG)) clean: - $(Q)rm -rf build/*.elf build/*.o + rm -rf build/*.elf build/*.o distclean: clean - $(Q)rm -rf build - $(Q)rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* + rm -rf build + rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* include $(srck)/Makefile

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Patch merged into coreboot/master: coreinfo: fix compilation
by gerrit＠coreboot.org 13 Jul '15

13 Jul '15

the following patch was just integrated into master: commit ccc55fdc6fae37a085e9f1a8a19a539728907ca1 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Jun 29 16:44:12 2015 -0700 coreinfo: fix compilation - extra rule for config.h creation - include kconfig.h from libpayload - libpayload symbols are conflicting with gcc builtins (e.g. log2) - ALIGN() is already defined in libpayload these days - move libpayload build directory under build/ Change-Id: I2aefdde26853253d58f6cf6e186e784871c1cb5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10717 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10717 for details. -gerrit

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Patch set updated for coreboot: Enable pages. Tested and working on QEMU.
by Stefan Reinauer 13 Jul '15

13 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5354 -gerrit commit 497de095b1321c820783a36eafb0d7458dc9f1d0 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sat Mar 8 17:33:12 2014 +0100 Enable pages. Tested and working on QEMU. Enable page tables in coreboot. We're going to have to do this at some point, when we hit x86_64; the ARM ports do paging in both 32- and 64-bit modes; MTRR is a PITA; and it's easy. The non-paging architectures are outnumbered by the paging architectures! This trial example just sets up a 4G identity map using 4M pages. It works for QEMU just fine to boot tinycore linux. The next step is to map the low 4M much more finely, with 4K pages, so we can catch NULL pointers. This will require reworking VGA bios support, which uses page 0. For SMP, we'll need to add code to let them also load page tables, but one thing at a time. Next I'll add code to support page table manipulation. With luck, we can stop fighting the MTRRs with all their pain and suffering. We can use the MTRRs for very coarse mappings and use the page tables to refine them. For example, we could stop using fixed MTRRs entirely since we can map parts of the low 1M as WP or even UC on a 4k granularity. For now we use this for machines where coreboot can live in the low 4G. For other cases, it's time to start thinking about 64-bit mode; since entering Long Mode requires page tables, we need to figure it out. The ARM V8 port is carving the way so this is as good a time as any. This code is enabled by CONFIG_PGE, which defaults to n. To turn it on navigate to architecture options in menuconfig. A remaining question is whether to turn off paging when we start the payload. For now, we turn it off. Also, if they payload returns, we hang until such time as we turn paging back on (which is easy, actually). Change-Id: Iea0192e5187c47e63d25f88eaa3e88cb6c58feb1 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/Kconfig | 12 +++ src/arch/x86/Makefile.inc | 3 + src/arch/x86/boot/boot.c | 20 ++++ src/arch/x86/init/failover.ld | 2 +- src/arch/x86/lib/c_start.S | 5 +- src/arch/x86/lib/pagetables.S | 244 ++++++++++++++++++++++++++++++++++++++++++ src/arch/x86/lib/paging.S | 58 ++++++++++ 7 files changed, 342 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 88b2592..500cca8 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -84,6 +84,18 @@ config NUM_IPI_STARTS int default 2 +config PGE + bool "Enable x86 page tables." + default n + help + In original coreboot we did not use page tables. The + MTRR code just keeps getting messier and if we turn + on paging it gets very easy. We can enable disable + caching on anything down to a 4k boundary. We can + control cache disable and write-back/writethrough + on each page. For now, this code creates an identity + map for 4G using 4M pages. + config ROMCC bool default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2448590..eeb5089 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -87,6 +87,9 @@ bootblock_inc = $(src)/arch/x86/init/prologue.inc bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc +ifeq ($(CONFIG_PGE),y) +bootblock_inc += $(src)/arch/x86/lib/paging.S +endif bootblock_inc += $(src)/arch/x86/lib/id.inc ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) bootblock_inc += $(src)/cpu/intel/fit/fit.inc diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index d86a6c3..78b0a3f 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -12,6 +12,12 @@ static void jmp_payload_no_bounce_buffer(void *entry) /* Jump to kernel */ __asm__ __volatile__( " cld \n\t" + /* Paging might have been on. We need to turn it off + * right before we jump + */ + " movl %%cr0, %%eax\n\t" + " andl $0x7fffffff, %%eax\n\t" + " movl %%edx, %%cr0\n\t" /* Now jump to the loaded image */ " call *%0\n\t" @@ -73,6 +79,16 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) " jmp *%%eax\n\t" "1: \n\t" + /* Paging might have been on. It's ok, + * the bounce buffer runs at same VA and PA. + * So we can turn paging off now. + */ + " movl %%cr0, %%eax\n\t" + " andl $0x7fffffff, %%eax\n\t" + " movl %%eax, %%cr0\n\t" + " jmp 1f\n\t" + "1:\n\t" + /* Copy the coreboot bounce buffer over coreboot */ /* Move ``longs'' the coreboot size is 4 byte aligned */ " movl 16(%%esp), %%edi\n\t" @@ -85,6 +101,10 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) " movl %5, %%eax\n\t" " movl 0(%%esp), %%ebx\n\t" " call *4(%%esp)\n\t" +#if CONFIG_PGE + /* TODO: turn paging back on. For now, just hang. */ + "1: jmp 1b\n\t" +#endif /* The loaded image returned? */ " cli \n\t" diff --git a/src/arch/x86/init/failover.ld b/src/arch/x86/init/failover.ld index d7aa47e..467f339 100644 --- a/src/arch/x86/init/failover.ld +++ b/src/arch/x86/init/failover.ld @@ -50,7 +50,7 @@ SECTIONS * address gets applied. */ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0) - 8192; /* Post-check proper SIPI vector. */ _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0), diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index dbed123..985d1af 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -33,7 +33,10 @@ _start: movl %eax, %gs post_code(POST_ENTRY_C_START) /* post 13 */ - + /* turn on paging (conditional on CONFIG_PGE) */ +#if CONFIG_PGE +#include "paging.S" +#endif cld /** poison the stack. Code should not count on the diff --git a/src/arch/x86/lib/pagetables.S b/src/arch/x86/lib/pagetables.S new file mode 100644 index 0000000..e87c1bf --- /dev/null +++ b/src/arch/x86/lib/pagetables.S @@ -0,0 +1,244 @@ + .long 1 + .align 4096 + +/* Create a PTE given an address. It's your responsibility to make + * sure the address meets all requirements, viz., low order 12 bits + * are zero. The PTE will have the Present (1) and Write (4) bits set. + */ +#define PTE(x) ((x)|5) +/* Create an entry for a 4K page, with Present bit (1) and Write bit (4) set + * The parameter is a page number, not an address. For 32-bit mode, use .long; + * for 64-bit mode, use .llong + */ +#define P4K(x) ((x<<12)|5) + +/* Create an entry for a 32-bit 4M page, with Page Size (0x80), Present bit + * (1) and Write bit (4) set The parameter is a 4M page number, not an + * address. + */ +#define P4M(x) ((x<<22) | 0x80 | 5) + +/* Create an entry for a 64-bit 2M page, with Page Size (0x80), + * Present bit (1) and Write bit (4) set The parameter is a page + * number, not an address. + */ +#define P2M(x) ((x<<21) | 0x80 | 5) + +/* Define a Page Map Level 2 of 4M entries to identity-map + * the low 4G of memory. This is just enough to get us into + * Long Mode. + */ +PageMapLevel2: + .long P4M(0x000),P4M(0x001),P4M(0x002),P4M(0x003),P4M(0x004),P4M(0x005),P4M(0x006),P4M(0x007) + .long P4M(0x008),P4M(0x009),P4M(0x00a),P4M(0x00b),P4M(0x00c),P4M(0x00d),P4M(0x00e),P4M(0x00f) + .long P4M(0x010),P4M(0x011),P4M(0x012),P4M(0x013),P4M(0x014),P4M(0x015),P4M(0x016),P4M(0x017) + .long P4M(0x018),P4M(0x019),P4M(0x01a),P4M(0x01b),P4M(0x01c),P4M(0x01d),P4M(0x01e),P4M(0x01f) + .long P4M(0x020),P4M(0x021),P4M(0x022),P4M(0x023),P4M(0x024),P4M(0x025),P4M(0x026),P4M(0x027) + .long P4M(0x028),P4M(0x029),P4M(0x02a),P4M(0x02b),P4M(0x02c),P4M(0x02d),P4M(0x02e),P4M(0x02f) + .long P4M(0x030),P4M(0x031),P4M(0x032),P4M(0x033),P4M(0x034),P4M(0x035),P4M(0x036),P4M(0x037) + .long P4M(0x038),P4M(0x039),P4M(0x03a),P4M(0x03b),P4M(0x03c),P4M(0x03d),P4M(0x03e),P4M(0x03f) + .long P4M(0x040),P4M(0x041),P4M(0x042),P4M(0x043),P4M(0x044),P4M(0x045),P4M(0x046),P4M(0x047) + .long P4M(0x048),P4M(0x049),P4M(0x04a),P4M(0x04b),P4M(0x04c),P4M(0x04d),P4M(0x04e),P4M(0x04f) + .long P4M(0x050),P4M(0x051),P4M(0x052),P4M(0x053),P4M(0x054),P4M(0x055),P4M(0x056),P4M(0x057) + .long P4M(0x058),P4M(0x059),P4M(0x05a),P4M(0x05b),P4M(0x05c),P4M(0x05d),P4M(0x05e),P4M(0x05f) + .long P4M(0x060),P4M(0x061),P4M(0x062),P4M(0x063),P4M(0x064),P4M(0x065),P4M(0x066),P4M(0x067) + .long P4M(0x068),P4M(0x069),P4M(0x06a),P4M(0x06b),P4M(0x06c),P4M(0x06d),P4M(0x06e),P4M(0x06f) + .long P4M(0x070),P4M(0x071),P4M(0x072),P4M(0x073),P4M(0x074),P4M(0x075),P4M(0x076),P4M(0x077) + .long P4M(0x078),P4M(0x079),P4M(0x07a),P4M(0x07b),P4M(0x07c),P4M(0x07d),P4M(0x07e),P4M(0x07f) + .long P4M(0x080),P4M(0x081),P4M(0x082),P4M(0x083),P4M(0x084),P4M(0x085),P4M(0x086),P4M(0x087) + .long P4M(0x088),P4M(0x089),P4M(0x08a),P4M(0x08b),P4M(0x08c),P4M(0x08d),P4M(0x08e),P4M(0x08f) + .long P4M(0x090),P4M(0x091),P4M(0x092),P4M(0x093),P4M(0x094),P4M(0x095),P4M(0x096),P4M(0x097) + .long P4M(0x098),P4M(0x099),P4M(0x09a),P4M(0x09b),P4M(0x09c),P4M(0x09d),P4M(0x09e),P4M(0x09f) + .long P4M(0x0a0),P4M(0x0a1),P4M(0x0a2),P4M(0x0a3),P4M(0x0a4),P4M(0x0a5),P4M(0x0a6),P4M(0x0a7) + .long P4M(0x0a8),P4M(0x0a9),P4M(0x0aa),P4M(0x0ab),P4M(0x0ac),P4M(0x0ad),P4M(0x0ae),P4M(0x0af) + .long P4M(0x0b0),P4M(0x0b1),P4M(0x0b2),P4M(0x0b3),P4M(0x0b4),P4M(0x0b5),P4M(0x0b6),P4M(0x0b7) + .long P4M(0x0b8),P4M(0x0b9),P4M(0x0ba),P4M(0x0bb),P4M(0x0bc),P4M(0x0bd),P4M(0x0be),P4M(0x0bf) + .long P4M(0x0c0),P4M(0x0c1),P4M(0x0c2),P4M(0x0c3),P4M(0x0c4),P4M(0x0c5),P4M(0x0c6),P4M(0x0c7) + .long P4M(0x0c8),P4M(0x0c9),P4M(0x0ca),P4M(0x0cb),P4M(0x0cc),P4M(0x0cd),P4M(0x0ce),P4M(0x0cf) + .long P4M(0x0d0),P4M(0x0d1),P4M(0x0d2),P4M(0x0d3),P4M(0x0d4),P4M(0x0d5),P4M(0x0d6),P4M(0x0d7) + .long P4M(0x0d8),P4M(0x0d9),P4M(0x0da),P4M(0x0db),P4M(0x0dc),P4M(0x0dd),P4M(0x0de),P4M(0x0df) + .long P4M(0x0e0),P4M(0x0e1),P4M(0x0e2),P4M(0x0e3),P4M(0x0e4),P4M(0x0e5),P4M(0x0e6),P4M(0x0e7) + .long P4M(0x0e8),P4M(0x0e9),P4M(0x0ea),P4M(0x0eb),P4M(0x0ec),P4M(0x0ed),P4M(0x0ee),P4M(0x0ef) + .long P4M(0x0f0),P4M(0x0f1),P4M(0x0f2),P4M(0x0f3),P4M(0x0f4),P4M(0x0f5),P4M(0x0f6),P4M(0x0f7) + .long P4M(0x0f8),P4M(0x0f9),P4M(0x0fa),P4M(0x0fb),P4M(0x0fc),P4M(0x0fd),P4M(0x0fe),P4M(0x0ff) + .long P4M(0x100),P4M(0x101),P4M(0x102),P4M(0x103),P4M(0x104),P4M(0x105),P4M(0x106),P4M(0x107) + .long P4M(0x108),P4M(0x109),P4M(0x10a),P4M(0x10b),P4M(0x10c),P4M(0x10d),P4M(0x10e),P4M(0x10f) + .long P4M(0x110),P4M(0x111),P4M(0x112),P4M(0x113),P4M(0x114),P4M(0x115),P4M(0x116),P4M(0x117) + .long P4M(0x118),P4M(0x119),P4M(0x11a),P4M(0x11b),P4M(0x11c),P4M(0x11d),P4M(0x11e),P4M(0x11f) + .long P4M(0x120),P4M(0x121),P4M(0x122),P4M(0x123),P4M(0x124),P4M(0x125),P4M(0x126),P4M(0x127) + .long P4M(0x128),P4M(0x129),P4M(0x12a),P4M(0x12b),P4M(0x12c),P4M(0x12d),P4M(0x12e),P4M(0x12f) + .long P4M(0x130),P4M(0x131),P4M(0x132),P4M(0x133),P4M(0x134),P4M(0x135),P4M(0x136),P4M(0x137) + .long P4M(0x138),P4M(0x139),P4M(0x13a),P4M(0x13b),P4M(0x13c),P4M(0x13d),P4M(0x13e),P4M(0x13f) + .long P4M(0x140),P4M(0x141),P4M(0x142),P4M(0x143),P4M(0x144),P4M(0x145),P4M(0x146),P4M(0x147) + .long P4M(0x148),P4M(0x149),P4M(0x14a),P4M(0x14b),P4M(0x14c),P4M(0x14d),P4M(0x14e),P4M(0x14f) + .long P4M(0x150),P4M(0x151),P4M(0x152),P4M(0x153),P4M(0x154),P4M(0x155),P4M(0x156),P4M(0x157) + .long P4M(0x158),P4M(0x159),P4M(0x15a),P4M(0x15b),P4M(0x15c),P4M(0x15d),P4M(0x15e),P4M(0x15f) + .long P4M(0x160),P4M(0x161),P4M(0x162),P4M(0x163),P4M(0x164),P4M(0x165),P4M(0x166),P4M(0x167) + .long P4M(0x168),P4M(0x169),P4M(0x16a),P4M(0x16b),P4M(0x16c),P4M(0x16d),P4M(0x16e),P4M(0x16f) + .long P4M(0x170),P4M(0x171),P4M(0x172),P4M(0x173),P4M(0x174),P4M(0x175),P4M(0x176),P4M(0x177) + .long P4M(0x178),P4M(0x179),P4M(0x17a),P4M(0x17b),P4M(0x17c),P4M(0x17d),P4M(0x17e),P4M(0x17f) + .long P4M(0x180),P4M(0x181),P4M(0x182),P4M(0x183),P4M(0x184),P4M(0x185),P4M(0x186),P4M(0x187) + .long P4M(0x188),P4M(0x189),P4M(0x18a),P4M(0x18b),P4M(0x18c),P4M(0x18d),P4M(0x18e),P4M(0x18f) + .long P4M(0x190),P4M(0x191),P4M(0x192),P4M(0x193),P4M(0x194),P4M(0x195),P4M(0x196),P4M(0x197) + .long P4M(0x198),P4M(0x199),P4M(0x19a),P4M(0x19b),P4M(0x19c),P4M(0x19d),P4M(0x19e),P4M(0x19f) + .long P4M(0x1a0),P4M(0x1a1),P4M(0x1a2),P4M(0x1a3),P4M(0x1a4),P4M(0x1a5),P4M(0x1a6),P4M(0x1a7) + .long P4M(0x1a8),P4M(0x1a9),P4M(0x1aa),P4M(0x1ab),P4M(0x1ac),P4M(0x1ad),P4M(0x1ae),P4M(0x1af) + .long P4M(0x1b0),P4M(0x1b1),P4M(0x1b2),P4M(0x1b3),P4M(0x1b4),P4M(0x1b5),P4M(0x1b6),P4M(0x1b7) + .long P4M(0x1b8),P4M(0x1b9),P4M(0x1ba),P4M(0x1bb),P4M(0x1bc),P4M(0x1bd),P4M(0x1be),P4M(0x1bf) + .long P4M(0x1c0),P4M(0x1c1),P4M(0x1c2),P4M(0x1c3),P4M(0x1c4),P4M(0x1c5),P4M(0x1c6),P4M(0x1c7) + .long P4M(0x1c8),P4M(0x1c9),P4M(0x1ca),P4M(0x1cb),P4M(0x1cc),P4M(0x1cd),P4M(0x1ce),P4M(0x1cf) + .long P4M(0x1d0),P4M(0x1d1),P4M(0x1d2),P4M(0x1d3),P4M(0x1d4),P4M(0x1d5),P4M(0x1d6),P4M(0x1d7) + .long P4M(0x1d8),P4M(0x1d9),P4M(0x1da),P4M(0x1db),P4M(0x1dc),P4M(0x1dd),P4M(0x1de),P4M(0x1df) + .long P4M(0x1e0),P4M(0x1e1),P4M(0x1e2),P4M(0x1e3),P4M(0x1e4),P4M(0x1e5),P4M(0x1e6),P4M(0x1e7) + .long P4M(0x1e8),P4M(0x1e9),P4M(0x1ea),P4M(0x1eb),P4M(0x1ec),P4M(0x1ed),P4M(0x1ee),P4M(0x1ef) + .long P4M(0x1f0),P4M(0x1f1),P4M(0x1f2),P4M(0x1f3),P4M(0x1f4),P4M(0x1f5),P4M(0x1f6),P4M(0x1f7) + .long P4M(0x1f8),P4M(0x1f9),P4M(0x1fa),P4M(0x1fb),P4M(0x1fc),P4M(0x1fd),P4M(0x1fe),P4M(0x1ff) + .long P4M(0x200),P4M(0x201),P4M(0x202),P4M(0x203),P4M(0x204),P4M(0x205),P4M(0x206),P4M(0x207) + .long P4M(0x208),P4M(0x209),P4M(0x20a),P4M(0x20b),P4M(0x20c),P4M(0x20d),P4M(0x20e),P4M(0x20f) + .long P4M(0x210),P4M(0x211),P4M(0x212),P4M(0x213),P4M(0x214),P4M(0x215),P4M(0x216),P4M(0x217) + .long P4M(0x218),P4M(0x219),P4M(0x21a),P4M(0x21b),P4M(0x21c),P4M(0x21d),P4M(0x21e),P4M(0x21f) + .long P4M(0x220),P4M(0x221),P4M(0x222),P4M(0x223),P4M(0x224),P4M(0x225),P4M(0x226),P4M(0x227) + .long P4M(0x228),P4M(0x229),P4M(0x22a),P4M(0x22b),P4M(0x22c),P4M(0x22d),P4M(0x22e),P4M(0x22f) + .long P4M(0x230),P4M(0x231),P4M(0x232),P4M(0x233),P4M(0x234),P4M(0x235),P4M(0x236),P4M(0x237) + .long P4M(0x238),P4M(0x239),P4M(0x23a),P4M(0x23b),P4M(0x23c),P4M(0x23d),P4M(0x23e),P4M(0x23f) + .long P4M(0x240),P4M(0x241),P4M(0x242),P4M(0x243),P4M(0x244),P4M(0x245),P4M(0x246),P4M(0x247) + .long P4M(0x248),P4M(0x249),P4M(0x24a),P4M(0x24b),P4M(0x24c),P4M(0x24d),P4M(0x24e),P4M(0x24f) + .long P4M(0x250),P4M(0x251),P4M(0x252),P4M(0x253),P4M(0x254),P4M(0x255),P4M(0x256),P4M(0x257) + .long P4M(0x258),P4M(0x259),P4M(0x25a),P4M(0x25b),P4M(0x25c),P4M(0x25d),P4M(0x25e),P4M(0x25f) + .long P4M(0x260),P4M(0x261),P4M(0x262),P4M(0x263),P4M(0x264),P4M(0x265),P4M(0x266),P4M(0x267) + .long P4M(0x268),P4M(0x269),P4M(0x26a),P4M(0x26b),P4M(0x26c),P4M(0x26d),P4M(0x26e),P4M(0x26f) + .long P4M(0x270),P4M(0x271),P4M(0x272),P4M(0x273),P4M(0x274),P4M(0x275),P4M(0x276),P4M(0x277) + .long P4M(0x278),P4M(0x279),P4M(0x27a),P4M(0x27b),P4M(0x27c),P4M(0x27d),P4M(0x27e),P4M(0x27f) + .long P4M(0x280),P4M(0x281),P4M(0x282),P4M(0x283),P4M(0x284),P4M(0x285),P4M(0x286),P4M(0x287) + .long P4M(0x288),P4M(0x289),P4M(0x28a),P4M(0x28b),P4M(0x28c),P4M(0x28d),P4M(0x28e),P4M(0x28f) + .long P4M(0x290),P4M(0x291),P4M(0x292),P4M(0x293),P4M(0x294),P4M(0x295),P4M(0x296),P4M(0x297) + .long P4M(0x298),P4M(0x299),P4M(0x29a),P4M(0x29b),P4M(0x29c),P4M(0x29d),P4M(0x29e),P4M(0x29f) + .long P4M(0x2a0),P4M(0x2a1),P4M(0x2a2),P4M(0x2a3),P4M(0x2a4),P4M(0x2a5),P4M(0x2a6),P4M(0x2a7) + .long P4M(0x2a8),P4M(0x2a9),P4M(0x2aa),P4M(0x2ab),P4M(0x2ac),P4M(0x2ad),P4M(0x2ae),P4M(0x2af) + .long P4M(0x2b0),P4M(0x2b1),P4M(0x2b2),P4M(0x2b3),P4M(0x2b4),P4M(0x2b5),P4M(0x2b6),P4M(0x2b7) + .long P4M(0x2b8),P4M(0x2b9),P4M(0x2ba),P4M(0x2bb),P4M(0x2bc),P4M(0x2bd),P4M(0x2be),P4M(0x2bf) + .long P4M(0x2c0),P4M(0x2c1),P4M(0x2c2),P4M(0x2c3),P4M(0x2c4),P4M(0x2c5),P4M(0x2c6),P4M(0x2c7) + .long P4M(0x2c8),P4M(0x2c9),P4M(0x2ca),P4M(0x2cb),P4M(0x2cc),P4M(0x2cd),P4M(0x2ce),P4M(0x2cf) + .long P4M(0x2d0),P4M(0x2d1),P4M(0x2d2),P4M(0x2d3),P4M(0x2d4),P4M(0x2d5),P4M(0x2d6),P4M(0x2d7) + .long P4M(0x2d8),P4M(0x2d9),P4M(0x2da),P4M(0x2db),P4M(0x2dc),P4M(0x2dd),P4M(0x2de),P4M(0x2df) + .long P4M(0x2e0),P4M(0x2e1),P4M(0x2e2),P4M(0x2e3),P4M(0x2e4),P4M(0x2e5),P4M(0x2e6),P4M(0x2e7) + .long P4M(0x2e8),P4M(0x2e9),P4M(0x2ea),P4M(0x2eb),P4M(0x2ec),P4M(0x2ed),P4M(0x2ee),P4M(0x2ef) + .long P4M(0x2f0),P4M(0x2f1),P4M(0x2f2),P4M(0x2f3),P4M(0x2f4),P4M(0x2f5),P4M(0x2f6),P4M(0x2f7) + .long P4M(0x2f8),P4M(0x2f9),P4M(0x2fa),P4M(0x2fb),P4M(0x2fc),P4M(0x2fd),P4M(0x2fe),P4M(0x2ff) + .long P4M(0x300),P4M(0x301),P4M(0x302),P4M(0x303),P4M(0x304),P4M(0x305),P4M(0x306),P4M(0x307) + .long P4M(0x308),P4M(0x309),P4M(0x30a),P4M(0x30b),P4M(0x30c),P4M(0x30d),P4M(0x30e),P4M(0x30f) + .long P4M(0x310),P4M(0x311),P4M(0x312),P4M(0x313),P4M(0x314),P4M(0x315),P4M(0x316),P4M(0x317) + .long P4M(0x318),P4M(0x319),P4M(0x31a),P4M(0x31b),P4M(0x31c),P4M(0x31d),P4M(0x31e),P4M(0x31f) + .long P4M(0x320),P4M(0x321),P4M(0x322),P4M(0x323),P4M(0x324),P4M(0x325),P4M(0x326),P4M(0x327) + .long P4M(0x328),P4M(0x329),P4M(0x32a),P4M(0x32b),P4M(0x32c),P4M(0x32d),P4M(0x32e),P4M(0x32f) + .long P4M(0x330),P4M(0x331),P4M(0x332),P4M(0x333),P4M(0x334),P4M(0x335),P4M(0x336),P4M(0x337) + .long P4M(0x338),P4M(0x339),P4M(0x33a),P4M(0x33b),P4M(0x33c),P4M(0x33d),P4M(0x33e),P4M(0x33f) + .long P4M(0x340),P4M(0x341),P4M(0x342),P4M(0x343),P4M(0x344),P4M(0x345),P4M(0x346),P4M(0x347) + .long P4M(0x348),P4M(0x349),P4M(0x34a),P4M(0x34b),P4M(0x34c),P4M(0x34d),P4M(0x34e),P4M(0x34f) + .long P4M(0x350),P4M(0x351),P4M(0x352),P4M(0x353),P4M(0x354),P4M(0x355),P4M(0x356),P4M(0x357) + .long P4M(0x358),P4M(0x359),P4M(0x35a),P4M(0x35b),P4M(0x35c),P4M(0x35d),P4M(0x35e),P4M(0x35f) + .long P4M(0x360),P4M(0x361),P4M(0x362),P4M(0x363),P4M(0x364),P4M(0x365),P4M(0x366),P4M(0x367) + .long P4M(0x368),P4M(0x369),P4M(0x36a),P4M(0x36b),P4M(0x36c),P4M(0x36d),P4M(0x36e),P4M(0x36f) + .long P4M(0x370),P4M(0x371),P4M(0x372),P4M(0x373),P4M(0x374),P4M(0x375),P4M(0x376),P4M(0x377) + .long P4M(0x378),P4M(0x379),P4M(0x37a),P4M(0x37b),P4M(0x37c),P4M(0x37d),P4M(0x37e),P4M(0x37f) + .long P4M(0x380),P4M(0x381),P4M(0x382),P4M(0x383),P4M(0x384),P4M(0x385),P4M(0x386),P4M(0x387) + .long P4M(0x388),P4M(0x389),P4M(0x38a),P4M(0x38b),P4M(0x38c),P4M(0x38d),P4M(0x38e),P4M(0x38f) + .long P4M(0x390),P4M(0x391),P4M(0x392),P4M(0x393),P4M(0x394),P4M(0x395),P4M(0x396),P4M(0x397) + .long P4M(0x398),P4M(0x399),P4M(0x39a),P4M(0x39b),P4M(0x39c),P4M(0x39d),P4M(0x39e),P4M(0x39f) + .long P4M(0x3a0),P4M(0x3a1),P4M(0x3a2),P4M(0x3a3),P4M(0x3a4),P4M(0x3a5),P4M(0x3a6),P4M(0x3a7) + .long P4M(0x3a8),P4M(0x3a9),P4M(0x3aa),P4M(0x3ab),P4M(0x3ac),P4M(0x3ad),P4M(0x3ae),P4M(0x3af) + .long P4M(0x3b0),P4M(0x3b1),P4M(0x3b2),P4M(0x3b3),P4M(0x3b4),P4M(0x3b5),P4M(0x3b6),P4M(0x3b7) + .long P4M(0x3b8),P4M(0x3b9),P4M(0x3ba),P4M(0x3bb),P4M(0x3bc),P4M(0x3bd),P4M(0x3be),P4M(0x3bf) + .long P4M(0x3c0),P4M(0x3c1),P4M(0x3c2),P4M(0x3c3),P4M(0x3c4),P4M(0x3c5),P4M(0x3c6),P4M(0x3c7) + .long P4M(0x3c8),P4M(0x3c9),P4M(0x3ca),P4M(0x3cb),P4M(0x3cc),P4M(0x3cd),P4M(0x3ce),P4M(0x3cf) + .long P4M(0x3d0),P4M(0x3d1),P4M(0x3d2),P4M(0x3d3),P4M(0x3d4),P4M(0x3d5),P4M(0x3d6),P4M(0x3d7) + .long P4M(0x3d8),P4M(0x3d9),P4M(0x3da),P4M(0x3db),P4M(0x3dc),P4M(0x3dd),P4M(0x3de),P4M(0x3df) + .long P4M(0x3e0),P4M(0x3e1),P4M(0x3e2),P4M(0x3e3),P4M(0x3e4),P4M(0x3e5),P4M(0x3e6),P4M(0x3e7) + .long P4M(0x3e8),P4M(0x3e9),P4M(0x3ea),P4M(0x3eb),P4M(0x3ec),P4M(0x3ed),P4M(0x3ee),P4M(0x3ef) + .long P4M(0x3f0),P4M(0x3f1),P4M(0x3f2),P4M(0x3f3),P4M(0x3f4),P4M(0x3f5),P4M(0x3f6),P4M(0x3f7) + .long P4M(0x3f8),P4M(0x3f9),P4M(0x3fa),P4M(0x3fb),P4M(0x3fc),P4M(0x3fd),P4M(0x3fe),P4M(0x3ff) + +#if 0 // someday +#if CONFIG_ARCH_X86_64 +/* 64 bit GDT ... */ +gdt64: + .quad $0x0000000000000000 /* NULL descriptor */ + .quad $0x0020980000000000 /* CS */ + +gdt64p: + .word 15 // 2*8-1 + .quad $gdt64 +.align 4096 + +pml2: .quad P2M(0x000),P2M(0x001),P2M(0x002),P2M(0x003),P2M(0x004),P2M(0x005),P2M(0x006),P2M(0x007) + .quad P2M(0x008),P2M(0x009),P2M(0x00a),P2M(0x00b),P2M(0x00c),P2M(0x00d),P2M(0x00e),P2M(0x00f) + .quad P2M(0x010),P2M(0x011),P2M(0x012),P2M(0x013),P2M(0x014),P2M(0x015),P2M(0x016),P2M(0x017) + .quad P2M(0x018),P2M(0x019),P2M(0x01a),P2M(0x01b),P2M(0x01c),P2M(0x01d),P2M(0x01e),P2M(0x01f) + .quad P2M(0x020),P2M(0x021),P2M(0x022),P2M(0x023),P2M(0x024),P2M(0x025),P2M(0x026),P2M(0x027) + .quad P2M(0x028),P2M(0x029),P2M(0x02a),P2M(0x02b),P2M(0x02c),P2M(0x02d),P2M(0x02e),P2M(0x02f) + .quad P2M(0x030),P2M(0x031),P2M(0x032),P2M(0x033),P2M(0x034),P2M(0x035),P2M(0x036),P2M(0x037) + .quad P2M(0x038),P2M(0x039),P2M(0x03a),P2M(0x03b),P2M(0x03c),P2M(0x03d),P2M(0x03e),P2M(0x03f) + .quad P2M(0x040),P2M(0x041),P2M(0x042),P2M(0x043),P2M(0x044),P2M(0x045),P2M(0x046),P2M(0x047) + .quad P2M(0x048),P2M(0x049),P2M(0x04a),P2M(0x04b),P2M(0x04c),P2M(0x04d),P2M(0x04e),P2M(0x04f) + .quad P2M(0x050),P2M(0x051),P2M(0x052),P2M(0x053),P2M(0x054),P2M(0x055),P2M(0x056),P2M(0x057) + .quad P2M(0x058),P2M(0x059),P2M(0x05a),P2M(0x05b),P2M(0x05c),P2M(0x05d),P2M(0x05e),P2M(0x05f) + .quad P2M(0x060),P2M(0x061),P2M(0x062),P2M(0x063),P2M(0x064),P2M(0x065),P2M(0x066),P2M(0x067) + .quad P2M(0x068),P2M(0x069),P2M(0x06a),P2M(0x06b),P2M(0x06c),P2M(0x06d),P2M(0x06e),P2M(0x06f) + .quad P2M(0x070),P2M(0x071),P2M(0x072),P2M(0x073),P2M(0x074),P2M(0x075),P2M(0x076),P2M(0x077) + .quad P2M(0x078),P2M(0x079),P2M(0x07a),P2M(0x07b),P2M(0x07c),P2M(0x07d),P2M(0x07e),P2M(0x07f) + .quad P2M(0x080),P2M(0x081),P2M(0x082),P2M(0x083),P2M(0x084),P2M(0x085),P2M(0x086),P2M(0x087) + .quad P2M(0x088),P2M(0x089),P2M(0x08a),P2M(0x08b),P2M(0x08c),P2M(0x08d),P2M(0x08e),P2M(0x08f) + .quad P2M(0x090),P2M(0x091),P2M(0x092),P2M(0x093),P2M(0x094),P2M(0x095),P2M(0x096),P2M(0x097) + .quad P2M(0x098),P2M(0x099),P2M(0x09a),P2M(0x09b),P2M(0x09c),P2M(0x09d),P2M(0x09e),P2M(0x09f) + .quad P2M(0x0a0),P2M(0x0a1),P2M(0x0a2),P2M(0x0a3),P2M(0x0a4),P2M(0x0a5),P2M(0x0a6),P2M(0x0a7) + .quad P2M(0x0a8),P2M(0x0a9),P2M(0x0aa),P2M(0x0ab),P2M(0x0ac),P2M(0x0ad),P2M(0x0ae),P2M(0x0af) + .quad P2M(0x0b0),P2M(0x0b1),P2M(0x0b2),P2M(0x0b3),P2M(0x0b4),P2M(0x0b5),P2M(0x0b6),P2M(0x0b7) + .quad P2M(0x0b8),P2M(0x0b9),P2M(0x0ba),P2M(0x0bb),P2M(0x0bc),P2M(0x0bd),P2M(0x0be),P2M(0x0bf) + .quad P2M(0x0c0),P2M(0x0c1),P2M(0x0c2),P2M(0x0c3),P2M(0x0c4),P2M(0x0c5),P2M(0x0c6),P2M(0x0c7) + .quad P2M(0x0c8),P2M(0x0c9),P2M(0x0ca),P2M(0x0cb),P2M(0x0cc),P2M(0x0cd),P2M(0x0ce),P2M(0x0cf) + .quad P2M(0x0d0),P2M(0x0d1),P2M(0x0d2),P2M(0x0d3),P2M(0x0d4),P2M(0x0d5),P2M(0x0d6),P2M(0x0d7) + .quad P2M(0x0d8),P2M(0x0d9),P2M(0x0da),P2M(0x0db),P2M(0x0dc),P2M(0x0dd),P2M(0x0de),P2M(0x0df) + .quad P2M(0x0e0),P2M(0x0e1),P2M(0x0e2),P2M(0x0e3),P2M(0x0e4),P2M(0x0e5),P2M(0x0e6),P2M(0x0e7) + .quad P2M(0x0e8),P2M(0x0e9),P2M(0x0ea),P2M(0x0eb),P2M(0x0ec),P2M(0x0ed),P2M(0x0ee),P2M(0x0ef) + .quad P2M(0x0f0),P2M(0x0f1),P2M(0x0f2),P2M(0x0f3),P2M(0x0f4),P2M(0x0f5),P2M(0x0f6),P2M(0x0f7) + .quad P2M(0x0f8),P2M(0x0f9),P2M(0x0fa),P2M(0x0fb),P2M(0x0fc),P2M(0x0fd),P2M(0x0fe),P2M(0x0ff) + .quad P2M(0x100),P2M(0x101),P2M(0x102),P2M(0x103),P2M(0x104),P2M(0x105),P2M(0x106),P2M(0x107) + .quad P2M(0x108),P2M(0x109),P2M(0x10a),P2M(0x10b),P2M(0x10c),P2M(0x10d),P2M(0x10e),P2M(0x10f) + .quad P2M(0x110),P2M(0x111),P2M(0x112),P2M(0x113),P2M(0x114),P2M(0x115),P2M(0x116),P2M(0x117) + .quad P2M(0x118),P2M(0x119),P2M(0x11a),P2M(0x11b),P2M(0x11c),P2M(0x11d),P2M(0x11e),P2M(0x11f) + .quad P2M(0x120),P2M(0x121),P2M(0x122),P2M(0x123),P2M(0x124),P2M(0x125),P2M(0x126),P2M(0x127) + .quad P2M(0x128),P2M(0x129),P2M(0x12a),P2M(0x12b),P2M(0x12c),P2M(0x12d),P2M(0x12e),P2M(0x12f) + .quad P2M(0x130),P2M(0x131),P2M(0x132),P2M(0x133),P2M(0x134),P2M(0x135),P2M(0x136),P2M(0x137) + .quad P2M(0x138),P2M(0x139),P2M(0x13a),P2M(0x13b),P2M(0x13c),P2M(0x13d),P2M(0x13e),P2M(0x13f) + .quad P2M(0x140),P2M(0x141),P2M(0x142),P2M(0x143),P2M(0x144),P2M(0x145),P2M(0x146),P2M(0x147) + .quad P2M(0x148),P2M(0x149),P2M(0x14a),P2M(0x14b),P2M(0x14c),P2M(0x14d),P2M(0x14e),P2M(0x14f) + .quad P2M(0x150),P2M(0x151),P2M(0x152),P2M(0x153),P2M(0x154),P2M(0x155),P2M(0x156),P2M(0x157) + .quad P2M(0x158),P2M(0x159),P2M(0x15a),P2M(0x15b),P2M(0x15c),P2M(0x15d),P2M(0x15e),P2M(0x15f) + .quad P2M(0x160),P2M(0x161),P2M(0x162),P2M(0x163),P2M(0x164),P2M(0x165),P2M(0x166),P2M(0x167) + .quad P2M(0x168),P2M(0x169),P2M(0x16a),P2M(0x16b),P2M(0x16c),P2M(0x16d),P2M(0x16e),P2M(0x16f) + .quad P2M(0x170),P2M(0x171),P2M(0x172),P2M(0x173),P2M(0x174),P2M(0x175),P2M(0x176),P2M(0x177) + .quad P2M(0x178),P2M(0x179),P2M(0x17a),P2M(0x17b),P2M(0x17c),P2M(0x17d),P2M(0x17e),P2M(0x17f) + .quad P2M(0x180),P2M(0x181),P2M(0x182),P2M(0x183),P2M(0x184),P2M(0x185),P2M(0x186),P2M(0x187) + .quad P2M(0x188),P2M(0x189),P2M(0x18a),P2M(0x18b),P2M(0x18c),P2M(0x18d),P2M(0x18e),P2M(0x18f) + .quad P2M(0x190),P2M(0x191),P2M(0x192),P2M(0x193),P2M(0x194),P2M(0x195),P2M(0x196),P2M(0x197) + .quad P2M(0x198),P2M(0x199),P2M(0x19a),P2M(0x19b),P2M(0x19c),P2M(0x19d),P2M(0x19e),P2M(0x19f) + .quad P2M(0x1a0),P2M(0x1a1),P2M(0x1a2),P2M(0x1a3),P2M(0x1a4),P2M(0x1a5),P2M(0x1a6),P2M(0x1a7) + .quad P2M(0x1a8),P2M(0x1a9),P2M(0x1aa),P2M(0x1ab),P2M(0x1ac),P2M(0x1ad),P2M(0x1ae),P2M(0x1af) + .quad P2M(0x1b0),P2M(0x1b1),P2M(0x1b2),P2M(0x1b3),P2M(0x1b4),P2M(0x1b5),P2M(0x1b6),P2M(0x1b7) + .quad P2M(0x1b8),P2M(0x1b9),P2M(0x1ba),P2M(0x1bb),P2M(0x1bc),P2M(0x1bd),P2M(0x1be),P2M(0x1bf) + .quad P2M(0x1c0),P2M(0x1c1),P2M(0x1c2),P2M(0x1c3),P2M(0x1c4),P2M(0x1c5),P2M(0x1c6),P2M(0x1c7) + .quad P2M(0x1c8),P2M(0x1c9),P2M(0x1ca),P2M(0x1cb),P2M(0x1cc),P2M(0x1cd),P2M(0x1ce),P2M(0x1cf) + .quad P2M(0x1d0),P2M(0x1d1),P2M(0x1d2),P2M(0x1d3),P2M(0x1d4),P2M(0x1d5),P2M(0x1d6),P2M(0x1d7) + .quad P2M(0x1d8),P2M(0x1d9),P2M(0x1da),P2M(0x1db),P2M(0x1dc),P2M(0x1dd),P2M(0x1de),P2M(0x1df) + .quad P2M(0x1e0),P2M(0x1e1),P2M(0x1e2),P2M(0x1e3),P2M(0x1e4),P2M(0x1e5),P2M(0x1e6),P2M(0x1e7) + .quad P2M(0x1e8),P2M(0x1e9),P2M(0x1ea),P2M(0x1eb),P2M(0x1ec),P2M(0x1ed),P2M(0x1ee),P2M(0x1ef) + .quad P2M(0x1f0),P2M(0x1f1),P2M(0x1f2),P2M(0x1f3),P2M(0x1f4),P2M(0x1f5),P2M(0x1f6),P2M(0x1f7) + .quad P2M(0x1f8),P2M(0x1f9),P2M(0x1fa),P2M(0x1fb),P2M(0x1fc),P2M(0x1fd),P2M(0x1fe),P2M(0x1ff) + +pml3: + .quad pml2 + 5 // PTE(pml2) +.align 4096 +pml4: + .quad pml3 + 5 // PTE(pml3) +#endif +#endif // someday diff --git a/src/arch/x86/lib/paging.S b/src/arch/x86/lib/paging.S new file mode 100644 index 0000000..71d3b36 --- /dev/null +++ b/src/arch/x86/lib/paging.S @@ -0,0 +1,58 @@ +#include <cpu/x86/cr.h> + + jmp code + +#include "pagetables.S" + +code: + movl $PageMapLevel2, %ecx /* load address of page directory */ + movl %ecx, %cr3 + jmp 1f +1: + movl %cr4, %edx + orl $CR4_PSE, %edx /* 4m pages */ + movl %edx, %cr4 + + movl %cr0, %edx + orl $CR0_PG, %edx + + movl $paging32, %ecx + movl %edx, %cr0 + jmp *%ecx + +/* if we get here, we're in paged 32-bit mode */ +paging32: +#if 0 // someday +#if CONFIG_ARCH_X86_64 + movl %cr4, %eax + andl $~Pse, %eax /* Page Size */ + orl $(Pge|Pae), %eax /* Page Global, Phys. Address */ + movl %eax, %cr4 + + movl $Efer, %ecx /* Extended Feature Enable */ + rdmsr + orl $Lme, %eax /* Long Mode Enable */ + wrmsr + + movl %cr0, %dx + andl $~(Cd|Nw|Ts|Mp), %edx + orl $(Pg|Wp), %edx /* Enable Paging */ + movl %edx, %cr0 + + jmp paging64 + +.code64 +paging64: + + movq gdt64, %RX + movl (%RX), %gdtr + + XORQ %edx, %edx + movw %edx, %ds /* not used in long mode */ + movw %edx, %es /* not used in long mode */ + movw %edx, %fs + movw %edx, %gs + movw %edx, %ss /* not used in long mode */ + +#endif +#endif //someday

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Patch set updated for coreboot: intel/sandybridge/gma: Add graphics PCI Device IDs 0x0162 and 0x0152
by Damien Zammit 13 Jul '15

13 Jul '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10896 -gerrit commit 24566490fc8ba2c22d9350ca6544dc1d255b8898 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Jul 13 16:10:52 2015 +1000 intel/sandybridge/gma: Add graphics PCI Device IDs 0x0162 and 0x0152 Change-Id: Ide0fd757cdd31a5b5ff184f7ab2d48e62ea50015 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/sandybridge/gma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 979d65a..c465694 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -651,7 +651,7 @@ static struct device_operations gma_func0_ops = { static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x0156, - 0x0166, + 0x0166, 0x0162, 0x0152, 0 }; static const struct pci_driver gma __pci_driver = {

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coreboot-gerrit July 2015