Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10884
-gerrit
commit 7890eeaf3e1c1d9208ec62724442887840467311
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Sat Jul 11 13:36:01 2015 -0500
timestamps: clarify in ramstage when not to reinit the cache
Commit bd1499d3 fixed a bug to not re-initialize the timestamp
cache in ramstage for EARLY_CBMEM_INIT. However, EARLY_CBMEM_INIT
was not included. Therefore, add this condition. This will result
in base_time being initialized to the passed in timestamp
for !EARLY_CBMEM_INIT platforms.
Change-Id: Ia1d744b3cfd28163f3339f2364efe59f7dcb719b
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/lib/timestamp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
index 7ead383..ca25093 100644
--- a/src/lib/timestamp.c
+++ b/src/lib/timestamp.c
@@ -202,7 +202,7 @@ void timestamp_init(uint64_t base)
/* In the EARLY_CBMEM_INIT case timestamps could have already been
* recovered. In those circumstances honor the cache which sits in BSS
* as it has already been initialized. */
- if (ENV_RAMSTAGE &&
+ if (ENV_RAMSTAGE && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) &&
ts_cache->cache_state != TIMESTAMP_CACHE_UNINITIALIZED)
return;
the following patch was just integrated into master:
commit 260a01f2cb025bcac6e4670be00ea29b95e53174
Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
Date: Sun Jul 12 11:49:16 2015 -0500
superio/smsc: Add support for SMSC DME1737
Change-Id: If2ba9ca48c809fe4f7dc0595a3cb3df168d630fd
Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
Reviewed-on: http://review.coreboot.org/10893
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/10893 for details.
-gerrit
the following patch was just integrated into master:
commit 8964717c4d9a7d0d74caa80f0147858adf87dea2
Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
Date: Sun Jul 12 11:47:56 2015 -0500
superio/smsc/dme1737: copy superio/smsc/lpc47b397
Change-Id: I3218bfaaa64bcad54fe97c6f887025356ccc9356
Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
Reviewed-on: http://review.coreboot.org/10892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/10892 for details.
-gerrit
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10904
-gerrit
commit ddfc47710ce13f133e7f5459114d023ced8c5457
Author: zbao <fishbaozi(a)gmail.com>
Date: Thu Jun 25 16:58:02 2015 -0400
AMD Merlin Falcon: Disable UMA if external graphics is used
For Carrizo, if the external is used as primary graphics, the
internal graphics can not be used. so we let the GFXUMA be
depended on ONBOARD_VGA_IS_PRIMARY.
Change-Id: If7031b74583a2b9805d16fcf669fe8be3b58ed40
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
src/mainboard/amd/bettong/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
index 1f2d888..7877499 100644
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
- select GFXUMA
+ select GFXUMA if ONBOARD_VGA_IS_PRIMARY
config MAINBOARD_DIR
string
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10903
-gerrit
commit 64e5246a3e53db0999b5cfd4a8510e65dc742092
Author: zbao <fishbaozi(a)gmail.com>
Date: Thu Jun 25 16:58:53 2015 -0400
x86 realmode: Setup the 8254 timer before running option rom
If the 8254 is not set up, the external graphics option rom
hangs and never returns.
The code is tested on AMD/bettong.
Change-Id: I0022de9d9a275a7d4b7a331ae7fcf793b9f4c5f5
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
src/device/oprom/realmode/x86.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c
index 14bcbc0..796c9fe 100644
--- a/src/device/oprom/realmode/x86.c
+++ b/src/device/oprom/realmode/x86.c
@@ -31,6 +31,7 @@
#include <device/pci_ids.h>
#include <lib/jpeg.h>
#include <pc80/i8259.h>
+#include <pc80/i8254.h>
#include <string.h>
#include <vbe.h>
@@ -326,6 +327,7 @@ void run_bios(struct device *dev, unsigned long addr)
* in some option roms.
*/
setup_i8259();
+ setup_i8254();
/* Set up some legacy information in the F segment */
setup_rombios();
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10902
-gerrit
commit 5213ec8e5f7d0c362e62f5708a7f117ae27bfded
Author: zbao <fishbaozi(a)gmail.com>
Date: Thu Jul 2 16:53:09 2015 -0400
AMD Merlin Falcon: Mask bit 31 of BIST while doing BIST check
This is a result of the Silcon Observation. On warm reset, the BIST
is 0x80000000, which causes BIST error. We skip checking this bit.
The update will be in CZ BKDG 1.05.
The code is tested on AMD/bettong.
Change-Id: I51c3f3567f758766079f7c8789f1ff072e1a7c53
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
src/mainboard/amd/bettong/romstage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 10813b3..a8a2777 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -48,7 +48,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
post_code(0x34);
- report_bist_failure(bist);
+ report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
/* Load MPB */
val = cpuid_eax(1);
the following patch was just integrated into master:
commit a9bc3bf59aaa24052f8d6e3827cdd901c85c7223
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Thu Jul 9 00:18:03 2015 +0200
tegra124/tegra210: Include stages.h in bootblock.c
Needed for the main() prototype
Change-Id: I921a77d8b131b751291d3a279b23ee18b13eca8d
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-on: http://review.coreboot.org/10862
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/10862 for details.
-gerrit
the following patch was just integrated into master:
commit 2687d934baa036c16d441375ff3a315a0803030e
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Thu Jul 9 00:17:02 2015 +0200
tegra210: Fix coding style in clock.c
Change-Id: I1a8ce0b8ec291a5ddd8fdefcda24842e2a3c692d
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-on: http://review.coreboot.org/10861
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/10861 for details.
-gerrit