coreboot-gerrit July 2015

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Patch merged into coreboot/master: fmap: Introduce new function to derive fmap name from offset/size
by gerrit＠coreboot.org 14 Jul '15

14 Jul '15

the following patch was just integrated into master: commit 995269062e631b83079c11bd91112fc0b71c523a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jul 9 11:27:44 2015 +0200 fmap: Introduce new function to derive fmap name from offset/size vboot passes around the offset and size of the region to use in later stages. To assign more meaning to this pair, provide a function that returns the fmap area name if there's a precise match (and an error otherwise). Change-Id: I5724b860271025c8cb8b390ecbd33352ea779660 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10865 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10865 for details. -gerrit

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Patch merged into coreboot/master: getac/p470: initialize timestamps in romstage
by gerrit＠coreboot.org 14 Jul '15

14 Jul '15

the following patch was just integrated into master: commit ad0dda767b9fc1357450e4de04bdf276c7bb40f1 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 13 19:25:01 2015 +0200 getac/p470: initialize timestamps in romstage Change-Id: I2f43684bbdd48f30039fe09275043ddf203d447c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10907 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10907 for details. -gerrit

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Patch set updated for coreboot: how many K8_REV_F boards with MEM_TRAIN_SEQ==1 are broken?
by Jonathan A. Kollasch 14 Jul '15

14 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10916 -gerrit commit 981b2ac10ef88b921e91dda2fdd1669fcc642b55 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Jul 14 08:20:18 2015 -0500 how many K8_REV_F boards with MEM_TRAIN_SEQ==1 are broken? Change-Id: Ib973650f860e8ebf45157b4607780988cbf5647f Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/northbridge/amd/amdk8/raminit_f_dqs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index ee3b609..d5b6bd1 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -2074,6 +2074,7 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 +#error this board is broken when multiple sockets populated struct sys_info *sysinfox = (void *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); wait_till_sysinfo_in_ram(); // use pci to get it

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New patch to review for coreboot: how many K8_REV_F boards with MEM_TRAIN_SEQ==1 are broken?
by Jonathan A. Kollasch 14 Jul '15

14 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10916 -gerrit commit cfcf229b6111fd605e019fc9c01d47c9933cd2bd Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Jul 14 08:20:18 2015 -0500 how many K8_REV_F boards with MEM_TRAIN_SEQ==1 are broken? Change-Id: Ib973650f860e8ebf45157b4607780988cbf5647f Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/cpu/amd/model_fxx/model_fxx_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index a6561ee..48a03d1 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -33,6 +33,7 @@ void cpus_ready_for_init(void) { #if CONFIG_K8_REV_F_SUPPORT #if CONFIG_MEM_TRAIN_SEQ == 1 +#error this board is broken when multiple sockets populated struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox);

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New patch to review for coreboot: [Not For Merge] K8 northbridge: validate CONFIG_CDB value
by Jonathan A. Kollasch 14 Jul '15

14 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10915 -gerrit commit a70caf9603047b071969e76f04168c1db42ada10 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Jul 14 07:59:45 2015 -0500 [Not For Merge] K8 northbridge: validate CONFIG_CDB value Change-Id: Iecdb3891997149b2c76763214967b49c7bdf7104 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/northbridge/amd/amdk8/northbridge.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c4fd3fd..2514143 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -207,6 +207,10 @@ static void amdk8_scan_chain(struct bus *link) sysconf.hcdn_reg[index] = link->hcdn_reg; } +#if CONFIG_CDB != 0x18 +#error CONFIG_CDB is not 0x18 +#endif + /* Do sb ht chain at first, in case s2885 put sb chain * (8131/8111) on link2, but put 8151 on link0. */

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Patch merged into coreboot/master: azalia: fix up and clean up shrinkage of boilerplate code
by gerrit＠coreboot.org 14 Jul '15

14 Jul '15

the following patch was just integrated into master: commit ec505ad21c923c114a16b2710a0113f657765430 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Jul 7 12:57:46 2015 -0500 azalia: fix up and clean up shrinkage of boilerplate code Should fix regression in HDA verb setup on nvidia mcp55 and intel sch southbridges. The mcp55 code could not find the mainboard's verb table because the table was not even being compiled in. The sch boards appeared to have the same issue. Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate shrink, so apply it to those too. Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078 (azalia: Shrink boilerplate) Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/10826 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10826 for details. -gerrit

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Patch merged into coreboot/master: amd/rs780: Fix typo
by gerrit＠coreboot.org 14 Jul '15

14 Jul '15

the following patch was just integrated into master: commit fb4233bb22602c3802da39200b85845407e0c496 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jul 14 10:11:49 2015 +0200 amd/rs780: Fix typo Change-Id: I08f7251f8fc42b9028b1fdb830546f9922ef43aa Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: YongGon Kim <ilios86(a)gmail.com> Reviewed-on: http://review.coreboot.org/10914 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> See http://review.coreboot.org/10914 for details. -gerrit

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Patch merged into coreboot/master: cbmem: convert x86 timestamps on OpenBSD
by gerrit＠coreboot.org 14 Jul '15

14 Jul '15

the following patch was just integrated into master: commit d00f180812279144ce09e2ad046973f3a384456c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Jul 13 16:53:50 2015 +0200 cbmem: convert x86 timestamps on OpenBSD Change-Id: I16bfe42a00d73209307655601edaa3a8ffc9c902 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10905 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10905 for details. -gerrit

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Patch merged into coreboot/master: intel/sandybridge/gma: Add graphics PCI Device IDs 0x0162 and 0x0152
by gerrit＠coreboot.org 14 Jul '15

14 Jul '15

the following patch was just integrated into master: commit 3162a1db7a723f3fb2c598386d85abbc1c04e5f9 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Jul 13 16:10:52 2015 +1000 intel/sandybridge/gma: Add graphics PCI Device IDs 0x0162 and 0x0152 Change-Id: Ide0fd757cdd31a5b5ff184f7ab2d48e62ea50015 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: http://review.coreboot.org/10896 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10896 for details. -gerrit

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New patch to review for coreboot: amd/rs780: Fix typo
by Patrick Georgi 14 Jul '15

14 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10914 -gerrit commit 9835e0eb361ecbb9ad6e51b97ebed9932e1e02a1 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jul 14 10:11:49 2015 +0200 amd/rs780: Fix typo Change-Id: I08f7251f8fc42b9028b1fdb830546f9922ef43aa Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: YongGon Kim <ilios86(a)gmail.com> --- src/southbridge/amd/rs780/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc index 1a8a17a..b02f45b 100644 --- a/src/southbridge/amd/rs780/Makefile.inc +++ b/src/southbridge/amd/rs780/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS790),y) +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS780),y) ramstage-y += rs780.c ramstage-y += cmn.c

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coreboot-gerrit July 2015