coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: Braswell: Add dummy microcode terminator
by Leroy P Leahy 13 Jul '15

13 Jul '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10911 -gerrit commit a6162dac13be26e405b0e32555822954beaba662 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 13 15:44:53 2015 -0700 Braswell: Add dummy microcode terminator Prevent duplication of the dummy microcode terminator by moving it from the microcode_blob.h file into the microcode_blob.c file. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I2109502cacac6bc73b53a823479ac20431726bfd Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/braswell/microcode/microcode_blob.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c index e0aeaff..a6e8ae6 100644 --- a/src/soc/intel/braswell/microcode/microcode_blob.c +++ b/src/soc/intel/braswell/microcode/microcode_blob.c @@ -19,4 +19,10 @@ unsigned microcode[] = { #include <microcode/microcode_blob.h> + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };

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New patch to review for coreboot: amd/model_fxx rev.F: emit P-states when no intermediates exist
by Jonathan A. Kollasch 13 Jul '15

13 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10910 -gerrit commit e793719ea6206d28132f1bafa5c7795ab9e1c65f Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 13 17:05:07 2015 -0500 amd/model_fxx rev.F: emit P-states when no intermediates exist Relevant for systems having processors that only have two (the minimum and maximum) P-states, such as the Opteron 2210 at 1.0 and 1.8GHz. Change-Id: Ic66fe6d10ce495c1bf21796cb7e1eb4e11e85283 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/cpu/amd/model_fxx/powernow_acpi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index f2aa596..ac505ee 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -194,11 +194,6 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) else PstateStep_coef = 2; - if (IntPstateSup == 0) { - printk(BIOS_INFO, "No intermediate P-states are supported\n"); - goto write_pstates; - } - /* Get the multiplier of the fid frequency */ /* * Fid multiplier is always 100 revF and revG. @@ -233,6 +228,11 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) Pstate_num++; } + if (IntPstateSup == 0) { + printk(BIOS_SPEW, "No intermediate P-states are supported\n"); + goto nointpstatesup; + } + Cur_feq = Max_feq; Cur_fid = Max_fid; /* Construct P1 state */ @@ -313,6 +313,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) Pstate_num++; } +nointpstatesup: /* Construct P[Min] State */ if (Max_fid == 0x2A && Max_vid != 0x0) { Pstate_fid[Pstate_num] = 0x2;

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New patch to review for coreboot: release: add release script
by Patrick Georgi 13 Jul '15

13 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10909 -gerrit commit ee0575fd7083dab78666dabb76caade8e0d0f507 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 13 22:48:46 2015 +0200 release: add release script Change-Id: Ib3cd29cf1875e7ad182262d7caa33ff35f28aa85 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/release/build-release | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/util/release/build-release b/util/release/build-release new file mode 100755 index 0000000..ae00dbf --- /dev/null +++ b/util/release/build-release @@ -0,0 +1,16 @@ +#!/bin/bash +# $1: new version name +set -e +if [ -z "$1" ]; then + echo "usage: $0 version" + echo "tags a new coreboot version and creates a tar archive" + exit 1 +fi +git clone --recurse-submodules http://review.coreboot.org/coreboot.git coreboot-$1 +cd coreboot-$1 +git submodule update --init --checkout +git tag -a --force $1 -m "coreboot version $1" +printf "$1-$(git log --pretty=%H|head -1)\n" > .coreboot-version +cd .. +tar --exclude-vcs --exclude=coreboot-${1}/3rdparty/blobs -cvf - coreboot-${1} |xz -9 > coreboot-${1}.tar.xz +tar --exclude-vcs -cvf - coreboot-${1}/3rdparty/blobs |xz -9 > coreboot-blobs-${1}.tar.xz

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Patch merged into coreboot/master: x86: flatten hierarchy
by gerrit＠coreboot.org 13 Jul '15

13 Jul '15

the following patch was just integrated into master: commit 6cb3a59fd5e754c3627b79db21c5bcc284bfd721 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Jul 13 09:39:15 2015 +0200 x86: flatten hierarchy It never made sense to have bootblock_* in init, but pirq_routing.c in boot, and some ld scripts on the main level while others live in subdirectories. This patch flattens the directory hierarchy and makes x86 more similar to the other architectures. Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10901 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/10901 for details. -gerrit

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Patch merged into coreboot/master: x86: Port x86 over to compile cleanly with x86-64
by gerrit＠coreboot.org 13 Jul '15

13 Jul '15

the following patch was just integrated into master: commit 9693885ad88d21ead7bd9ebc32f3e4901841b18b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:23:48 2015 -0700 x86: Port x86 over to compile cleanly with x86-64 Change-Id: I26f1bbf027435be593f11bce4780111dcaf7cb86 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10586 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/10586 for details. -gerrit

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Patch merged into coreboot/master: version: allow stating the coreboot revision in .coreboot-version
by gerrit＠coreboot.org 13 Jul '15

13 Jul '15

the following patch was just integrated into master: commit 492a07593b3d74d4b10fce95e5229cbd4535b1cb Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 13 20:43:28 2015 +0200 version: allow stating the coreboot revision in .coreboot-version If .git doesn't exist, try to fetch the coreboot version from a file, before falling back to a hard-code. Change-Id: Idee8019c9a2b766fe69535367614c5254498335a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10908 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10908 for details. -gerrit

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New patch to review for coreboot: version: allow stating the coreboot revision in .coreboot-version
by Patrick Georgi 13 Jul '15

13 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10908 -gerrit commit 9d34d1f3f426cd2abb32893c12f3b3548b30d02a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 13 20:43:28 2015 +0200 version: allow stating the coreboot revision in .coreboot-version If .git doesn't exist, try to fetch the coreboot version from a file, before falling back to a hard-code. Change-Id: Idee8019c9a2b766fe69535367614c5254498335a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- .gitignore | 1 + Makefile.inc | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index f7447b4..770a62d 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ .config .config.old +.coreboot-version .xcompile .ccwrap build/ diff --git a/Makefile.inc b/Makefile.inc index 3995fbc..347e07b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -23,7 +23,9 @@ GIT:=$(shell [ -d "$(top)/.git" ] && command -v git) # misleadingly named, this is the coreboot version export KERNELVERSION := $(strip $(if $(GIT),\ $(shell git describe --dirty --always || git describe),\ - 4.0$(KERNELREVISION))) + $(if $(wildcard $(top)/.coreboot-version),\ + $(shell cat $(top)/.coreboot-version),\ + coreboot-unknown$(KERNELREVISION)))) ####################################################################### # Basic component discovery

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New patch to review for coreboot: getac/p470: initialize timestamps in romstage
by Patrick Georgi 13 Jul '15

13 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10907 -gerrit commit a0bafb9ad6e019cee866231838c2e1ea1dd6dfb4 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 13 19:25:01 2015 +0200 getac/p470: initialize timestamps in romstage Change-Id: I2f43684bbdd48f30039fe09275043ddf203d447c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/getac/p470/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 6205aed..22a14c2 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -34,6 +34,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <timestamp.h> #include "option_table.h" void setup_ich7_gpios(void) @@ -267,6 +268,9 @@ void main(unsigned long bist) { int s3resume = 0; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + if (bist == 0) enable_lapic();

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New patch to review for coreboot: winent/mb6047: move power_on_after_fail out of RTC century byte
by Jonathan A. Kollasch 13 Jul '15

13 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10906 -gerrit commit 8299aecb37f1f0ece8b2d10eb21d54da9efaa493 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 13 10:39:44 2015 -0500 winent/mb6047: move power_on_after_fail out of RTC century byte Change-Id: I3cf6a579f4e62a59828e81aa63c3a1a020a15ea6 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/winent/mb6047/cmos.layout | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/winent/mb6047/cmos.layout b/src/mainboard/winent/mb6047/cmos.layout index 85fa992..affac0a 100644 --- a/src/mainboard/winent/mb6047/cmos.layout +++ b/src/mainboard/winent/mb6047/cmos.layout @@ -9,7 +9,8 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +400 8 h 0 century +408 1 e 1 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi

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Patch set updated for coreboot: cbmem: export base_time in timestamp table
by Aaron Durbin 13 Jul '15

13 Jul '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10883 -gerrit commit 72c643d0963454c22022307bf89d53ae25bd4877 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Jul 11 12:44:10 2015 -0500 cbmem: export base_time in timestamp table It's helpful to know the base_time (1st timestamp) in the timestamp table because it provides more information like the accumulated time before the first timestamp was recorded. In order to maximize this information report the base time as an entry that is printed. It's called '1st timestamp'. The implementation turns all the timestamp entries into absolute times so one can observe both absolute and relative time for each marker. Change-Id: I1334a2d980e3bcc2968a3bd6493c68b9efcca7ae Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbmem/cbmem.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 3bc0fcd..80bf673 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -396,6 +396,8 @@ static const struct timestamp_id_to_name { u32 id; const char *name; } timestamp_ids[] = { + /* Marker to report base_time. */ + { 0, "1st timestamp" }, { TS_START_ROMSTAGE, "start of rom stage" }, { TS_BEFORE_INITRAM, "before ram initialization" }, { TS_AFTER_INITRAM, "after ram initialization" }, @@ -487,6 +489,7 @@ static void dump_timestamps(void) int i; struct timestamp_table *tst_p; size_t size; + uint64_t prev_stamp; if (timestamps.tag != LB_TAG_TIMESTAMPS) { fprintf(stderr, "No timestamps found in coreboot table.\n"); @@ -502,10 +505,19 @@ static void dump_timestamps(void) unmap_memory(); tst_p = map_memory_size((unsigned long)timestamps.cbmem_addr, size); + /* Report the base time within the table. */ + prev_stamp = 0; + timestamp_print_entry(0, tst_p->base_time, prev_stamp); + prev_stamp = tst_p->base_time; + for (i = 0; i < tst_p->num_entries; i++) { - const struct timestamp_entry *tse_p = tst_p->entries + i; - timestamp_print_entry(tse_p->entry_id, tse_p->entry_stamp, - i ? tse_p[-1].entry_stamp : 0); + uint64_t stamp; + const struct timestamp_entry *tse = &tst_p->entries[i]; + + /* Make all timestamps absolute. */ + stamp = tse->entry_stamp + tst_p->base_time; + timestamp_print_entry(tse->entry_id, stamp, prev_stamp); + prev_stamp = stamp; } unmap_memory();

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coreboot-gerrit July 2015