coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

New patch to review for coreboot: intel raminit: fix timB high adjust calculation
by Patrick Rudolph 12 Jul '15

12 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10889 -gerrit commit d12f201508f2b1fa690f0a297440190b9aeb4830 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jul 12 12:17:21 2015 +0200 intel raminit: fix timB high adjust calculation Issue observed: Any memory DIMM placed in channel0 slots stops at "c320c discovery failed". The same memory DIMM works when placed in channel1 slots. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMMs: * elixir 1GB 1Rx8 PC3-10600U M2Y1G64CB88A5N * crucial 2GB 256Mx64 CT2566aBA160BJ * corsair 8GB CMZ16GX3M2A1866C9 Problem description: In case of good timmings (all bits are set) an offset of 3*64 was applied. The following test (c320c discovery) failed only on those byte-lanes. Adding an offset of zero resolves this issue. The system boots with every DIMM tested placed in Channel0 slots. Simplified the remaining code to allow more offsets to be returned. Change-Id: Iea426ea4470640ce254f16e958a395644ff1a55c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 29 +++++++++++++--------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 0c98b7a..dc3168c 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -2283,18 +2283,23 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) static int get_timB_high_adjust(u64 val) { int i; - if (val >= 0xfffffffffffff000LL) - return 3; - if (val >= 0xfffffffffff00000LL) - return -1; - if (val >= 0xfffffff000000000LL) - return -2; - if (val >= 0xfff0000000000000LL) - return -3; - - for (i = 0; i < 8; i++) - if (val >> (8 * (7 - i) + 4)) - return i; + + /* good */ + if (val == 0xffffffffffffffffLL) + return 0; + + if (val >= 0xf000000000000000LL) { + /* needs negative adjustment */ + for (i = 0; i < 8; i++) + if (val << (8 * (7 - i) + 4)) + return -i; + } else { + /* needs positive adjustment */ + for (i = 0; i < 8; i++) + if (val >> (8 * (7 - i) + 4)) + return i; + } + return 8; }

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New patch to review for coreboot: intel raminit: whitespace fixes and improved logging
by Patrick Rudolph 12 Jul '15

12 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10888 -gerrit commit 0c082fe80e440cd552e1097f4614a03958499892 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jul 12 11:39:45 2015 +0200 intel raminit: whitespace fixes and improved logging Remove whitespace errors and print the unmodified timB value, too. Change-Id: If69244a5d47424e3e984fdf782ea9d2d3c466d86 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 25 +++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 3740a02..0c98b7a 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -2300,7 +2300,7 @@ static int get_timB_high_adjust(u64 val) static void adjust_high_timB(ramctr_timing * ctrl) { - int channel, slotrank, lane; + int channel, slotrank, lane, old; write32(DEFAULT_MCHBAR + 0x3400, 0x200); FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); @@ -2370,17 +2370,18 @@ static void adjust_high_timB(ramctr_timing * ctrl) wait_428c(channel); FOR_ALL_LANES { u64 res = - read32(DEFAULT_MCHBAR + lane_registers[lane] + - 0x100 * channel + 4); - res |= - ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] + - 0x100 * channel + 8)) << 32; - ctrl->timings[channel][slotrank].lanes[lane].timB += - get_timB_high_adjust(res) * 64; - - printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x\n", channel, - slotrank, lane, + read32(DEFAULT_MCHBAR + lane_registers[lane] + + 0x100 * channel + 4); + res |= + ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] + + 0x100 * channel + 8)) << 32; + old = ctrl->timings[channel][slotrank].lanes[lane].timB; + ctrl->timings[channel][slotrank].lanes[lane].timB += + get_timB_high_adjust(res) * 64; + + printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res); + printram("Bval+: %d, %d, %d, %x -> %x\n", channel, + slotrank, lane, old, ctrl->timings[channel][slotrank].lanes[lane]. timB); }

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Patch set updated for coreboot: intel sandybridge: add VGA pci device id
by Patrick Rudolph 12 Jul '15

12 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10798 -gerrit commit ddc5f55052c0b46848c93d0c37bd1da4203d3372 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jul 5 13:29:41 2015 +0200 intel sandybridge: add VGA pci device id Add VGA pci device id 0x0152 for Intel IvyBridge CPUs. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H Change-Id: Ia546fdf0cc3bbd4c0ef6b5fd969232f105bceb22 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/early_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 21ef223..e77cf22 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -96,6 +96,7 @@ static void sandybridge_setup_graphics(void) case 0x0116: /* GT2 Mobile */ case 0x0122: /* GT2 Desktop >=1.3GHz */ case 0x0126: /* GT2 Mobile >=1.3GHz */ + case 0x0152: /* IvyBridge */ case 0x0156: /* IvyBridge */ case 0x0162: /* IvyBridge */ case 0x0166: /* IvyBridge */

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Patch merged into coreboot/master: amd/.../hudson: Warn if HUDSON_FWM_POSITION is not inside CBFS
by gerrit＠coreboot.org 11 Jul '15

11 Jul '15

the following patch was just integrated into master: commit d139c48a23cd308caef4e79aeedd03f6392d6847 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 28 14:12:29 2015 -0600 amd/.../hudson: Warn if HUDSON_FWM_POSITION is not inside CBFS Display a warning if CONFIG_HUDSON_FWM_POSITION is not inside CBFS. This can be extended to other Kconfig values for CBFS. Change-Id: I2423f7b361dda8aac5dab409fa7b656de486f635 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10683 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10683 for details. -gerrit

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Patch merged into coreboot/master: Calculate HUDSON_FWM_POSITION and display warning on mismatch
by gerrit＠coreboot.org 11 Jul '15

11 Jul '15

the following patch was just integrated into master: commit d12d65fc54c31ee2635c0249a1d92c2e70bc1498 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 28 14:06:23 2015 -0600 Calculate HUDSON_FWM_POSITION and display warning on mismatch This patch calculates the address where the chipset firmware descriptor should be located and compares it against the actual value from Kconfig. If the two don't match, it puts up a warning. This could probably replace the config variable completely, but I wanted to see how other people felt before doing that. I seem to recall that the value used to be calculated, so I figure that there must be a reason it's done this way at this point. If we do want to keep the Kconfig setting, this patch could also be modified to just verify that the HUDSON_FWM_POSITION is inside the ROM space. Change-Id: I94addf463e2c694a94eef218ec855103a3bb5da5 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10682 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10682 for details. -gerrit

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Patch merged into coreboot/master: arch/x86/Makefile.inc: Calculate CBFS_BASE_ADDRESS variable
by gerrit＠coreboot.org 11 Jul '15

11 Jul '15

the following patch was just integrated into master: commit 16bc7e82d8ec9f27955c2291c8ab1dd638a5ca33 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 28 13:49:16 2015 -0600 arch/x86/Makefile.inc: Calculate CBFS_BASE_ADDRESS variable The CBFS_BASE_ADDRESS can be compared against values used with cbfstool to generate warnings. This can help cut down on mistakes and debug time. Change-Id: I149007dd637661f799a0f2cdb079d11df726ca86 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10681 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10681 for details. -gerrit

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Patch merged into coreboot/master: Makefile.inc: Add math macros
by gerrit＠coreboot.org 11 Jul '15

11 Jul '15

the following patch was just integrated into master: commit 47abc54ec3eea1a660cfbe3bb935ef6d3ace9de0 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jul 3 12:54:14 2015 -0600 Makefile.inc: Add math macros Add macros to standardize math done in the Makefiles in a posix compliant manner. int-multiply takes an arbitrary list of values to multiply, the same as the int-addition macro. The other macros only work on two values at a time. Change-Id: I3b754b9bcde26f33edc4f945d5af3d5444f383c7 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10874 for details. -gerrit

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New patch to review for coreboot: x86emu/debug.h: remove #ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVEL
by Martin Roth 11 Jul '15

11 Jul '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10887 -gerrit commit c53b27327be88ddaa8e496b78e39afaec9d8f287 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jul 11 14:01:12 2015 -0600 x86emu/debug.h: remove #ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVEL This protection didn't make sense to me - it seems like things would probably break if printf wasn't defined anyway. Change-Id: Ifb6bad46e193b35c13b7ad4946511fec74beff92 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/device/oprom/x86emu/debug.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/device/oprom/x86emu/debug.h b/src/device/oprom/x86emu/debug.h index 6858f15..186c161 100644 --- a/src/device/oprom/x86emu/debug.h +++ b/src/device/oprom/x86emu/debug.h @@ -42,10 +42,8 @@ /*---------------------- Macros and type definitions ----------------------*/ -#ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVEL /* printf is not available in coreboot... use printk */ #define printf(x...) printk(BIOS_DEBUG, x) -#endif /* checks to be enabled for "runtime" */

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New patch to review for coreboot: Verify Kconfigs symbols are not zero for hex and int type symbols
by Martin Roth 11 Jul '15

11 Jul '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10886 -gerrit commit 1d207852f4c03277b39ee014d7f6dd2534507440 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jul 11 13:56:58 2015 -0600 Verify Kconfigs symbols are not zero for hex and int type symbols For hex and int type kconfig symbols, IS_ENABLED() doesn't work. Instead check to make sure they're defined and not zero. In some cases, zero might be a valid value, but it didn't look like zero was valid in these cases. Change-Id: Ib51fb31b3babffbf25ed3ae4ed11a2dc9a4be709 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/cpu/x86/mtrr/earlymtrr.c | 2 +- src/drivers/elog/boot_count.c | 4 ++-- src/include/cpu/x86/mtrr.h | 4 ++-- src/include/pc80/mc146818rtc.h | 4 ++-- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 4 +--- 5 files changed, 8 insertions(+), 10 deletions(-) diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 3db676b..9561d8d 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -50,7 +50,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) wrmsr(msr_nr, msr); } -#if defined(CONFIG_XIP_ROM_SIZE) +#if defined(CONFIG_XIP_ROM_SIZE) && CONFIG_XIP_ROM_SIZE /* enable write through caching so we can do execute in place * on the flash rom. * Determine address by calculating the XIP_ROM_SIZE sized area with diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index 0b5c402..e853e36 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -34,10 +34,10 @@ # include "option_table.h" # define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3) #else -# if defined(CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET) +# if defined(CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET) && CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET # define BOOT_COUNT_CMOS_OFFSET CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET # else -# error "Must define CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET" +# error "Must configure CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET" # endif #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 86ce57b..bd0b603 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -87,8 +87,8 @@ void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type); (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) -#if !defined(CONFIG_RAMTOP) -# error "CONFIG_RAMTOP not defined" +#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP +# error "CONFIG_RAMTOP not configured" #endif #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index c74af66..0e15273 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -186,10 +186,10 @@ unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); # include "option_table.h" # define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3) #else -# if defined(CONFIG_CMOS_POST_OFFSET) +# if defined(CONFIG_CMOS_POST_OFFSET) && CONFIG_CMOS_POST_OFFSET # define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET # else -# error "Must define CONFIG_CMOS_POST_OFFSET" +# error "Must configure CONFIG_CMOS_POST_OFFSET" # endif #endif diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index ce73894..6006e67 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -179,12 +179,10 @@ Method(_INI, 0) { /* Determine the OS we're running on */ OSFL() -#ifdef CONFIG_HUDSON_IMC_FWM -#if CONFIG_HUDSON_IMC_FWM +#if defined(CONFIG_HUDSON_IMC_FWM) && CONFIG_HUDSON_IMC_FWM #include "acpi/AmdImc.asl" /* Hudson IMC function */ ITZE() /* enable IMC Fan Control*/ #endif -#endif } /* End Method(_SB._INI) */ Method(OSFL, 0){

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New patch to review for coreboot: Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()
by Martin Roth 11 Jul '15

11 Jul '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10885 -gerrit commit ad13d86711020b75101959c3cd0cd2169801e82c Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jul 11 13:42:54 2015 -0600 Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED() Kconfigs symbols of type bool are always defined, and can be tested with the IS_ENABLED() macro. symbol type except string. Change-Id: Ic4ba79f519ee2a53d39c10859bbfa9c32015b19d Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/arch/arm64/armv8/bootblock_simple.c | 2 +- src/arch/riscv/bootblock_simple.c | 2 +- src/cpu/x86/mtrr/earlymtrr.c | 2 +- src/include/device/dram/ddr3.h | 2 +- src/include/device/early_smbus.h | 2 +- src/lib/ramstage.ld | 2 +- src/lib/rmodule.ld | 2 +- src/northbridge/intel/haswell/gma.c | 2 +- src/soc/broadcom/cygnus/ddr_init.c | 38 +++++++++++++++---------------- src/soc/broadcom/cygnus/ddr_init_table.c | 2 +- src/southbridge/intel/i82801ix/i82801ix.h | 2 +- 11 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/arch/arm64/armv8/bootblock_simple.c b/src/arch/arm64/armv8/bootblock_simple.c index 5e00890..6cb55e6 100644 --- a/src/arch/arm64/armv8/bootblock_simple.c +++ b/src/arch/arm64/armv8/bootblock_simple.c @@ -55,7 +55,7 @@ void main(void) //bootblock_mainboard_init(); } -#ifdef CONFIG_BOOTBLOCK_CONSOLE +#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE) console_init(); exception_init(); #endif diff --git a/src/arch/riscv/bootblock_simple.c b/src/arch/riscv/bootblock_simple.c index 50cd90d..a10cdaf 100644 --- a/src/arch/riscv/bootblock_simple.c +++ b/src/arch/riscv/bootblock_simple.c @@ -56,7 +56,7 @@ void main(void) //bootblock_mainboard_init(); } -#ifdef CONFIG_BOOTBLOCK_CONSOLE +#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE) console_init(); exception_init(); #endif diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 0471a9e..3db676b 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -19,7 +19,7 @@ void set_var_mtrr( wrmsr(MTRRphysMask_MSR(reg), maskm); } -#if !defined(CONFIG_CACHE_AS_RAM) || !CONFIG_CACHE_AS_RAM +#if !IS_ENABLED(CONFIG_CACHE_AS_RAM) static void cache_ramstage(void) { /* Enable caching for lower 1MB and ram stage using variable mtrr */ diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 295ea25..7f969b3 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -55,7 +55,7 @@ * disabled. * @{ */ -#if defined(CONFIG_DEBUG_RAM_SETUP) && (CONFIG_DEBUG_RAM_SETUP) +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) #else #define printram(x, ...) diff --git a/src/include/device/early_smbus.h b/src/include/device/early_smbus.h index 437a569..1da3f07 100644 --- a/src/include/device/early_smbus.h +++ b/src/include/device/early_smbus.h @@ -55,7 +55,7 @@ /** * \brief printk macro for SMBus debugging */ -#if defined(CONFIG_DEBUG_SMBUS) && (CONFIG_DEBUG_SMBUS) +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) #define printsmbus(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) #else #define printsmbus(x, ...) diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld index 402f495..432df40 100644 --- a/src/lib/ramstage.ld +++ b/src/lib/ramstage.ld @@ -34,7 +34,7 @@ _etext = .; } : to_load -#ifdef CONFIG_COVERAGE +#if IS_ENABLED(CONFIG_COVERAGE) .ctors : { . = ALIGN(0x100); __CTOR_LIST__ = .; diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 0e9c880..e6b4da7 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -30,7 +30,7 @@ SECTIONS /* C read-only data. */ . = ALIGN(16); -#ifdef CONFIG_COVERAGE +#if IS_ENABLED(CONFIG_COVERAGE) __CTOR_LIST__ = .; *(.ctors); LONG(0); diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 21a285c..3c50a17 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -460,7 +460,7 @@ static void gma_func0_init(struct device *dev) dp.panel_power_up_delay = conf->gpu_panel_power_up_delay; dp.panel_power_cycle_delay = conf->gpu_panel_power_cycle_delay; -#ifdef CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) init_fb = developer_mode_enabled() || recovery_mode_enabled(); #endif lightup_ok = panel_lightup(&dp, init_fb); diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index a8369ec..f885cec 100755 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -45,7 +45,7 @@ extern unsigned int ddr3_init_tab_1066[]; #define CONFIG_DRAM_FREQ 667 extern unsigned int ddr3_init_tab_1333[]; #endif -#ifdef CONFIG_CYGNUS_DDR800 +#if IS_ENABLED(CONFIG_CYGNUS_DDR800) #define CONFIG_DRAM_FREQ 800 extern unsigned int ddr3_init_tab_1600[]; #endif @@ -64,7 +64,7 @@ int cygnus_phy_powerup(void); void ddr_init2(void); void PRE_SRX(void); -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) void PRE_SRX(void) { uint32_t readvalue = 0; @@ -281,7 +281,7 @@ void iproc_clear_ecc_syndrome(void) } #endif -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit) { uint32_t ndiv, mdiv, pdiv, ddrclk, data; @@ -306,7 +306,7 @@ uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit) #endif -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) int cygnus_phy_powerup(void) { @@ -1187,7 +1187,7 @@ static int clear_ddr(uint32_t offset, uint32_t size) extern void restore_shmoo_config(and28_shmoo_config_param_t *shmoo_control_para); #endif -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) static int simple_ddr_crc32_check(void) { return 0; @@ -1226,7 +1226,7 @@ void ddr_init2(void) uint32_t status, sku_id, ddr_clk, dev_id = 0; uint32_t unit = 0; uint32_t skip_shmoo = 0; -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) uint32_t pwrctli0 = reg32_read((volatile uint32_t *)IHOST_SCU_POWER_STATUS) & 0x3; skip_shmoo = reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG) & 0x1; @@ -1239,22 +1239,22 @@ void ddr_init2(void) skip_shmoo = 1; reg32_write((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL, reg32_read((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL)| 0x1); } -#endif /* defined(CONFIG_SOC_BROADCOM_CYGNUS) */ +#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */ dev_id = dev_id; -#ifdef CONFIG_SOC_BROADCOM_CYGNUS +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) and28_shmoo_dram_info_t sdi; and28_shmoo_config_param_t config_param; #endif -#ifndef CONFIG_SOC_BROADCOM_CYGNUS +#if !IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) dev_id = (reg32_read((volatile uint32_t *)ChipcommonA_ChipID)) & 0x0000ffff; #else dev_id = 0x5800; cygnus_phy_powerup(); #endif -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 8) & 0x0f; #else sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 2) & 0x03; @@ -1279,7 +1279,7 @@ void ddr_init2(void) goto done; } printk(BIOS_INFO, "DDR type: DDR%d\n", (ddr_type == 1)? 3 : 4); -#elif defined(CONFIG_SOC_BROADCOM_CYGNUS) +#elif IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) ddr_type = 1; #else ddr_type = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x1; @@ -1337,7 +1337,7 @@ void ddr_init2(void) } #endif /* defined(CONFIG_IPROC_P7) */ -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) /* Get the DDR S1 and S2 out of reset */ reg32_write((volatile uint32_t *)DDR_S1_IDM_RESET_CONTROL, 0); reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0); @@ -1357,7 +1357,7 @@ void ddr_init2(void) reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0); /* Set the ddr_ck to 400 MHz, 2x memc clock */ reg32_write_masked((volatile uint32_t *)DDR_S1_IDM_IO_CONTROL_DIRECT, 0xfff << 16, /*ddr_clk*/ 0x190 << 16); -#endif /* defined(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) */ +#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) */ #if defined(CONFIG_IPROC_P7) if (is_ddr_32bit()) { @@ -1398,7 +1398,7 @@ void ddr_init2(void) return; } -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) if(!skip_shmoo) { printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_dram_info_set\n"); @@ -1433,7 +1433,7 @@ void ddr_init2(void) #error "DRAM config is not set" #endif -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) if(!skip_shmoo) { printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_phy_init\n"); @@ -1481,7 +1481,7 @@ void ddr_init2(void) ddr_init_regs(ddr3_init_tab_1333); break; #endif -#if (defined(CONFIG_DDR750) || defined(CONFIG_CYGNUS_DDR800)) +#if (defined(CONFIG_DDR750) || IS_ENABLED(CONFIG_CYGNUS_DDR800)) case 750: case 800: ddr_init_regs(ddr3_init_tab_1600); @@ -1514,7 +1514,7 @@ void ddr_init2(void) /* Start the DDR */ reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_00, 0x01); -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) if(!skip_shmoo) { while(!(reg32_read((volatile uint32_t *)DDR_DENALI_CTL_175) & 0x100)); @@ -1605,7 +1605,7 @@ void ddr_init2(void) //dump_phy_regs(); -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) /* SRX */ if(skip_shmoo) { @@ -1652,7 +1652,7 @@ wakeup: "ldr r5, [r3]\n" "mov lr, #0\n" "mov pc, r5\n"); -#endif /* defined(CONFIG_SOC_BROADCOM_CYGNUS) */ +#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */ done: /* Reclaim everything we have previously allocated for temporary usage. */ diff --git a/src/soc/broadcom/cygnus/ddr_init_table.c b/src/soc/broadcom/cygnus/ddr_init_table.c index d925895..7c8a89f 100644 --- a/src/soc/broadcom/cygnus/ddr_init_table.c +++ b/src/soc/broadcom/cygnus/ddr_init_table.c @@ -1488,7 +1488,7 @@ const unsigned int ddr3_init_tab_1333[] = { }; #endif -#ifdef CONFIG_CYGNUS_DDR800 +#if IS_ENABLED(CONFIG_CYGNUS_DDR800) const unsigned int ddr3_init_tab_1600[] = { 14, 0x01000000, 36, 0x0a140a0a, diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index adf81cc..1793ead 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -35,7 +35,7 @@ #define DEFAULT_RCBA 0xfed1c000 #endif -#ifdef CONFIG_BOARD_EMULATION_QEMU_X86_Q35 +#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) /* * Qemu has the fw_cfg interface at 0x510. Move the pmbase to a * non-conflicting address. No need to worry about speedstep, it

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coreboot-gerrit July 2015