coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: southbridge/amd/pi/hudson: Fix HUDSON_DISABLE_IMC kconfig warning
by gerrit＠coreboot.org 12 Jul '15

12 Jul '15

the following patch was just integrated into master: commit ba566bdc8b451a9b6906359c2cea2df1eaebe8ee Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 28 09:44:31 2015 -0600 southbridge/amd/pi/hudson: Fix HUDSON_DISABLE_IMC kconfig warning Platforms selecting the HUDSON_DISABLE_IMC symbol were showing the warning: warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_AMD_AGESA_BINARY_PI) selects HUDSON_DISABLE_IMC which has unmet direct dependencies (SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN) By moving the definition of the symbol outside of the if block and removing the default n, we can get rid of the warning without changing the value for any platform. Change-Id: I5c1bdfbcf3c5c44ee05b8c5e679f6854d784d8dc Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10680 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/10680 for details. -gerrit

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Patch merged into coreboot/master: x86emu/debug.h: remove #ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVEL
by gerrit＠coreboot.org 12 Jul '15

12 Jul '15

the following patch was just integrated into master: commit 3a391fd20cb1ec9a5677832ee338639e95d6757a Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jul 11 14:01:12 2015 -0600 x86emu/debug.h: remove #ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVEL This protection didn't make sense to me - it seems like things would probably break if printf wasn't defined anyway. Change-Id: Ifb6bad46e193b35c13b7ad4946511fec74beff92 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10887 for details. -gerrit

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Patch merged into coreboot/master: Update crossgcc Makefile for new buildgcc arguments
by gerrit＠coreboot.org 12 Jul '15

12 Jul '15

the following patch was just integrated into master: commit 403ba7726a0235c7399fec75baa769ca4eacc018 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 27 19:09:05 2015 -0600 Update crossgcc Makefile for new buildgcc arguments The script `util/crossgcc/buildgcc` was rewritten in commit 85b07d68 (buildgcc: move to a package centric user interface) and the switches changed. This patch does the following: - IASL was split out of the gcc builds, so needs a target of its own. - Add clang build target - Update the build-ARCH targets as buildgcc -G no longer builds gcc. - Rework all the targets to use common targets to call buildgcc - Split the tempfile clean from the regular clean - Change the 'all' target to leave the tempfiles until all architectures are built so that if one fails and needs a rebuild, it doesn't have to start from scratch. - Add an all_without_gdb target - Add clang build to all Change-Id: I4ff720eab6d9b72d00757fd2b632e6d9a6c25aa3 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10679 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10679 for details. -gerrit

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New patch to review for coreboot: superio/smsc/dme1737: new superio support
by Jonathan A. Kollasch 12 Jul '15

12 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10893 -gerrit commit c8779d288e68082fa17f15d8adc34a2edd0442ff Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sun Jul 12 11:49:16 2015 -0500 superio/smsc/dme1737: new superio support Change-Id: If2ba9ca48c809fe4f7dc0595a3cb3df168d630fd Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/dme1737/Makefile.inc | 4 +- src/superio/smsc/dme1737/dme1737.h | 21 +++--- src/superio/smsc/dme1737/early_serial.c | 4 +- src/superio/smsc/dme1737/superio.c | 112 ++++---------------------------- 6 files changed, 30 insertions(+), 114 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index ceb53a6..00d4126 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -21,6 +21,8 @@ config SUPERIO_WANTS_14MHZ_CLOCK bool +config SUPERIO_SMSC_DME1737 + bool config SUPERIO_SMSC_FDC37M60X bool config SUPERIO_SMSC_FDC37N972 diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 78cb2ae..1856884 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -18,6 +18,7 @@ ## Foundation, Inc. ## +subdirs-y += dme1737 subdirs-y += fdc37m60x subdirs-y += fdc37n972 subdirs-y += lpc47b272 diff --git a/src/superio/smsc/dme1737/Makefile.inc b/src/superio/smsc/dme1737/Makefile.inc index 5e359d7..fcd8ff1 100644 --- a/src/superio/smsc/dme1737/Makefile.inc +++ b/src/superio/smsc/dme1737/Makefile.inc @@ -20,5 +20,5 @@ ## Foundation, Inc. ## -romstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c -ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c +romstage-$(CONFIG_SUPERIO_SMSC_DME1737) += early_serial.c +ramstage-$(CONFIG_SUPERIO_SMSC_DME1737) += superio.c diff --git a/src/superio/smsc/dme1737/dme1737.h b/src/superio/smsc/dme1737/dme1737.h index bc70ba9..ee2d43d 100644 --- a/src/superio/smsc/dme1737/dme1737.h +++ b/src/superio/smsc/dme1737/dme1737.h @@ -20,20 +20,19 @@ * Foundation, Inc. */ -#ifndef SUPERIO_SMSC_LPC47B397_H -#define SUPERIO_SMSC_LPC47B397_H +#ifndef SUPERIO_SMSC_DME1737_H +#define SUPERIO_SMSC_DME1737_H -#define LPC47B397_FDC 0 /* Floppy */ -#define LPC47B397_PP 3 /* Parallel Port */ -#define LPC47B397_SP1 4 /* Com1 */ -#define LPC47B397_SP2 5 /* Com2 */ -#define LPC47B397_KBC 7 /* Keyboard & Mouse */ -#define LPC47B397_HWM 8 /* HW Monitor */ -#define LPC47B397_RT 10 /* Runtime reg*/ +#define DME1737_FDC 0 /* Floppy */ +#define DME1737_PP 3 /* Parallel Port */ +#define DME1737_SP1 4 /* Com1 */ +#define DME1737_SP2 5 /* Com2 */ +#define DME1737_KBC 7 /* Keyboard & Mouse */ +#define DME1737_RT 10 /* Runtime reg*/ #include <arch/io.h> #include <stdint.h> -void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase); +void dme1737_enable_serial(pnp_devfn_t dev, u16 iobase); -#endif /* SUPERIO_SMSC_LPC47B397_H */ +#endif /* SUPERIO_SMSC_DME1737_H */ diff --git a/src/superio/smsc/dme1737/early_serial.c b/src/superio/smsc/dme1737/early_serial.c index f5b321e..d2d4764 100644 --- a/src/superio/smsc/dme1737/early_serial.c +++ b/src/superio/smsc/dme1737/early_serial.c @@ -23,7 +23,7 @@ #include <arch/io.h> #include <device/pnp.h> #include <stdint.h> -#include "lpc47b397.h" +#include "dme1737.h" static void pnp_enter_conf_state(pnp_devfn_t dev) { @@ -37,7 +37,7 @@ static void pnp_exit_conf_state(pnp_devfn_t dev) outb(0xaa, port); } -void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) +void dme1737_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c index a9a8092..528f71d 100644 --- a/src/superio/smsc/dme1737/superio.c +++ b/src/superio/smsc/dme1737/superio.c @@ -29,123 +29,37 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "lpc47b397.h" +#include "dme1737.h" -static void enable_hwm_smbus(struct device *dev) -{ - /* Enable SensorBus register access. */ - u8 reg8; - - reg8 = pnp_read_config(dev, 0xf0); - reg8 |= (1 << 1); - pnp_write_config(dev, 0xf0, reg8); -} - -static void lpc47b397_init(struct device *dev) +static void dme1737_init(struct device *dev) { if (!dev->enabled) return; switch(dev->path.pnp.device) { - case LPC47B397_KBC: + case DME1737_KBC: pc_keyboard_init(); break; } } -static void lpc47b397_pnp_enable_resources(struct device *dev) -{ - pnp_enable_resources(dev); - - pnp_enter_conf_mode(dev); - switch(dev->path.pnp.device) { - case LPC47B397_HWM: - printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n"); - pnp_set_logical_device(dev); - enable_hwm_smbus(dev); - break; - } - /* dump_pnp_device(dev); */ - pnp_exit_conf_mode(dev); -} - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, - .enable_resources = lpc47b397_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47b397_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, -}; - -#define HWM_INDEX 0 -#define HWM_DATA 1 -#define SB_INDEX 0x0b -#define SB_DATA0 0x0c -#define SB_DATA1 0x0d -#define SB_DATA2 0x0e -#define SB_DATA3 0x0f - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - unsigned int device; - struct resource *res; - int result; - - device = dev->path.i2c.device; - - res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - - pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */ - - /* We only read it one byte one time. */ - result = pnp_read_index(res->base + SB_INDEX, address); - - return result; -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - unsigned int device; - struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - - pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */ - - /* We only write it one byte one time. */ - pnp_write_index(res->base+SB_INDEX, address, val); - - return 0; -} - -static struct smbus_bus_operations lops_smbus_bus = { - /* .recv_byte = lsmbus_recv_byte, */ - /* .send_byte = lsmbus_send_byte, */ - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct device_operations ops_hwm = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = lpc47b397_pnp_enable_resources, + .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, - .init = lpc47b397_init, - .ops_smbus_bus = &lops_smbus_bus, + .init = dme1737_init, .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, - { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, - { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, - { &ops_hwm, LPC47B397_HWM, PNP_IO0, {0x07f0, 0}, }, - { &ops, LPC47B397_RT, PNP_IO0, {0x0780, 0}, }, + { &ops, DME1737_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, DME1737_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, DME1737_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, DME1737_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, DME1737_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, DME1737_RT, PNP_IO0, {0x0780, 0}, }, }; static void enable_dev(struct device *dev) @@ -154,7 +68,7 @@ static void enable_dev(struct device *dev) ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -struct chip_operations superio_smsc_lpc47b397_ops = { - CHIP_NAME("SMSC LPC47B397 Super I/O") +struct chip_operations superio_smsc_dme1737_ops = { + CHIP_NAME("SMSC DME1737 Super I/O") .enable_dev = enable_dev, };

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New patch to review for coreboot: superio/smsc/dme1737: copy superio/smsc/lpc47b397
by Jonathan A. Kollasch 12 Jul '15

12 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10892 -gerrit commit 54c3dad65a997740b7f0ac3f74a7a45e8265341a Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sun Jul 12 11:47:56 2015 -0500 superio/smsc/dme1737: copy superio/smsc/lpc47b397 Change-Id: I3218bfaaa64bcad54fe97c6f887025356ccc9356 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/superio/smsc/dme1737/Makefile.inc | 24 +++++ src/superio/smsc/dme1737/dme1737.h | 39 ++++++++ src/superio/smsc/dme1737/early_serial.c | 48 ++++++++++ src/superio/smsc/dme1737/superio.c | 160 ++++++++++++++++++++++++++++++++ 4 files changed, 271 insertions(+) diff --git a/src/superio/smsc/dme1737/Makefile.inc b/src/superio/smsc/dme1737/Makefile.inc new file mode 100644 index 0000000..5e359d7 --- /dev/null +++ b/src/superio/smsc/dme1737/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +romstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c +ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c diff --git a/src/superio/smsc/dme1737/dme1737.h b/src/superio/smsc/dme1737/dme1737.h new file mode 100644 index 0000000..bc70ba9 --- /dev/null +++ b/src/superio/smsc/dme1737/dme1737.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef SUPERIO_SMSC_LPC47B397_H +#define SUPERIO_SMSC_LPC47B397_H + +#define LPC47B397_FDC 0 /* Floppy */ +#define LPC47B397_PP 3 /* Parallel Port */ +#define LPC47B397_SP1 4 /* Com1 */ +#define LPC47B397_SP2 5 /* Com2 */ +#define LPC47B397_KBC 7 /* Keyboard & Mouse */ +#define LPC47B397_HWM 8 /* HW Monitor */ +#define LPC47B397_RT 10 /* Runtime reg*/ + +#include <arch/io.h> +#include <stdint.h> + +void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_SMSC_LPC47B397_H */ diff --git a/src/superio/smsc/dme1737/early_serial.c b/src/superio/smsc/dme1737/early_serial.c new file mode 100644 index 0000000..f5b321e --- /dev/null +++ b/src/superio/smsc/dme1737/early_serial.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "lpc47b397.h" + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c new file mode 100644 index 0000000..a9a8092 --- /dev/null +++ b/src/superio/smsc/dme1737/superio.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <device/smbus.h> +#include <string.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "lpc47b397.h" + +static void enable_hwm_smbus(struct device *dev) +{ + /* Enable SensorBus register access. */ + u8 reg8; + + reg8 = pnp_read_config(dev, 0xf0); + reg8 |= (1 << 1); + pnp_write_config(dev, 0xf0, reg8); +} + +static void lpc47b397_init(struct device *dev) +{ + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case LPC47B397_KBC: + pc_keyboard_init(); + break; + } +} + +static void lpc47b397_pnp_enable_resources(struct device *dev) +{ + pnp_enable_resources(dev); + + pnp_enter_conf_mode(dev); + switch(dev->path.pnp.device) { + case LPC47B397_HWM: + printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n"); + pnp_set_logical_device(dev); + enable_hwm_smbus(dev); + break; + } + /* dump_pnp_device(dev); */ + pnp_exit_conf_mode(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = lpc47b397_pnp_enable_resources, + .enable = pnp_alt_enable, + .init = lpc47b397_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, +}; + +#define HWM_INDEX 0 +#define HWM_DATA 1 +#define SB_INDEX 0x0b +#define SB_DATA0 0x0c +#define SB_DATA1 0x0d +#define SB_DATA2 0x0e +#define SB_DATA3 0x0f + +static int lsmbus_read_byte(struct device *dev, u8 address) +{ + unsigned int device; + struct resource *res; + int result; + + device = dev->path.i2c.device; + + res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); + + pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */ + + /* We only read it one byte one time. */ + result = pnp_read_index(res->base + SB_INDEX, address); + + return result; +} + +static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) +{ + unsigned int device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); + + pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */ + + /* We only write it one byte one time. */ + pnp_write_index(res->base+SB_INDEX, address, val); + + return 0; +} + +static struct smbus_bus_operations lops_smbus_bus = { + /* .recv_byte = lsmbus_recv_byte, */ + /* .send_byte = lsmbus_send_byte, */ + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, +}; + +static struct device_operations ops_hwm = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = lpc47b397_pnp_enable_resources, + .enable = pnp_alt_enable, + .init = lpc47b397_init, + .ops_smbus_bus = &lops_smbus_bus, + .ops_pnp_mode = &pnp_conf_mode_55_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops_hwm, LPC47B397_HWM, PNP_IO0, {0x07f0, 0}, }, + { &ops, LPC47B397_RT, PNP_IO0, {0x0780, 0}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_lpc47b397_ops = { + CHIP_NAME("SMSC LPC47B397 Super I/O") + .enable_dev = enable_dev, +};

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Patch merged into coreboot/master: Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()
by gerrit＠coreboot.org 12 Jul '15

12 Jul '15

the following patch was just integrated into master: commit c4e49f62621429a363b092d1a6df11d2cf380465 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jul 11 13:42:54 2015 -0600 Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED() Kconfigs symbols of type bool are always defined, and can be tested with the IS_ENABLED() macro. symbol type except string. Change-Id: Ic4ba79f519ee2a53d39c10859bbfa9c32015b19d Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10885 for details. -gerrit

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New patch to review for coreboot: intel raminit: improve logging
by Patrick Rudolph 12 Jul '15

12 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10891 -gerrit commit 09e69a72e16bea1cad80c0a9bc417dd21f4554b0 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jul 12 17:06:41 2015 +0200 intel raminit: improve logging Print the old timB value to observes changes made. Change-Id: Iecec4918f1d95560b6e7933a169ccce83fcf073d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9abee23..d56d60d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -2304,7 +2304,7 @@ static int get_timB_high_adjust(u64 val) static void adjust_high_timB(ramctr_timing * ctrl) { - int channel, slotrank, lane; + int channel, slotrank, lane, old; write32(DEFAULT_MCHBAR + 0x3400, 0x200); FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); @@ -2379,12 +2379,13 @@ static void adjust_high_timB(ramctr_timing * ctrl) res |= ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] + 0x100 * channel + 8)) << 32; + old = ctrl->timings[channel][slotrank].lanes[lane].timB; ctrl->timings[channel][slotrank].lanes[lane].timB += get_timB_high_adjust(res) * 64; printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x\n", channel, - slotrank, lane, + printram("Bval+: %d, %d, %d, %x -> %x\n", channel, + slotrank, lane, old, ctrl->timings[channel][slotrank].lanes[lane]. timB); }

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New patch to review for coreboot: intel raminit: rewrite timB high adjust calculation
by Patrick Rudolph 12 Jul '15

12 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10890 -gerrit commit 41659878d1df7a64305a2103ac0b79c8473a7609 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jul 12 17:01:42 2015 +0200 intel raminit: rewrite timB high adjust calculation Found while doing code review. Simplify the code by using a loop for positive and negative phase adjustments. Change-Id: I0980443d0d2815bccef969709fddecc07d61a788 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 23 +++++++++++----------- 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 982a03d..9abee23 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -2288,18 +2288,17 @@ static int get_timB_high_adjust(u64 val) if (val == 0xffffffffffffffffLL) return 0; - if (val >= 0xfffffffffffff000LL) - return 3; - if (val >= 0xfffffffffff00000LL) - return -1; - if (val >= 0xfffffff000000000LL) - return -2; - if (val >= 0xfff0000000000000LL) - return -3; - - for (i = 0; i < 8; i++) - if (val >> (8 * (7 - i) + 4)) - return i; + if (val >= 0xf000000000000000LL) { + /* needs negative adjustment */ + for (i = 0; i < 8; i++) + if (val << (8 * (7 - i) + 4)) + return -i; + } else { + /* needs positive adjustment */ + for (i = 0; i < 8; i++) + if (val >> (8 * (7 - i) + 4)) + return i; + } return 8; }

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Patch set updated for coreboot: intel raminit: whitespace fixes
by Patrick Rudolph 12 Jul '15

12 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10888 -gerrit commit b111006e83902bf8dd1b0fe18e0cfa97e5e22f95 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jul 12 11:39:45 2015 +0200 intel raminit: whitespace fixes Remove whitespace errors. Change-Id: If69244a5d47424e3e984fdf782ea9d2d3c466d86 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 3740a02..02825f8 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -2370,16 +2370,16 @@ static void adjust_high_timB(ramctr_timing * ctrl) wait_428c(channel); FOR_ALL_LANES { u64 res = - read32(DEFAULT_MCHBAR + lane_registers[lane] + - 0x100 * channel + 4); - res |= - ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] + - 0x100 * channel + 8)) << 32; - ctrl->timings[channel][slotrank].lanes[lane].timB += - get_timB_high_adjust(res) * 64; - - printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x\n", channel, + read32(DEFAULT_MCHBAR + lane_registers[lane] + + 0x100 * channel + 4); + res |= + ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] + + 0x100 * channel + 8)) << 32; + ctrl->timings[channel][slotrank].lanes[lane].timB += + get_timB_high_adjust(res) * 64; + + printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res); + printram("Bval+: %d, %d, %d, %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane]. timB);

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Patch set updated for coreboot: intel raminit: fix timB high adjust calculation
by Patrick Rudolph 12 Jul '15

12 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10889 -gerrit commit 05fa277450fe8f1d8e2d044a7e6182d4b72292f5 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jul 12 12:17:21 2015 +0200 intel raminit: fix timB high adjust calculation Issue observed: Any memory DIMM placed in channel0 slots stops at "c320c discovery failed". The same memory DIMM works when placed in channel1 slots. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMMs: * elixir 1GB 1Rx8 PC3-10600U M2Y1G64CB88A5N * crucial 2GB 256Mx64 CT2566aBA160BJ * corsair 8GB CMZ16GX3M2A1866C9 Problem description: In case of good timmings (all bits are set) an offset of 3*64 was applied. The following test (c320c discovery) failed only on those byte-lanes. Problem solution: Don't modify timB in case of good timings measured. Final testing result: The system boots with every DIMM placed in channel 0 slots. Change-Id: Iea426ea4470640ce254f16e958a395644ff1a55c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 02825f8..982a03d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -2283,6 +2283,11 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) static int get_timB_high_adjust(u64 val) { int i; + + /* good */ + if (val == 0xffffffffffffffffLL) + return 0; + if (val >= 0xfffffffffffff000LL) return 3; if (val >= 0xfffffffffff00000LL)

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coreboot-gerrit July 2015