coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

New patch to review for coreboot: timestamps: clarify in ramstage when not reinit the cache
by Aaron Durbin 11 Jul '15

11 Jul '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10884 -gerrit commit 8b12250fc2b4e4f82d6449004a99c9c94d8d6205 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Jul 11 13:36:01 2015 -0500 timestamps: clarify in ramstage when not reinit the cache Commit bd1499d3 fixed a bug to not re-initialize the timestamp cache in ramstage for EARLY_CBMEM_INIT. However, EARLY_CBMEM_INIT was not included. Therefore, add this condition. This will result in base_time being initialized to the passed in timestamp for !EARLY_CBMEM_INIT platforms. Change-Id: Ia1d744b3cfd28163f3339f2364efe59f7dcb719b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/timestamp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 7ead383..ca25093 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -202,7 +202,7 @@ void timestamp_init(uint64_t base) /* In the EARLY_CBMEM_INIT case timestamps could have already been * recovered. In those circumstances honor the cache which sits in BSS * as it has already been initialized. */ - if (ENV_RAMSTAGE && + if (ENV_RAMSTAGE && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) && ts_cache->cache_state != TIMESTAMP_CACHE_UNINITIALIZED) return;

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New patch to review for coreboot: cbmem: export base_time in timestamp table
by Aaron Durbin 11 Jul '15

11 Jul '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10883 -gerrit commit 2e37e38948b7b6af673b42e05a11e791ee0b6f9b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Jul 11 12:44:10 2015 -0500 cbmem: export base_time in timestamp table It's helpful to know the base_time (1st timestamp) in the timestamp table because it provides more information like the accumulated time before the first timestamp was recorded. In order to maximize this information report the base time as an entry that is printed. It's called '1st timestamp'. The implementation turns all the timestamp entries into absolute time to make the logic clearer as base_time acts as a pseudo entry. Change-Id: I1334a2d980e3bcc2968a3bd6493c68b9efcca7ae Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbmem/cbmem.c | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 3bc0fcd..0bd35f2 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -457,7 +457,7 @@ static const struct timestamp_id_to_name { { TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" } }; -void timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) +static const char *timestamp_name(uint32_t id) { int i; const char *name; @@ -470,6 +470,12 @@ void timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) } } + return name; +} + +void timestamp_print_entry(uint32_t id, const char *name, + uint64_t stamp, uint64_t prev_stamp) +{ printf("%4d:", id); printf("%-50s", name); print_norm(arch_convert_raw_ts_entry(stamp)); @@ -486,7 +492,9 @@ static void dump_timestamps(void) { int i; struct timestamp_table *tst_p; + struct timestamp_table *abs_table; size_t size; + uint64_t prev_stamp; if (timestamps.tag != LB_TAG_TIMESTAMPS) { fprintf(stderr, "No timestamps found in coreboot table.\n"); @@ -502,13 +510,30 @@ static void dump_timestamps(void) unmap_memory(); tst_p = map_memory_size((unsigned long)timestamps.cbmem_addr, size); - for (i = 0; i < tst_p->num_entries; i++) { - const struct timestamp_entry *tse_p = tst_p->entries + i; - timestamp_print_entry(tse_p->entry_id, tse_p->entry_stamp, - i ? tse_p[-1].entry_stamp : 0); + abs_table = malloc(size); + if (!abs_table) { + fprintf(stderr, "Not enough memory for timestamps.\n"); + exit(1); } - + memcpy(abs_table, tst_p, size); unmap_memory(); + + /* Make all timestamps absolute. */ + for (i = 0; i < abs_table->num_entries; i++) + abs_table->entries[i].entry_stamp += abs_table->base_time; + + timestamp_print_entry(0, "1st timestamp", abs_table->base_time, 0); + + prev_stamp = abs_table->base_time; + for (i = 0; i < abs_table->num_entries; i++) { + const struct timestamp_entry *tse = &abs_table->entries[i]; + const char *name = timestamp_name(tse->entry_id); + timestamp_print_entry(tse->entry_id, name, + tse->entry_stamp, prev_stamp); + prev_stamp = tse->entry_stamp; + } + + free(abs_table); } /* dump the cbmem console */

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New patch to review for coreboot: [NOTFORMERGE] Enable USB debug by default for build testing
by Paul Menzel 11 Jul '15

11 Jul '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10882 -gerrit commit 0dd9e35e2c4caf101918ff22356fd3ff90ad5af5 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jul 11 15:35:38 2015 +0200 [NOTFORMERGE] Enable USB debug by default for build testing Enable USB debug to build test Change-Id: If742c1b393fe4655696d8e201fb0ff87dc8d712f [1]. Also fix whitespace. [1] http://review.coreboot.org/10646 Change-Id: I81c58c8a7f1c9e681465a20d312dcd0a8c14a049 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/console/Kconfig | 2 +- src/drivers/usb/Kconfig | 2 +- src/include/device/pci_ehci.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 7d6fa0e..5bddb66 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -111,7 +111,7 @@ config SPKMODEM config CONSOLE_USB bool "USB dongle console output" depends on USBDEBUG - default n + default y help Send coreboot debug output to USB. diff --git a/src/drivers/usb/Kconfig b/src/drivers/usb/Kconfig index c05705e..2d36072 100644 --- a/src/drivers/usb/Kconfig +++ b/src/drivers/usb/Kconfig @@ -11,7 +11,7 @@ config HAVE_USBDEBUG_OPTIONS config USBDEBUG bool "USB 2.0 EHCI debug dongle support" - default n + default y depends on HAVE_USBDEBUG help This option allows you to use a so-called USB EHCI Debug device diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index b916d01..e6ee8ca 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -3,7 +3,7 @@ * * Copyright (C) 2007 AMD * Copyright (C) 2015 Sage Electronic Engineering, LLC. - * + * * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. * * This program is free software; you can redistribute it and/or modify

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Patch merged into coreboot/master: Fix GCC 5.1 compile issue seen at Linux Arch
by gerrit＠coreboot.org 11 Jul '15

11 Jul '15

the following patch was just integrated into master: commit 8cce701b56d8c6f780a3d77639dc3328acfacfbe Author: Anatol Pomozov <anatol.pomozov(a)gmail.com> Date: Fri Jul 10 17:30:01 2015 -0700 Fix GCC 5.1 compile issue seen at Linux Arch rmodule.c: In function ‘rmodule_create’: rmodule.c:287:29: error: ‘phdr’ may be used uninitialized in this function [-Werror=maybe-uninitialized] (phdr->p_vaddr + phdr->p_memsz))) { ^ rmodule.c:204:14: note: ‘phdr’ was declared here Elf64_Phdr *phdr; ^ Change-Id: I94a235253610348484eef218ec855103a3bb5da5 Signed-off-by: Anatol Pomozov <anatol.pomozov(a)gmail.com> Reviewed-on: http://review.coreboot.org/10881 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info(a)gluglug.org.uk> See http://review.coreboot.org/10881 for details. -gerrit

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New patch to review for coreboot: Fix GCC 5.1 compile issue seen at Linux Arch
by Anatol Pomozov 11 Jul '15

11 Jul '15

Anatol Pomozov (anatol.pomozov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10881 -gerrit commit 552f80ea2c12358e91d22a6b3a9a9764ce60bb8d Author: Anatol Pomozov <anatol.pomozov(a)gmail.com> Date: Fri Jul 10 17:30:01 2015 -0700 Fix GCC 5.1 compile issue seen at Linux Arch rmodule.c: In function ‘rmodule_create’: rmodule.c:287:29: error: ‘phdr’ may be used uninitialized in this function [-Werror=maybe-uninitialized] (phdr->p_vaddr + phdr->p_memsz))) { ^ rmodule.c:204:14: note: ‘phdr’ was declared here Elf64_Phdr *phdr; ^ Change-Id: I94a235253610348484eef218ec855103a3bb5da5 Signed-off-by: Anatol Pomozov <anatol.pomozov(a)gmail.com> --- util/cbfstool/rmodule.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index b94e0c2..f93f4f6 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -201,7 +201,7 @@ static int find_program_segment(struct rmod_context *ctx) int i; int nsegments; struct parsed_elf *pelf; - Elf64_Phdr *phdr; + Elf64_Phdr *phdr = NULL; pelf = &ctx->pelf;

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Patch merged into coreboot/master: timestamps: don't drop ramstage timestamps with EARLY_CBMEM_INIT
by gerrit＠coreboot.org 10 Jul '15

10 Jul '15

the following patch was just integrated into master: commit bd1499d338659b5f483793e96c7e0f43c1c11f4d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 10 01:51:14 2015 -0500 timestamps: don't drop ramstage timestamps with EARLY_CBMEM_INIT While running ramstage with the EARLY_CBMEM_INIT config the timestamp cache was re-initialized and subsequently used. The result was that the ramstage timestamps would be dropped from cbmem. The reason is that the ramstage timestamps perpetually lived in ramstage BSS never getting sync'd back into cbmem. The fix is to honor the cache state in ramstage in the timestamp_init() path. Also, make cache_state a fixed bit width to allow for different architectures across the pre-ramstage stages. TEST=Used qemu-armv7 as a test harness with debugging info. Change-Id: Ibb276e513278e81cb741b1e1f6dbd1e8051cc907 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10880 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10880 for details. -gerrit

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Patch set updated for coreboot: timestamps: don't drop ramstage timestamps with EARLY_CBMEM_INIT
by Aaron Durbin 10 Jul '15

10 Jul '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10880 -gerrit commit 4237e1efe193c7f765e8a1b96ccdca5060f4d3b0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 10 01:51:14 2015 -0500 timestamps: don't drop ramstage timestamps with EARLY_CBMEM_INIT While running ramstage with the EARLY_CBMEM_INIT config the timestamp cache was re-initialized and subsequently used. The result was that the ramstage timestamps would be dropped from cbmem. The reason is that the ramstage timestamps perpetually lived in ramstage BSS never getting sync'd back into cbmem. The fix is to honor the cache state in ramstage in the timestamp_init() path. Also, make cache_state a fixed bit width to allow for different architectures across the pre-ramstage stages. TEST=Used qemu-armv7 as a test harness with debugging info. Change-Id: Ibb276e513278e81cb741b1e1f6dbd1e8051cc907 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/timestamp.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 51e63b2..7ead383 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -34,7 +34,7 @@ #define MAX_TIMESTAMP_CACHE 16 struct __attribute__((__packed__)) timestamp_cache { - int cache_state; + uint32_t cache_state; struct timestamp_table table; /* The struct timestamp_table has a 0 length array as its last field. * The following 'entries' array serves as the storage space for the @@ -199,6 +199,13 @@ void timestamp_init(uint64_t base) return; } + /* In the EARLY_CBMEM_INIT case timestamps could have already been + * recovered. In those circumstances honor the cache which sits in BSS + * as it has already been initialized. */ + if (ENV_RAMSTAGE && + ts_cache->cache_state != TIMESTAMP_CACHE_UNINITIALIZED) + return; + timestamp_cache_init(ts_cache, base); }

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New patch to review for coreboot: timestamps: don't drop ramstage timestamps with EARLY_CBMEM_INIT
by Aaron Durbin 10 Jul '15

10 Jul '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10880 -gerrit commit 859f5ba16727fdffdea12cb3ad7c3f627ffbf978 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 10 01:51:14 2015 -0500 timestamps: don't drop ramstage timestamps with EARLY_CBMEM_INIT While running ramstage with the EARLY_CBMEM_INIT config the timestamp cache was re-initialized and subsequently used. The result was that the ramstage timestamps would be dropped from cbmem. The reason is that the ramstage timestamps perpetually lived in ramstage BSS never getting sync'd back into cbmem. The fix is to honor the cache state in ramstage in the timestamp_init() path. TEST=Used qemu-armv7 as a test harness with debugging info. Change-Id: Ibb276e513278e81cb741b1e1f6dbd1e8051cc907 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/timestamp.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 51e63b2..7ead383 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -34,7 +34,7 @@ #define MAX_TIMESTAMP_CACHE 16 struct __attribute__((__packed__)) timestamp_cache { - int cache_state; + uint32_t cache_state; struct timestamp_table table; /* The struct timestamp_table has a 0 length array as its last field. * The following 'entries' array serves as the storage space for the @@ -199,6 +199,13 @@ void timestamp_init(uint64_t base) return; } + /* In the EARLY_CBMEM_INIT case timestamps could have already been + * recovered. In those circumstances honor the cache which sits in BSS + * as it has already been initialized. */ + if (ENV_RAMSTAGE && + ts_cache->cache_state != TIMESTAMP_CACHE_UNINITIALIZED) + return; + timestamp_cache_init(ts_cache, base); }

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New patch to review for coreboot: libpayload: Fix arithmetic precedence in div_round_up()
by Patrick Georgi 10 Jul '15

10 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10879 -gerrit commit 6dc055404f9512a387108324db34ebc68f991c3f Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jul 9 15:47:07 2015 -0700 libpayload: Fix arithmetic precedence in div_round_up() Well, this is just embarrassing... BRANCH=None BUG=None TEST=None Change-Id: I7c443d2100b6861d736320ac14c1bd9965937a66 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 455e3784882ea1b76bcf8e17724869e37d9c629d Original-Change-Id: Ia33e98aeaa8e78e3e3d2c7547e673a623ea86ce2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284596 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- payloads/libpayload/include/libpayload.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index c09fc17..8f17b58 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -64,7 +64,7 @@ #define MAX(a,b) ((a) > (b) ? (a) : (b)) #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -static inline u32 div_round_up(u32 n, u32 d) { return n + d - 1 / d; } +static inline u32 div_round_up(u32 n, u32 d) { return (n + d - 1) / d; } #define LITTLE_ENDIAN 1234 #define BIG_ENDIAN 4321

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New patch to review for coreboot: t210: Add TZDRAM_BASE param to BL31_MAKEARGS
by Patrick Georgi 10 Jul '15

10 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10878 -gerrit commit 584b44ef784019e8f189a85f1b8f354746f1a557 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 7 21:35:56 2015 -0700 t210: Add TZDRAM_BASE param to BL31_MAKEARGS 1. Make TTB_SIZE Kconfig option 2. Add Kconfig option for maximum secure component size 3. Add check in Makefile to ensure that Trustzone area is big enough to hold TTB and secure components 4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE BUG=chrome-os-partner:42319 BRANCH=None Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284074 Original-Reviewed-by: Varun Wadekar <vwadekar(a)nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/Kconfig | 13 +++++++++++++ src/soc/nvidia/tegra210/Makefile.inc | 22 ++++++++++++++++++++++ .../nvidia/tegra210/include/soc/mmu_operations.h | 3 --- src/soc/nvidia/tegra210/mmu_operations.c | 2 +- src/soc/nvidia/tegra210/secmon.c | 2 +- 5 files changed, 37 insertions(+), 5 deletions(-) diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 7aa932a..7aff588 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -102,6 +102,19 @@ config TRUSTZONE_CARVEOUT_SIZE_MB help Size of Trust Zone area in MiB to reserve in memory map. +config TTB_SIZE_MB + hex "Size of TTB" + default 0x4 + help + Maximum size of Translation Table Buffer in MiB. + +config SEC_COMPONENT_SIZE_MB + hex "Size of resident EL3 components" + default 0x10 + help + Maximum size of resident EL3 components in MiB including BL31 and + Secure OS. + # Default to 700MHz. This value is based on nv bootloader setting. config PLLX_KHZ int diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 98e752c..3b2dc7c 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -146,6 +146,28 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" $(CBOOTIMAGE) $(CBOOTIMAGE_OPTS) $(BCT_WRAPPER) $@ +# We need to ensure that TZ memory has enough space to hold TTB and resident EL3 +# components (including BL31 and Secure OS) +ttb_size=$(shell printf "%d" $(CONFIG_TTB_SIZE_MB)) +sec_size=$(shell printf "%d" $(CONFIG_SEC_COMPONENT_SIZE_MB)) +req_tz_size=$(shell expr $(ttb_size) + $(sec_size)) + +tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) + +ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1) + $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be atleast as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") +endif + +# BL31 component is placed towards the end of 32-bit address space. This assumes +# that TrustZone memory is placed at the end of 32-bit address space. Within the +# TZ memory, we place TTB at the beginning and then remaining space can be used +# up by BL31 and secure OS. Calculate TZDRAM_BASE i.e. base of BL31 component +# by: +# 0x1000 = end of 32-bit address space in MiB +# 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) = start of TZ memory in MiB +# 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB) +# = skip TTB buffer and get base address of BL31 +BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB)) << 20)) BL31_MAKEARGS += PLAT=tegra TARGET_SOC=t210 # MTC fw diff --git a/src/soc/nvidia/tegra210/include/soc/mmu_operations.h b/src/soc/nvidia/tegra210/include/soc/mmu_operations.h index 6a81e7c..a6e42aa 100644 --- a/src/soc/nvidia/tegra210/include/soc/mmu_operations.h +++ b/src/soc/nvidia/tegra210/include/soc/mmu_operations.h @@ -22,7 +22,4 @@ void tegra210_mmu_init(void); -/* Default ttb size of 4MiB */ -#define TTB_SIZE 0x4 - #endif //__SOC_NVIDIA_TEGRA210_MMU_OPERATIONS_H__ diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c index 2ee6b80..66a93e1 100644 --- a/src/soc/nvidia/tegra210/mmu_operations.c +++ b/src/soc/nvidia/tegra210/mmu_operations.c @@ -77,7 +77,7 @@ void tegra210_mmu_init(void) /* Place page tables at the base of the trust zone region. */ carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); tz_base_mib *= MiB; - ttb_size_mib = TTB_SIZE * MiB; + ttb_size_mib = CONFIG_TTB_SIZE_MB * MiB; mmu_init(map, (void *)tz_base_mib, ttb_size_mib); mmu_enable(); } diff --git a/src/soc/nvidia/tegra210/secmon.c b/src/soc/nvidia/tegra210/secmon.c index 66ebed2..c093607 100644 --- a/src/soc/nvidia/tegra210/secmon.c +++ b/src/soc/nvidia/tegra210/secmon.c @@ -43,7 +43,7 @@ void soc_get_secmon_base_size(uint64_t *base, size_t *size) soc_get_secure_mem(&tz_base, &tz_size); - ttb_size = TTB_SIZE * MiB; + ttb_size = CONFIG_TTB_SIZE_MB * MiB; *base = tz_base + ttb_size; *size = tz_size - ttb_size;

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coreboot-gerrit July 2015