coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 6e944c4 imgtech/pistachio: Give some more space to the bootblock
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 6e944c467ca28a8c4d7d0c0ff4b6e2ad8232a55b Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 21:19:00 2015 +0200 imgtech/pistachio: Give some more space to the bootblock The memory layout isn't very clear here, since there are two regions (bootblock and "SRAM") that are actually the same. So when increasing the bootblock's size, we also need to move the romstage around. Change-Id: Ib158a4ef96b7c1dd1132b6e8bd47a0eb9c3951d9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10035 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10035 for details. -gerrit

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New patch to review for coreboot: 146df7c crossgcc: improve error message on missing tools
by Patrick Georgi 29 Apr '15

29 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10036 -gerrit commit 146df7c431cb37a4e1749464d01b00414f942850 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 23:30:15 2015 +0200 crossgcc: improve error message on missing tools People were confused about the 'missing toolchain', so improve the error message. Change-Id: Icaee338aeedce2255bcfdafe5407c9df02ad9c4a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index f2faefb..a29a338 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -125,7 +125,7 @@ searchtool() fi fi fi - printf "${RED}ERROR:${red} Missing toolchain: $1${NC}\n" >&2 + printf "${RED}ERROR:${red} Missing tool: Please install $1 (eg using your OS packaging system)${NC}\n" >&2 [ -z "$3" ] && exit 1 false }

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Patch set updated for coreboot: 1cc5bb2 New mainboard: Lenovo T500
by Francis Rowe 29 Apr '15

29 Apr '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9181 -gerrit commit 1cc5bb2c8bd8cb94b60086e5e291c4a7811bb1b0 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Tue Mar 31 22:51:22 2015 +0100 New mainboard: Lenovo T500 Clone of Lenovo T400. It works/boots, but needs more testing. Change-Id: I7ace604ca7fede44ce78277561d31e3083fc6c8c Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/t400/Kconfig | 2 +- src/mainboard/lenovo/t500/Kconfig | 7 +++++++ src/mainboard/lenovo/t500/board_info.txt | 6 ++++++ 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index 4fc56cd..3dee443 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -47,6 +47,11 @@ config BOARD_LENOVO_T430S help Lenovo T430s laptop. Consult wiki for details. +config BOARD_LENOVO_T500 + bool "ThinkPad T500" + help + Lenovo T500 laptop. Consult wiki for details. + config BOARD_LENOVO_T520 bool "ThinkPad T520" help @@ -85,6 +90,7 @@ source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t400/Kconfig" source "src/mainboard/lenovo/t420s/Kconfig" source "src/mainboard/lenovo/t430s/Kconfig" +source "src/mainboard/lenovo/t500/Kconfig" source "src/mainboard/lenovo/t520/Kconfig" source "src/mainboard/lenovo/t530/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 8287f5e..0b6f563 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T400 || BOARD_LENOVO_R400 +if BOARD_LENOVO_T400 || BOARD_LENOVO_R400 || BOARD_LENOVO_T500 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y diff --git a/src/mainboard/lenovo/t500/Kconfig b/src/mainboard/lenovo/t500/Kconfig new file mode 100644 index 0000000..e1e8420 --- /dev/null +++ b/src/mainboard/lenovo/t500/Kconfig @@ -0,0 +1,7 @@ +if BOARD_LENOVO_T500 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T500" + +endif diff --git a/src/mainboard/lenovo/t500/board_info.txt b/src/mainboard/lenovo/t500/board_info.txt new file mode 100644 index 0000000..007ec6c --- /dev/null +++ b/src/mainboard/lenovo/t500/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-16 or SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Clone of: lenovo/t400

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Patch set updated for coreboot: 6af0b02 lenovo/r400: Add clone of Lenovo T400
by Francis Rowe 29 Apr '15

29 Apr '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8393 -gerrit commit 6af0b026ba5eff274838579d7f5c4ae449824836 Author: Michał Masłowski <mtjm(a)mtjm.eu> Date: Tue Feb 3 23:26:05 2015 +0100 lenovo/r400: Add clone of Lenovo T400 The existing code for the Lenovo T400 works without changes on the Lenovo R400. The vendor BIOS provides different HDA verbs as the connectors are on the front and not the right, but this doesn't provide enough benefit to justify having different source files. This used to be based on the X200 code, now based on T400. This should still be replaced with a separate port, with the differences implemented, instead of being a clone. Change-Id: I1dadddd7250ab80a4c40c2435865d72e3e5d99c9 Signed-off-by: Michał Masłowski <mtjm(a)mtjm.eu> Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/r400/Kconfig | 7 +++++++ src/mainboard/lenovo/r400/board_info.txt | 6 ++++++ src/mainboard/lenovo/t400/Kconfig | 6 +++++- util/nvidia/cbootimage | 2 +- 5 files changed, 25 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index b6da044..4fc56cd 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -70,6 +70,11 @@ config BOARD_LENOVO_G505S help Lenovo G505s +config BOARD_LENOVO_R400 + bool "ThinkPad R400" + help + Lenovo R400 laptop. Consult wiki for details. + endchoice source "src/mainboard/lenovo/x60/Kconfig" @@ -84,6 +89,7 @@ source "src/mainboard/lenovo/t520/Kconfig" source "src/mainboard/lenovo/t530/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" source "src/mainboard/lenovo/g505s/Kconfig" +source "src/mainboard/lenovo/r400/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/lenovo/r400/Kconfig b/src/mainboard/lenovo/r400/Kconfig new file mode 100644 index 0000000..0966bf1 --- /dev/null +++ b/src/mainboard/lenovo/r400/Kconfig @@ -0,0 +1,7 @@ +if BOARD_LENOVO_R400 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad R400" + +endif diff --git a/src/mainboard/lenovo/r400/board_info.txt b/src/mainboard/lenovo/r400/board_info.txt new file mode 100644 index 0000000..007ec6c --- /dev/null +++ b/src/mainboard/lenovo/r400/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-16 or SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Clone of: lenovo/t400 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 392ce692..8287f5e 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T400 +if BOARD_LENOVO_T400 || BOARD_LENOVO_R400 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -26,10 +26,14 @@ config MAINBOARD_DIR string default lenovo/t400 +if BOARD_LENOVO_T400 + config MAINBOARD_PART_NUMBER string default "ThinkPad T400" +endif + config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/util/nvidia/cbootimage b/util/nvidia/cbootimage index 2eb9a86..b7d5b2d 160000 --- a/util/nvidia/cbootimage +++ b/util/nvidia/cbootimage @@ -1 +1 @@ -Subproject commit 2eb9a86724db0d86c9ab9b6aeca21d1000d74e78 +Subproject commit b7d5b2d6a6dd05874d86ee900ff441d261f9034c

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New patch to review for coreboot: d5eef7a imgtech/pistachio: Give some more space to the bootblock
by Patrick Georgi 29 Apr '15

29 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10035 -gerrit commit d5eef7aaffbb2668213750149a7bed94d0553278 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 21:19:00 2015 +0200 imgtech/pistachio: Give some more space to the bootblock The memory layout isn't very clear here, since there are two regions (bootblock and "SRAM") that are actually the same. So when increasing the bootblock's size, we also need to move the romstage around. Change-Id: Ib158a4ef96b7c1dd1132b6e8bd47a0eb9c3951d9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index c7ea04b..e9f6c59 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -38,12 +38,12 @@ SECTIONS * and then through the identity mapping in ROM stage. */ SRAM_START(0x1a000000) - ROMSTAGE(0x1a004800, 36K) - PRERAM_CBFS_CACHE(0x1a00d800, 74K) + ROMSTAGE(0x1a005000, 36K) + PRERAM_CBFS_CACHE(0x1a00e000, 72K) SRAM_END(0x1a020000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. */ - BOOTBLOCK(0x9a000000, 18K) + BOOTBLOCK(0x9a000000, 20K) /* * Let's use SRAM for stack and CBMEM console. Always accessed

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New patch to review for coreboot: 7a03935 intel/broadwell: Don't select MONOTONIC_TIMER_MSR
by Patrick Georgi 29 Apr '15

29 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10034 -gerrit commit 7a03935bdc207166575d181654e07876dae8c67b Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 20:44:06 2015 +0200 intel/broadwell: Don't select MONOTONIC_TIMER_MSR That's a Haswell exclusive, used nowhere else, but confusing when hunting for the monotonic timer used on that SoC. Change-Id: I60ec523e54e5af0d2a418bcb9145de452a3a4ea9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/samus/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 6 ------ 3 files changed, 8 deletions(-) diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index 664faf1..f655b29 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select MONOTONIC_TIMER_MSR select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 98b2790..5a064d1 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT - select MONOTONIC_TIMER_MSR select INTEL_INT15 select CHROMEOS_RAMOOPS_DYNAMIC diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index d840632..151b1a4 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -173,12 +173,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs. -config MONOTONIC_TIMER_MSR - def_bool y - select HAVE_MONOTONIC_TIMER - help - Provide a monotonic timer using the 24MHz MSR counter. - config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n

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New patch to review for coreboot: f78979e intel/broadwell: Build monotonic timer driver for SMM
by Patrick Georgi 29 Apr '15

29 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10033 -gerrit commit f78979e069d20571990fa37424bf782e65962f50 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 20:43:44 2015 +0200 intel/broadwell: Build monotonic timer driver for SMM SPI flash drivers need it. Change-Id: I63d79472d70d75f7907e7620755c228d5a4918e1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index ec6b9ae..9905ca2 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += memmap.c romstage-y += memmap.c ramstage-y += minihd.c ramstage-y += monotonic_timer.c +smm-y += monotonic_timer.c ramstage-y += pch.c romstage-y += pch.c ramstage-y += pcie.c

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New patch to review for coreboot: 3fa8135 arch/arm: only include subdirectories for ARM builds
by Patrick Georgi 29 Apr '15

29 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10032 -gerrit commit 3fa813599cca482ddb1c2d22025357a7a8427730 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 20:28:03 2015 +0200 arch/arm: only include subdirectories for ARM builds Change-Id: Ieac02fcc4508f7c1b194802453d6222b902a38a2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/arm/Makefile.inc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 272a495..afb8d20 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -20,11 +20,6 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -############################################################################### -# Take care of subdirectories -############################################################################### -subdirs-y += libgcc/ -subdirs-y += armv4/ armv7/ ############################################################################### # ARM specific options @@ -36,6 +31,9 @@ CBFSTOOL_PRE_OPTS = -b 0 endif ifeq ($(CONFIG_ARCH_ARM),y) +subdirs-y += libgcc/ +subdirs-y += armv4/ armv7/ + stages_c = $(src)/arch/arm/stages.c stages_o = $(obj)/arch/arm/stages.o

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New patch to review for coreboot: 0986b7d kbuild: Don't require intel/common changes for every soc
by Stefan Reinauer 29 Apr '15

29 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10031 -gerrit commit 0986b7d280d9ce83a0f56feb47a4eaf07ce25e6b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 29 10:45:22 2015 -0700 kbuild: Don't require intel/common changes for every soc In the true spirit of separating components more strictly and allowing to add new components to coreboot without touching existing code, move Intel common code selection to the soc Kconfig and out of src/soc/intel/common/Makefile.inc Change-Id: I0a70656bb9f4550b6088e9f45e68b5106c0eb9af Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/common/Kconfig | 5 +++++ src/soc/intel/common/Makefile.inc | 2 +- 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 214a1ac..0b3e176 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC + select SOC_INTEL_COMMON config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index d840632..91249ee 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select PER_DEVICE_ACPI_TABLES + select SOC_INTEL_COMMON config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 1dce4e3..8b5cef3 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -1,3 +1,8 @@ +config SOC_INTEL_COMMON + bool + help + common code for Intel SOCs + if HAVE_MRC config CACHE_MRC_SETTINGS diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 46786e2..6d40aa7 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL)$(CONFIG_SOC_INTEL_BROADWELL),y) +ifeq ($(CONFIG_SOC_INTEL_COMMON),y) ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c

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New patch to review for coreboot: 448570a intel/broadwell: bootstate mechanism doesn't exist in SMM
by Patrick Georgi 29 Apr '15

29 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10030 -gerrit commit 448570a8ed231b535a283a36ba6f77005af0866c Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 19:11:30 2015 +0200 intel/broadwell: bootstate mechanism doesn't exist in SMM So don't try to use it. Change-Id: Ia600ba654bde36d3ea8a0f3185afae00fe50bfe9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 0fca059..44285a9 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -312,12 +312,14 @@ void spi_init(void) pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } +#ifndef __SMM__ static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); +#endif int spi_claim_bus(struct spi_slave *slave) {

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coreboot-gerrit April 2015