coreboot-gerrit April 2015

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Patch set updated for coreboot: 451476c vendorcode/intel: Add FSP 1.1 header files
by Leroy P Leahy 29 Apr '15

29 Apr '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9974 -gerrit commit 451476c80b5a44308e3e518d69565907a61337df Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Apr 20 15:08:28 2015 -0700 vendorcode/intel: Add FSP 1.1 header files The second step in adding support for FSP 1.1 is to add the header files. Updates may be done manually to these files but only to support FSP 1.1. An FSPx_y tree should be added in the future as FSP binaries migrate to new FSP specifications. The files are provided in an EDK2 style tree to allow direct comparison with the EDK2 tree. BRANCH=none BUG=None TEST=Build for Braswell or Skylake boards using FSP 1.1. Change-Id: If0e2fbe3cf9d39b18009552af5c861eff24043a0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- .../intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h | 308 +++++++++++++++++++++ .../fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h | 157 +++++++++++ 2 files changed, 465 insertions(+) diff --git a/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h b/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h new file mode 100644 index 0000000..6a621d6 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h @@ -0,0 +1,308 @@ +/** @file + Intel FSP API definition from Intel Firmware Support Package External + Architecture Specification, April 2014, revision 001. + + Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FSP_API_H_ +#define _FSP_API_H_ + +#define FSP_STATUS EFI_STATUS +#define FSPAPI EFIAPI + +/** + FSP Init continuation function prototype. + Control will be returned to this callback function after FspInit API call. + + @param[in] Status Status of the FSP INIT API. + @param[in] HobBufferPtr Pointer to the HOB data structure defined in the PI specification. +**/ +typedef +VOID +(* CONTINUATION_PROC) ( + IN EFI_STATUS Status, + IN VOID *HobListPtr + ); + +#pragma pack(1) + +typedef struct { + /// + /// Base address of the microcode region. + /// + UINT32 MicrocodeRegionBase; + /// + /// Length of the microcode region. + /// + UINT32 MicrocodeRegionLength; + /// + /// Base address of the cacheable flash region. + /// + UINT32 CodeRegionBase; + /// + /// Length of the cacheable flash region. + /// + UINT32 CodeRegionLength; +} FSP_TEMP_RAM_INIT_PARAMS; + +typedef struct { + /// + /// Non-volatile storage buffer pointer. + /// + VOID *NvsBufferPtr; + /// + /// Runtime buffer pointer + /// + VOID *RtBufferPtr; + /// + /// Continuation function address + /// + CONTINUATION_PROC ContinuationFunc; +} FSP_INIT_PARAMS; + +typedef struct { + /// + /// Stack top pointer used by the bootloader. + /// The new stack frame will be set up at this location after FspInit API call. + /// + UINT32 *StackTop; + /// + /// Current system boot mode. + /// + UINT32 BootMode; + /// + /// User platform configuraiton data region pointer. + /// + VOID *UpdDataRgnPtr; + /// + /// The size of memory to be reserved below the top of low usable memory (TOLUM) + /// for BootLoader usage. This is optional and value can be zero. If non-zero, the + /// size must be a multiple of 4KB. FSP EAS v1.1 + /// + UINT32 BootLoaderTolumSize; + /// + /// Reserved + /// + UINT32 Reserved[6]; +} FSP_INIT_RT_COMMON_BUFFER; + +typedef enum { + /// + /// Notification code for post PCI enuermation + /// + EnumInitPhaseAfterPciEnumeration = 0x20, + /// + /// Notification code before transfering control to the payload + /// + EnumInitPhaseReadyToBoot = 0x40 +} FSP_INIT_PHASE; + +typedef struct { + /// + /// Notification phase used for NotifyPhase API + /// + FSP_INIT_PHASE Phase; +} NOTIFY_PHASE_PARAMS; + +typedef struct { + /// + /// Non-volatile storage buffer pointer. + /// + VOID *NvsBufferPtr; + /// + /// Runtime buffer pointer + /// + VOID *RtBufferPtr; + /// + /// Pointer to the HOB data structure defined in the PI specification + /// + VOID **HobListPtr; +} FSP_MEMORY_INIT_PARAMS; + +#pragma pack() + +/** + This FSP API is called soon after coming out of reset and before memory and stack is + available. This FSP API will load the microcode update, enable code caching for the + region specified by the boot loader and also setup a temporary stack to be used until + main memory is initialized. + + A hardcoded stack can be set up with the following values, and the "esp" register + initialized to point to this hardcoded stack. + 1. The return address where the FSP will return control after setting up a temporary + stack. + 2. A pointer to the input parameter structure + + However, since the stack is in ROM and not writeable, this FSP API cannot be called + using the "call" instruction, but needs to be jumped to. + + @param[in] TempRaminitParamPtr Address pointer to the FSP_TEMP_RAM_INIT_PARAMS structure. + + @retval EFI_SUCCESS Temp RAM was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid.. + @retval EFI_NOT_FOUND No valid microcode was found in the microcode region. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR Temp RAM initialization failed. + + If this function is successful, the FSP initializes the ECX and EDX registers to point to + a temporary but writeable memory range available to the boot loader and returns with + FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary + memory range and EDX points to the end of the range. Boot loader is free to use the + whole range described. Typically the boot loader can reload the ESP register to point + to the end of this returned range so that it can be used as a standard stack. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_TEMP_RAM_INIT) ( + IN FSP_TEMP_RAM_INIT_PARAMS *FspTempRamInitPtr + ); + +/** + This FSP API is called after TempRamInitEntry. This FSP API initializes the memory, + the CPU and the chipset to enable normal operation of these devices. This FSP API + accepts a pointer to a data structure that will be platform dependent and defined for + each FSP binary. This will be documented in the Integration Guide for each FSP + release. + The boot loader provides a continuation function as a parameter when calling FspInit. + After FspInit completes its execution, it does not return to the boot loader from where + it was called but instead returns control to the boot loader by calling the continuation + function which is passed to FspInit as an argument. + + @param[in] FspInitParamPtr Address pointer to the FSP_INIT_PARAMS structure. + + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_INIT) ( + IN OUT FSP_INIT_PARAMS *FspInitParamPtr + ); + +#define FSP_FSP_INIT FSP_INIT + +/** + This FSP API is used to notify the FSP about the different phases in the boot process. + This allows the FSP to take appropriate actions as needed during different initialization + phases. The phases will be platform dependent and will be documented with the FSP + release. The current FSP supports two notify phases: + Post PCI enumeration + Ready To Boot + + @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS + + @retval EFI_SUCCESS The notification was handled successfully. + @retval EFI_UNSUPPORTED The notification was not called in the proper order. + @retval EFI_INVALID_PARAMETER The notification code is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_NOTIFY_PHASE) ( + IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr + ); + +/** + This FSP API is called after TempRamInit and initializes the memory. + This FSP API accepts a pointer to a data structure that will be platform dependent + and defined for each FSP binary. This will be documented in Integration guide with + each FSP release. + After FspMemInit completes its execution, it passes the pointer to the HobList and + returns to the boot loader from where it was called. Bootloader is responsible to + migrate it's stack and data to Memory. + FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to + complete the silicon initialization and provides bootloader an opportunity to get + control after system memory is available and before the temporary RAM is torn down. + These APIs are mutually exclusive to the FspInit API. + + @param[in][out] FspMemoryInitParamPtr Address pointer to the FSP_MEMORY_INIT_PARAMS + structure. + + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_MEMORY_INIT) ( + IN OUT FSP_MEMORY_INIT_PARAMS *FspMemoryInitParamPtr + ); + + +/** + This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary + memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure + that will be platform dependent and defined for each FSP binary. This will be + documented in Integration Guide. + FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to + complete the silicon initialization and provides bootloader an opportunity to get + control after system memory is available and before the temporary RAM is torn down. + These APIs are mutually exclusive to the FspInit API. + + @param[in][out] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure. + This structure is normally defined in the Integration Guide. + And if it is not defined in the Integration Guide, pass NULL. + + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_TEMP_RAM_EXIT) ( + IN OUT VOID *TempRamExitParamPtr + ); + + +/** + This FSP API is called after TempRamExit API. + FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the + silicon initialization. + These APIs are mutually exclusive to the FspInit API. + + @param[in][out] FspSiliconInitParamPtr Pointer to the Silicon Init parameters structure. + This structure is normally defined in the Integration Guide. + And if it is not defined in the Integration Guide, pass NULL. + + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_SILICON_INIT) ( + IN OUT VOID *FspSiliconInitParamPtr + ); + +/// +/// FSP API Return Status Code for backward compatibility with v1.0 +///@{ +#define FSP_SUCCESS EFI_SUCCESS +#define FSP_INVALID_PARAMETER EFI_INVALID_PARAMETER +#define FSP_UNSUPPORTED EFI_UNSUPPORTED +#define FSP_NOT_READY EFI_NOT_READY +#define FSP_DEVICE_ERROR EFI_DEVICE_ERROR +#define FSP_OUT_OF_RESOURCES EFI_OUT_OF_RESOURCES +#define FSP_VOLUME_CORRUPTED EFI_VOLUME_CORRUPTED +#define FSP_NOT_FOUND EFI_NOT_FOUND +#define FSP_TIMEOUT EFI_TIMEOUT +#define FSP_ABORTED EFI_ABORTED +#define FSP_INCOMPATIBLE_VERSION EFI_INCOMPATIBLE_VERSION +#define FSP_SECURITY_VIOLATION EFI_SECURITY_VIOLATION +#define FSP_CRC_ERROR EFI_CRC_ERROR +///@} + +#endif diff --git a/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h b/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h new file mode 100644 index 0000000..47d463c --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h @@ -0,0 +1,157 @@ +/** @file + Intel FSP Info Header definition from Intel Firmware Support Package External + Architecture Specification, April 2014, revision 001. + + Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FSP_INFO_HEADER_H_ +#define _FSP_INFO_HEADER_H_ + +#define FSP_HEADER_REVISION_1 1 +#define FSP_HEADER_REVISION_2 2 + +#define FSPE_HEADER_REVISION_1 1 +#define FSPP_HEADER_REVISION_1 1 + +/// +/// Fixed FSP header offset in the FSP image +/// +#define FSP_INFO_HEADER_OFF 0x94 + +#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x + +#pragma pack(1) + +typedef struct { + /// + /// Byte 0x00: Signature ('FSPH') for the FSP Information Header + /// + UINT32 Signature; + /// + /// Byte 0x04: Length of the FSP Information Header + /// + UINT32 HeaderLength; + /// + /// Byte 0x08: Reserved + /// + UINT8 Reserved1[3]; + /// + /// Byte 0x0B: Revision of the FSP Information Header + /// + UINT8 HeaderRevision; + /// + /// Byte 0x0C: Revision of the FSP binary + /// + UINT32 ImageRevision; + + + /// + /// Byte 0x10: Signature string that will help match the FSP Binary to a supported + /// hardware configuration. + /// + CHAR8 ImageId[8]; + /// + /// Byte 0x18: Size of the entire FSP binary + /// + UINT32 ImageSize; + /// + /// Byte 0x1C: FSP binary preferred base address + /// + UINT32 ImageBase; + + + /// + /// Byte 0x20: Attribute for the FSP binary + /// + UINT32 ImageAttribute; + /// + /// Byte 0x24: Offset of the FSP configuration region + /// + UINT32 CfgRegionOffset; + /// + /// Byte 0x28: Size of the FSP configuration region + /// + UINT32 CfgRegionSize; + /// + /// Byte 0x2C: Number of API entries this FSP supports + /// + UINT32 ApiEntryNum; + + + /// + /// Byte 0x30: The offset for the API to setup a temporary stack till the memory + /// is initialized. + /// + UINT32 TempRamInitEntryOffset; + /// + /// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC) + /// + UINT32 FspInitEntryOffset; + /// + /// Byte 0x38: The offset for the API to inform the FSP about the different stages + /// in the boot process + /// + UINT32 NotifyPhaseEntryOffset; + + /// + /// Below fields are added in FSP Revision 2 + /// + + /// + /// Byte 0x3C: The offset for the API to initialize the memory + /// + UINT32 FspMemoryInitEntryOffset; + /// + /// Byte 0x40: The offset for the API to tear down temporary RAM + /// + UINT32 TempRamExitEntryOffset; + /// + /// Byte 0x44: The offset for the API to initialize the CPU and chipset + /// + UINT32 FspSiliconInitEntryOffset; + +} FSP_INFO_HEADER; + +/// +/// Below structure is added in FSP version 2 +/// +typedef struct { + /// + /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header + /// + UINT32 Signature; + /// + /// Byte 0x04: Length of the FSP Extended Header + /// + UINT32 HeaderLength; + /// + /// Byte 0x08: Revision of the FSP Extended Header + /// + UINT8 Revision; + /// + /// Byte 0x09: Reserved for future use. + /// + UINT8 Reserved; + /// + /// Byte 0x0A: An OEM-supplied string that defines the OEM + /// + CHAR8 OemId[6]; + /// + /// Byte 0x10: An OEM-supplied revision number. Larger numbers are assumed to be newer revisions. + /// + UINT32 OemRevision; + +} FSP_EXTENTED_HEADER; + +#pragma pack() + +#endif

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New patch to review for coreboot: b8a86cd vboot: add and rejuggle Kconfig options
by Aaron Durbin 29 Apr '15

29 Apr '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10024 -gerrit commit b8a86cd42545491ae2ffa890593e774d489c42cd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 28 16:17:25 2015 -0500 vboot: add and rejuggle Kconfig options The ChromeOS machines employing vboot verfication require different combinations of support: 1. When vboot verification starts. 2. Is the vboot code a separate stage or program? 3. If a separate stage, does the that vboot program (verstage) return to the stage that loaded the verstage? For the above, #1 is dependent on when to load/run vboot logic which is orthogonal to #2. However, #3 is dependent on #2. The logic to act on the combinations follows in subsequent patches. Change-Id: I39ef7a7c2858e7de43aa99c38121e85a57f1f2f6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/marvell/bg4cd/Kconfig | 2 +- src/vendorcode/google/chromeos/vboot2/Kconfig | 37 ++++++++++++++-------- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 4 +++ 3 files changed, 28 insertions(+), 15 deletions(-) diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig index 96fd8ef..9c0dc14 100644 --- a/src/soc/marvell/bg4cd/Kconfig +++ b/src/soc/marvell/bg4cd/Kconfig @@ -32,7 +32,7 @@ config SOC_MARVELL_BG4CD select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select GENERIC_GPIO_LIB - select VERSTAGE_IN_BOOTBLOCK + select VBOOT_STARTS_IN_BOOTBLOCK if SOC_MARVELL_BG4CD diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig index 3b5c594..8396113 100644 --- a/src/vendorcode/google/chromeos/vboot2/Kconfig +++ b/src/vendorcode/google/chromeos/vboot2/Kconfig @@ -16,6 +16,20 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +config VBOOT_STARTS_IN_BOOTBLOCK + bool + default n + depends on VBOOT_VERIFY_FIRMWARE + help + Firmware verification happens during or at the end of bootblock. + +config VBOOT_STARTS_IN_ROMSTAGE + bool + default n + depends on VBOOT_VERIFY_FIRMWARE && !VBOOT_STARTS_IN_BOOTBLOCK + help + Firmware verification happens during or at the end of romstage. + config VBOOT2_MOCK_SECDATA bool "Mock secdata for firmware verification" default n @@ -27,16 +41,6 @@ config VBOOT2_MOCK_SECDATA can be used during development when a TPM is not present or broken. THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES. -config RETURN_FROM_VERSTAGE - bool "return from verstage" - default n - depends on VBOOT_VERIFY_FIRMWARE - help - If this is set, the verstage returns back to the bootblock instead of - exits to the romstage so that the verstage space can be reused by the - romstage. Useful if a ram space is too small to fit both the verstage - and the romstage. - config VBOOT_DISABLE_DEV_ON_RECOVERY bool "Disable dev mode on recovery requests" default n @@ -46,15 +50,20 @@ config VBOOT_DISABLE_DEV_ON_RECOVERY developer mode as soon as recovery request is detected. This is handy on embedded devices with limited input capabilities. -config VERSTAGE_IN_BOOTBLOCK +config SEPARATE_VERSTAGE bool default n depends on VBOOT_VERIFY_FIRMWARE -config SEPARATE_VERSTAGE +config RETURN_FROM_VERSTAGE bool - default !VERSTAGE_IN_BOOTBLOCK - depends on VBOOT_VERIFY_FIRMWARE + default n + depends on SEPARATE_VERSTAGE + help + If this is set, the verstage returns back to the calling stage instead + of exiting to the succeeding stage so that the verstage space can be + reused by the succeeding stage. This is useful if a ram space is too + small to fit both the verstage and the succeeding stage. # These VBOOT_X_INDEX are the position of X in FW_MAIN_A/B region. The index # table is created by cros_bundle_firmware at build time based on the positions diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index b2d2dc1..4c53aed 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -63,5 +63,9 @@ fallback/verstage-file = $(objcbfs)/verstage.elf fallback/verstage-type = stage fallback/verstage-compression = none else +ifeq ($(VBOOT_STARTS_IN_BOOTBLOCK),y) bootblock-srcs += $(objgenerated)/libverstage.a +else +romstage-srcs += $(objgenerated)/libverstage.a endif +endif # CONFIG_SEPARATE_VERSTAGE

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New patch to review for coreboot: 9299829 vboot: move Kconfig options for stage indicies
by Aaron Durbin 29 Apr '15

29 Apr '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10023 -gerrit commit 92998295f77ecd470497c40cd58e3be258e0a9bb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 28 16:02:17 2015 -0500 vboot: move Kconfig options for stage indicies With vboot1 out of the way place all the associated Kconfig options in vboot2's Kconfig file (excluding main vboot verify option). More options will be added to accomodate vboot's various combinations of use cases. Change-Id: I17b06d741a36a5e2fefb2757651a61bfed61ae1e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/Kconfig | 37 --------------------------- src/vendorcode/google/chromeos/vboot2/Kconfig | 37 +++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index a75237e..90e3505 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -140,43 +140,6 @@ config VBOOT_VERIFY_FIRMWARE Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the components of the firmware (stages, payload, etc). -# These VBOOT_X_INDEX are the position of X in FW_MAIN_A/B region. The index -# table is created by cros_bundle_firmware at build time based on the positions -# of the blobs listed in fmap.dts and stored at the top of FW_MAIN_A/B region. -# Unfortunately, there is no programmatical link between the blob list and the -# index number here. -config VBOOT_BOOT_LOADER_INDEX - hex "Bootloader component index" - default 0 - depends on VBOOT_VERIFY_FIRMWARE - help - This is the index of the bootloader component in the verified - firmware block. - -config VBOOT_REFCODE_INDEX - hex "Reference code firmware index" - default 1 - depends on VBOOT_VERIFY_FIRMWARE - help - This is the index of the reference code component in the verified - firmware block. - -config VBOOT_RAMSTAGE_INDEX - hex "Ramstage component index" - default 1 - depends on VBOOT_VERIFY_FIRMWARE - help - This is the index of the ramstage component in the verified - firmware block. - -config VBOOT_ROMSTAGE_INDEX - hex "Romstage component index" - default 2 - depends on VBOOT_VERIFY_FIRMWARE - help - This is the index of the romstage component in the verified - firmware block. - config NO_TPM_RESUME bool default n diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig index b27b5b7..3b5c594 100644 --- a/src/vendorcode/google/chromeos/vboot2/Kconfig +++ b/src/vendorcode/google/chromeos/vboot2/Kconfig @@ -55,3 +55,40 @@ config SEPARATE_VERSTAGE bool default !VERSTAGE_IN_BOOTBLOCK depends on VBOOT_VERIFY_FIRMWARE + +# These VBOOT_X_INDEX are the position of X in FW_MAIN_A/B region. The index +# table is created by cros_bundle_firmware at build time based on the positions +# of the blobs listed in fmap.dts and stored at the top of FW_MAIN_A/B region. +# Unfortunately, there is no programmatical link between the blob list and the +# index number here. +config VBOOT_ROMSTAGE_INDEX + hex "Romstage component index" + default 2 + depends on VBOOT_VERIFY_FIRMWARE + help + This is the index of the romstage component in the verified + firmware block. + +config VBOOT_RAMSTAGE_INDEX + hex "Ramstage component index" + default 1 + depends on VBOOT_VERIFY_FIRMWARE + help + This is the index of the ramstage component in the verified + firmware block. + +config VBOOT_REFCODE_INDEX + hex "Reference code firmware index" + default 1 + depends on VBOOT_VERIFY_FIRMWARE + help + This is the index of the reference code component in the verified + firmware block. + +config VBOOT_BOOT_LOADER_INDEX + hex "Bootloader component index" + default 0 + depends on VBOOT_VERIFY_FIRMWARE + help + This is the index of the bootloader component in the verified + firmware block.

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New patch to review for coreboot: c858818 program loading: add optional is_loader_active() callback
by Aaron Durbin 29 Apr '15

29 Apr '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10022 -gerrit commit c85881827fcfb58f1110c2621074a7af2afbd6fc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 28 15:59:12 2015 -0500 program loading: add optional is_loader_active() callback Add a way for a loader to indicate if it is active. Such users of this callback would be vboot which can indicate to the rest of the system that it isn't active. is_loader_active() also gives vboot a chance to perform the necessary work to make said decision. Change-Id: I6679ac75b19bb1bfff9c2b709da5591986f752ff Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/program_loading.h | 3 +++ src/lib/loaders/load_and_run_payload.c | 17 +++++++++++++++++ src/lib/loaders/load_and_run_ramstage.c | 19 ++++++++++++++++++- src/lib/loaders/load_and_run_romstage.c | 17 ++++++++++++++++- 4 files changed, 54 insertions(+), 2 deletions(-) diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 02e6f5f..ca80b0e 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -103,6 +103,9 @@ void platform_prog_run(struct prog *prog); struct prog_loader_ops { const char *name; + /* Determine if the loader is the active one. If so returns 1 else 0 + * or < 0 on error. */ + int (*is_loader_active)(struct prog *prog); /* Returns < 0 on error or 0 on success. This function needs to do * different things depending on the prog type. See definition * of struct prog above. */ diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 0e08d88..7a08097 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -54,7 +54,24 @@ void payload_load(void) struct prog *payload = &global_payload; for (i = 0; i < ARRAY_SIZE(payload_ops); i++) { + /* Default loader state is active. */ + int ret = 1; + ops = payload_ops[i]; + + if (ops->is_loader_active != NULL) + ret = ops->is_loader_active(payload); + + if (ret == 0) { + printk(BIOS_DEBUG, "%s payload loader inactive.\n", + ops->name); + continue; + } else if (ret < 0) { + printk(BIOS_DEBUG, "%s payload loader failure.\n", + ops->name); + continue; + } + if (ops->prepare(payload) < 0) { printk(BIOS_DEBUG, "%s: could not locate payload.\n", ops->name); diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c index 153e38e..fddea4d 100644 --- a/src/lib/loaders/load_and_run_ramstage.c +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -83,8 +83,25 @@ void run_ramstage(void) run_ramstage_from_resume(romstage_handoff_find_or_add(), &ramstage); for (i = 0; i < ARRAY_SIZE(loaders); i++) { + /* Default loader state is active. */ + int ret = 1; + ops = loaders[i]; - printk(BIOS_DEBUG, "Trying %s ramstage loader.\n", ops->name); + + if (ops->is_loader_active != NULL) + ret = ops->is_loader_active(&ramstage); + + if (ret == 0) { + printk(BIOS_DEBUG, "%s ramstage loader inactive.\n", + ops->name); + continue; + } else if (ret < 0) { + printk(BIOS_DEBUG, "%s ramstage loader failure.\n", + ops->name); + continue; + } + + printk(BIOS_DEBUG, "%s ramstage loader active.\n", ops->name); load_ramstage(ops, &ramstage); } diff --git a/src/lib/loaders/load_and_run_romstage.c b/src/lib/loaders/load_and_run_romstage.c index 1c2ed77..b54bfc7 100644 --- a/src/lib/loaders/load_and_run_romstage.c +++ b/src/lib/loaders/load_and_run_romstage.c @@ -41,11 +41,26 @@ void run_romstage(void) }; for (i = 0; i < ARRAY_SIZE(loaders); i++) { + /* Default loader state is active. */ + int ret = 1; const struct prog_loader_ops *ops; ops = loaders[i]; - printk(BIOS_DEBUG, "Trying %s romstage loader.\n", ops->name); + if (ops->is_loader_active != NULL) + ret = ops->is_loader_active(&romstage); + + if (ret == 0) { + printk(BIOS_DEBUG, "%s romstage loader inactive.\n", + ops->name); + continue; + } else if (ret < 0) { + printk(BIOS_DEBUG, "%s romstage loader failure.\n", + ops->name); + continue; + } + + printk(BIOS_DEBUG, "%s romstage loader active.\n", ops->name); timestamp_add_now(TS_START_COPYROM);

1 0

Patch merged into coreboot/master: f394715 gitconfig: Use the right make executable in git hooks
by gerrit＠coreboot.org 28 Apr '15

28 Apr '15

the following patch was just integrated into master: commit f3947152775e3b13c7bec25aac30bec602d1e14e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Apr 28 21:36:11 2015 +0200 gitconfig: Use the right make executable in git hooks When installing git hooks through $(MAKE) gitconfig, make knows itself (and is a GNU make). So let it splice itself into hooks where necessary by replacing %MAKE%. Change-Id: Iaf778bfa3f17a8fe31312f871571ed89a9de5385 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10018 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10018 for details. -gerrit

1 0

Patch merged into coreboot/master: 7cb26b4 buildgcc: OpenBSD's tar and patch are sufficient, too
by gerrit＠coreboot.org 28 Apr '15

28 Apr '15

the following patch was just integrated into master: commit 7cb26b4a6e8a413ff3d9d07966b63afbfcdb6749 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Apr 28 21:29:22 2015 +0200 buildgcc: OpenBSD's tar and patch are sufficient, too No need to enforce GNU versions for them. Change-Id: Ieeb43298331fbefbcc1e230d41a90e9df56993eb Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10017 for details. -gerrit

1 0

New patch to review for coreboot: 3ae9b80 Use __ROMSTAGE__ to denote romstage
by Patrick Georgi 28 Apr '15

28 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10020 -gerrit commit 3ae9b802e064c70e003bedd89bd56e41d0b7207e Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Apr 28 22:43:31 2015 +0200 Use __ROMSTAGE__ to denote romstage There were some remaining places that used __PRE_RAM__ for romstage, while it really means 'bootblock or romstage'. Change-Id: Id9ba0486ee56ea4a27425d826a9256cc20f5b518 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/x86/Makefile.inc | 4 ++-- src/include/rules.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a2e68cc..8b37d7a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -182,12 +182,12 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h printf " ROMCC romstage.inc\n" - $(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@ + $(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@ else $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" - $(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ + $(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc @printf " POST romstage.inc\n" diff --git a/src/include/rules.h b/src/include/rules.h index 3f5262c..1a27fc6 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -31,7 +31,7 @@ #define ENV_SECMON 0 #define ENV_VERSTAGE 0 -#elif defined(__PRE_RAM__) +#elif defined(__ROMSTAGE__) #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 1 #define ENV_RAMSTAGE 0

1 0

Patch set updated for coreboot: c067319 [Do not Merge] try to add 945G based board here is the serial log: https://www.dropbox.com/s/8imkvxm8xnozmhd/log.txt?dl=0 "Memory will be driven at 667MHz with CAS=5 clocks" is wrong
by HAOUAS Elyes 28 Apr '15

28 Apr '15

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9971 -gerrit commit c06731973e4b76a0579a4b83b44ee6bca5c60818 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Apr 23 12:10:17 2015 +0200 [Do not Merge] try to add 945G based board here is the serial log: https://www.dropbox.com/s/8imkvxm8xnozmhd/log.txt?dl=0 "Memory will be driven at 667MHz with CAS=5 clocks" is wrong Change-Id: I97401a39a958a17f2f9120539362e3fa7819a742 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/nec/945g-m4/Kconfig | 42 +++++ src/mainboard/nec/945g-m4/Kconfig.name | 2 + src/mainboard/nec/945g-m4/acpi/ec.asl | 1 + src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl | 83 +++++++++ src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl | 103 ++++++++++++ src/mainboard/nec/945g-m4/acpi/platform.asl | 90 ++++++++++ src/mainboard/nec/945g-m4/acpi/superio.asl | 92 ++++++++++ src/mainboard/nec/945g-m4/acpi/thermal.asl | 94 +++++++++++ src/mainboard/nec/945g-m4/acpi/video.asl | 43 +++++ src/mainboard/nec/945g-m4/acpi_tables.c | 77 +++++++++ src/mainboard/nec/945g-m4/board_info.txt | 7 + src/mainboard/nec/945g-m4/cmos.layout | 194 +++++++++++++++++++++ src/mainboard/nec/945g-m4/devicetree.cb | 116 +++++++++++++ src/mainboard/nec/945g-m4/dsdt.asl | 44 +++++ src/mainboard/nec/945g-m4/hda_verb.c | 5 + src/mainboard/nec/945g-m4/irq_tables.c | 61 +++++++ src/mainboard/nec/945g-m4/mainboard.c | 94 +++++++++++ src/mainboard/nec/945g-m4/mptable.c | 106 ++++++++++++ src/mainboard/nec/945g-m4/romstage.c | 204 +++++++++++++++++++++++ src/mainboard/nec/945g-m4/smihandler.c | 49 ++++++ src/mainboard/nec/945g-m4/superio_hwm.c | 161 ++++++++++++++++++ src/mainboard/nec/945g-m4/superio_hwm.h | 25 +++ src/northbridge/intel/i945/gma.c | 14 +- src/northbridge/intel/i945/raminit.c | 37 +++- 24 files changed, 1730 insertions(+), 14 deletions(-) diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig new file mode 100644 index 0000000..791a8f9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/Kconfig @@ -0,0 +1,42 @@ +if BOARD_NEC_945G_M4 +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627EHG + select HAVE_ACPI_TABLES + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + +config MAINBOARD_DIR + string + default nec/945g-m4 + +config MAINBOARD_PART_NUMBER + string + default "945G-M4" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 4 + +#config VGA_BIOS_FILE +# string +# default "amipci_01.20" +endif # BOARD_NEC_945G_M4 diff --git a/src/mainboard/nec/945g-m4/Kconfig.name b/src/mainboard/nec/945g-m4/Kconfig.name new file mode 100644 index 0000000..46571f0 --- /dev/null +++ b/src/mainboard/nec/945g-m4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_NEC_945G_M4 + bool "945G-M" diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl new file mode 100644 index 0000000..8f20f9d --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ec.asl @@ -0,0 +1 @@ +//to make the compiler happy diff --git a/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..fb57b5e --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for i945G */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 10 }, + Package() { 0x0001ffff, 1, 0, 11 }, + Package() { 0x0001ffff, 2, 0, 12 }, + Package() { 0x0001ffff, 3, 0, 13 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 10 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 10 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 10 }, + Package() { 0x001cffff, 1, 0, 11 }, + Package() { 0x001cffff, 2, 0, 12 }, + Package() { 0x001cffff, 3, 0, 13 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 17 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 13 }, + Package() { 0x001dffff, 3, 0, 12 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 11 }, + Package() { 0x001effff, 1, 0, 24 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 12 }, + Package() { 0x001fffff, 1, 0, 13 }, + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..c108d3f --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16}, + + Package() { 0x0001ffff, 0, 0, 20}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 22}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 21}, + Package() { 0x0002ffff, 1, 0, 22}, + Package() { 0x0002ffff, 2, 0, 23}, + Package() { 0x0002ffff, 3, 0, 20}, + + Package() { 0x0003ffff, 0, 0, 22}, + Package() { 0x0003ffff, 1, 0, 23}, + Package() { 0x0003ffff, 2, 0, 20}, + Package() { 0x0003ffff, 3, 0, 21}, + + Package() { 0x0004ffff, 0, 0, 23}, + Package() { 0x0004ffff, 1, 0, 20}, + Package() { 0x0004ffff, 2, 0, 21}, + Package() { 0x0004ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 19}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 17}, + Package() { 0x0005ffff, 3, 0, 16}, + + Package() { 0x0006ffff, 0, 0, 18}, + Package() { 0x0006ffff, 1, 0, 17}, + Package() { 0x0006ffff, 2, 0, 16}, + Package() { 0x0006ffff, 3, 0, 19}, + + Package() { 0x0009ffff, 0, 0, 21}, + Package() { 0x0009ffff, 1, 0, 22}, + Package() { 0x0009ffff, 2, 0, 23}, + Package() { 0x0009ffff, 3, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} + diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl new file mode 100644 index 0000000..6770348 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/platform.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl new file mode 100644 index 0000000..997a33a --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/superio.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + Name(_DDN, "COM1") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + Name(_DDN, "COM2") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl new file mode 100644 index 0000000..d1774d4 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x64) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (0xf5c) // Value for Rocky + } + + // Method (_AC1, 0, Serialized) + // { + // Return (0xf5c) + // } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (Add (0x0aac, 0x50)) // FIXME + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (0xaaf) // FIXME + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + Return (0xaac) // FIXME + } + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU1, \_PR.CPU2}) + } + Return (Package() {\_PR.CPU1}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/video.asl b/src/mainboard/nec/945g-m4/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c new file mode 100644 index 0000000..dba2953 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi_tables.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> + +#include "southbridge/intel/i82801gx/nvs.h" +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt new file mode 100644 index 0000000..8c6f8c8 --- /dev/null +++ b/src/mainboard/nec/945g-m4/board_info.txt @@ -0,0 +1,7 @@ +Board name:945G-M4 (Rev: B) +Category: µATX 24.4 cm x 24.4 cm Form Factor +Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=d… +ROM package: PLCC +ROM protocol: FWH +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/nec/945g-m4/cmos.layout b/src/mainboard/nec/945g-m4/cmos.layout new file mode 100644 index 0000000..b3e8c4e --- /dev/null +++ b/src/mainboard/nec/945g-m4/cmos.layout @@ -0,0 +1,194 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 40 r 0 unused + +# coreboot config options: mainboard specific options +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature + +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 + +#971 13 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# Fan Cruise Control +8 0 Disabled +8 1 Speed +#8 2 Thermal +# Fan Speed (Rotations per Minute) +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 +# +# Temperature (�C/�F) +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb new file mode 100644 index 0000000..550195d --- /dev/null +++ b/src/mainboard/nec/945g-m4/devicetree.cb @@ -0,0 +1,116 @@ +chip northbridge/intel/i945 + device cpu_cluster 0 on + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + end + device domain 0 on + device pci 00.0 on end # 82945G/GZ/P/PL Memory Controller Hub [8086:2770] + device pci 02.0 on end # 82945G/GZ Integrated Graphics Controller [8086:2772] + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x8a" + register "pirqb_routing" = "0x85" + register "pirqc_routing" = "0x8a" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x87" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x1" + + device pci 1c.0 on end # PCI Express Gigabit Ethernet Controller [10ec:8168] + device pci 1d.0 on end # NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] + device pci 1d.1 on end # NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9] + device pci 1d.2 on end # NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca] + device pci 1d.3 on end # NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb] + device pci 1d.7 on end # NM10/ICH7 Family USB2 EHCI Controller [8086:27cc] + device pci 1e.0 on end # 82801 PCI Bridge [8086:244e] + device pci 1e.2 on end # 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de] + device pci 1f.0 on # 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] + + chip superio/winbond/w83627ehg # Super I/O Winbond + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.5 on # Keyboard + end + + device pnp 2e.106 on # Serial flash interface + io 0x60 = 0x100 + end + + device pnp 2e.007 on # GPIO 1 + end + + device pnp 2e.107 off # Game port + io 0x60 = 0x201 + end + + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + + device pnp 2e.307 on # GPIO 6 + end + + device pnp 2e.8 off # WDTO#, PLED + end + + device pnp 2e.009 on # GPIO 2 + end + + device pnp 2e.109 on # GPIO 3 + end + + device pnp 2e.209 on # GPIO 4 + end + + device pnp 2e.309 on # GPIO 5 + end + + device pnp 2e.a on # ACPI + end + + device pnp 2e.b on # Hardware monitor + io 0x60 = 0xa10 + irq 0x70 = 0 + end + + end # Winbond + end # LPC + + device pci 1f.1 on end # 82801G (ICH7 Family) IDE Controller [8086:27df] + device pci 1f.2 on end # NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0] + device pci 1f.3 on end # NM10/ICH7 Family SMBus Controller [8086:27da] + end # i82801gx + end # domain 0 +end diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl new file mode 100644 index 0000000..05a93d3 --- /dev/null +++ b/src/mainboard/nec/945g-m4/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("dsdt.aml", "DSDT", 1, "COREv4", "COREBOOT", 0x00000108) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + //#include "acpi/platform.asl" + + // General Purpose Events + //#include "acpi/gpe.asl" + + //#include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/nec/945g-m4/hda_verb.c b/src/mainboard/nec/945g-m4/hda_verb.c new file mode 100644 index 0000000..aaa0a93 --- /dev/null +++ b/src/mainboard/nec/945g-m4/hda_verb.c @@ -0,0 +1,5 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; +const u32 pc_beep_verbs[0] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/nec/945g-m4/irq_tables.c b/src/mainboard/nec/945g-m4/irq_tables.c new file mode 100644 index 0000000..4b050fe --- /dev/null +++ b/src/mainboard/nec/945g-m4/irq_tables.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 14, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xb, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1e << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x60, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x1b << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0}, + {0x03, (0x03 << 3) | 0x0, {{0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x4, 0x0}, + {0x03, (0x04 << 3) | 0x0, {{0x62, 0xdcf8}, {0x6b, 0xdcf8}, {0x60, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0}, + {0x03, (0x05 << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x6, 0x0}, + {0x03, (0x01 << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x1, 0x0}, + {0x03, (0x02 << 3) | 0x0, {{0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x2, 0x0}, + {0x03, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/nec/945g-m4/mainboard.c b/src/mainboard/nec/945g-m4/mainboard.c new file mode 100644 index 0000000..d872d95 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mainboard.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include "superio_hwm.h" + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f35: /* Boot Display */ + X86_AX = 0x005f; // Success + X86_CL = BOOT_DISPLAY_DEFAULT; + break; + case 0x5f40: /* Boot Panel Type */ + // M.x86.R_AX = 0x015f; // Supported but failed + X86_AX = 0x005f; // Success + X86_CL = 3; // Display ID + break; + default: + /* Interrupt was not handled */ + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif +/* Audio Setup */ + +extern u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + // Default VERB is fine on this mainboard. + cim_verb_data = NULL; + cim_verb_data_size = 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +// hwm_setup(); /* commented while debugging */ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/nec/945g-m4/mptable.c b/src/mainboard/nec/945g-m4/mptable.c new file mode 100644 index 0000000..7276028 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mptable.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#define INTA 0x00 +#define INTB 0x01 +#define INTC 0x02 +#define INTD 0x03 +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LOCAL_APIC_ADDR); + smp_write_processors(mc); + /* Bus: Bus ID Type */ + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 2, "PCI "); + my_smp_write_bus(mc, 3, "PCI "); + my_smp_write_bus(mc, 4, "ISA "); + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 0x1, 0x20, VIO_APIC_VADDR); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x1, 0x1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x3, 0x1, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x4, 0x1, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x6, 0x1, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x7, 0x1, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x1, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x9, 0x1, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xc, 0x1, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xd, 0x1, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xe, 0x1, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xf, 0x1, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x01 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1e << 2) | INTA, 0x1, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x1, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x02 << 2) | INTA, 0x1, 0x13); + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); +/* mptable_lintsrc(mc, isa_bus); */ + /* Compute the checksums */ + return mptable_finalize(mc); +} +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 1); + return (unsigned long)smp_write_config_table(v); +} +/*MP Config Extended Table Entries: +-- +System Address Space + bus ID: 0 address type: I/O address + address base: 0x600000000000 + address range: 0x148000000000 +Extended Table HOSED! +*/ diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c new file mode 100644 index 0000000..d1e6ed0 --- /dev/null +++ b/src/mainboard/nec/945g-m4/romstage.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/romstage.h> +#include <lib.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <halt.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void setup_ich7_gpios(void) +{ + + printk(BIOS_DEBUG, "GPIOS..."); + /* General Registers */ + outl(0x1f9fffc3, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xebffffbf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x0000af03, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000000f7, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(LPC_DEV, 0x64, 0xd0); + // LPC I/O decode range + pci_write_config16(LPC_DEV, 0x80, 0x0010); + // LPC Interface Enables + pci_write_config16(LPC_DEV, 0x82, 0x340f); + // GEN1_DEC. LPC interface generic decode Rang1 + pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); + // GEN2_DEC. LPC interface generic decode Rang2 + pci_write_config32(LPC_DEV, 0x88, 0x00fc4701); + +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(RC) |= (1 << 2);// to check if we need to enable it once again on RAM init + RCBA32(D31IP) = 0x42210; + RCBA32(D30IP) = 0x2100; + RCBA32(D29IP) = 0x10004321; + RCBA32(D28IP) = 0x214321; + RCBA32(D27IP) = 1; + RCBA16(D31IR) = 0x0132; + RCBA16(D30IR) = 0x0146; + RCBA32(D29IR) = 0x0237; + RCBA32(D28IR) = 0x3201; + RCBA32(D27IR) = 0x0146; + reg32 = RCBA32(0x020c); + reg32 &= 0x7fc0c0c0; + reg32 |= 0x10804; + RCBA32(0x020c)= reg32; + reg32 = RCBA32(RPC + 4); + reg32 &= 0xebffffff; + reg32 |= 0x28000000; + RCBA32(RPC + 4) = reg32; + RCBA32(0x214) = 0x10030549; + RCBA32(0x218) = 0x00020504; + RCBA32(0x220 /*BCR*/) = 0xffffffc5; + reg32 = RCBA32(0x2024 /*CIR6*/); + reg32 &= 0xffffff; + reg32 |= 0xd000000; + RCBA32(0x2024 /*CIR6*/) = reg32; + RCBA32(0x1ac) |= 2; + reg32 = RCBA32(0x200 /*CIR4*/); + reg32 &= 0xc1d0e0c8; + reg32 |= 0x1102008; + RCBA32(0x200 /*CIR4*/) = reg32; + RCBA16(0x208c) |= 0xf0000; + RCBA16(0x20ac) |= 0xf0000; + RCBA16(0x20cc) |= 0xf0000; + RCBA16(0x20ec) |= 0xf0000; + reg8 = RCBA8(0x3430 /*CIR8*/); + reg8 &= 0xfc; + reg8 |= 1; + RCBA8(0x3430 /*CIR8*/) = reg8; + RCBA32(GCS) |= (1 << 2); + RCBA32(0x0088 /*CIR1*/) |= 0x0011d000; + RCBA16(0x01fc /*CIR3*/) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + + reg32 = RCBA32(0x3410 /*GCS*/); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + RCBA32(FD /*0x3418*/) |= (1 << 0); + RCBA32(0x3418/*FD*/) |= (1 << 0); + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + RCBA32(HPTC /*0x3404*/) = 0x80; + //reg32 = RCBA32(0x2034 /*CIR7*/); + //reg32 &= ~(0x0f << 16); + //reg32 |= (5 << 16); + //RCBA32(0x2034 /*CIR7*/) = reg32; +} + +void main(unsigned long bist) +{ + int s3resume = 0; +device_t dev; + if (bist == 0) + enable_lapic(); + + ich7_enable_lpc(); + /* Set up the console */ +// winbond_enable_serial(SERIAL_DEV,CONFIG_TTYS0_BASE); + + dev=PNP_DEV(0x2e, W83627EHG_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + + console_init(); + + report_bist_failure(bist); + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + halt(); + } + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + + i945_early_initialization(); + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(s3resume ? 2 : 0, NULL); + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); + +} diff --git a/src/mainboard/nec/945g-m4/smihandler.c b/src/mainboard/nec/945g-m4/smihandler.c new file mode 100644 index 0000000..d1f4f7b --- /dev/null +++ b/src/mainboard/nec/945g-m4/smihandler.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801gx/nvs.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + gnvs->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c new file mode 100644 index 0000000..622f8e8 --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#include <arch/io.h> +#include <pc80/mc146818rtc.h> + +#include "superio_hwm.h" + +/* Hardware Monitor */ + +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 + +#define FAN_SPEED_5625 0 +//#define FAN_TEMPERATURE_30DEGC 0 + +#define HWM_BASE 0x290 + +static void hwm_write(u8 reg, u8 value) +{ + outb(reg, HWM_BASE + 0x05); // Index port + outb(value, HWM_BASE + 0x06); // Data port +} + +static void hwm_bank(u8 bank) +{ + hwm_write(0x2e, bank); +} + +struct fan_speed { + u8 fan_in; + u16 fan_speed; +}; + +// FANIN Target Speed Register +// FANIN = 337500 / RPM +struct fan_speed fan_speeds[] = { + { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, + { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, + { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, + { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } +}; + +struct temperature { + u8 deg_celsius; + u8 deg_fahrenheit; +}; + +struct temperature temperatures[] = { + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, + { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, + { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } +}; + +void hwm_setup(void) +{ + int cpufan_control = 0, sysfan_control = 0; + int cpufan_speed = 0, sysfan_speed = 0; + int cpufan_temperature = 0, sysfan_temperature = 0; + + if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) + cpufan_speed = FAN_SPEED_5625; + //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + + if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) + sysfan_speed = FAN_SPEED_5625; + //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + + // hwm_write(0x31, 0x20); // AVCC high limit + // hwm_write(0x34, 0x06); // VIN2 low limit + + hwm_bank(0); + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + + hwm_bank(4); + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset + + hwm_bank(0x80); // Default + + u8 fan_config = 0; + // 00 FANOUT is Manual Mode + // 01 FANOUT is Thermal Cruise Mode + // 10 FANOUT is Fan Speed Cruise Mode + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + } + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + } + // This register must be written first + hwm_write(0x04, fan_config); + + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + break; + } + + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + break; + } + + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time + + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + + hwm_write(0x40, 0x01); // Init, but no SMI# +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h new file mode 100644 index 0000000..346b97c --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_HWM_H +#define SUPERIO_HWM_H + +void hwm_setup(void); + +#endif /* SUPERIO_HWM_H */ diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index e5f2d35..4f3cdf2 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -519,23 +519,27 @@ static struct device_operations gma_func1_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short pci_device_ids[] = { +static const unsigned short i945_gma_func0_ids[] = { 0x2772, - 0x2776, 0x27a2, - 0x27a6, 0x27ae, 0 }; +static const unsigned short i945_gma_func1_ids[] = { + 0x2776, + 0x27a6, + 0 +}; + static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .devices = i945_gma_func0_ids, }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .devices = i945_gma_func1_ids, }; diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index bd6e0c9..1b8ccf0 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2326,18 +2326,32 @@ static void sdram_pre_jedec_initialization(void) u32 reg32; reg32 = MCHBAR32(WCC); - reg32 &= 0x113ff3ff; - reg32 |= (4 << 29) | (3 << 25) | (1 << 10); - MCHBAR32(WCC) = reg32; + if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770) + { + reg32 &= 0xf3fff7ff; + reg32 |= (1 << 25) | (3 << 22) | (1 << 10); + MCHBAR32(WCC) = reg32; + MCHBAR32(MMARB0) |= (3 << 7)|(3 << 8); + MCHBAR32(MMARB1) |= (1 << 18)|(3 << 12); + if (pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4) & 0x2000 && pci_read_config32(PCI_DEV(0, 0x00,0), 0x54) & 8) + { + MCHBAR32(MMARB1) &= ~(7 << 8); + } + MCHBAR32(MMARB1 +4) |= (3 << 12); + } else { + reg32 &= 0x113ff3ff; + reg32 |= (4 << 29) | (3 << 25) | (1 << 10); - MCHBAR32(SMVREFC) |= (1 << 6); + MCHBAR32(WCC) = reg32; - MCHBAR32(MMARB0) &= ~(3 << 17); - MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16); + MCHBAR32(SMVREFC) |= (1 << 6); - MCHBAR32(MMARB1) &= ~(7 << 8); - MCHBAR32(MMARB1) |= (3 << 8); + MCHBAR32(MMARB0) &= ~(3 << 17); + MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16); + MCHBAR32(MMARB1) &= ~(7 << 8); + MCHBAR32(MMARB1) |= (3 << 8); + } /* Adaptive Idle Timer Control */ MCHBAR32(C0AIT) = 0x000006c4; MCHBAR32(C0AIT+4) = 0x871a066d; @@ -2617,6 +2631,11 @@ static void sdram_power_management(struct sys_info *sysinfo) reg8 |= (1 << 2); pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8); +if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770) { + MCHBAR16(MIPMC4) |= 0x6000; + MCHBAR16(MIPMC5) |= 0x6000; + MCHBAR16(MIPMC6) |= 0x6000; +}else{ #ifdef C2_SELF_REFRESH_DISABLE if (integrated_graphics) { @@ -2641,7 +2660,7 @@ static void sdram_power_management(struct sys_info *sysinfo) } #endif - +} reg32 = MCHBAR32(PMCFG); reg32 &= ~(3 << 17); reg32 |= (2 << 17);

1 0

New patch to review for coreboot: e4bcccb rules.h: add verstage macro
by Patrick Georgi 28 Apr '15

28 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10019 -gerrit commit e4bcccb346deac93bfbefbe77fb76191ed2ae629 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Apr 28 22:26:23 2015 +0200 rules.h: add verstage macro Change-Id: I5ba32e80a825a1f86d0e32da23e5fa0a2d85f4cd Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/include/rules.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/include/rules.h b/src/include/rules.h index a99d3e2..3f5262c 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -29,6 +29,7 @@ #define ENV_RAMSTAGE 0 #define ENV_SMM 0 #define ENV_SECMON 0 +#define ENV_VERSTAGE 0 #elif defined(__PRE_RAM__) #define ENV_BOOTBLOCK 0 @@ -36,6 +37,7 @@ #define ENV_RAMSTAGE 0 #define ENV_SMM 0 #define ENV_SECMON 0 +#define ENV_VERSTAGE 0 #elif defined(__SMM__) #define ENV_BOOTBLOCK 0 @@ -43,6 +45,7 @@ #define ENV_RAMSTAGE 0 #define ENV_SMM 1 #define ENV_SECMON 0 +#define ENV_VERSTAGE 0 #elif defined(__SECMON__) #define ENV_BOOTBLOCK 0 @@ -50,6 +53,15 @@ #define ENV_RAMSTAGE 0 #define ENV_SMM 0 #define ENV_SECMON 1 +#define ENV_VERSTAGE 0 + +#elif defined(__VERSTAGE__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_SECMON 0 +#define ENV_VERSTAGE 1 #else #define ENV_BOOTBLOCK 0 @@ -57,6 +69,7 @@ #define ENV_RAMSTAGE 1 #define ENV_SMM 0 #define ENV_SECMON 0 +#define ENV_VERSTAGE 0 #endif /* For romstage and ramstage always build with simple device model, ie.

1 0

Patch set updated for coreboot: a731aa8 kbuild: automatically include SOCs
by Stefan Reinauer 28 Apr '15

28 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9799 -gerrit commit a731aa8db264e38ed445ff041cb097f43f19211f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 27 14:03:57 2015 -0700 kbuild: automatically include SOCs This change switches all SOC vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in soc/Makefile.inc or in soc/<vendor>/Makefile.inc. This means, vendor and SOC directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 2 +- src/soc/Makefile.inc | 12 ------------ src/soc/broadcom/Makefile.inc | 20 -------------------- src/soc/broadcom/cygnus/Makefile.inc | 4 ++++ src/soc/imgtec/Makefile.inc | 1 - src/soc/imgtec/pistachio/Makefile.inc | 3 +++ src/soc/intel/Makefile.inc | 3 --- src/soc/intel/baytrail/Makefile.inc | 5 ++++- src/soc/intel/broadwell/Makefile.inc | 5 ++++- src/soc/intel/common/Makefile.inc | 4 ++++ src/soc/intel/fsp_baytrail/Makefile.inc | 5 +++++ src/soc/marvell/Makefile.inc | 20 -------------------- src/soc/marvell/bg4cd/Makefile.inc | 4 ++++ src/soc/nvidia/Makefile.inc | 2 -- src/soc/nvidia/tegra124/Makefile.inc | 4 ++++ src/soc/nvidia/tegra132/Makefile.inc | 4 ++++ src/soc/qualcomm/Makefile.inc | 1 - src/soc/qualcomm/ipq806x/Makefile.inc | 4 ++++ src/soc/rockchip/Makefile.inc | 20 -------------------- src/soc/rockchip/rk3288/Makefile.inc | 4 ++++ src/soc/samsung/Makefile.inc | 2 -- src/soc/samsung/exynos5250/Makefile.inc | 4 ++++ src/soc/samsung/exynos5420/Makefile.inc | 4 ++++ src/soc/ucb/Makefile.inc | 1 - src/soc/ucb/riscv/Makefile.inc | 5 ++++- 25 files changed, 57 insertions(+), 86 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 4bcee0d..49db1fc 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs # root source directories of coreboot subdirs-y := src/lib src/console src/device subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) -subdirs-y += src/soc +subdirs-y += $(wildcard src/soc/*/*) subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom subdirs-y += $(wildcard src/arch/*) diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc deleted file mode 100644 index bbcfd2c..0000000 --- a/src/soc/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -################################################################################ -## Subdirectories -################################################################################ -subdirs-y += broadcom -subdirs-y += imgtec -subdirs-y += intel -subdirs-y += marvell -subdirs-y += nvidia -subdirs-y += qualcomm -subdirs-y += rockchip -subdirs-y += samsung -subdirs-y += ucb diff --git a/src/soc/broadcom/Makefile.inc b/src/soc/broadcom/Makefile.inc deleted file mode 100644 index 165f923..0000000 --- a/src/soc/broadcom/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2015 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOC_BROADCOM_CYGNUS) += cygnus diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc index 4e09bed..cfec7d4 100644 --- a/src/soc/broadcom/cygnus/Makefile.inc +++ b/src/soc/broadcom/cygnus/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOC_BROADCOM_CYGNUS),y) + bootblock-y += bootblock.c bootblock-y += cbmem.c bootblock-y += i2c.c @@ -102,3 +104,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.tmp \ $(objutil)/broadcom/secimage/secimage -out $@ \ -config util/broadcom/unauth.cfg \ -hmac util/broadcom/khmacsha256 -bl $< + +endif diff --git a/src/soc/imgtec/Makefile.inc b/src/soc/imgtec/Makefile.inc deleted file mode 100644 index 60a9909..0000000 --- a/src/soc/imgtec/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_CPU_IMGTEC_PISTACHIO) += pistachio diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index 0a3d456..010ddb6 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -19,6 +19,8 @@ # MA 02110-1301 USA # +ifeq ($(CONFIG_CPU_IMGTEC_PISTACHIO),y) + # We enable CBFS_SPI_WRAPPER for Pistachio targets. bootblock-y += clocks.c bootblock-y += spi.c @@ -55,3 +57,4 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL) @printf " BIMGTOOL $(subst $(obj)/,,$(@))\n" $(BIMGTOOL) $< $@ $(call loadaddr,bootblock) +endif diff --git a/src/soc/intel/Makefile.inc b/src/soc/intel/Makefile.inc deleted file mode 100644 index f86d6ca..0000000 --- a/src/soc/intel/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -subdirs-$(CONFIG_SOC_INTEL_BAYTRAIL) += baytrail -subdirs-$(CONFIG_SOC_INTEL_BROADWELL) += broadwell -subdirs-$(CONFIG_SOC_INTEL_FSP_BAYTRAIL) += fsp_baytrail diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 6d28c78..78e2da6 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,7 +1,8 @@ +ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) + subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage -subdirs-y += ../common subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -102,3 +103,5 @@ mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x mrc.bin-type := mrc PHONY += baytrail_add_me + +endif diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index ec6b9ae..8b4a0c1 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,7 +1,8 @@ +ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) + subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage -subdirs-y += ../common subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -128,3 +129,5 @@ cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) mrc.bin-type := mrc + +endif diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index d340308..46786e2 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,6 +1,10 @@ +ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL)$(CONFIG_SOC_INTEL_BROADWELL),y) + ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c + +endif diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 2dfb9cb..af4871c 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -17,6 +17,9 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + +ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y) + subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic @@ -87,3 +90,5 @@ endif endif endif + +endif diff --git a/src/soc/marvell/Makefile.inc b/src/soc/marvell/Makefile.inc deleted file mode 100644 index ef7bcd9..0000000 --- a/src/soc/marvell/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOC_MARVELL_BG4CD) += bg4cd diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc index 4a58e6f..c433d37 100644 --- a/src/soc/marvell/bg4cd/Makefile.inc +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOC_MARVELL_BG4CD),y) + bootblock-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += bootblock_asm.S bootblock-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += bootblock.c @@ -50,3 +52,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" @mkdir -p $(dir $@) @mv $< $@ + +endif diff --git a/src/soc/nvidia/Makefile.inc b/src/soc/nvidia/Makefile.inc deleted file mode 100644 index 100cb94..0000000 --- a/src/soc/nvidia/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_SOC_NVIDIA_TEGRA124) += tegra124 -subdirs-$(CONFIG_SOC_NVIDIA_TEGRA132) += tegra132 diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 49669eb..78054f4 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOC_NVIDIA_TEGRA124),y) + bootblock-y += bootblock.c bootblock-y += bootblock_asm.S bootblock-y += cbfs.c @@ -102,3 +104,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) $(CBOOTIMAGE) echo "BootLoader = $<,$(call loadaddr,bootblock),$(call loadaddr,bootblock),Complete;" >> $(BCT_WRAPPER) @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" $(CBOOTIMAGE) $(BCT_WRAPPER) $@ + +endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index bfa7088..44976d1 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOC_NVIDIA_TEGRA132),y) + bootblock-y += bootblock.c bootblock-y += bootblock_asm.S bootblock-y += cbfs.c @@ -150,3 +152,5 @@ MTS_FILE_CBFS = mts cbfs-files-y += $(MTS_FILE_CBFS) $(MTS_FILE_CBFS)-file := $(MTS_FILE) $(MTS_FILE_CBFS)-type := raw + +endif diff --git a/src/soc/qualcomm/Makefile.inc b/src/soc/qualcomm/Makefile.inc deleted file mode 100644 index 06b2f2f..0000000 --- a/src/soc/qualcomm/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOC_QC_IPQ806X) += ipq806x diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 6aa10f8..3eb070e 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOC_QC_IPQ806X),y) + bootblock-y += clock.c bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c @@ -88,3 +90,5 @@ mbn-root := 3rdparty/cpu/qualcomm/ipq806x $(foreach f,$(mbn-files),$(eval cbfs-files-y += $(f))\ $(eval $(f)-file := $(mbn-root)/$(f))\ $(eval $(f)-type := raw)) + +endif diff --git a/src/soc/rockchip/Makefile.inc b/src/soc/rockchip/Makefile.inc deleted file mode 100644 index aa67f5c..0000000 --- a/src/soc/rockchip/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Rockchip Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOC_ROCKCHIP_RK3288) += rk3288 diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 441a97f..be41327 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOC_ROCKCHIP_RK3288),y) + IDBTOOL = util/rockchip/make_idb.py #bootblock-y += bootblock.c @@ -79,3 +81,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" @mkdir -p $(dir $@) @$(IDBTOOL) --from=$< --to=$@ --enable-align + +endif diff --git a/src/soc/samsung/Makefile.inc b/src/soc/samsung/Makefile.inc deleted file mode 100644 index 496b5f7..0000000 --- a/src/soc/samsung/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5250) += exynos5250 -subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5420) += exynos5420 diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc index 6525637..1cde349 100644 --- a/src/soc/samsung/exynos5250/Makefile.inc +++ b/src/soc/samsung/exynos5250/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_CPU_SAMSUNG_EXYNOS5250),y) + bootblock-y += spi.c alternate_cbfs.c bootblock-y += bootblock.c bootblock-y += pinmux.c timer.c power.c @@ -51,3 +53,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n" util/exynos/fixed_cksum.py $< $<.cksum 32768 cat 3rdparty/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@ + +endif diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc index 7eb407e..e42fc9a 100644 --- a/src/soc/samsung/exynos5420/Makefile.inc +++ b/src/soc/samsung/exynos5420/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_CPU_SAMSUNG_EXYNOS5420),y) + bootblock-y += spi.c alternate_cbfs.c bootblock-y += bootblock.c bootblock-y += pinmux.c timer.c power.c @@ -53,3 +55,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n" util/exynos/variable_cksum.py $< $<.cksum cat 3rdparty/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@ + +endif diff --git a/src/soc/ucb/Makefile.inc b/src/soc/ucb/Makefile.inc deleted file mode 100644 index fe40742..0000000 --- a/src/soc/ucb/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOC_UCB_RISCV) += riscv diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index c25a2fc..1072a2b 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,3 +1,6 @@ -romstage-y += cbmem.c +ifeq ($(CONFIG_SOC_UCB_RISCV),y) +romstage-y += cbmem.c ramstage-y += cbmem.c + +endif

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coreboot-gerrit April 2015