coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: c278064 urara: UART: CONSOLE_SERIAL selected in Pistachio configuration file; configuration needed to enable UART.
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9186 -gerrit commit c27806457fadc14d6ad0c720ce27c3d9216812ed Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Oct 31 17:55:59 2014 +0000 urara: UART: CONSOLE_SERIAL selected in Pistachio configuration file; configuration needed to enable UART. BUG=chrome-os-partner:31438 TEST=built urara bootblock and ran it on the Pistachio FPGA, observed exepected console output BRANCH=none Change-Id: I1a56ae34ce553e66b4d18f0561ca4b3287863d1e Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: f9a83da568e5cfb4c377f3b33a8ce11a7d8d0bd5 Original-Change-Id: I4947ea8608593ec3f44e336ebdf3930f44493ec9 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226841 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/imgtec/pistachio/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 83408bd..183c457 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -24,6 +24,7 @@ config CPU_IMGTEC_PISTACHIO select DYNAMIC_CBMEM select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER + select CONSOLE_SERIAL select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING

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New patch to review for coreboot: 0da4bd9 urara: UART: line control setting configuration added: 8bit, 1 stop bit, no parity
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9185 -gerrit commit 0da4bd9e6829a70e90ad85e620c0a659a6f56954 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Thu Oct 30 14:49:53 2014 +0000 urara: UART: line control setting configuration added: 8bit, 1 stop bit, no parity BUG=chrome-os-partner:31438 TEST=built urara bootblock and ran it on the Pistachio FPGA, observed expected console output. BRANCH=none Change-Id: Iface623f0b267f851e6d162d0321d56e3713a785 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 4122ae983dba907c10d0d0980863ae7bf94eda5e Original-Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226551 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/mainboard/google/urara/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index 231c97e..bde26d6 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -46,4 +46,8 @@ config DRAM_SIZE_MB int default 256 +config TTYS0_LCS + int + default 3 + endif

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New patch to review for coreboot: 140f72b pistachio: add gpio type definition
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9184 -gerrit commit 140f72bbc53284f96e5ca8d9e69da25fde75df85 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Oct 28 19:15:52 2014 -0700 pistachio: add gpio type definition This is necessary to support generic gpio interface in src/lib. This file will be later populated with more GPIO definitions. BRANCH=none BUG=chrome-os-partner:31438 TEST=none Change-Id: I3fa93f1b3b1ce99d921bbfb378b3f7ae4eb652c2 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 26f564ee10a770d57cb4af0a8ab5a264aaf1a7cd Original-Change-Id: I68c9c3a28fcc747575436b502cb25b31afed8700 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226181 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/include/soc/gpio.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/soc/imgtec/pistachio/include/soc/gpio.h b/src/soc/imgtec/pistachio/include/soc/gpio.h new file mode 100644 index 0000000..f6f1499 --- /dev/null +++ b/src/soc/imgtec/pistachio/include/soc/gpio.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_IMGTECH_PISTACHIO_GPIO_H__ +#define __SOC_IMGTECH_PISTACHIO_GPIO_H__ + +typedef unsigned gpio_t; + +#endif // __SOC_IMGTECH_PISTACHIO_GPIO_H__

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New patch to review for coreboot: c863c96 mips: do not place branch instructions in branch delay slot
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9183 -gerrit commit c863c96fc2f806a785d193b86e4492a6d1b6adb8 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Oct 3 09:47:13 2014 -0700 mips: do not place branch instructions in branch delay slot A branch instruction in a branch delay slot confuses the execution pipeline and causes an exception. bootblock.S was written 'by hand', has a branch instruction in branch delay slot and includes '.set noreorder' directive, which causes it to crash when trying to branch to main(). Adding a nop instruction fixes the problem. Also adding a nop after the last branch in the file just in case main() returns and the object linked next starts with a branch. BUG=chrome-os-partner:31438 TEST=Running on the simulator can reach main() now Change-Id: I0882b2eb5ce426f5a311018ffbb6f37a2ca64d98 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221421 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/mips/bootblock.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S index dbde803..f369e00 100644 --- a/src/arch/mips/bootblock.S +++ b/src/arch/mips/bootblock.S @@ -39,6 +39,10 @@ _start: /* Run main */ b main - /* Should never return from main. */ -2: + /* + * Should never return from main. Make sure there is no branch in the + * branch delay slot. + */ +2: nop b 2b + nop /* Make sure there is no branch after this either. */

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coreboot-gerrit April 2015