coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: d5c82af northbridge/amd/amdmct: Pack MCT and DCT info structs
by gerrit＠coreboot.org 01 Apr '15

01 Apr '15

the following patch was just integrated into master: commit d5c82afa37f99a6db8ebb06d0e3c4c0ad4e488db Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Mar 29 16:21:23 2015 -0500 northbridge/amd/amdmct: Pack MCT and DCT info structs This allows safe access of romstage MCT values from ramstage Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9158 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9158 for details. -gerrit

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Patch merged into coreboot/master: 2e1f183 amd/pi/hudson: INCLUDES was renamed to CPPFLAGS_common
by gerrit＠coreboot.org 01 Apr '15

01 Apr '15

the following patch was just integrated into master: commit 2e1f18336dd4f955e42e8bbe18dbd45b3a3bd85d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Mar 31 00:22:38 2015 +0200 amd/pi/hudson: INCLUDES was renamed to CPPFLAGS_common And this path is already included properly elsewhere. Change-Id: I9fc6887fc047a9df1c4cb6fa4f841abb16f6d548 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/9174 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/9174 for details. -gerrit

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Patch merged into coreboot/master: 4418776 chromeos: INCLUDES was renamed to CPPFLAGS_common
by gerrit＠coreboot.org 01 Apr '15

01 Apr '15

the following patch was just integrated into master: commit 44187764af997cd46badc39dcd5a4d8da83b0af5 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Mar 31 00:21:52 2015 +0200 chromeos: INCLUDES was renamed to CPPFLAGS_common Change-Id: I39841c5358c53e6d2325d1304fd6cdfadb7f7ac4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/9173 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/9173 for details. -gerrit

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New patch to review for coreboot: 9894cf6 pistachio: add timer frequency for SOC; correct platform ID
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9193 -gerrit commit 9894cf6ca45e1cc0fa2ca0bf097e8f5b087eb5d0 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Mon Jan 19 02:39:18 2015 +0000 pistachio: add timer frequency for SOC; correct platform ID Corrected platform ID and added timer frequency for SOC. The timer frequency is half the CPU frequency. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: If7e03232106b52f2522fc7da586bdaf95f5eefec Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: d94789950d5300bbe5defbf529480d8d545e743e Original-Change-Id: I1187e4b5280eaf796777d882a2e154e2808e9e37 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241426 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/soc/imgtec/pistachio/cpu.h | 12 ++++++++---- src/soc/imgtec/pistachio/monotonic_timer.c | 19 ++++++++++++++++--- 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/src/soc/imgtec/pistachio/cpu.h b/src/soc/imgtec/pistachio/cpu.h index 72775b5..8995219 100644 --- a/src/soc/imgtec/pistachio/cpu.h +++ b/src/soc/imgtec/pistachio/cpu.h @@ -18,14 +18,18 @@ #ifndef __SOC_IMGTEC_DANUBE_CPU_H__ #define __SOC_IMGTEC_DANUBE_CPU_H__ +#include <arch/io.h> + #define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 #define IMG_SPIM1_BASE_ADDRESS 0xB8101000 /* - * Reading at this address allows to identify the platform the code is running - * on. + * This register holds the FPGA image version + * If we're not working on the FPGA this will be 0 */ -#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060)) -#define IMG_PLATFORM_ID_SILICON 0xF00D0006 +#define PRIMARY_FPGA_VERSION 0xB8149060 +#define IMG_PLATFORM_ID() read32(PRIMARY_FPGA_VERSION) +#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */ +#define IMG_PLATFORM_ID_SILICON 0 #endif diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index 99c147b..c2408b0 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -23,6 +23,9 @@ #include <arch/cpu.h> #include <soc/cpu.h> +#define PISTACHIO_CLOCK_SWITCH 0xB8144200 +#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 + static int get_count_mhz_freq(void) { static unsigned count_mhz_freq; @@ -30,10 +33,20 @@ static int get_count_mhz_freq(void) if (!count_mhz_freq) { if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) count_mhz_freq = 25; /* FPGA board */ - /* - * Will need some means of finding out the counter - * frequency on a real SOC + else { + /* If MIPS PLL external bypass bit is set, it means + * that the MIPS PLL is already set up to work at a + * frequency of 550 MHz; otherwise, the crystal is + * used with a frequency of 52 MHz */ + if (read32(PISTACHIO_CLOCK_SWITCH) & + MIPS_EXTERN_PLL_BYPASS_MASK) + /* Half MIPS PLL freq. */ + count_mhz_freq = 275; + else + /* Half Xtal freq. */ + count_mhz_freq = 26; + } } return count_mhz_freq; }

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New patch to review for coreboot: 263f9a5 pistachio: add SOC descriptor
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9192 -gerrit commit 263f9a563feabf8a68a523f8d114873651b725dc Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Dec 1 18:34:37 2014 -0800 pistachio: add SOC descriptor With this descriptor added ramstage properly allocates memory resources and creates entries in coreboot table. This also allows to proceed to booting depthcharge, as it now can be loaded into the existing memory. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the set of patches applied the firmware properly finds depthcharge in CBFS, uncompresses it and attempts to start: ... Booting payload fallback/payload from cbfs Loading segment from rom address 0x9b000058 code (compression=1) New segment dstaddr 0x80124020 memsize 0x2099a0 srcaddr 0x9b000090 filesize 0xbbe Loading segment from rom address 0x9b000074 Entry Point 0x80124038 Loading Segment: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe lb: [0x0000000080000000, 0x0000000080013858) Post relocation: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe using LZMA [ 0x80124020, 8012596c, 0x8032d9c0) <- 9b000090 Clearing Segment: addr: 0x000000008012596c memsz: 0x0000000000208054 dest 80124020, end 8032d9c0, bouncebuffer 8ffd4f50 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 129 run 34579421 exit 129 Jumping to boot code at 80124038 ERROR: dropped a timestamp entry CPU0: stack: 9a00c800 - 9a00d800, lowest used address 9a00d498, stack used: 872 bytes entry = 80124038 Change-Id: I15809e146407d66b04f2a97c47c961fdccb8e175 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: a1577c5532a064426a3ea88b6f7f30ccdae24eaf Original-Change-Id: Ifed5550f2c18430e9ae06ad1ecacaa13191b5995 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232571 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/urara/devicetree.cb | 1 + src/soc/imgtec/pistachio/Makefile.inc | 1 + src/soc/imgtec/pistachio/soc.c | 48 ++++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/src/mainboard/google/urara/devicetree.cb b/src/mainboard/google/urara/devicetree.cb index a328b9d..e3eb091 100644 --- a/src/mainboard/google/urara/devicetree.cb +++ b/src/mainboard/google/urara/devicetree.cb @@ -20,6 +20,7 @@ # chip soc/imgtec/pistachio + device cpu_cluster 0 on end chip drivers/generic/generic # I2C0 controller device i2c 6 on end # Fake component for testing end diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index 1f39714..d693a1c 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -34,6 +34,7 @@ bootblock-y += monotonic_timer.c ramstage-y += cbmem.c ramstage-y += monotonic_timer.c +ramstage-y += soc.c romstage-y += cbmem.c romstage-y += romstage.c diff --git a/src/soc/imgtec/pistachio/soc.c b/src/soc/imgtec/pistachio/soc.c new file mode 100644 index 0000000..7c2884f --- /dev/null +++ b/src/soc/imgtec/pistachio/soc.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The Chromium OS Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <symbols.h> + +static void soc_read_resources(device_t dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, + (CONFIG_DRAM_SIZE_MB * MiB) / KiB); +} + +static void soc_init(device_t dev) +{ + printk(BIOS_INFO, "CPU: Imgtec Pistachio\n"); +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_imgtec_pistachio_ops = { + CHIP_NAME("SOC: Imgtec Pistachio") + .enable_dev = enable_soc_dev, +};

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New patch to review for coreboot: b4645fb pistachio: set correct CBMEM top address
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9191 -gerrit commit b4645fbb74741b12b8188a1697f9b0031c083f8f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Nov 29 15:31:40 2014 -0800 pistachio: set correct CBMEM top address This is required for proper dynamic CBMEM operation. BRANCH=none BUG=chrome-os-partner:31438 TEST=urara ramstage does not crash anymore in CBMEM initialization Change-Id: Id8e001be20fc245c91b2639f89775e594b0de966 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b7c6e4090d76a172c269bff002428015cc8aac8a Original-Change-Id: I5d44907443724891c8cff805208a7a3bb8e36752 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232292 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/cbmem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c index 5fb6c0e..1aed030 100644 --- a/src/soc/imgtec/pistachio/cbmem.c +++ b/src/soc/imgtec/pistachio/cbmem.c @@ -21,9 +21,9 @@ #include <cbmem.h> #include <stdlib.h> +#include <symbols.h> void *cbmem_top(void) { - uintptr_t top = MIN(CONFIG_DRAM_SIZE_MB, 256) << 20; - return (void *)(top + CONFIG_SYS_SDRAM_BASE); + return _dram + (CONFIG_DRAM_SIZE_MB << 20); }

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New patch to review for coreboot: 68aa5db pistachio: allow more room for bootblock
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9190 -gerrit commit 68aa5db015ac7358592bffcce3973ce60bfbc756 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Nov 29 15:28:23 2014 -0800 pistachio: allow more room for bootblock 32K is a more appropriate room for Pistachio bootblock. BRANCH=none BUG=chrome-os-partner:31438 TEST=there is no bootblock overflow even when compiled with -O0. Change-Id: I454746ce0b9daabc93ccbf3316655fac836af8ff Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 56adf22ba12f5a7c69d11c0c720996de32ca9149 Original-Change-Id: I74b6674aea95b1138e2168527239e2cfb4a7ad42 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232291 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index e939f09..40017f7 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -43,12 +43,12 @@ config BOOTBLOCK_BASE config CBFS_ROM_OFFSET hex - default 0x4100 + default 0x8100 config CBFS_HEADER_ROM_OFFSET # Effectively the maximum size of the bootblock hex - default 0x4000 + default 0x8000 config ROMSTAGE_BASE hex

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New patch to review for coreboot: 7bd3092 pistachio: enable early console
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9189 -gerrit commit 7bd30926a0e0d0ff108ceec480b2d99c73045f8f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Nov 11 19:55:07 2014 -0800 pistachio: enable early console Adding this configuration option enables romstage console output. Ideally this setting should be enabled automatically in case the bootblock console is enabled. BRANCH=none BUG=chrome-os-partner:31438 TEST=romstage messages show up on the console Change-Id: I5823fc737f4c65a4222592a8857ac89e7fe0ba3e Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 30f5f64ffcb8ab938781d87b7928dc3b19c58504 Original-Change-Id: I710e05ce24e1aeccc90aead50336f00dec52fff0 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229202 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 48ffc43..e939f09 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -25,6 +25,7 @@ config CPU_IMGTEC_PISTACHIO select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select CONSOLE_SERIAL + select EARLY_CONSOLE select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING

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New patch to review for coreboot: b9ff729 pistachio: implement timer support
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9188 -gerrit commit b9ff7293ae190ce483088c9aa2fe6d45a99621b8 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Nov 5 17:50:09 2014 -0800 pistachio: implement timer support C0_COUNT register is a free running counter clocked by the CPU frequency divided by two. On the FPGA board it results in 25 MHz, on real SOCs it will have to be figured out later. Some magic addresses and numbers are used to find out if the code is running on the FPGA board. timestamp_get() and timer_monotonic_get() are kept in the same file. The CPU initialization makes sure that CO COUNT is in fact enabled and starts from zero. BRANCH=none BUG=chrome-os-partner:33595,chrome-os-partner:31438 TEST=with timer enabled, the startup code properly initializes UART and prints the coreboot bootblock banner message on the serial console. Change-Id: I98fe330b961f677448b222917ab7d586494ed4b7 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: a7324221c1d856ac72fa2b0ab586b5ea8cab3a05 Original-Change-Id: I2d518213de939e91a35f8aea174aed76d297dd72 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227888 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/Makefile.inc | 3 --- src/soc/imgtec/pistachio/bootblock.c | 15 +++++++++++++++ src/soc/imgtec/pistachio/cpu.h | 7 +++++++ src/soc/imgtec/pistachio/monotonic_timer.c | 26 +++++++++++++++++++++++++- src/soc/imgtec/pistachio/timestamp.c | 19 ------------------- 5 files changed, 47 insertions(+), 23 deletions(-) diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index b91bb1b5..1f39714 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -31,16 +31,13 @@ ramstage-y += uart.c endif bootblock-y += monotonic_timer.c -bootblock-y += timestamp.c ramstage-y += cbmem.c ramstage-y += monotonic_timer.c -ramstage-y += timestamp.c romstage-y += cbmem.c romstage-y += romstage.c romstage-y += monotonic_timer.c -romstage-y += timestamp.c # Generate the actual coreboot bootblock code $(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index f6cc76b..9011264 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -19,6 +19,21 @@ * MA 02110-1301 USA */ +#include <stdint.h> +#include <arch/cpu.h> + static void bootblock_cpu_init(void) { + uint32_t cause; + + /* + * Make sure the count register is counting by clearing the "Disable + * Counter" bit, in case it is set. + */ + cause = read_c0_cause(); + if (cause & C0_CAUSE_DC) + write_c0_cause(cause & ~(C0_CAUSE_DC)); + + /* And make sure that it starts from zero. */ + write_c0_count(0); } diff --git a/src/soc/imgtec/pistachio/cpu.h b/src/soc/imgtec/pistachio/cpu.h index c61c58d..72775b5 100644 --- a/src/soc/imgtec/pistachio/cpu.h +++ b/src/soc/imgtec/pistachio/cpu.h @@ -21,4 +21,11 @@ #define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 #define IMG_SPIM1_BASE_ADDRESS 0xB8101000 +/* + * Reading at this address allows to identify the platform the code is running + * on. + */ +#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060)) +#define IMG_PLATFORM_ID_SILICON 0xF00D0006 + #endif diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index a8fe27c..99c147b 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -17,9 +17,33 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> #include <timer.h> +#include <timestamp.h> +#include <arch/cpu.h> +#include <soc/cpu.h> + +static int get_count_mhz_freq(void) +{ + static unsigned count_mhz_freq; + + if (!count_mhz_freq) { + if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) + count_mhz_freq = 25; /* FPGA board */ + /* + * Will need some means of finding out the counter + * frequency on a real SOC + */ + } + return count_mhz_freq; +} void timer_monotonic_get(struct mono_time *mt) { - /* to be defined */ + mt->microseconds = (long)timestamp_get(); +} + +uint64_t timestamp_get(void) +{ + return read_c0_count()/get_count_mhz_freq(); } diff --git a/src/soc/imgtec/pistachio/timestamp.c b/src/soc/imgtec/pistachio/timestamp.c deleted file mode 100644 index f0dc5ad..0000000 --- a/src/soc/imgtec/pistachio/timestamp.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <timestamp.h> - -uint64_t timestamp_get(void) -{ - return 0; -}

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New patch to review for coreboot: 922c66d urara: Fix CBFS header definitions
by Stefan Reinauer 01 Apr '15

01 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9187 -gerrit commit 922c66d4609570ba2f890740fe0e1e6661387c9e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Nov 4 16:12:05 2014 -0800 urara: Fix CBFS header definitions Urara CBFS header configuration is broken. CBFS header needs to be right above the bootblock, and the CBFS data - 0x100 bytes above, to allow room for proper CBFS wrapper structures. Ideally only the header offset should be specified (and even that could be derived from the bootblock size). But this is a more generic problem to be addressed with different architectures' image layout requirements in mind. BRANCH=none BUG=chrome-os-partner:31438 TEST=coreboot image passes the integrity check now (it was failing before because CBGS header was overlaying the bootblock) $ FEATURES=noclean emerge-urara coreboot $ /build/urara/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/build/util/bimgtool/bimgtool \ /build/urara/firmware/coreboot.rom.serial $ cbfstool /build/urara/firmware/coreboot.rom.serial print coreboot.rom.serial: 1024 kB, bootblocksize 9956, romsize 1048576, offset 0x4100 alignment: 64 bytes, architecture: mips Name Offset Type Size fallback/romstage 0x4100 stage 7100 fallback/ramstage 0x5d00 stage 18995 config 0xa780 raw 2452 (empty) 0xb140 null 1003096 Change-Id: Id615bdcc6261dea9f36a409bd90f1e4764353bb9 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 8a0115963aa7460e4c7255ab8508d7d52d67fb67 Original-Change-Id: Id200ab5421661ef39b7c7713e931c39153fdc8be Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227523 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/cpu/mips/Kconfig | 5 ----- src/soc/imgtec/pistachio/Kconfig | 4 ++++ 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/cpu/mips/Kconfig b/src/cpu/mips/Kconfig index 093a1f0..2230c14 100644 --- a/src/cpu/mips/Kconfig +++ b/src/cpu/mips/Kconfig @@ -30,8 +30,3 @@ config BOOTBLOCK_ROM_OFFSET hex depends on CPU_MIPS default 0x00 - -config CBFS_HEADER_ROM_OFFSET - hex - depends on CPU_MIPS - default 0x10 diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 183c457..48ffc43 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -41,6 +41,10 @@ config BOOTBLOCK_BASE default 0x9b000000 config CBFS_ROM_OFFSET + hex + default 0x4100 + +config CBFS_HEADER_ROM_OFFSET # Effectively the maximum size of the bootblock hex default 0x4000

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coreboot-gerrit April 2015