coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 807d193 vboot: remove vboot_helper.c
by Patrick Georgi 28 Apr '15

28 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9960 -gerrit commit 807d1933bcc498a9b89d38e87515e011f9ce6cff Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 22 10:50:34 2015 -0500 vboot: remove vboot_helper.c This file was moved previously to get it out of the way for easier merging from the chromium repo. It's not used currently so remove it. Change-Id: I8e691623f29ac2218b83bc46f5b4a348e0e1b3ef Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/vboot_helper.c | 168 -------------------------- 1 file changed, 168 deletions(-) diff --git a/src/vendorcode/google/chromeos/vboot_helper.c b/src/vendorcode/google/chromeos/vboot_helper.c deleted file mode 100644 index be1f296..0000000 --- a/src/vendorcode/google/chromeos/vboot_helper.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stddef.h> -#include <string.h> -#include "chromeos.h" -#include <boot/coreboot_tables.h> -#include <cbfs.h> -#include <cbmem.h> -#include <console/console.h> -#include <program_loading.h> -#include "vboot_handoff.h" - -int vboot_enable_developer(void) -{ - struct vboot_handoff *vbho; - - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vbho == NULL) { - printk(BIOS_ERR, "%s: Couldn't find vboot_handoff structure!\n", - __func__); - return 0; - } - - return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER); -} - -int vboot_enable_recovery(void) -{ - struct vboot_handoff *vbho; - - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vbho == NULL) - return 0; - - return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_RECOVERY); -} - -int __attribute__((weak)) clear_recovery_mode_switch(void) -{ - // Can be implemented by a mainboard - return 0; -} - -int vboot_skip_display_init(void) -{ - struct vboot_handoff *vbho; - - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vbho == NULL) - return 0; - - return !(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DISPLAY); -} - -void *vboot_get_region(uintptr_t offset_addr, size_t size, void *dest) -{ - if (IS_ENABLED(CONFIG_SPI_FLASH_MEMORY_MAPPED)) { - if (dest != NULL) - return memcpy(dest, (void *)offset_addr, size); - else - return (void *)offset_addr; - } else { - struct cbfs_media default_media, *media = &default_media; - void *cache; - - init_default_cbfs_media(media); - media->open(media); - if (dest != NULL) { - cache = dest; - if (media->read(media, dest, offset_addr, size) != size) - cache = NULL; - } else { - cache = media->map(media, offset_addr, size); - if (cache == CBFS_MEDIA_INVALID_MAP_ADDRESS) - cache = NULL; - } - media->close(media); - return cache; - } -} - -int __attribute((weak)) vboot_get_sw_write_protect(void) -{ - // Can be implemented by a platform / mainboard - return 0; -} - -static void *vboot_get_payload(size_t *len) -{ - struct vboot_handoff *vboot_handoff; - struct firmware_component *fwc; - - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vboot_handoff == NULL) - return NULL; - - if (CONFIG_VBOOT_BOOT_LOADER_INDEX >= MAX_PARSED_FW_COMPONENTS) { - printk(BIOS_ERR, "Invalid boot loader index: %d\n", - CONFIG_VBOOT_BOOT_LOADER_INDEX); - return NULL; - } - - fwc = &vboot_handoff->components[CONFIG_VBOOT_BOOT_LOADER_INDEX]; - - if (len != NULL) - *len = fwc->size; - - printk(BIOS_DEBUG, "Booting 0x%x byte payload at 0x%08x.\n", - fwc->size, fwc->address); - - return (void *)fwc->address; -} - -static int vboot_locate_payload(struct payload *payload) -{ - void *buffer; - size_t size; - - buffer = vboot_get_payload(&size); - - if (buffer == NULL) - return -1; - - payload->backing_store.data = buffer; - payload->backing_store.size = size; - - return 0; -} - -const struct payload_loader_ops vboot_payload_loader = { - .name = "VBOOT", - .locate = vboot_locate_payload, -}; - -int vboot_get_handoff_info(void **addr, uint32_t *size) -{ - struct vboot_handoff *vboot_handoff; - - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vboot_handoff == NULL) - return -1; - - *addr = vboot_handoff; - *size = sizeof(*vboot_handoff); - return 0; -}

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Patch set updated for coreboot: 0e41a6f chromeos: remove VBOOT2_VERIFY_FIRMWARE option
by Patrick Georgi 28 Apr '15

28 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9958 -gerrit commit 0e41a6fb770bf9266fe56137bf7e786c8124f9a1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 22 10:41:42 2015 -0500 chromeos: remove VBOOT2_VERIFY_FIRMWARE option There's no need to have the VBOOT2_VERIFY_FIRMWARE distinction because it's the only game in town. Change-Id: I82aab665934c27829e1a04115bf499ae527a91aa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/Makefile.inc | 3 --- src/lib/coreboot_table.c | 2 +- src/mainboard/google/nyan_blaze/Kconfig | 3 +-- src/mainboard/google/nyan_blaze/romstage.c | 6 +++--- src/mainboard/google/rush/memlayout.ld | 2 +- src/mainboard/google/rush_ryu/memlayout.ld | 2 +- src/soc/marvell/bg4cd/Kconfig | 2 +- src/soc/marvell/bg4cd/Makefile.inc | 4 ++-- src/vendorcode/google/chromeos/Kconfig | 12 ++++++------ src/vendorcode/google/chromeos/Makefile.inc | 2 +- src/vendorcode/google/chromeos/chromeos.h | 6 +++--- src/vendorcode/google/chromeos/vbnv_flash.c | 6 ------ src/vendorcode/google/chromeos/vboot2/Kconfig | 19 +++++-------------- src/vendorcode/google/chromeos/vboot_helper.c | 7 ------- 14 files changed, 25 insertions(+), 51 deletions(-) diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 8757c0b..70db2e2 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -13,11 +13,8 @@ romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c -ifeq ($(CONFIG_VBOOT2_VERIFY_FIRMWARE),y) verstage-y += ec.c crosec_proto.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c -endif - diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 8319c03..4af50ed 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -195,7 +195,7 @@ static void lb_vbnv(struct lb_header *header) #endif } -#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE +#if CONFIG_VBOOT_VERIFY_FIRMWARE static void lb_vboot_handoff(struct lb_header *header) { void *addr; diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 54e6ef3..3b7c555 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -85,8 +85,7 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS config VBOOT_RAMSTAGE_INDEX hex - default 0x3 if VBOOT2_VERIFY_FIRMWARE - default 0x2 + default 0x3 config FLASHMAP_OFFSET hex diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index c9510d6..12b2ffb 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -58,7 +58,7 @@ static void __attribute__((noinline)) romstage(void) u32 dram_end_mb = sdram_max_addressable_mb(); u32 dram_size_mb = dram_end_mb - dram_start_mb; -#if !CONFIG_VBOOT2_VERIFY_FIRMWARE +#if !CONFIG_VBOOT_VERIFY_FIRMWARE configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ @@ -95,7 +95,7 @@ static void __attribute__((noinline)) romstage(void) early_mainboard_init(); -#if CONFIG_VBOOT2_VERIFY_FIRMWARE +#if CONFIG_VBOOT_VERIFY_FIRMWARE entry = vboot2_load_ramstage(); #else early_mainboard_init(); @@ -108,7 +108,7 @@ static void __attribute__((noinline)) romstage(void) /* Stub to force arm_init_caches to the top, before any stack/memory accesses */ void main(void) { -#if !CONFIG_VBOOT2_VERIFY_FIRMWARE +#if !CONFIG_VBOOT_VERIFY_FIRMWARE asm volatile ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip"); #endif diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld index d8fdb9a..367a88e 100644 --- a/src/mainboard/google/rush/memlayout.ld +++ b/src/mainboard/google/rush/memlayout.ld @@ -1,4 +1,4 @@ -#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE) +#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) #include <soc/memlayout_vboot2.ld> #else #include <soc/memlayout.ld> diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld index d8fdb9a..367a88e 100644 --- a/src/mainboard/google/rush_ryu/memlayout.ld +++ b/src/mainboard/google/rush_ryu/memlayout.ld @@ -1,4 +1,4 @@ -#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE) +#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) #include <soc/memlayout_vboot2.ld> #else #include <soc/memlayout.ld> diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig index 725f561..96fd8ef 100644 --- a/src/soc/marvell/bg4cd/Kconfig +++ b/src/soc/marvell/bg4cd/Kconfig @@ -24,7 +24,7 @@ config SOC_MARVELL_BG4CD select ARCH_RAMSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_VERSTAGE_ARMV7_M - select ARM_BOOTBLOCK_CUSTOM if VBOOT2_VERIFY_FIRMWARE + select ARM_BOOTBLOCK_CUSTOM if VBOOT_VERIFY_FIRMWARE select BOOTBLOCK_CONSOLE select CPU_HAS_BOOTBLOCK_INIT select DYNAMIC_CBMEM diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc index a540250..4a58e6f 100644 --- a/src/soc/marvell/bg4cd/Makefile.inc +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -17,8 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -bootblock-$(CONFIG_VBOOT2_VERIFY_FIRMWARE) += bootblock_asm.S -bootblock-$(CONFIG_VBOOT2_VERIFY_FIRMWARE) += bootblock.c +bootblock-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += bootblock_asm.S +bootblock-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += bootblock.c bootblock-y += cbmem.c bootblock-y += i2c.c diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index cf3bd07..a75237e 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -104,7 +104,7 @@ config FLASHMAP_OFFSET config EC_SOFTWARE_SYNC bool "Enable EC software sync" default n - depends on VBOOT_VERIFY_FIRMWARE || VBOOT2_VERIFY_FIRMWARE + depends on VBOOT_VERIFY_FIRMWARE help EC software sync is a mechanism where the AP helps the EC verify its firmware similar to how vboot verifies the main system firmware. This @@ -128,14 +128,14 @@ config VBOOT_OPROM_MATTERS config VIRTUAL_DEV_SWITCH bool "Virtual developer switch support" default n - depends on VBOOT_VERIFY_FIRMWARE || VBOOT2_VERIFY_FIRMWARE + depends on VBOOT_VERIFY_FIRMWARE help Whether this platform has a virtual developer switch. config VBOOT_VERIFY_FIRMWARE bool "Verify firmware with vboot." default n - depends on CHROMEOS + depends on CHROMEOS && HAVE_HARD_RESET help Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the components of the firmware (stages, payload, etc). @@ -148,7 +148,7 @@ config VBOOT_VERIFY_FIRMWARE config VBOOT_BOOT_LOADER_INDEX hex "Bootloader component index" default 0 - depends on VBOOT_VERIFY_FIRMWARE || VBOOT2_VERIFY_FIRMWARE + depends on VBOOT_VERIFY_FIRMWARE help This is the index of the bootloader component in the verified firmware block. @@ -164,7 +164,7 @@ config VBOOT_REFCODE_INDEX config VBOOT_RAMSTAGE_INDEX hex "Ramstage component index" default 1 - depends on VBOOT_VERIFY_FIRMWARE || VBOOT2_VERIFY_FIRMWARE + depends on VBOOT_VERIFY_FIRMWARE help This is the index of the ramstage component in the verified firmware block. @@ -172,7 +172,7 @@ config VBOOT_RAMSTAGE_INDEX config VBOOT_ROMSTAGE_INDEX hex "Romstage component index" default 2 - depends on VBOOT2_VERIFY_FIRMWARE + depends on VBOOT_VERIFY_FIRMWARE help This is the index of the romstage component in the verified firmware block. diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 873b81f..33cdb26 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -54,5 +54,5 @@ CFLAGS_common += -DMOCK_TPM=0 endif VB_SOURCE := vboot_reference -subdirs-$(CONFIG_VBOOT2_VERIFY_FIRMWARE) += vboot2 +subdirs-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot2 CPPFLAGS_common += -I$(VB_SOURCE)/firmware/include diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 78be422..3e427b9 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -62,18 +62,18 @@ static inline int vboot_skip_display_init(void) { return 0; } struct romstage_handoff; -#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE +#if CONFIG_VBOOT_VERIFY_FIRMWARE /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); void *vboot_get_payload(int *len); -#else /* CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE */ +#else /* CONFIG_VBOOT_VERIFY_FIRMWARE */ static inline void vboot_verify_firmware(struct romstage_handoff *h) {} static inline void *vboot_get_payload(int *len) { return NULL; } static inline int vboot_get_handoff_info(void **addr, uint32_t *size) { return -1; } -#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE */ +#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ int vboot_get_sw_write_protect(void); diff --git a/src/vendorcode/google/chromeos/vbnv_flash.c b/src/vendorcode/google/chromeos/vbnv_flash.c index 97a2a82..4cc87b6 100644 --- a/src/vendorcode/google/chromeos/vbnv_flash.c +++ b/src/vendorcode/google/chromeos/vbnv_flash.c @@ -29,13 +29,7 @@ #include "chromeos.h" #include "vbnv_layout.h" -#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) -#define BLOB_SIZE VBNV_BLOCK_SIZE -#elif IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE) #define BLOB_SIZE VB2_NVDATA_SIZE -#else -#error unable to determine BLOB_SIZE -#endif /* FMAP descriptor of the NVRAM area */ static struct vboot_region nvram_region; diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig index 0591006..b27b5b7 100644 --- a/src/vendorcode/google/chromeos/vboot2/Kconfig +++ b/src/vendorcode/google/chromeos/vboot2/Kconfig @@ -16,19 +16,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config VBOOT2_VERIFY_FIRMWARE - bool "Firmware Verification with vboot2" - default y if VBOOT_VERIFY_FIRMARE - depends on CHROMEOS && HAVE_HARD_RESET - select COLLECT_TIMESTAMPS - help - Enabling VBOOT2_VERIFY_FIRMWARE will use vboot2 to verify the romstage - and boot loader. - config VBOOT2_MOCK_SECDATA bool "Mock secdata for firmware verification" default n - depends on VBOOT2_VERIFY_FIRMWARE + depends on VBOOT_VERIFY_FIRMWARE help Enabling VBOOT2_MOCK_SECDATA will mock secdata for the firmware verification to avoid access to a secdata storage (typically TPM). @@ -39,7 +30,7 @@ config VBOOT2_MOCK_SECDATA config RETURN_FROM_VERSTAGE bool "return from verstage" default n - depends on VBOOT2_VERIFY_FIRMWARE + depends on VBOOT_VERIFY_FIRMWARE help If this is set, the verstage returns back to the bootblock instead of exits to the romstage so that the verstage space can be reused by the @@ -49,7 +40,7 @@ config RETURN_FROM_VERSTAGE config VBOOT_DISABLE_DEV_ON_RECOVERY bool "Disable dev mode on recovery requests" default n - depends on VBOOT2_VERIFY_FIRMWARE + depends on VBOOT_VERIFY_FIRMWARE help When this option is enabled, the Chrome OS device leaves the developer mode as soon as recovery request is detected. This is @@ -58,9 +49,9 @@ config VBOOT_DISABLE_DEV_ON_RECOVERY config VERSTAGE_IN_BOOTBLOCK bool default n - depends on VBOOT2_VERIFY_FIRMWARE + depends on VBOOT_VERIFY_FIRMWARE config SEPARATE_VERSTAGE bool default !VERSTAGE_IN_BOOTBLOCK - depends on VBOOT2_VERIFY_FIRMWARE + depends on VBOOT_VERIFY_FIRMWARE diff --git a/src/vendorcode/google/chromeos/vboot_helper.c b/src/vendorcode/google/chromeos/vboot_helper.c index 4fb3338..be1f296 100644 --- a/src/vendorcode/google/chromeos/vboot_helper.c +++ b/src/vendorcode/google/chromeos/vboot_helper.c @@ -105,12 +105,6 @@ int __attribute((weak)) vboot_get_sw_write_protect(void) return 0; } -#if CONFIG_VBOOT2_VERIFY_FIRMWARE - -void *vboot_get_payload(int *len) { return NULL; } - -#else /* CONFIG_VBOOT2_VERIFY_FIRMWARE */ - static void *vboot_get_payload(size_t *len) { struct vboot_handoff *vboot_handoff; @@ -137,7 +131,6 @@ static void *vboot_get_payload(size_t *len) return (void *)fwc->address; } -#endif static int vboot_locate_payload(struct payload *payload) {

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Patch set updated for coreboot: ea945f2 boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEX
by Patrick Georgi 28 Apr '15

28 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9959 -gerrit commit ea945f249d6617864938dfa5c5451c27e35d24b3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 22 10:48:01 2015 -0500 boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEX These options will need to just be selected in within the .config files. There's not need in duplicating all these options. Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/bolt/Kconfig | 4 ---- src/mainboard/google/cosmos/Kconfig | 4 ---- src/mainboard/google/falco/Kconfig | 4 ---- src/mainboard/google/nyan/Kconfig | 4 ---- src/mainboard/google/nyan_big/Kconfig | 4 ---- src/mainboard/google/nyan_blaze/Kconfig | 4 ---- src/mainboard/google/panther/Kconfig | 4 ---- src/mainboard/google/peppy/Kconfig | 4 ---- src/mainboard/google/rambi/Kconfig | 8 -------- src/mainboard/google/rush/Kconfig | 7 ------- src/mainboard/google/rush_ryu/Kconfig | 7 ------- src/mainboard/google/samus/Kconfig | 8 -------- src/mainboard/google/slippy/Kconfig | 4 ---- src/mainboard/google/veyron_brain/Kconfig | 11 ----------- src/mainboard/google/veyron_danger/Kconfig | 11 ----------- src/mainboard/google/veyron_jerry/Kconfig | 4 ---- src/mainboard/google/veyron_mighty/Kconfig | 4 ---- src/mainboard/google/veyron_pinky/Kconfig | 4 ---- src/mainboard/google/veyron_rialto/Kconfig | 11 ----------- src/mainboard/google/veyron_speedy/Kconfig | 4 ---- src/mainboard/intel/wtm2/Kconfig | 8 -------- 21 files changed, 123 deletions(-) diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index d575d26..c901b8f 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -21,10 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select CHROMEOS_VBNV_CMOS -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - config MAINBOARD_DIR string default google/bolt diff --git a/src/mainboard/google/cosmos/Kconfig b/src/mainboard/google/cosmos/Kconfig index 8cd9983..99d8a64 100644 --- a/src/mainboard/google/cosmos/Kconfig +++ b/src/mainboard/google/cosmos/Kconfig @@ -44,10 +44,6 @@ config MAINBOARD_VENDOR string default "Google" -config VBOOT_RAMSTAGE_INDEX - hex - default 0x3 - config BOOT_MEDIA_SPI_BUS int default 2 diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 683712e..c836110 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -24,10 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select CHROMEOS_VBNV_CMOS -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - config MAINBOARD_DIR string default google/falco diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 58edf61..a91eddd 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -81,10 +81,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 1 -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - config FLASHMAP_OFFSET hex default 0x00100000 diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 555b5d1..9aac110 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -82,10 +82,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 1 -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - config FLASHMAP_OFFSET hex default 0x00100000 diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 3b7c555..d7d92d6 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -83,10 +83,6 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 1 -config VBOOT_RAMSTAGE_INDEX - hex - default 0x3 - config FLASHMAP_OFFSET hex default 0x00100000 diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 76c1a12..6fdb46c 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -21,10 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select PHYSICAL_REC_SWITCH select CHROMEOS_VBNV_CMOS -config VBOOT_RAMSTAGE_INDEX - hex - default 0x1 - config MAINBOARD_DIR string default google/panther diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index ea7c334..05234d0 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -26,10 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select CHROMEOS_VBNV_CMOS -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - config MAINBOARD_DIR string default google/peppy diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 1461539..4c9e891 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -15,14 +15,6 @@ config BOARD_SPECIFIC_OPTIONS select ALWAYS_LOAD_OPROM select CHROMEOS_VBNV_CMOS -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - -config VBOOT_REFCODE_INDEX - hex - default 0x3 - config MAINBOARD_DIR string default google/rambi diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index cb6da1c..9cb0223 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -82,13 +82,6 @@ config BOOT_MEDIA_SPI_CHIP_SELECT help Which chip select to use for boot media. -# For rush, we are using vboot2. Thus, index for stages: -# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2 -# VBOOT_RAMSTAGE_INDEX -> Use 0x3 -config VBOOT_RAMSTAGE_INDEX - hex - default 0x3 - config DRIVER_TPM_I2C_BUS hex default 0x2 diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index 2961cbe..2a7e0fb 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -79,13 +79,6 @@ config BOOT_MEDIA_SPI_CHIP_SELECT help Which chip select to use for boot media. -# For ryu, we are using vboot2. Thus, index for stages: -# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2 -# VBOOT_RAMSTAGE_INDEX -> Use 0x3 -config VBOOT_RAMSTAGE_INDEX - hex - default 0x3 - config DRIVER_TPM_I2C_BUS hex default 0x2 diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index ee28b3c..664faf1 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -21,14 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select CHROMEOS_VBNV_CMOS -config VBOOT_RAMSTAGE_INDEX - hex - default 0x3 - -config VBOOT_REFCODE_INDEX - hex - default 0x4 - config MAINBOARD_DIR string default google/samus diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 0b1976a..48e5825 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -23,10 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select CHROMEOS_VBNV_CMOS -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - config MAINBOARD_DIR string default google/slippy diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index bea618c..c5ff0bb 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -49,17 +49,6 @@ config MAINBOARD_VENDOR string default "Google" -# The 'ecrwhash' is removed from FMAP on Brain, since we don't have EC. -# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are -# better approaches for vboot2 to find right index. -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - -config VBOOT_ROMSTAGE_INDEX - hex - default 0x1 - config BOOT_MEDIA_SPI_BUS int default 2 diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index f6e0060..d65a6c0 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -49,17 +49,6 @@ config MAINBOARD_VENDOR string default "Google" -# The 'ecrwhash' is removed from FMAP on Danger, since we don't have EC. -# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are -# better approaches for vboot2 to find right index. -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - -config VBOOT_ROMSTAGE_INDEX - hex - default 0x1 - config BOOT_MEDIA_SPI_BUS int default 2 diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig index be0b736..f025829 100644 --- a/src/mainboard/google/veyron_jerry/Kconfig +++ b/src/mainboard/google/veyron_jerry/Kconfig @@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US int default 100 -config VBOOT_RAMSTAGE_INDEX - hex - default 0x3 - config BOOT_MEDIA_SPI_BUS int default 2 diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig index 58972ad..4cccbb5 100644 --- a/src/mainboard/google/veyron_mighty/Kconfig +++ b/src/mainboard/google/veyron_mighty/Kconfig @@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US int default 100 -config VBOOT_RAMSTAGE_INDEX - hex - default 0x3 - config BOOT_MEDIA_SPI_BUS int default 2 diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index 87d24f0..c30039c 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US int default 100 -config VBOOT_RAMSTAGE_INDEX - hex - default 0x3 - config BOOT_MEDIA_SPI_BUS int default 2 diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 597dd19..dc7d045 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -48,17 +48,6 @@ config MAINBOARD_VENDOR string default "Google" -# The 'ecrwhash' is removed from FMAP on Rialto, since we don't have EC. -# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are -# better approaches for vboot2 to find right index. -config VBOOT_RAMSTAGE_INDEX - hex - default 0x2 - -config VBOOT_ROMSTAGE_INDEX - hex - default 0x1 - config BOOT_MEDIA_SPI_BUS int default 2 diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig index 6a51457..1729b64 100644 --- a/src/mainboard/google/veyron_speedy/Kconfig +++ b/src/mainboard/google/veyron_speedy/Kconfig @@ -60,10 +60,6 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US int default 100 -config VBOOT_RAMSTAGE_INDEX - hex - default 0x3 - config BOOT_MEDIA_SPI_BUS int default 2 diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index f23a803..98b2790 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -16,14 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHROMEOS_RAMOOPS_DYNAMIC select CHROMEOS_VBNV_CMOS -config VBOOT_RAMSTAGE_INDEX - hex - default 0x1 - -config VBOOT_REFCODE_INDEX - hex - default 0x2 - config MAINBOARD_DIR string default intel/wtm2

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Patch merged into coreboot/master: 6d65f79 vboot: remove vboot1
by gerrit＠coreboot.org 28 Apr '15

28 Apr '15

the following patch was just integrated into master: commit 6d65f796db04927bfc8324f50ad0816cec9673b6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 21 15:33:01 2015 -0500 vboot: remove vboot1 In preparation for moving to vboot2 for all verified boot paths bring over Kconfig options to the common area from vboot1. Also remove vboot1 directory entirely. Change-Id: Iccc4b570216f834886618f0ba5f2e1dd6c01db4b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9957 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9957 for details. -gerrit

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New patch to review for coreboot: b8765b5 Makefile x86 SMM: Move smm_wrap recipes
by Kyösti Mälkki 28 Apr '15

28 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10014 -gerrit commit b8765b540d420d3957bf69a468c574436f581f9e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 10 11:52:53 2015 +0300 Makefile x86 SMM: Move smm_wrap recipes This is not used together with SMM_MODULES. Change-Id: I52621787cfa5a9e3863c150ce64f62aceb423eb4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/smm/Makefile.inc | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 517f00b..5164970 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -34,22 +34,6 @@ smm-c-deps:=$$(OPTION_TABLE_H) $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --start-group $(smm-objs) $(COMPILER_RT_smm) --end-group -$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) - $(LD_smm) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o - $(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map - $(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm - -# change to the target path because objcopy will use the path name in its -# ELF symbol names. -$(obj)/cpu/x86/smm/smm_wrap.ramstage.manual: $(obj)/cpu/x86/smm/smm_wrap - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - cd $(obj)/cpu/x86/smm; $(OBJCOPY_smm) -I binary smm -O elf32-i386 -B i386 smm_wrap.ramstage.manual -else - cd $(obj)/cpu/x86/smm; $(OBJCOPY_smm) -I binary smm -O elf64-x86_64 -B x86_64 smm_wrap.ramstage.manual -endif - - ifeq ($(CONFIG_SMM_MODULES),y) smmstub-y += smm_stub.S @@ -97,6 +81,21 @@ endif else # CONFIG_SMM_MODULES +$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) + $(LD_smm) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o + $(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map + $(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm + +# change to the target path because objcopy will use the path name in its +# ELF symbol names. +$(obj)/cpu/x86/smm/smm_wrap.ramstage.manual: $(obj)/cpu/x86/smm/smm_wrap + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) + cd $(obj)/cpu/x86/smm; $(OBJCOPY_smm) -I binary smm -O elf32-i386 -B i386 smm_wrap.ramstage.manual +else + cd $(obj)/cpu/x86/smm; $(OBJCOPY_smm) -I binary smm -O elf64-x86_64 -B x86_64 smm_wrap.ramstage.manual +endif + ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.S ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm_wrap.manual

1 0

Patch merged into coreboot/master: 599c32d marvell/bg4cd: merge verstage into bootblock
by gerrit＠coreboot.org 28 Apr '15

28 Apr '15

the following patch was just integrated into master: commit 599c32d8ef908f0b9723eb864f0a8695f6a76758 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Dec 3 12:09:58 2014 -0800 marvell/bg4cd: merge verstage into bootblock If verified boot is enabled, merge verstage into bootblock. This also requires custom bootblock code to actually call into verstage. [pg: modified to match upstream] BUG=chrome-os-partner:32631 BRANCH=ToT TEST=booted on cosmos development board. Change-Id: I53251aac966ee15da24232c23fefa636de8b253b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2b8ada263017b46afa755b5acb759574184dba06 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: Ia0e1236357aa32bf553fb8cc98f3a8d29de17f45 Original-Reviewed-on: https://chromium-review.googlesource.com/229795 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/10008 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10008 for details. -gerrit

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Patch merged into coreboot/master: efc6aa0 vboot2: Allow merging verstage into bootblock
by gerrit＠coreboot.org 28 Apr '15

28 Apr '15

the following patch was just integrated into master: commit efc6aa0eb928a27e625eb62ca848de7e191c5b67 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Apr 27 18:13:50 2015 +0200 vboot2: Allow merging verstage into bootblock Change-Id: I31cd7f84db8b7176c8854f33421aab5c176cd5ce Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10007 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10007 for details. -gerrit

1 0

Patch merged into coreboot/master: 8f2b0dc vboot2: Always enable timestamps
by gerrit＠coreboot.org 28 Apr '15

28 Apr '15

the following patch was just integrated into master: commit 8f2b0dc16ba4395ded62bd10f23ce6f67a1b1a7c Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Apr 27 18:13:15 2015 +0200 vboot2: Always enable timestamps The vboot2 code requires them. Change-Id: I9afaf9b373297b0eebce9ffd7cc05766dee7d6fd Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10006 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10006 for details. -gerrit

1 0

Patch merged into coreboot/master: 66cdba7 vboot2: get rid of global variable that is used locally and only once
by gerrit＠coreboot.org 28 Apr '15

28 Apr '15

the following patch was just integrated into master: commit 66cdba7ea5729a4d96207f305d25ca5bde9eb0b0 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Apr 27 18:10:34 2015 +0200 vboot2: get rid of global variable that is used locally and only once Change-Id: Iaf6d6a8857451fb16916aaae97a6fd5c51bc8cc4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10005 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10005 for details. -gerrit

1 0

Patch merged into coreboot/master: ba80887 vboot2: Build verstage archive, then use that for building the stage
by gerrit＠coreboot.org 28 Apr '15

28 Apr '15

the following patch was just integrated into master: commit ba80887cfdbca8e804a4191997a9beaa5ce44f6f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Apr 27 18:09:22 2015 +0200 vboot2: Build verstage archive, then use that for building the stage This slightly streamlines integrating the vboot2 library and prepares for merging verstage and bootblock on selected devices. Change-Id: I2163d1411d0c0c6bf80bce64796e1b6a5a02b802 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10004 for details. -gerrit

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