coreboot-gerrit April 2015

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Patch set updated for coreboot: 4242b41 kbuild: automatically include southbridges
by Stefan Reinauer 27 Apr '15

27 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9796 -gerrit commit 4242b41048da0ced784476a947f155fe24410f80 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 27 14:02:36 2015 -0700 kbuild: automatically include southbridges This change switches all southbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in southbridge/Makefile.inc or in southbridge/<vendor>/Makefile.inc. In order to be able to drop southbridge/amd/Makefile.inc, some scattered source files had to be moved to a southbridge/amd/common directory, in accordance to what we are doing on other architectures already. This means, vendor and southbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 5 +- src/mainboard/amd/lamar/mainboard.c | 2 +- src/mainboard/amd/lamar/mptable.c | 2 +- src/mainboard/amd/persimmon/mainboard.c | 2 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/biostar/am1ml/mainboard.c | 2 +- src/mainboard/biostar/am1ml/mptable.c | 2 +- src/mainboard/gizmosphere/gizmo2/mainboard.c | 2 +- src/mainboard/gizmosphere/gizmo2/mptable.c | 2 +- src/mainboard/hp/abm/mainboard.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 2 +- src/mainboard/pcengines/apu1/mainboard.c | 2 +- src/mainboard/pcengines/apu1/mptable.c | 2 +- src/southbridge/Makefile.inc | 10 -- src/southbridge/amd/Makefile.inc | 27 ---- src/southbridge/amd/agesa/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/pci.c | 2 +- src/southbridge/amd/amd8111/Makefile.inc | 4 + src/southbridge/amd/amd8131/Makefile.inc | 4 + src/southbridge/amd/amd8132/Makefile.inc | 4 + src/southbridge/amd/amd8151/Makefile.inc | 4 + src/southbridge/amd/amd_pci_util.c | 204 ------------------------ src/southbridge/amd/amd_pci_util.h | 48 ------ src/southbridge/amd/cimx/Makefile.inc | 9 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/amd/common/Makefile.inc | 7 + src/southbridge/amd/common/amd_pci_util.c | 204 ++++++++++++++++++++++++ src/southbridge/amd/common/amd_pci_util.h | 48 ++++++ src/southbridge/amd/cs5535/Makefile.inc | 4 + src/southbridge/amd/cs5536/Makefile.inc | 6 +- src/southbridge/amd/pi/hudson/pci.c | 2 +- src/southbridge/amd/rs690/Makefile.inc | 4 + src/southbridge/amd/rs780/Makefile.inc | 4 + src/southbridge/amd/sb600/Makefile.inc | 4 + src/southbridge/amd/sb700/Makefile.inc | 4 + src/southbridge/amd/sb800/Makefile.inc | 4 + src/southbridge/amd/sr5650/Makefile.inc | 4 + src/southbridge/broadcom/Makefile.inc | 3 - src/southbridge/broadcom/bcm21000/Makefile.inc | 4 + src/southbridge/broadcom/bcm5780/Makefile.inc | 4 + src/southbridge/broadcom/bcm5785/Makefile.inc | 4 + src/southbridge/dmp/Makefile.inc | 20 --- src/southbridge/dmp/vortex86ex/Makefile.inc | 4 + src/southbridge/intel/Makefile.inc | 19 --- src/southbridge/intel/bd82x6x/Makefile.inc | 4 + src/southbridge/intel/common/Makefile.inc | 4 + src/southbridge/intel/esb6300/Makefile.inc | 4 + src/southbridge/intel/fsp_bd82x6x/Makefile.inc | 4 + src/southbridge/intel/fsp_rangeley/Makefile.inc | 4 + src/southbridge/intel/i3100/Makefile.inc | 4 + src/southbridge/intel/i82371eb/Makefile.inc | 4 + src/southbridge/intel/i82801ax/Makefile.inc | 4 + src/southbridge/intel/i82801bx/Makefile.inc | 4 + src/southbridge/intel/i82801cx/Makefile.inc | 4 + src/southbridge/intel/i82801dx/Makefile.inc | 4 + src/southbridge/intel/i82801ex/Makefile.inc | 4 + src/southbridge/intel/i82801gx/Makefile.inc | 4 + src/southbridge/intel/i82801ix/Makefile.inc | 4 + src/southbridge/intel/i82870/Makefile.inc | 4 + src/southbridge/intel/ibexpeak/Makefile.inc | 4 + src/southbridge/intel/lynxpoint/Makefile.inc | 4 + src/southbridge/intel/sch/Makefile.inc | 4 + src/southbridge/nvidia/Makefile.inc | 2 - src/southbridge/nvidia/ck804/Makefile.inc | 4 + src/southbridge/nvidia/mcp55/Makefile.inc | 4 + src/southbridge/rdc/Makefile.inc | 1 - src/southbridge/rdc/r8610/Makefile.inc | 4 + src/southbridge/ricoh/Makefile.inc | 1 - src/southbridge/ricoh/rl5c476/Makefile.inc | 4 + src/southbridge/sis/Makefile.inc | 1 - src/southbridge/sis/sis966/Makefile.inc | 4 + src/southbridge/ti/Makefile.inc | 22 --- src/southbridge/ti/pci1x2x/Makefile.inc | 6 +- src/southbridge/ti/pci7420/Makefile.inc | 4 + src/southbridge/ti/pcixx12/Makefile.inc | 4 + src/southbridge/via/Makefile.inc | 2 - src/southbridge/via/k8t890/Makefile.inc | 4 + src/southbridge/via/vt8237r/Makefile.inc | 4 + 79 files changed, 463 insertions(+), 383 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index b67f145..fee227c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -52,11 +52,10 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs ####################################################################### # root source directories of coreboot -subdirs-y := src/lib src/console src/device src/ec src/southbridge src/soc +subdirs-y := src/lib src/console src/device src/ec $(wildcard src/southbridge/*/*) src/soc subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom -subdirs-y += src/arch/arm src/arch/arm64 src/arch/mips src/arch/riscv -subdirs-y += src/arch/x86 +subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += site-local diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index e73a3e8..079abdb 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -32,7 +32,7 @@ #include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <southbridge/amd/pi/hudson/pci_devs.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c index 8b5b5ea..d29127c 100644 --- a/src/mainboard/amd/lamar/mptable.c +++ b/src/mainboard/amd/lamar/mptable.c @@ -27,7 +27,7 @@ #include <cpu/amd/amdfam15.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> #include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 58ac983..9479b2b 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -24,7 +24,7 @@ #include <arch/io.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 0cf57bd..b5f6535 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -27,7 +27,7 @@ #include <stdint.h> #include <cpu/amd/amdfam14.h> #include <SBPLATFORM.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index fed21ba..d402150 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -33,7 +33,7 @@ #include <northbridge/amd/agesa/agesawrapper.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c index b2851ff..f80b974 100644 --- a/src/mainboard/biostar/am1ml/mptable.c +++ b/src/mainboard/biostar/am1ml/mptable.c @@ -27,7 +27,7 @@ #include <cpu/amd/amdfam16.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> static void *smp_write_config_table(void *v) diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index c4a20c6..a95e2ee 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <cpu/amd/agesa/s3_resume.h> diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c index 192b0c0..c61952f 100644 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ b/src/mainboard/gizmosphere/gizmo2/mptable.c @@ -27,7 +27,7 @@ #include <cpu/amd/amdfam16.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> static void *smp_write_config_table(void *v) diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index adb7093..71193bb 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -26,7 +26,7 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <cpu/amd/agesa/s3_resume.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d67e072..2dc92e7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -30,7 +30,7 @@ #include <device/pci.h> #include <device/pci_def.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <southbridge/amd/cimx/cimx_util.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index cc73c83..5d02877 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -30,7 +30,7 @@ #include <stdint.h> #include <string.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 1ba0e23..3b8541c 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -24,7 +24,7 @@ #include <arch/io.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c index 03fa9f3..95a00af 100644 --- a/src/mainboard/pcengines/apu1/mptable.c +++ b/src/mainboard/pcengines/apu1/mptable.c @@ -27,7 +27,7 @@ #include <stdint.h> #include <cpu/amd/amdfam14.h> #include <SBPLATFORM.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> diff --git a/src/southbridge/Makefile.inc b/src/southbridge/Makefile.inc deleted file mode 100644 index 106752b..0000000 --- a/src/southbridge/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -subdirs-y += amd -subdirs-y += broadcom -subdirs-y += dmp -subdirs-y += intel -subdirs-y += nvidia -subdirs-y += rdc -subdirs-y += ricoh -subdirs-y += sis -subdirs-y += ti -subdirs-y += via diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc deleted file mode 100644 index cfb89d5..0000000 --- a/src/southbridge/amd/Makefile.inc +++ /dev/null @@ -1,27 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8131) += amd8131 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8132) += amd8132 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8151) += amd8151 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS690) += rs690 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB600) += sb600 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += pi -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += pi - -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index fdd5d80..89d41b4 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -16,5 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 5858cd2..cf1626d 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "hudson.h" -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <bootstate.h> diff --git a/src/southbridge/amd/amd8111/Makefile.inc b/src/southbridge/amd/amd8111/Makefile.inc index c5b2688..4c9ebae 100644 --- a/src/southbridge/amd/amd8111/Makefile.inc +++ b/src/southbridge/amd/amd8111/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y) + ramstage-y += amd8111.c ramstage-y += usb.c ramstage-y += lpc.c @@ -9,3 +11,5 @@ ramstage-y += nic.c ramstage-y += pci.c ramstage-y += smbus.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/amd/amd8131/Makefile.inc b/src/southbridge/amd/amd8131/Makefile.inc index ce96c97..8ec2691 100644 --- a/src/southbridge/amd/amd8131/Makefile.inc +++ b/src/southbridge/amd/amd8131/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8131),y) + ramstage-y += bridge.c + +endif diff --git a/src/southbridge/amd/amd8132/Makefile.inc b/src/southbridge/amd/amd8132/Makefile.inc index ce96c97..75dce39 100644 --- a/src/southbridge/amd/amd8132/Makefile.inc +++ b/src/southbridge/amd/amd8132/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y) + ramstage-y += bridge.c + +endif diff --git a/src/southbridge/amd/amd8151/Makefile.inc b/src/southbridge/amd/amd8151/Makefile.inc index dcb3c73..07edf58 100644 --- a/src/southbridge/amd/amd8151/Makefile.inc +++ b/src/southbridge/amd/amd8151/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8151),y) + ramstage-y += agp3.c + +endif diff --git a/src/southbridge/amd/amd_pci_util.c b/src/southbridge/amd/amd_pci_util.c deleted file mode 100644 index 9f2cc5c..0000000 --- a/src/southbridge/amd/amd_pci_util.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/pci.h> -#include <arch/io.h> -#include <string.h> -#include "amd_pci_util.h" -#include <pc80/i8259.h> -#include "amd_pci_int_defs.h" -#include "amd_pci_int_types.h" - -#ifndef __PRE_RAM__ - -const struct pirq_struct * pirq_data_ptr = NULL; -u32 pirq_data_size = 0; -const u8 * intr_data_ptr = NULL; -const u8 * picr_data_ptr = NULL; - -/* - * Read the FCH PCI_INTR registers 0xC00/0xC01 at a - * given index and a given PIC (0) or IOAPIC (1) mode - */ -u8 read_pci_int_idx(u8 index, int mode) -{ - outb((mode << 7) | index, PCI_INTR_INDEX); - return inb(PCI_INTR_DATA); -} - -/* - * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 - * at a given index and PIC (0) or IOAPIC (1) mode - */ -void write_pci_int_idx(u8 index, int mode, u8 data) -{ - outb((mode << 7) | index, PCI_INTR_INDEX); - outb(data, PCI_INTR_DATA); -} - -/* - * Write the FCH PCI_INTR registers 0xC00/0xC01 with values - * given in global variables intr_data and picr_data. - * These variables are defined in mainboard.c - */ -void write_pci_int_table (void) -{ - u8 byte; - - if(picr_data_ptr == NULL || intr_data_ptr == NULL){ - printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" - "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); - return; - } - - /* PIC IRQ routine */ - printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n" - "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); - for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { - if (intr_types[byte]) { - write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); - printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", - byte, intr_types[byte], read_pci_int_idx(byte, 0)); - } - } - - /* APIC IRQ routine */ - printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n" - "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); - for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { - if (intr_types[byte]) { - write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); - printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", - byte, intr_types[byte], read_pci_int_idx(byte, 1)); - } - } -} - -/* - * Function to write the PCI config space Interrupt - * registers based on the values given in PCI_INTR - * table at I/O port 0xC00/0xC01 - */ -void write_pci_cfg_irqs(void) -{ - device_t dev = NULL; /* Our current device to route IRQs to */ - device_t target_dev = NULL; /* The bridge that a device may be connected to */ - u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ - u16 target_pin = 0; /* Pin we will search our tables for */ - u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ - u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ - u8 bus = 0; /* A PCI Device Bus number */ - u16 devfn = 0; /* A PCI Device and Function number */ - u8 bridged_device = 0; /* This device is on a PCI bridge */ - u32 i = 0; - - if (pirq_data_ptr == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" - " 'mainboard_pirq_data' structure does not exist\n"); - return; - } - - /* Populate the PCI cfg space header with the IRQ assignment */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); - - for (dev = all_devices; dev; dev = dev->next) { - /* - * Step 1: Get the INT_PIN and device structure to look for in the - * PCI_INTR table pirq_data - */ - target_dev = NULL; - target_pin = get_pci_irq_pins(dev, &target_dev); - if (target_dev == NULL) - continue; - - if (target_pin < 1) - continue; - - /* Get the original INT_PIN for record keeping */ - int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); - if (int_pin < 1 || int_pin > 4) - continue; /* Device has invalid INT_PIN so skip it */ - - bus = target_dev->bus->secondary; - devfn = target_dev->path.pci.devfn; - - /* - * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR - * register (0xC00) index for this device - */ - pci_intr_idx = 0xBAD; /* Will check to make sure it changed */ - for (i = 0; i < pirq_data_size; i++) { - if (pirq_data_ptr[i].devfn != devfn) - continue; - - /* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */ - pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; - printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i); - break; - } - - /* - * Step 3: Make sure we got a valid index and use it to get - * the IRQ number from the PCI_INTR register table - */ - if (pci_intr_idx == 0xBAD) { /* Not on a bridge or in pirq_data table, skip it */ - printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn); - continue; - } else if (pci_intr_idx == 0x1F) { /* Index found is not defined */ - printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n"); - continue; - } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { /* Index out of bounds */ - printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n", - __func__, pci_intr_idx, FCH_INT_TABLE_SIZE); - continue; - } - - /* Find the value to program into the INT_LINE register from the PCI_INTR registers */ - int_line = read_pci_int_idx(pci_intr_idx, 0); - if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ - printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n"); - continue; - } - - /* - * Step 4: Program the INT_LINE register in this device's - * PCI config space with the IRQ number we found in step 3 - * and make it Level Triggered - */ - pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); - - /* Set this IRQ to level triggered since it is used by a PCI device */ - i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); - - /* - * Step 5: Print out debug info and move on to next device - */ - printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", - int_pin, pin_to_str(int_pin)); - if (bridged_device) - printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - target_pin, pin_to_str(target_pin)); - printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" - "\tINT_LINE\t: 0x%X (IRQ %d)\n", - pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line); - } /* for (dev = all_devices) */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); -} -#endif /* __PRE_RAM__ */ diff --git a/src/southbridge/amd/amd_pci_util.h b/src/southbridge/amd/amd_pci_util.h deleted file mode 100644 index 1d1e52b..0000000 --- a/src/southbridge/amd/amd_pci_util.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef AMD_PCI_UTIL_H -#define AMD_PCI_UTIL_H - -#include <stdint.h> -#include "amd_pci_int_defs.h" - -/* FCH index/data registers */ -#define PCI_INTR_INDEX 0xc00 -#define PCI_INTR_DATA 0xc01 - -#ifndef __PRE_RAM__ - -struct pirq_struct { - u8 devfn; - u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ -}; - -extern const struct pirq_struct * pirq_data_ptr; -extern u32 pirq_data_size; -extern const u8 * intr_data_ptr; -extern const u8 * picr_data_ptr; - -u8 read_pci_int_idx(u8 index, int mode); -void write_pci_int_idx(u8 index, int mode, u8 data); -void write_pci_cfg_irqs(void); -void write_pci_int_table (void); -#endif /* __PRE_RAM */ - -#endif /* AMD_PCI_UTIL_H */ diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index aacfc58..0754469 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -16,10 +16,15 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 -romstage-y += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c -ramstage-y += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index f4a7aa3..ffa3290 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -38,7 +38,7 @@ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ #include "smbus.h" #include "fan.h" -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> /*implement in mainboard.c*/ void set_pcie_reset(void); diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc new file mode 100644 index 0000000..1f847cd --- /dev/null +++ b/src/southbridge/amd/common/Makefile.inc @@ -0,0 +1,7 @@ +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c new file mode 100644 index 0000000..9f2cc5c --- /dev/null +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include "amd_pci_util.h" +#include <pc80/i8259.h> +#include "amd_pci_int_defs.h" +#include "amd_pci_int_types.h" + +#ifndef __PRE_RAM__ + +const struct pirq_struct * pirq_data_ptr = NULL; +u32 pirq_data_size = 0; +const u8 * intr_data_ptr = NULL; +const u8 * picr_data_ptr = NULL; + +/* + * Read the FCH PCI_INTR registers 0xC00/0xC01 at a + * given index and a given PIC (0) or IOAPIC (1) mode + */ +u8 read_pci_int_idx(u8 index, int mode) +{ + outb((mode << 7) | index, PCI_INTR_INDEX); + return inb(PCI_INTR_DATA); +} + +/* + * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 + * at a given index and PIC (0) or IOAPIC (1) mode + */ +void write_pci_int_idx(u8 index, int mode, u8 data) +{ + outb((mode << 7) | index, PCI_INTR_INDEX); + outb(data, PCI_INTR_DATA); +} + +/* + * Write the FCH PCI_INTR registers 0xC00/0xC01 with values + * given in global variables intr_data and picr_data. + * These variables are defined in mainboard.c + */ +void write_pci_int_table (void) +{ + u8 byte; + + if(picr_data_ptr == NULL || intr_data_ptr == NULL){ + printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" + "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); + return; + } + + /* PIC IRQ routine */ + printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n" + "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); + for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { + if (intr_types[byte]) { + write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); + printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", + byte, intr_types[byte], read_pci_int_idx(byte, 0)); + } + } + + /* APIC IRQ routine */ + printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n" + "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); + for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { + if (intr_types[byte]) { + write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); + printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", + byte, intr_types[byte], read_pci_int_idx(byte, 1)); + } + } +} + +/* + * Function to write the PCI config space Interrupt + * registers based on the values given in PCI_INTR + * table at I/O port 0xC00/0xC01 + */ +void write_pci_cfg_irqs(void) +{ + device_t dev = NULL; /* Our current device to route IRQs to */ + device_t target_dev = NULL; /* The bridge that a device may be connected to */ + u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ + u16 target_pin = 0; /* Pin we will search our tables for */ + u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ + u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ + u8 bus = 0; /* A PCI Device Bus number */ + u16 devfn = 0; /* A PCI Device and Function number */ + u8 bridged_device = 0; /* This device is on a PCI bridge */ + u32 i = 0; + + if (pirq_data_ptr == NULL) { + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" + " 'mainboard_pirq_data' structure does not exist\n"); + return; + } + + /* Populate the PCI cfg space header with the IRQ assignment */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); + + for (dev = all_devices; dev; dev = dev->next) { + /* + * Step 1: Get the INT_PIN and device structure to look for in the + * PCI_INTR table pirq_data + */ + target_dev = NULL; + target_pin = get_pci_irq_pins(dev, &target_dev); + if (target_dev == NULL) + continue; + + if (target_pin < 1) + continue; + + /* Get the original INT_PIN for record keeping */ + int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); + if (int_pin < 1 || int_pin > 4) + continue; /* Device has invalid INT_PIN so skip it */ + + bus = target_dev->bus->secondary; + devfn = target_dev->path.pci.devfn; + + /* + * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR + * register (0xC00) index for this device + */ + pci_intr_idx = 0xBAD; /* Will check to make sure it changed */ + for (i = 0; i < pirq_data_size; i++) { + if (pirq_data_ptr[i].devfn != devfn) + continue; + + /* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */ + pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; + printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i); + break; + } + + /* + * Step 3: Make sure we got a valid index and use it to get + * the IRQ number from the PCI_INTR register table + */ + if (pci_intr_idx == 0xBAD) { /* Not on a bridge or in pirq_data table, skip it */ + printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn); + continue; + } else if (pci_intr_idx == 0x1F) { /* Index found is not defined */ + printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n"); + continue; + } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { /* Index out of bounds */ + printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n", + __func__, pci_intr_idx, FCH_INT_TABLE_SIZE); + continue; + } + + /* Find the value to program into the INT_LINE register from the PCI_INTR registers */ + int_line = read_pci_int_idx(pci_intr_idx, 0); + if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ + printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n"); + continue; + } + + /* + * Step 4: Program the INT_LINE register in this device's + * PCI config space with the IRQ number we found in step 3 + * and make it Level Triggered + */ + pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); + + /* Set this IRQ to level triggered since it is used by a PCI device */ + i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); + + /* + * Step 5: Print out debug info and move on to next device + */ + printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", + int_pin, pin_to_str(int_pin)); + if (bridged_device) + printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", + target_pin, pin_to_str(target_pin)); + printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" + "\tINT_LINE\t: 0x%X (IRQ %d)\n", + pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line); + } /* for (dev = all_devices) */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); +} +#endif /* __PRE_RAM__ */ diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h new file mode 100644 index 0000000..1d1e52b --- /dev/null +++ b/src/southbridge/amd/common/amd_pci_util.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_UTIL_H +#define AMD_PCI_UTIL_H + +#include <stdint.h> +#include "amd_pci_int_defs.h" + +/* FCH index/data registers */ +#define PCI_INTR_INDEX 0xc00 +#define PCI_INTR_DATA 0xc01 + +#ifndef __PRE_RAM__ + +struct pirq_struct { + u8 devfn; + u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ +}; + +extern const struct pirq_struct * pirq_data_ptr; +extern u32 pirq_data_size; +extern const u8 * intr_data_ptr; +extern const u8 * picr_data_ptr; + +u8 read_pci_int_idx(u8 index, int mode); +void write_pci_int_idx(u8 index, int mode, u8 data); +void write_pci_cfg_irqs(void); +void write_pci_int_table (void); +#endif /* __PRE_RAM */ + +#endif /* AMD_PCI_UTIL_H */ diff --git a/src/southbridge/amd/cs5535/Makefile.inc b/src/southbridge/amd/cs5535/Makefile.inc index 6f65e2e..3785cd4 100644 --- a/src/southbridge/amd/cs5535/Makefile.inc +++ b/src/southbridge/amd/cs5535/Makefile.inc @@ -1,4 +1,8 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5535),y) + ramstage-y += cs5535.c #ramstage-y += pci.c #ramstage-y += ide.c ramstage-y += chipsetinit.c + +endif diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc index f36dcc5..2da076e 100644 --- a/src/southbridge/amd/cs5536/Makefile.inc +++ b/src/southbridge/amd/cs5536/Makefile.inc @@ -17,8 +17,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y) + ramstage-y += cs5536.c ramstage-y += ide.c ramstage-y += pirq.c ramstage-y += smbus.c -romstage-y += smbus.c \ No newline at end of file +romstage-y += smbus.c + +endif diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index 70e2c18..5e71b4b 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "hudson.h" -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <bootstate.h> static void pci_init(struct device *dev) diff --git a/src/southbridge/amd/rs690/Makefile.inc b/src/southbridge/amd/rs690/Makefile.inc index e0cf927..c80ed9b 100644 --- a/src/southbridge/amd/rs690/Makefile.inc +++ b/src/southbridge/amd/rs690/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y) + ramstage-y += rs690.c ramstage-y += cmn.c ramstage-y += pcie.c ramstage-y += ht.c ramstage-y += gfx.c + +endif diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc index bf51d83..1a8a17a 100644 --- a/src/southbridge/amd/rs780/Makefile.inc +++ b/src/southbridge/amd/rs780/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS790),y) + ramstage-y += rs780.c ramstage-y += cmn.c ramstage-y += pcie.c ramstage-y += ht.c ramstage-y += gfx.c + +endif diff --git a/src/southbridge/amd/sb600/Makefile.inc b/src/southbridge/amd/sb600/Makefile.inc index 37fe57d..cd5bb61 100644 --- a/src/southbridge/amd/sb600/Makefile.inc +++ b/src/southbridge/amd/sb600/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y) + ramstage-y += sb600.c ramstage-y += usb.c ramstage-y += lpc.c @@ -10,3 +12,5 @@ ramstage-y += pci.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c + +endif diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 6e772fe..5ec8431 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB700),y) + ramstage-y += sb700.c ramstage-y += usb.c ramstage-y += lpc.c @@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c romstage-y += smbus.c + +endif diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc index d665af4..fca4a98 100644 --- a/src/southbridge/amd/sb800/Makefile.inc +++ b/src/southbridge/amd/sb800/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB800),y) + ramstage-y += sb800.c ramstage-y += usb.c ramstage-y += lpc.c @@ -11,3 +13,5 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c + +endif diff --git a/src/southbridge/amd/sr5650/Makefile.inc b/src/southbridge/amd/sr5650/Makefile.inc index 3c17be0..f695a11 100644 --- a/src/southbridge/amd/sr5650/Makefile.inc +++ b/src/southbridge/amd/sr5650/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SR5650),y) + ramstage-y += sr5650.c ramstage-y += pcie.c ramstage-y += ht.c romstage-y += early_setup.c + +endif diff --git a/src/southbridge/broadcom/Makefile.inc b/src/southbridge/broadcom/Makefile.inc deleted file mode 100644 index c9de93d..0000000 --- a/src/southbridge/broadcom/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM21000) += bcm21000 -subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5780) += bcm5780 -subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785) += bcm5785 diff --git a/src/southbridge/broadcom/bcm21000/Makefile.inc b/src/southbridge/broadcom/bcm21000/Makefile.inc index f85aeb1..d298c8e 100644 --- a/src/southbridge/broadcom/bcm21000/Makefile.inc +++ b/src/southbridge/broadcom/bcm21000/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM21000),y) + ramstage-y += pcie.c + +endif diff --git a/src/southbridge/broadcom/bcm5780/Makefile.inc b/src/southbridge/broadcom/bcm5780/Makefile.inc index 4eb834a..d4f83ed 100644 --- a/src/southbridge/broadcom/bcm5780/Makefile.inc +++ b/src/southbridge/broadcom/bcm5780/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5870),y) + ramstage-y += nic.c ramstage-y += pcix.c ramstage-y += pcie.c + +endif diff --git a/src/southbridge/broadcom/bcm5785/Makefile.inc b/src/southbridge/broadcom/bcm5785/Makefile.inc index b8427c4..70fba1f 100644 --- a/src/southbridge/broadcom/bcm5785/Makefile.inc +++ b/src/southbridge/broadcom/bcm5785/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785),y) + ramstage-y += bcm5785.c ramstage-y += usb.c ramstage-y += lpc.c @@ -5,3 +7,5 @@ ramstage-y += sb_pci_main.c ramstage-y += ide.c ramstage-y += sata.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/dmp/Makefile.inc b/src/southbridge/dmp/Makefile.inc deleted file mode 100644 index a94e935..0000000 --- a/src/southbridge/dmp/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 DMP Electronics Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOUTHBRIDGE_DMP_VORTEX86EX) += vortex86ex diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc index 5471faa..968930b 100644 --- a/src/southbridge/dmp/vortex86ex/Makefile.inc +++ b/src/southbridge/dmp/vortex86ex/Makefile.inc @@ -17,7 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_DMP_VORTEX86EX),y) + ramstage-y += southbridge.c ramstage-y += hard_reset.c ramstage-y += ide_sd_sata.c ramstage-y += audio.c + +endif diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc deleted file mode 100644 index dd20d46..0000000 --- a/src/southbridge/intel/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON) += common -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_ESB6300) += esb6300 -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I3100) += i3100 -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801AX) += i82801ax -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801BX) += i82801bx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) += i82801ix -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870 -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += bd82x6x -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += bd82x6x -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) += ibexpeak -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) += lynxpoint -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) += fsp_bd82x6x -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_rangeley diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 83de051..234c009 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -107,3 +109,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) endif PHONY += bd82x6x_add_me + +endif diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 4374ebc..5c613eb 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -17,5 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) + romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c + +endif diff --git a/src/southbridge/intel/esb6300/Makefile.inc b/src/southbridge/intel/esb6300/Makefile.inc index bb70fdc..fba8c23 100644 --- a/src/southbridge/intel/esb6300/Makefile.inc +++ b/src/southbridge/intel/esb6300/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_ESB6300),y) + ramstage-y += esb6300.c ramstage-y += reset.c ramstage-y += uhci.c @@ -10,3 +12,5 @@ ramstage-y += pci.c ramstage-y += pic.c ramstage-y += bridge1c.c ramstage-y += ac97.c + +endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc index 208611b..1bfed23 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -71,3 +73,5 @@ endif PHONY += bd82x6x_add_me CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x + +endif diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index 48ac522..1d33052 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -48,3 +50,5 @@ rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL) endif PHONY += rangeley_add_descriptor + +endif diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc index dc3d039..bcc6d06 100644 --- a/src/southbridge/intel/i3100/Makefile.inc +++ b/src/southbridge/intel/i3100/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I3100),y) + ramstage-y += i3100.c ramstage-y += uhci.c ramstage-y += lpc.c @@ -8,3 +10,5 @@ ramstage-y += pci.c ramstage-y += ioapic.c ramstage-y += reset.c ramstage-y += pciexp_portb.c + +endif diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 0aae455..0ab2531 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) + ramstage-y += i82371eb.c ramstage-y += isa.c ramstage-y += ide.c @@ -30,3 +32,5 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c romstage-y += early_pm.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801ax/Makefile.inc b/src/southbridge/intel/i82801ax/Makefile.inc index aeb1e54..48eadf3 100644 --- a/src/southbridge/intel/i82801ax/Makefile.inc +++ b/src/southbridge/intel/i82801ax/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801AX),y) + ramstage-y += i82801ax.c ramstage-y += ac97.c ramstage-y += ide.c @@ -30,3 +32,5 @@ ramstage-y += reset.c ramstage-y += watchdog.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801bx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc index f070f05..44a2ac8 100644 --- a/src/southbridge/intel/i82801bx/Makefile.inc +++ b/src/southbridge/intel/i82801bx/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801BX),y) + ramstage-y += i82801bx.c ramstage-y += ac97.c ramstage-y += ide.c @@ -31,3 +33,5 @@ ramstage-y += reset.c ramstage-y += watchdog.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801cx/Makefile.inc b/src/southbridge/intel/i82801cx/Makefile.inc index c375476..ab95982 100644 --- a/src/southbridge/intel/i82801cx/Makefile.inc +++ b/src/southbridge/intel/i82801cx/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801CX),y) + ramstage-y += i82801cx.c ramstage-y += usb.c ramstage-y += lpc.c @@ -6,3 +8,5 @@ ramstage-y += ac97.c #ramstage-y += nic.c ramstage-y += pci.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index e412ef9..d10383c 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -19,6 +19,8 @@ ## MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y) + ramstage-y += i82801dx.c ramstage-y += ac97.c ramstage-y += ide.c @@ -33,3 +35,5 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc index fb76a98..240eaf0 100644 --- a/src/southbridge/intel/i82801ex/Makefile.inc +++ b/src/southbridge/intel/i82801ex/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801EX),y) + ramstage-y += i82801ex.c ramstage-y += uhci.c ramstage-y += lpc.c @@ -9,3 +11,5 @@ ramstage-y += pci.c ramstage-y += ac97.c ramstage-y += watchdog.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 6e4d42e..fa1721f 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) + ramstage-y += i82801gx.c ramstage-y += ac97.c ramstage-y += azalia.c @@ -39,3 +41,5 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c early_lpc.c + +endif diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index a6580c4..19f5bb4 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y) + ramstage-y += i82801ix.c ramstage-y += pci.c ramstage-y += lpc.c @@ -40,3 +42,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_init.c romstage-y += early_smbus.c romstage-y += dmi_setup.c + +endif diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc index 190aa4f..790bd01 100644 --- a/src/southbridge/intel/i82870/Makefile.inc +++ b/src/southbridge/intel/i82870/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y) + ramstage-y += ioapic.c ramstage-y += pcibridge.c #ramstage-y += pci_parity.c + +endif diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 393655d..f09db1a 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -100,3 +102,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) endif PHONY += bd82x6x_add_me + +endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 3b7663e..df68db2 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -104,3 +106,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) endif PHONY += lynxpoint_add_me + +endif diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc index 0bdd475..bfdbe04 100644 --- a/src/southbridge/intel/sch/Makefile.inc +++ b/src/southbridge/intel/sch/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_SCH),y) + ramstage-y += south.c ramstage-y += audio.c ramstage-y += lpc.c @@ -39,3 +41,5 @@ cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin cmc.bin-file := $(call strip_quotes,$(CONFIG_CMC_FILE)) cmc.bin-type := raw cmc.bin-position := 0xfffd0000 + +endif diff --git a/src/southbridge/nvidia/Makefile.inc b/src/southbridge/nvidia/Makefile.inc deleted file mode 100644 index 13bf3e4..0000000 --- a/src/southbridge/nvidia/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) += ck804 -subdirs-$(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) += mcp55 diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index c88da39..de1162a 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_CK804),y) + ramstage-y += ck804.c ramstage-y += usb.c ramstage-y += lpc.c @@ -21,3 +23,5 @@ romstage-y += early_smbus.c chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index e2f8553..3e24f1c 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y) + ramstage-y += mcp55.c ramstage-y += azalia.c ramstage-y += ht.c @@ -20,3 +22,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/rdc/Makefile.inc b/src/southbridge/rdc/Makefile.inc deleted file mode 100644 index 34f3efd..0000000 --- a/src/southbridge/rdc/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_RDC_R8610) += r8610 diff --git a/src/southbridge/rdc/r8610/Makefile.inc b/src/southbridge/rdc/r8610/Makefile.inc index 3484c95..c6866bc 100644 --- a/src/southbridge/rdc/r8610/Makefile.inc +++ b/src/southbridge/rdc/r8610/Makefile.inc @@ -17,4 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_RDC_R8610),y) + ramstage-y += r8610.c + +endif diff --git a/src/southbridge/ricoh/Makefile.inc b/src/southbridge/ricoh/Makefile.inc deleted file mode 100644 index 3969392..0000000 --- a/src/southbridge/ricoh/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_RICOH_RL5C476) += rl5c476 diff --git a/src/southbridge/ricoh/rl5c476/Makefile.inc b/src/southbridge/ricoh/rl5c476/Makefile.inc index 3156706..3fa232f 100644 --- a/src/southbridge/ricoh/rl5c476/Makefile.inc +++ b/src/southbridge/ricoh/rl5c476/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_RICOH_RL5C476),y) + ramstage-y += rl5c476.c + +endif diff --git a/src/southbridge/sis/Makefile.inc b/src/southbridge/sis/Makefile.inc deleted file mode 100644 index 45332ca..0000000 --- a/src/southbridge/sis/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_SIS_SIS966) += sis966 diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index 5cf5954..71fff02 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_SIS_SIS966),y) + ramstage-y += sis761.c ramstage-y += sis966.c ramstage-y += lpc.c @@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/ti/Makefile.inc b/src/southbridge/ti/Makefile.inc deleted file mode 100644 index 2bd00e7..0000000 --- a/src/southbridge/ti/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI7420) += pci7420 -subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCIXX12) += pcixx12 -subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x diff --git a/src/southbridge/ti/pci1x2x/Makefile.inc b/src/southbridge/ti/pci1x2x/Makefile.inc index 7c0e4aa..4f2a3d3 100644 --- a/src/southbridge/ti/pci1x2x/Makefile.inc +++ b/src/southbridge/ti/pci1x2x/Makefile.inc @@ -1 +1,5 @@ -ramstage-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x.c +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI1X2X),y) + +ramstage-y += pci1x2x.c + +endif diff --git a/src/southbridge/ti/pci7420/Makefile.inc b/src/southbridge/ti/pci7420/Makefile.inc index d919258..66cfa90 100644 --- a/src/southbridge/ti/pci7420/Makefile.inc +++ b/src/southbridge/ti/pci7420/Makefile.inc @@ -17,5 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI7420),y) + ramstage-y += cardbus.c ramstage-y += firewire.c + +endif diff --git a/src/southbridge/ti/pcixx12/Makefile.inc b/src/southbridge/ti/pcixx12/Makefile.inc index bdd2cf3..6ab571b 100644 --- a/src/southbridge/ti/pcixx12/Makefile.inc +++ b/src/southbridge/ti/pcixx12/Makefile.inc @@ -17,4 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCIXX12),y) + ramstage-y += pcixx12.c + +endif diff --git a/src/southbridge/via/Makefile.inc b/src/southbridge/via/Makefile.inc deleted file mode 100644 index db19438..0000000 --- a/src/southbridge/via/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890 -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8237R) += vt8237r diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 634ccd1..18cb5aa 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y) + ramstage-y += ctrl.c ramstage-y += dram.c ramstage-y += bridge.c @@ -10,3 +12,5 @@ ramstage-y += chrome.c chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/via/vt8237r/Makefile.inc b/src/southbridge/via/vt8237r/Makefile.inc index de69ffd..2630602 100644 --- a/src/southbridge/via/vt8237r/Makefile.inc +++ b/src/southbridge/via/vt8237r/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_VIA_VT8237R),y) + ramstage-y += vt8237r.c ramstage-y += ctrl.c ramstage-y += ide.c @@ -27,3 +29,5 @@ ramstage-$(CONFIG_PIRQ_ROUTE) += pirq.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +endif

1 0

Patch set updated for coreboot: 1395f49 kbuild: automatically include SOCs
by Stefan Reinauer 27 Apr '15

27 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9799 -gerrit commit 1395f49bfea0ce04dd861222442e1601cf856d80 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 27 14:03:57 2015 -0700 kbuild: automatically include SOCs This change switches all SOC vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in soc/Makefile.inc or in soc/<vendor>/Makefile.inc. This means, vendor and SOC directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 2 +- src/soc/Makefile.inc | 12 ------------ src/soc/broadcom/Makefile.inc | 20 -------------------- src/soc/broadcom/cygnus/Makefile.inc | 4 ++++ src/soc/imgtec/Makefile.inc | 1 - src/soc/imgtec/pistachio/Makefile.inc | 3 +++ src/soc/intel/Makefile.inc | 3 --- src/soc/intel/baytrail/Makefile.inc | 5 ++++- src/soc/intel/broadwell/Makefile.inc | 5 ++++- src/soc/intel/common/Makefile.inc | 4 ++++ src/soc/intel/fsp_baytrail/Makefile.inc | 5 +++++ src/soc/marvell/Kconfig | 20 -------------------- src/soc/marvell/Makefile.inc | 20 -------------------- src/soc/marvell/bg4cd/Makefile.inc | 4 ++++ src/soc/nvidia/Makefile.inc | 2 -- src/soc/nvidia/tegra124/Makefile.inc | 4 ++++ src/soc/nvidia/tegra132/Makefile.inc | 4 ++++ src/soc/qualcomm/Makefile.inc | 1 - src/soc/qualcomm/ipq806x/Makefile.inc | 4 ++++ src/soc/rockchip/Makefile.inc | 20 -------------------- src/soc/rockchip/rk3288/Makefile.inc | 4 ++++ src/soc/samsung/Makefile.inc | 2 -- src/soc/samsung/exynos5250/Makefile.inc | 4 ++++ src/soc/samsung/exynos5420/Makefile.inc | 4 ++++ src/soc/ucb/Makefile.inc | 1 - src/soc/ucb/riscv/Makefile.inc | 5 ++++- 26 files changed, 57 insertions(+), 106 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 460393b..f4ee3d6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -54,7 +54,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs # root source directories of coreboot subdirs-y := src/lib src/console src/device subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) -subdirs-y += src/soc +subdirs-y += $(wildcard src/soc/*/*) subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom subdirs-y += $(wildcard src/arch/*) diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc deleted file mode 100644 index bbcfd2c..0000000 --- a/src/soc/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -################################################################################ -## Subdirectories -################################################################################ -subdirs-y += broadcom -subdirs-y += imgtec -subdirs-y += intel -subdirs-y += marvell -subdirs-y += nvidia -subdirs-y += qualcomm -subdirs-y += rockchip -subdirs-y += samsung -subdirs-y += ucb diff --git a/src/soc/broadcom/Makefile.inc b/src/soc/broadcom/Makefile.inc deleted file mode 100644 index 165f923..0000000 --- a/src/soc/broadcom/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2015 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOC_BROADCOM_CYGNUS) += cygnus diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc index 4e09bed..cfec7d4 100644 --- a/src/soc/broadcom/cygnus/Makefile.inc +++ b/src/soc/broadcom/cygnus/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOC_BROADCOM_CYGNUS),y) + bootblock-y += bootblock.c bootblock-y += cbmem.c bootblock-y += i2c.c @@ -102,3 +104,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.tmp \ $(objutil)/broadcom/secimage/secimage -out $@ \ -config util/broadcom/unauth.cfg \ -hmac util/broadcom/khmacsha256 -bl $< + +endif diff --git a/src/soc/imgtec/Makefile.inc b/src/soc/imgtec/Makefile.inc deleted file mode 100644 index 60a9909..0000000 --- a/src/soc/imgtec/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_CPU_IMGTEC_PISTACHIO) += pistachio diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index 0a3d456..010ddb6 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -19,6 +19,8 @@ # MA 02110-1301 USA # +ifeq ($(CONFIG_CPU_IMGTEC_PISTACHIO),y) + # We enable CBFS_SPI_WRAPPER for Pistachio targets. bootblock-y += clocks.c bootblock-y += spi.c @@ -55,3 +57,4 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL) @printf " BIMGTOOL $(subst $(obj)/,,$(@))\n" $(BIMGTOOL) $< $@ $(call loadaddr,bootblock) +endif diff --git a/src/soc/intel/Makefile.inc b/src/soc/intel/Makefile.inc deleted file mode 100644 index f86d6ca..0000000 --- a/src/soc/intel/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -subdirs-$(CONFIG_SOC_INTEL_BAYTRAIL) += baytrail -subdirs-$(CONFIG_SOC_INTEL_BROADWELL) += broadwell -subdirs-$(CONFIG_SOC_INTEL_FSP_BAYTRAIL) += fsp_baytrail diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 6d28c78..78e2da6 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,7 +1,8 @@ +ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) + subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage -subdirs-y += ../common subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -102,3 +103,5 @@ mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x mrc.bin-type := mrc PHONY += baytrail_add_me + +endif diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index ec6b9ae..8b4a0c1 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,7 +1,8 @@ +ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) + subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage -subdirs-y += ../common subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -128,3 +129,5 @@ cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) mrc.bin-type := mrc + +endif diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index d340308..46786e2 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,6 +1,10 @@ +ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL)$(CONFIG_SOC_INTEL_BROADWELL),y) + ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c + +endif diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 2dfb9cb..af4871c 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -17,6 +17,9 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + +ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y) + subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic @@ -87,3 +90,5 @@ endif endif endif + +endif diff --git a/src/soc/marvell/Kconfig b/src/soc/marvell/Kconfig deleted file mode 100644 index 95b8c50..0000000 --- a/src/soc/marvell/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -source src/soc/marvell/bg4cd/Kconfig diff --git a/src/soc/marvell/Makefile.inc b/src/soc/marvell/Makefile.inc deleted file mode 100644 index ef7bcd9..0000000 --- a/src/soc/marvell/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOC_MARVELL_BG4CD) += bg4cd diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc index 4cbca00..4fee80d 100644 --- a/src/soc/marvell/bg4cd/Makefile.inc +++ b/src/soc/marvell/bg4cd/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOC_MARVELL_BG4CD),y) + bootblock-y += cbmem.c bootblock-y += i2c.c bootblock-y += monotonic_timer.c @@ -47,3 +49,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" @mkdir -p $(dir $@) @mv $< $@ + +endif diff --git a/src/soc/nvidia/Makefile.inc b/src/soc/nvidia/Makefile.inc deleted file mode 100644 index 100cb94..0000000 --- a/src/soc/nvidia/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_SOC_NVIDIA_TEGRA124) += tegra124 -subdirs-$(CONFIG_SOC_NVIDIA_TEGRA132) += tegra132 diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 49669eb..78054f4 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOC_NVIDIA_TEGRA124),y) + bootblock-y += bootblock.c bootblock-y += bootblock_asm.S bootblock-y += cbfs.c @@ -102,3 +104,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) $(CBOOTIMAGE) echo "BootLoader = $<,$(call loadaddr,bootblock),$(call loadaddr,bootblock),Complete;" >> $(BCT_WRAPPER) @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" $(CBOOTIMAGE) $(BCT_WRAPPER) $@ + +endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index bfa7088..44976d1 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOC_NVIDIA_TEGRA132),y) + bootblock-y += bootblock.c bootblock-y += bootblock_asm.S bootblock-y += cbfs.c @@ -150,3 +152,5 @@ MTS_FILE_CBFS = mts cbfs-files-y += $(MTS_FILE_CBFS) $(MTS_FILE_CBFS)-file := $(MTS_FILE) $(MTS_FILE_CBFS)-type := raw + +endif diff --git a/src/soc/qualcomm/Makefile.inc b/src/soc/qualcomm/Makefile.inc deleted file mode 100644 index 06b2f2f..0000000 --- a/src/soc/qualcomm/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOC_QC_IPQ806X) += ipq806x diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 6aa10f8..3eb070e 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOC_QC_IPQ806X),y) + bootblock-y += clock.c bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c @@ -88,3 +90,5 @@ mbn-root := 3rdparty/cpu/qualcomm/ipq806x $(foreach f,$(mbn-files),$(eval cbfs-files-y += $(f))\ $(eval $(f)-file := $(mbn-root)/$(f))\ $(eval $(f)-type := raw)) + +endif diff --git a/src/soc/rockchip/Makefile.inc b/src/soc/rockchip/Makefile.inc deleted file mode 100644 index aa67f5c..0000000 --- a/src/soc/rockchip/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Rockchip Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOC_ROCKCHIP_RK3288) += rk3288 diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 441a97f..be41327 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOC_ROCKCHIP_RK3288),y) + IDBTOOL = util/rockchip/make_idb.py #bootblock-y += bootblock.c @@ -79,3 +81,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" @mkdir -p $(dir $@) @$(IDBTOOL) --from=$< --to=$@ --enable-align + +endif diff --git a/src/soc/samsung/Makefile.inc b/src/soc/samsung/Makefile.inc deleted file mode 100644 index 496b5f7..0000000 --- a/src/soc/samsung/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5250) += exynos5250 -subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5420) += exynos5420 diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc index 6525637..1cde349 100644 --- a/src/soc/samsung/exynos5250/Makefile.inc +++ b/src/soc/samsung/exynos5250/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_CPU_SAMSUNG_EXYNOS5250),y) + bootblock-y += spi.c alternate_cbfs.c bootblock-y += bootblock.c bootblock-y += pinmux.c timer.c power.c @@ -51,3 +53,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n" util/exynos/fixed_cksum.py $< $<.cksum 32768 cat 3rdparty/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@ + +endif diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc index 7eb407e..e42fc9a 100644 --- a/src/soc/samsung/exynos5420/Makefile.inc +++ b/src/soc/samsung/exynos5420/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_CPU_SAMSUNG_EXYNOS5420),y) + bootblock-y += spi.c alternate_cbfs.c bootblock-y += bootblock.c bootblock-y += pinmux.c timer.c power.c @@ -53,3 +55,5 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n" util/exynos/variable_cksum.py $< $<.cksum cat 3rdparty/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@ + +endif diff --git a/src/soc/ucb/Makefile.inc b/src/soc/ucb/Makefile.inc deleted file mode 100644 index fe40742..0000000 --- a/src/soc/ucb/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOC_UCB_RISCV) += riscv diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index c25a2fc..1072a2b 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,3 +1,6 @@ -romstage-y += cbmem.c +ifeq ($(CONFIG_SOC_UCB_RISCV),y) +romstage-y += cbmem.c ramstage-y += cbmem.c + +endif

1 0

Patch set updated for coreboot: 184dd37 kbuild: automatically include ECs
by Stefan Reinauer 27 Apr '15

27 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9798 -gerrit commit 184dd375b446e4219bd24b79fcb072f21033abe0 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 27 14:03:47 2015 -0700 kbuild: automatically include ECs This change switches all ECs and the generic EC ACPI code to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in ec/Makefile.inc or in ec/<vendor>/Makefile.inc. This means, vendor and ec directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I29d757d1f8c10a1d0167a76fd0d0f97bac576f6d Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 4 +++- src/ec/Makefile.inc | 2 -- src/ec/acpi/Makefile.inc | 4 ++++ src/ec/compal/Makefile.inc | 1 - src/ec/compal/ene932/Makefile.inc | 4 ++++ src/ec/google/Makefile.inc | 1 - src/ec/google/chromeec/Makefile.inc | 3 +++ src/ec/kontron/Makefile.inc | 1 - src/ec/kontron/it8516e/Makefile.inc | 4 ++++ src/ec/lenovo/Makefile.inc | 2 -- src/ec/lenovo/h8/Makefile.inc | 4 ++++ src/ec/lenovo/pmh7/Makefile.inc | 4 ++++ src/ec/quanta/Makefile.inc | 2 -- src/ec/quanta/ene_kb3940q/Makefile.inc | 5 ++++- src/ec/quanta/it8518/Makefile.inc | 4 ++++ src/ec/smsc/Makefile.inc | 1 - src/ec/smsc/mec1308/Makefile.inc | 4 ++++ 17 files changed, 38 insertions(+), 12 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index fee227c..460393b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -52,7 +52,9 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs ####################################################################### # root source directories of coreboot -subdirs-y := src/lib src/console src/device src/ec $(wildcard src/southbridge/*/*) src/soc +subdirs-y := src/lib src/console src/device +subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) +subdirs-y += src/soc subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom subdirs-y += $(wildcard src/arch/*) diff --git a/src/ec/Makefile.inc b/src/ec/Makefile.inc deleted file mode 100644 index be3da45..0000000 --- a/src/ec/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_EC_ACPI) += acpi -subdirs-y += compal google kontron lenovo smsc quanta diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index b39aaa2..efdd4b1 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_EC_ACPI),y) + ramstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c + +endif diff --git a/src/ec/compal/Makefile.inc b/src/ec/compal/Makefile.inc deleted file mode 100644 index ce75ca6..0000000 --- a/src/ec/compal/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_EC_COMPAL_ENE932) += ene932 diff --git a/src/ec/compal/ene932/Makefile.inc b/src/ec/compal/ene932/Makefile.inc index fb898be..effe34c 100644 --- a/src/ec/compal/ene932/Makefile.inc +++ b/src/ec/compal/ene932/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_EC_COMPAL_ENE932),y) + ramstage-y += ec.c smm-y += ec.c smm-y += ../../../lib/delay.c + +endif diff --git a/src/ec/google/Makefile.inc b/src/ec/google/Makefile.inc deleted file mode 100644 index 9ca3f0f..0000000 --- a/src/ec/google/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_EC_GOOGLE_CHROMEEC) += chromeec diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 8757c0b..5a36f42 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y) + ramstage-y += ec.c crosec_proto.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c @@ -21,3 +23,4 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c endif +endif diff --git a/src/ec/kontron/Makefile.inc b/src/ec/kontron/Makefile.inc deleted file mode 100644 index 8c3b7c7..0000000 --- a/src/ec/kontron/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_EC_KONTRON_IT8516E) += it8516e diff --git a/src/ec/kontron/it8516e/Makefile.inc b/src/ec/kontron/it8516e/Makefile.inc index 1275cf3..6ef87cd 100644 --- a/src/ec/kontron/it8516e/Makefile.inc +++ b/src/ec/kontron/it8516e/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_EC_KONTRON_IT8516E),y) + ramstage-y += ec.c + +endif diff --git a/src/ec/lenovo/Makefile.inc b/src/ec/lenovo/Makefile.inc deleted file mode 100644 index 8865030..0000000 --- a/src/ec/lenovo/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_EC_LENOVO_H8) += h8 -subdirs-$(CONFIG_EC_LENOVO_PMH7) += pmh7 diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index 9fef94c..4829e7b 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_EC_LENOVO_H8),y) + ramstage-y += h8.c + +endif diff --git a/src/ec/lenovo/pmh7/Makefile.inc b/src/ec/lenovo/pmh7/Makefile.inc index f42e0e4..a619cc7 100644 --- a/src/ec/lenovo/pmh7/Makefile.inc +++ b/src/ec/lenovo/pmh7/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_EC_LENOVO_PMH7),y) + ramstage-y += pmh7.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmh7.c romstage-y += pmh7.c + +endif diff --git a/src/ec/quanta/Makefile.inc b/src/ec/quanta/Makefile.inc deleted file mode 100644 index c128aec..0000000 --- a/src/ec/quanta/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_EC_QUANTA_ENE_KB3940Q) += ene_kb3940q -subdirs-$(CONFIG_EC_QUANTA_IT8518) += it8518 diff --git a/src/ec/quanta/ene_kb3940q/Makefile.inc b/src/ec/quanta/ene_kb3940q/Makefile.inc index 1ce9a46..a1ae764 100644 --- a/src/ec/quanta/ene_kb3940q/Makefile.inc +++ b/src/ec/quanta/ene_kb3940q/Makefile.inc @@ -1,4 +1,7 @@ +ifeq ($(CONFIG_EC_QUANTA_ENE_KB3940Q),y) + ramstage-y += ec.c smm-y += ec.c - smm-y += ../../../lib/delay.c + +endif diff --git a/src/ec/quanta/it8518/Makefile.inc b/src/ec/quanta/it8518/Makefile.inc index ccceb6f..daf75ef 100644 --- a/src/ec/quanta/it8518/Makefile.inc +++ b/src/ec/quanta/it8518/Makefile.inc @@ -1,4 +1,8 @@ +ifeq ($(CONFIG_EC_QUANTA_IT8518),y) + romstage-y += ec.c ramstage-y += ec.c smm-y += ec.c smm-y += ../../../lib/delay.c + +endif diff --git a/src/ec/smsc/Makefile.inc b/src/ec/smsc/Makefile.inc deleted file mode 100644 index 3dd9cce..0000000 --- a/src/ec/smsc/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_EC_SMSC_MEC1308) += mec1308 diff --git a/src/ec/smsc/mec1308/Makefile.inc b/src/ec/smsc/mec1308/Makefile.inc index 0accda3..c45f65d 100644 --- a/src/ec/smsc/mec1308/Makefile.inc +++ b/src/ec/smsc/mec1308/Makefile.inc @@ -1,2 +1,6 @@ +ifeq ($(CONFIG_EC_SMSC_MEC1308),y) + ramstage-y += ec.c smm-y += ec.c + +endif

1 0

Patch set updated for coreboot: 1ec8925 kbuild: automatically include northbridges
by Stefan Reinauer 27 Apr '15

27 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9800 -gerrit commit 1ec8925c7f1ea7c64c95b44c9d915544869e6c1c Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 27 14:04:38 2015 -0700 kbuild: automatically include northbridges This change switches all northbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in northbridge/Makefile.inc or in northbridge/<vendor>/Makefile.inc. This means, vendor and northbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I8468154dbfaaaffcba9fda27ba2d7b9049ad5c19 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 4 ++-- src/northbridge/Makefile.inc | 5 ----- src/northbridge/amd/Makefile.inc | 8 -------- src/northbridge/amd/agesa/Makefile.inc | 5 +++++ src/northbridge/amd/amdfam10/Makefile.inc | 4 ++++ src/northbridge/amd/amdk8/Makefile.inc | 4 ++++ src/northbridge/amd/cimx/Makefile.inc | 4 ++++ src/northbridge/amd/gx2/Makefile.inc | 4 ++++ src/northbridge/amd/lx/Makefile.inc | 4 ++++ src/northbridge/amd/pi/Makefile.inc | 4 ++++ src/northbridge/dmp/Makefile.inc | 20 -------------------- src/northbridge/dmp/vortex86ex/Makefile.inc | 4 ++++ src/northbridge/intel/Makefile.inc | 21 --------------------- src/northbridge/intel/e7501/Makefile.inc | 4 ++++ src/northbridge/intel/e7505/Makefile.inc | 4 ++++ src/northbridge/intel/fsp_rangeley/Makefile.inc | 3 +++ src/northbridge/intel/fsp_sandybridge/Makefile.inc | 3 +++ src/northbridge/intel/gm45/Makefile.inc | 4 ++++ src/northbridge/intel/haswell/Makefile.inc | 3 +++ src/northbridge/intel/i3100/Makefile.inc | 4 ++++ src/northbridge/intel/i440bx/Makefile.inc | 4 ++++ src/northbridge/intel/i440lx/Makefile.inc | 4 ++++ src/northbridge/intel/i5000/Makefile.inc | 4 ++++ src/northbridge/intel/i82810/Makefile.inc | 4 ++++ src/northbridge/intel/i82830/Makefile.inc | 4 ++++ src/northbridge/intel/i855/Makefile.inc | 4 ++++ src/northbridge/intel/i945/Makefile.inc | 4 ++++ src/northbridge/intel/nehalem/Makefile.inc | 3 +++ src/northbridge/intel/sandybridge/Makefile.inc | 3 +++ src/northbridge/intel/sch/Makefile.inc | 4 ++++ src/northbridge/rdc/Makefile.inc | 1 - src/northbridge/rdc/r8610/Makefile.inc | 4 ++++ src/northbridge/via/Makefile.inc | 4 ---- src/northbridge/via/cn700/Makefile.inc | 4 ++++ src/northbridge/via/cx700/Makefile.inc | 4 ++++ src/northbridge/via/vx800/Makefile.inc | 4 ++++ src/northbridge/via/vx900/Makefile.inc | 4 ++++ 37 files changed, 118 insertions(+), 61 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index f4ee3d6..2069c33 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -54,8 +54,8 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs # root source directories of coreboot subdirs-y := src/lib src/console src/device subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) -subdirs-y += $(wildcard src/soc/*/*) -subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode +subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) +subdirs-y += src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) diff --git a/src/northbridge/Makefile.inc b/src/northbridge/Makefile.inc deleted file mode 100644 index 1a5b1c8..0000000 --- a/src/northbridge/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -subdirs-y += amd -subdirs-y += dmp -subdirs-y += intel -subdirs-y += rdc -subdirs-y += via diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc deleted file mode 100644 index 80e9961..0000000 --- a/src/northbridge/amd/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) += amdfam10 -subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8 -subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 -subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx -subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA) += agesa -subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI) += pi - -subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 8cf9ae3..09d2d50 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -16,6 +16,9 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y) + subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 @@ -26,3 +29,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += def_callouts.c agesawrapper.c eventlog.c ramstage-y += def_callouts.c agesawrapper.c eventlog.c + +endif diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc index 65bdc03..8a105fd 100644 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ b/src/northbridge/amd/amdfam10/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) + ramstage-y += northbridge.c ramstage-y += misc_control.c romstage-y += amdfam10_util.c @@ -12,3 +14,5 @@ ramstage-y += get_pci1234.c # Enable this if you want to check the values of the PCI routing registers. # Call show_all_routes() anywhere amdfam10.h is included. #ramstage-y += util.c + +endif diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc index eeef9e8..29274f4 100644 --- a/src/northbridge/amd/amdk8/Makefile.inc +++ b/src/northbridge/amd/amdk8/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDK8),y) + ramstage-y += northbridge.c ramstage-y += misc_control.c ramstage-y += get_sblk_pci1234.c @@ -27,3 +29,5 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c # #end # + +endif diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc index 80844c8..a3b1657 100644 --- a/src/northbridge/amd/cimx/Makefile.inc +++ b/src/northbridge/amd/cimx/Makefile.inc @@ -17,4 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_AMD_NB_CIMX),y) + subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 + +endif diff --git a/src/northbridge/amd/gx2/Makefile.inc b/src/northbridge/amd/gx2/Makefile.inc index ad904c4..7936acb 100644 --- a/src/northbridge/amd/gx2/Makefile.inc +++ b/src/northbridge/amd/gx2/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_NORTHBRIDGE_AMD_GX2),y) + ramstage-y += northbridge.c ramstage-y += northbridgeinit.c ramstage-y += grphinit.c + +endif diff --git a/src/northbridge/amd/lx/Makefile.inc b/src/northbridge/amd/lx/Makefile.inc index 5ff227d..19d9e44 100644 --- a/src/northbridge/amd/lx/Makefile.inc +++ b/src/northbridge/amd/lx/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_NORTHBRIDGE_AMD_LX),y) + ramstage-y += northbridge.c ramstage-y += northbridgeinit.c ramstage-y += grphinit.c romstage-y += raminit.c + +endif diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index 3ded87f..9cd7410 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -17,6 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y) + subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 @@ -24,3 +26,5 @@ romstage-y += agesawrapper.c romstage-y += def_callouts.c ramstage-y += agesawrapper.c ramstage-y += def_callouts.c + +endif diff --git a/src/northbridge/dmp/Makefile.inc b/src/northbridge/dmp/Makefile.inc deleted file mode 100644 index 3cfcc48..0000000 --- a/src/northbridge/dmp/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 DMP Electronics Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_NORTHBRIDGE_DMP_VORTEX86EX) += vortex86ex diff --git a/src/northbridge/dmp/vortex86ex/Makefile.inc b/src/northbridge/dmp/vortex86ex/Makefile.inc index 82b07fd..9c83eff 100644 --- a/src/northbridge/dmp/vortex86ex/Makefile.inc +++ b/src/northbridge/dmp/vortex86ex/Makefile.inc @@ -17,5 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_NORTHBRIDGE_DMP_VORTEX86EX),y) + ramstage-y += northbridge.c ramstage-y += xgi_oprom.c + +endif diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc deleted file mode 100644 index 90fa696..0000000 --- a/src/northbridge/intel/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7501) += e7501 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7505) += e7505 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I3100) += i3100 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440BX) += i440bx -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440LX) += i440lx -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_GM45) += gm45 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += nehalem -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += sandybridge -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += sandybridge -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_sandybridge -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_sandybridge -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_rangeley diff --git a/src/northbridge/intel/e7501/Makefile.inc b/src/northbridge/intel/e7501/Makefile.inc index 23eada5..756dc89 100644 --- a/src/northbridge/intel/e7501/Makefile.inc +++ b/src/northbridge/intel/e7501/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7501),y) + ramstage-y += northbridge.c + +endif diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc index 8c50e40..89a5b8c 100644 --- a/src/northbridge/intel/e7505/Makefile.inc +++ b/src/northbridge/intel/e7505/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y) + ramstage-y += northbridge.c romstage-y += raminit.c romstage-y += debug.c + +endif diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index 6cb6cb2..e9f7a85 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -18,6 +18,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY),y) + subdirs-y += fsp ramstage-y += northbridge.c ramstage-y += raminit.c @@ -36,3 +38,4 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/ CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/fsp +endif diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc index ca6f345..c4e699a 100644 --- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc +++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc @@ -18,6 +18,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE),y) + subdirs-y += fsp ramstage-y += northbridge.c ramstage-y += ram_calc.c @@ -36,3 +38,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_sandybridge/fsp +endif diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 1352525..5fb9a44 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -17,6 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y) + romstage-y += early_init.c romstage-y += early_reset.c romstage-y += delay.c @@ -38,3 +40,5 @@ ramstage-y += northbridge.c ramstage-y += gma.c smm-$(CONFIG_HAVE_SMI_HANDLER) += delay.c + +endif diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index ab7e6ef..0173dbf 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -17,6 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y) + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c @@ -52,3 +54,4 @@ mrc.cache-position := 0xfffe0000 mrc.cache-type := mrc_cache endif +endif diff --git a/src/northbridge/intel/i3100/Makefile.inc b/src/northbridge/intel/i3100/Makefile.inc index 3ad40f5..16291bf 100644 --- a/src/northbridge/intel/i3100/Makefile.inc +++ b/src/northbridge/intel/i3100/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I3100),y) + ramstage-y += northbridge.c ramstage-y += pciexp_porta.c ramstage-y += pciexp_porta_ep80579.c + +endif diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index 137d24f..2b32f2b 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -18,7 +18,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) + ramstage-y += northbridge.c romstage-y += raminit.c romstage-y += debug.c + +endif diff --git a/src/northbridge/intel/i440lx/Makefile.inc b/src/northbridge/intel/i440lx/Makefile.inc index a67331f..dc1a1df 100644 --- a/src/northbridge/intel/i440lx/Makefile.inc +++ b/src/northbridge/intel/i440lx/Makefile.inc @@ -18,4 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440LX),y) + ramstage-y += northbridge.c + +endif diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index 767cd7e..3c98e66 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -17,6 +17,10 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I5000),y) + ramstage-y += northbridge.c romstage-y += raminit.c cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S + +endif diff --git a/src/northbridge/intel/i82810/Makefile.inc b/src/northbridge/intel/i82810/Makefile.inc index 137d24f..1fb5e2d 100644 --- a/src/northbridge/intel/i82810/Makefile.inc +++ b/src/northbridge/intel/i82810/Makefile.inc @@ -18,7 +18,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I82810),y) + ramstage-y += northbridge.c romstage-y += raminit.c romstage-y += debug.c + +endif diff --git a/src/northbridge/intel/i82830/Makefile.inc b/src/northbridge/intel/i82830/Makefile.inc index 2394570..ebbae81 100644 --- a/src/northbridge/intel/i82830/Makefile.inc +++ b/src/northbridge/intel/i82830/Makefile.inc @@ -1,4 +1,8 @@ +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I82830),y) + ramstage-y += northbridge.c ramstage-y += vga.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +endif diff --git a/src/northbridge/intel/i855/Makefile.inc b/src/northbridge/intel/i855/Makefile.inc index 23eada5..4dfc358 100644 --- a/src/northbridge/intel/i855/Makefile.inc +++ b/src/northbridge/intel/i855/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I855),y) + ramstage-y += northbridge.c + +endif diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index d3a795c..19bba6d 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -17,6 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y) + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c @@ -29,3 +31,5 @@ romstage-y += errata.c romstage-y += debug.c smm-y += udelay.c + +endif diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index ff65628..0b58f8d 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -17,6 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y) + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c @@ -42,3 +44,4 @@ mrc.cache-file := $(obj)/mrc.cache mrc.cache-position := 0xfffe0000 mrc.cache-type := mrc_cache +endif diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 3930a6e..9f554f7 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -17,6 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE)$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y) + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c @@ -65,3 +67,4 @@ mrc.cache-position := $(mrc-cache-position-y) mrc.cache-type := mrc_cache endif +endif diff --git a/src/northbridge/intel/sch/Makefile.inc b/src/northbridge/intel/sch/Makefile.inc index 16152b7..7757179 100644 --- a/src/northbridge/intel/sch/Makefile.inc +++ b/src/northbridge/intel/sch/Makefile.inc @@ -17,7 +17,11 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SCH),y) + ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += port_access.c ramstage-y += acpi.c + +endif diff --git a/src/northbridge/rdc/Makefile.inc b/src/northbridge/rdc/Makefile.inc deleted file mode 100644 index 9b7a0d0..0000000 --- a/src/northbridge/rdc/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_NORTHBRIDGE_RDC_R8610) += r8610 diff --git a/src/northbridge/rdc/r8610/Makefile.inc b/src/northbridge/rdc/r8610/Makefile.inc index 35e423a..0f2f866 100644 --- a/src/northbridge/rdc/r8610/Makefile.inc +++ b/src/northbridge/rdc/r8610/Makefile.inc @@ -18,4 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_NORTHBRIDGE_RDC_R8610),y) + ramstage-y += northbridge.c + +endif diff --git a/src/northbridge/via/Makefile.inc b/src/northbridge/via/Makefile.inc deleted file mode 100644 index b3d595e..0000000 --- a/src/northbridge/via/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700 -subdirs-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700 -subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX800) += vx800 -subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX900) += vx900 diff --git a/src/northbridge/via/cn700/Makefile.inc b/src/northbridge/via/cn700/Makefile.inc index ebe915f..9feddd5 100644 --- a/src/northbridge/via/cn700/Makefile.inc +++ b/src/northbridge/via/cn700/Makefile.inc @@ -18,6 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_NORTHBRIDGE_VIA_CN700),y) + ramstage-y += northbridge.c ramstage-y += agp.c ramstage-y += vga.c + +endif diff --git a/src/northbridge/via/cx700/Makefile.inc b/src/northbridge/via/cx700/Makefile.inc index 03b52c6..57bf2b5 100644 --- a/src/northbridge/via/cx700/Makefile.inc +++ b/src/northbridge/via/cx700/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_NORTHBRIDGE_VIA_CX700),y) + ramstage-y += reset.c ramstage-y += northbridge.c @@ -24,3 +26,5 @@ ramstage-y += agp.c ramstage-y += lpc.c ramstage-y += sata.c ramstage-y += vga.c + +endif diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc index 2305db9..951fc71 100644 --- a/src/northbridge/via/vx800/Makefile.inc +++ b/src/northbridge/via/vx800/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_NORTHBRIDGE_VIA_VX800),y) + ramstage-y += northbridge.c ramstage-y += vga.c ramstage-y += lpc.c @@ -25,3 +27,5 @@ ramstage-y += ide.c chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index b510309..6178c11 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -17,6 +17,8 @@ ## along with this program. If not, see <http://www.gnu.org/licenses/>. ## +ifeq ($(CONFIG_NORTHBRIDGE_VIA_VX900),y) + romstage-y += pci_util.c romstage-y += early_smbus.c romstage-y += early_vx900.c @@ -46,3 +48,5 @@ ramstage-y += ./../../../drivers/pc80/vga/vga_io.c chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc bootblock-y += romstrap.ld + +endif

1 0

Patch merged into coreboot/master: d0398f1 cbfstool: remove gcc-specific -Og flag
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit d0398f135f61c8e9c4d50655d08a35d2816690fb Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sun Apr 26 21:41:41 2015 +0200 cbfstool: remove gcc-specific -Og flag The new -Og optimization level is only available in gcc version 4.8 or higher. Clang fails on this too as of now (with "invalid integral value 'g' in '-Og'"). The gain of this does not outweigh this limitation at all. The flag was added in 0e53931. Change-Id: I2b2dfc786369653d768f25be94b53329451ae1b4 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: http://review.coreboot.org/9999 Tested-by: build bot (Jenkins) Reviewed-by: Sol Boucher <solb(a)chromium.org> See http://review.coreboot.org/9999 for details. -gerrit

1 0

Patch set updated for coreboot: c82e8b6 kbuild: automatically include ECs
by Stefan Reinauer 27 Apr '15

27 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9798 -gerrit commit c82e8b6fb1c21cd3daaf7f130998b33952e6612c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Apr 17 23:50:33 2015 -0700 kbuild: automatically include ECs This change switches all ECs and the generic EC ACPI code to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in ec/Makefile.inc or in ec/<vendor>/Makefile.inc. This means, vendor and ec directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I29d757d1f8c10a1d0167a76fd0d0f97bac576f6d Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 4 +++- src/ec/Makefile.inc | 2 -- src/ec/acpi/Makefile.inc | 4 ++++ src/ec/compal/Makefile.inc | 1 - src/ec/compal/ene932/Makefile.inc | 4 ++++ src/ec/google/Makefile.inc | 1 - src/ec/google/chromeec/Makefile.inc | 3 +++ src/ec/kontron/Makefile.inc | 1 - src/ec/kontron/it8516e/Makefile.inc | 4 ++++ src/ec/lenovo/Makefile.inc | 2 -- src/ec/lenovo/h8/Makefile.inc | 4 ++++ src/ec/lenovo/pmh7/Makefile.inc | 4 ++++ src/ec/quanta/Makefile.inc | 2 -- src/ec/quanta/ene_kb3940q/Makefile.inc | 5 ++++- src/ec/quanta/it8518/Makefile.inc | 4 ++++ src/ec/smsc/Makefile.inc | 1 - src/ec/smsc/mec1308/Makefile.inc | 4 ++++ 17 files changed, 38 insertions(+), 12 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index fee227c..460393b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -52,7 +52,9 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs ####################################################################### # root source directories of coreboot -subdirs-y := src/lib src/console src/device src/ec $(wildcard src/southbridge/*/*) src/soc +subdirs-y := src/lib src/console src/device +subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) +subdirs-y += src/soc subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom subdirs-y += $(wildcard src/arch/*) diff --git a/src/ec/Makefile.inc b/src/ec/Makefile.inc deleted file mode 100644 index be3da45..0000000 --- a/src/ec/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_EC_ACPI) += acpi -subdirs-y += compal google kontron lenovo smsc quanta diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index b39aaa2..efdd4b1 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_EC_ACPI),y) + ramstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c + +endif diff --git a/src/ec/compal/Makefile.inc b/src/ec/compal/Makefile.inc deleted file mode 100644 index ce75ca6..0000000 --- a/src/ec/compal/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_EC_COMPAL_ENE932) += ene932 diff --git a/src/ec/compal/ene932/Makefile.inc b/src/ec/compal/ene932/Makefile.inc index fb898be..effe34c 100644 --- a/src/ec/compal/ene932/Makefile.inc +++ b/src/ec/compal/ene932/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_EC_COMPAL_ENE932),y) + ramstage-y += ec.c smm-y += ec.c smm-y += ../../../lib/delay.c + +endif diff --git a/src/ec/google/Makefile.inc b/src/ec/google/Makefile.inc deleted file mode 100644 index 9ca3f0f..0000000 --- a/src/ec/google/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_EC_GOOGLE_CHROMEEC) += chromeec diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 8757c0b..5a36f42 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y) + ramstage-y += ec.c crosec_proto.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c @@ -21,3 +23,4 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c endif +endif diff --git a/src/ec/kontron/Makefile.inc b/src/ec/kontron/Makefile.inc deleted file mode 100644 index 8c3b7c7..0000000 --- a/src/ec/kontron/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_EC_KONTRON_IT8516E) += it8516e diff --git a/src/ec/kontron/it8516e/Makefile.inc b/src/ec/kontron/it8516e/Makefile.inc index 1275cf3..6ef87cd 100644 --- a/src/ec/kontron/it8516e/Makefile.inc +++ b/src/ec/kontron/it8516e/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_EC_KONTRON_IT8516E),y) + ramstage-y += ec.c + +endif diff --git a/src/ec/lenovo/Makefile.inc b/src/ec/lenovo/Makefile.inc deleted file mode 100644 index 8865030..0000000 --- a/src/ec/lenovo/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_EC_LENOVO_H8) += h8 -subdirs-$(CONFIG_EC_LENOVO_PMH7) += pmh7 diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index 9fef94c..4829e7b 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_EC_LENOVO_H8),y) + ramstage-y += h8.c + +endif diff --git a/src/ec/lenovo/pmh7/Makefile.inc b/src/ec/lenovo/pmh7/Makefile.inc index f42e0e4..a619cc7 100644 --- a/src/ec/lenovo/pmh7/Makefile.inc +++ b/src/ec/lenovo/pmh7/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_EC_LENOVO_PMH7),y) + ramstage-y += pmh7.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmh7.c romstage-y += pmh7.c + +endif diff --git a/src/ec/quanta/Makefile.inc b/src/ec/quanta/Makefile.inc deleted file mode 100644 index c128aec..0000000 --- a/src/ec/quanta/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_EC_QUANTA_ENE_KB3940Q) += ene_kb3940q -subdirs-$(CONFIG_EC_QUANTA_IT8518) += it8518 diff --git a/src/ec/quanta/ene_kb3940q/Makefile.inc b/src/ec/quanta/ene_kb3940q/Makefile.inc index 1ce9a46..a1ae764 100644 --- a/src/ec/quanta/ene_kb3940q/Makefile.inc +++ b/src/ec/quanta/ene_kb3940q/Makefile.inc @@ -1,4 +1,7 @@ +ifeq ($(CONFIG_EC_QUANTA_ENE_KB3940Q),y) + ramstage-y += ec.c smm-y += ec.c - smm-y += ../../../lib/delay.c + +endif diff --git a/src/ec/quanta/it8518/Makefile.inc b/src/ec/quanta/it8518/Makefile.inc index ccceb6f..daf75ef 100644 --- a/src/ec/quanta/it8518/Makefile.inc +++ b/src/ec/quanta/it8518/Makefile.inc @@ -1,4 +1,8 @@ +ifeq ($(CONFIG_EC_QUANTA_IT8518),y) + romstage-y += ec.c ramstage-y += ec.c smm-y += ec.c smm-y += ../../../lib/delay.c + +endif diff --git a/src/ec/smsc/Makefile.inc b/src/ec/smsc/Makefile.inc deleted file mode 100644 index 3dd9cce..0000000 --- a/src/ec/smsc/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_EC_SMSC_MEC1308) += mec1308 diff --git a/src/ec/smsc/mec1308/Makefile.inc b/src/ec/smsc/mec1308/Makefile.inc index 0accda3..c45f65d 100644 --- a/src/ec/smsc/mec1308/Makefile.inc +++ b/src/ec/smsc/mec1308/Makefile.inc @@ -1,2 +1,6 @@ +ifeq ($(CONFIG_EC_SMSC_MEC1308),y) + ramstage-y += ec.c smm-y += ec.c + +endif

1 0

Patch set updated for coreboot: b38205d kbuild: automatically include southbridges
by Stefan Reinauer 27 Apr '15

27 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9796 -gerrit commit b38205dc64564af5bba1d601d02c51afbe135d3a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 27 13:47:06 2015 -0700 kbuild: automatically include southbridges This change switches all southbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in southbridge/Makefile.inc or in southbridge/<vendor>/Makefile.inc. In order to be able to drop southbridge/amd/Makefile.inc, some scattered source files had to be moved to a southbridge/amd/common directory, in accordance to what we are doing on other architectures already. This means, vendor and southbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 5 +- src/mainboard/amd/persimmon/mainboard.c | 2 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/biostar/am1ml/mainboard.c | 2 +- src/mainboard/biostar/am1ml/mptable.c | 2 +- src/mainboard/gizmosphere/gizmo2/mainboard.c | 2 +- src/mainboard/gizmosphere/gizmo2/mptable.c | 2 +- src/mainboard/hp/abm/mainboard.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 2 +- src/mainboard/pcengines/apu1/mainboard.c | 2 +- src/mainboard/pcengines/apu1/mptable.c | 2 +- src/southbridge/Makefile.inc | 10 -- src/southbridge/amd/Makefile.inc | 27 ---- src/southbridge/amd/agesa/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/pci.c | 2 +- src/southbridge/amd/amd8111/Makefile.inc | 4 + src/southbridge/amd/amd8131/Makefile.inc | 4 + src/southbridge/amd/amd8132/Makefile.inc | 4 + src/southbridge/amd/amd8151/Makefile.inc | 4 + src/southbridge/amd/amd_pci_util.c | 204 ------------------------ src/southbridge/amd/amd_pci_util.h | 48 ------ src/southbridge/amd/cimx/Makefile.inc | 9 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/amd/common/Makefile.inc | 7 + src/southbridge/amd/common/amd_pci_util.c | 204 ++++++++++++++++++++++++ src/southbridge/amd/common/amd_pci_util.h | 48 ++++++ src/southbridge/amd/cs5535/Makefile.inc | 4 + src/southbridge/amd/cs5536/Makefile.inc | 6 +- src/southbridge/amd/pi/hudson/pci.c | 2 +- src/southbridge/amd/rs690/Makefile.inc | 4 + src/southbridge/amd/rs780/Makefile.inc | 4 + src/southbridge/amd/sb600/Makefile.inc | 4 + src/southbridge/amd/sb700/Makefile.inc | 4 + src/southbridge/amd/sb800/Makefile.inc | 4 + src/southbridge/amd/sr5650/Makefile.inc | 4 + src/southbridge/broadcom/Makefile.inc | 3 - src/southbridge/broadcom/bcm21000/Makefile.inc | 4 + src/southbridge/broadcom/bcm5780/Makefile.inc | 4 + src/southbridge/broadcom/bcm5785/Makefile.inc | 4 + src/southbridge/dmp/Makefile.inc | 20 --- src/southbridge/dmp/vortex86ex/Makefile.inc | 4 + src/southbridge/intel/Makefile.inc | 19 --- src/southbridge/intel/bd82x6x/Makefile.inc | 4 + src/southbridge/intel/common/Makefile.inc | 4 + src/southbridge/intel/esb6300/Makefile.inc | 4 + src/southbridge/intel/fsp_bd82x6x/Makefile.inc | 4 + src/southbridge/intel/fsp_rangeley/Makefile.inc | 4 + src/southbridge/intel/i3100/Makefile.inc | 4 + src/southbridge/intel/i82371eb/Makefile.inc | 4 + src/southbridge/intel/i82801ax/Makefile.inc | 4 + src/southbridge/intel/i82801bx/Makefile.inc | 4 + src/southbridge/intel/i82801cx/Makefile.inc | 4 + src/southbridge/intel/i82801dx/Makefile.inc | 4 + src/southbridge/intel/i82801ex/Makefile.inc | 4 + src/southbridge/intel/i82801gx/Makefile.inc | 4 + src/southbridge/intel/i82801ix/Makefile.inc | 4 + src/southbridge/intel/i82870/Makefile.inc | 4 + src/southbridge/intel/ibexpeak/Makefile.inc | 4 + src/southbridge/intel/lynxpoint/Makefile.inc | 4 + src/southbridge/intel/sch/Makefile.inc | 4 + src/southbridge/nvidia/Makefile.inc | 2 - src/southbridge/nvidia/ck804/Makefile.inc | 4 + src/southbridge/nvidia/mcp55/Makefile.inc | 4 + src/southbridge/rdc/Makefile.inc | 1 - src/southbridge/rdc/r8610/Makefile.inc | 4 + src/southbridge/ricoh/Makefile.inc | 1 - src/southbridge/ricoh/rl5c476/Makefile.inc | 4 + src/southbridge/sis/Makefile.inc | 1 - src/southbridge/sis/sis966/Makefile.inc | 4 + src/southbridge/ti/Makefile.inc | 22 --- src/southbridge/ti/pci1x2x/Makefile.inc | 6 +- src/southbridge/ti/pci7420/Makefile.inc | 4 + src/southbridge/ti/pcixx12/Makefile.inc | 4 + src/southbridge/via/Makefile.inc | 2 - src/southbridge/via/k8t890/Makefile.inc | 4 + src/southbridge/via/vt8237r/Makefile.inc | 4 + 77 files changed, 461 insertions(+), 381 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index b67f145..fee227c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -52,11 +52,10 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs ####################################################################### # root source directories of coreboot -subdirs-y := src/lib src/console src/device src/ec src/southbridge src/soc +subdirs-y := src/lib src/console src/device src/ec $(wildcard src/southbridge/*/*) src/soc subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom -subdirs-y += src/arch/arm src/arch/arm64 src/arch/mips src/arch/riscv -subdirs-y += src/arch/x86 +subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += site-local diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 58ac983..9479b2b 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -24,7 +24,7 @@ #include <arch/io.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 0cf57bd..b5f6535 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -27,7 +27,7 @@ #include <stdint.h> #include <cpu/amd/amdfam14.h> #include <SBPLATFORM.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index fed21ba..d402150 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -33,7 +33,7 @@ #include <northbridge/amd/agesa/agesawrapper.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c index b2851ff..f80b974 100644 --- a/src/mainboard/biostar/am1ml/mptable.c +++ b/src/mainboard/biostar/am1ml/mptable.c @@ -27,7 +27,7 @@ #include <cpu/amd/amdfam16.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> static void *smp_write_config_table(void *v) diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index c4a20c6..a95e2ee 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <cpu/amd/agesa/s3_resume.h> diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c index 192b0c0..c61952f 100644 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ b/src/mainboard/gizmosphere/gizmo2/mptable.c @@ -27,7 +27,7 @@ #include <cpu/amd/amdfam16.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> static void *smp_write_config_table(void *v) diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index adb7093..71193bb 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -26,7 +26,7 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <cpu/amd/agesa/s3_resume.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d67e072..2dc92e7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -30,7 +30,7 @@ #include <device/pci.h> #include <device/pci_def.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <southbridge/amd/cimx/cimx_util.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index cc73c83..5d02877 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -30,7 +30,7 @@ #include <stdint.h> #include <string.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 1ba0e23..3b8541c 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -24,7 +24,7 @@ #include <arch/io.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c index 03fa9f3..95a00af 100644 --- a/src/mainboard/pcengines/apu1/mptable.c +++ b/src/mainboard/pcengines/apu1/mptable.c @@ -27,7 +27,7 @@ #include <stdint.h> #include <cpu/amd/amdfam14.h> #include <SBPLATFORM.h> -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> diff --git a/src/southbridge/Makefile.inc b/src/southbridge/Makefile.inc deleted file mode 100644 index 106752b..0000000 --- a/src/southbridge/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -subdirs-y += amd -subdirs-y += broadcom -subdirs-y += dmp -subdirs-y += intel -subdirs-y += nvidia -subdirs-y += rdc -subdirs-y += ricoh -subdirs-y += sis -subdirs-y += ti -subdirs-y += via diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc deleted file mode 100644 index cfb89d5..0000000 --- a/src/southbridge/amd/Makefile.inc +++ /dev/null @@ -1,27 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8131) += amd8131 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8132) += amd8132 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8151) += amd8151 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS690) += rs690 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB600) += sb600 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += pi -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += pi - -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index fdd5d80..89d41b4 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -16,5 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 5858cd2..cf1626d 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "hudson.h" -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <bootstate.h> diff --git a/src/southbridge/amd/amd8111/Makefile.inc b/src/southbridge/amd/amd8111/Makefile.inc index c5b2688..4c9ebae 100644 --- a/src/southbridge/amd/amd8111/Makefile.inc +++ b/src/southbridge/amd/amd8111/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y) + ramstage-y += amd8111.c ramstage-y += usb.c ramstage-y += lpc.c @@ -9,3 +11,5 @@ ramstage-y += nic.c ramstage-y += pci.c ramstage-y += smbus.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/amd/amd8131/Makefile.inc b/src/southbridge/amd/amd8131/Makefile.inc index ce96c97..8ec2691 100644 --- a/src/southbridge/amd/amd8131/Makefile.inc +++ b/src/southbridge/amd/amd8131/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8131),y) + ramstage-y += bridge.c + +endif diff --git a/src/southbridge/amd/amd8132/Makefile.inc b/src/southbridge/amd/amd8132/Makefile.inc index ce96c97..75dce39 100644 --- a/src/southbridge/amd/amd8132/Makefile.inc +++ b/src/southbridge/amd/amd8132/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y) + ramstage-y += bridge.c + +endif diff --git a/src/southbridge/amd/amd8151/Makefile.inc b/src/southbridge/amd/amd8151/Makefile.inc index dcb3c73..07edf58 100644 --- a/src/southbridge/amd/amd8151/Makefile.inc +++ b/src/southbridge/amd/amd8151/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8151),y) + ramstage-y += agp3.c + +endif diff --git a/src/southbridge/amd/amd_pci_util.c b/src/southbridge/amd/amd_pci_util.c deleted file mode 100644 index 9f2cc5c..0000000 --- a/src/southbridge/amd/amd_pci_util.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/pci.h> -#include <arch/io.h> -#include <string.h> -#include "amd_pci_util.h" -#include <pc80/i8259.h> -#include "amd_pci_int_defs.h" -#include "amd_pci_int_types.h" - -#ifndef __PRE_RAM__ - -const struct pirq_struct * pirq_data_ptr = NULL; -u32 pirq_data_size = 0; -const u8 * intr_data_ptr = NULL; -const u8 * picr_data_ptr = NULL; - -/* - * Read the FCH PCI_INTR registers 0xC00/0xC01 at a - * given index and a given PIC (0) or IOAPIC (1) mode - */ -u8 read_pci_int_idx(u8 index, int mode) -{ - outb((mode << 7) | index, PCI_INTR_INDEX); - return inb(PCI_INTR_DATA); -} - -/* - * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 - * at a given index and PIC (0) or IOAPIC (1) mode - */ -void write_pci_int_idx(u8 index, int mode, u8 data) -{ - outb((mode << 7) | index, PCI_INTR_INDEX); - outb(data, PCI_INTR_DATA); -} - -/* - * Write the FCH PCI_INTR registers 0xC00/0xC01 with values - * given in global variables intr_data and picr_data. - * These variables are defined in mainboard.c - */ -void write_pci_int_table (void) -{ - u8 byte; - - if(picr_data_ptr == NULL || intr_data_ptr == NULL){ - printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" - "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); - return; - } - - /* PIC IRQ routine */ - printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n" - "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); - for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { - if (intr_types[byte]) { - write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); - printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", - byte, intr_types[byte], read_pci_int_idx(byte, 0)); - } - } - - /* APIC IRQ routine */ - printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n" - "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); - for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { - if (intr_types[byte]) { - write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); - printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", - byte, intr_types[byte], read_pci_int_idx(byte, 1)); - } - } -} - -/* - * Function to write the PCI config space Interrupt - * registers based on the values given in PCI_INTR - * table at I/O port 0xC00/0xC01 - */ -void write_pci_cfg_irqs(void) -{ - device_t dev = NULL; /* Our current device to route IRQs to */ - device_t target_dev = NULL; /* The bridge that a device may be connected to */ - u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ - u16 target_pin = 0; /* Pin we will search our tables for */ - u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ - u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ - u8 bus = 0; /* A PCI Device Bus number */ - u16 devfn = 0; /* A PCI Device and Function number */ - u8 bridged_device = 0; /* This device is on a PCI bridge */ - u32 i = 0; - - if (pirq_data_ptr == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" - " 'mainboard_pirq_data' structure does not exist\n"); - return; - } - - /* Populate the PCI cfg space header with the IRQ assignment */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); - - for (dev = all_devices; dev; dev = dev->next) { - /* - * Step 1: Get the INT_PIN and device structure to look for in the - * PCI_INTR table pirq_data - */ - target_dev = NULL; - target_pin = get_pci_irq_pins(dev, &target_dev); - if (target_dev == NULL) - continue; - - if (target_pin < 1) - continue; - - /* Get the original INT_PIN for record keeping */ - int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); - if (int_pin < 1 || int_pin > 4) - continue; /* Device has invalid INT_PIN so skip it */ - - bus = target_dev->bus->secondary; - devfn = target_dev->path.pci.devfn; - - /* - * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR - * register (0xC00) index for this device - */ - pci_intr_idx = 0xBAD; /* Will check to make sure it changed */ - for (i = 0; i < pirq_data_size; i++) { - if (pirq_data_ptr[i].devfn != devfn) - continue; - - /* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */ - pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; - printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i); - break; - } - - /* - * Step 3: Make sure we got a valid index and use it to get - * the IRQ number from the PCI_INTR register table - */ - if (pci_intr_idx == 0xBAD) { /* Not on a bridge or in pirq_data table, skip it */ - printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn); - continue; - } else if (pci_intr_idx == 0x1F) { /* Index found is not defined */ - printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n"); - continue; - } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { /* Index out of bounds */ - printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n", - __func__, pci_intr_idx, FCH_INT_TABLE_SIZE); - continue; - } - - /* Find the value to program into the INT_LINE register from the PCI_INTR registers */ - int_line = read_pci_int_idx(pci_intr_idx, 0); - if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ - printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n"); - continue; - } - - /* - * Step 4: Program the INT_LINE register in this device's - * PCI config space with the IRQ number we found in step 3 - * and make it Level Triggered - */ - pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); - - /* Set this IRQ to level triggered since it is used by a PCI device */ - i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); - - /* - * Step 5: Print out debug info and move on to next device - */ - printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", - int_pin, pin_to_str(int_pin)); - if (bridged_device) - printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - target_pin, pin_to_str(target_pin)); - printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" - "\tINT_LINE\t: 0x%X (IRQ %d)\n", - pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line); - } /* for (dev = all_devices) */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); -} -#endif /* __PRE_RAM__ */ diff --git a/src/southbridge/amd/amd_pci_util.h b/src/southbridge/amd/amd_pci_util.h deleted file mode 100644 index 1d1e52b..0000000 --- a/src/southbridge/amd/amd_pci_util.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef AMD_PCI_UTIL_H -#define AMD_PCI_UTIL_H - -#include <stdint.h> -#include "amd_pci_int_defs.h" - -/* FCH index/data registers */ -#define PCI_INTR_INDEX 0xc00 -#define PCI_INTR_DATA 0xc01 - -#ifndef __PRE_RAM__ - -struct pirq_struct { - u8 devfn; - u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ -}; - -extern const struct pirq_struct * pirq_data_ptr; -extern u32 pirq_data_size; -extern const u8 * intr_data_ptr; -extern const u8 * picr_data_ptr; - -u8 read_pci_int_idx(u8 index, int mode); -void write_pci_int_idx(u8 index, int mode, u8 data); -void write_pci_cfg_irqs(void); -void write_pci_int_table (void); -#endif /* __PRE_RAM */ - -#endif /* AMD_PCI_UTIL_H */ diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index aacfc58..0754469 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -16,10 +16,15 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # + subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 -romstage-y += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c -ramstage-y += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index f4a7aa3..ffa3290 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -38,7 +38,7 @@ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ #include "smbus.h" #include "fan.h" -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> /*implement in mainboard.c*/ void set_pcie_reset(void); diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc new file mode 100644 index 0000000..1f847cd --- /dev/null +++ b/src/southbridge/amd/common/Makefile.inc @@ -0,0 +1,7 @@ +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c new file mode 100644 index 0000000..9f2cc5c --- /dev/null +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include "amd_pci_util.h" +#include <pc80/i8259.h> +#include "amd_pci_int_defs.h" +#include "amd_pci_int_types.h" + +#ifndef __PRE_RAM__ + +const struct pirq_struct * pirq_data_ptr = NULL; +u32 pirq_data_size = 0; +const u8 * intr_data_ptr = NULL; +const u8 * picr_data_ptr = NULL; + +/* + * Read the FCH PCI_INTR registers 0xC00/0xC01 at a + * given index and a given PIC (0) or IOAPIC (1) mode + */ +u8 read_pci_int_idx(u8 index, int mode) +{ + outb((mode << 7) | index, PCI_INTR_INDEX); + return inb(PCI_INTR_DATA); +} + +/* + * Write a value to the FCH PCI_INTR registers 0xC00/0xC01 + * at a given index and PIC (0) or IOAPIC (1) mode + */ +void write_pci_int_idx(u8 index, int mode, u8 data) +{ + outb((mode << 7) | index, PCI_INTR_INDEX); + outb(data, PCI_INTR_DATA); +} + +/* + * Write the FCH PCI_INTR registers 0xC00/0xC01 with values + * given in global variables intr_data and picr_data. + * These variables are defined in mainboard.c + */ +void write_pci_int_table (void) +{ + u8 byte; + + if(picr_data_ptr == NULL || intr_data_ptr == NULL){ + printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" + "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); + return; + } + + /* PIC IRQ routine */ + printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n" + "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); + for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { + if (intr_types[byte]) { + write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); + printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", + byte, intr_types[byte], read_pci_int_idx(byte, 0)); + } + } + + /* APIC IRQ routine */ + printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n" + "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); + for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { + if (intr_types[byte]) { + write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); + printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", + byte, intr_types[byte], read_pci_int_idx(byte, 1)); + } + } +} + +/* + * Function to write the PCI config space Interrupt + * registers based on the values given in PCI_INTR + * table at I/O port 0xC00/0xC01 + */ +void write_pci_cfg_irqs(void) +{ + device_t dev = NULL; /* Our current device to route IRQs to */ + device_t target_dev = NULL; /* The bridge that a device may be connected to */ + u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ + u16 target_pin = 0; /* Pin we will search our tables for */ + u16 int_line = 0; /* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */ + u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ + u8 bus = 0; /* A PCI Device Bus number */ + u16 devfn = 0; /* A PCI Device and Function number */ + u8 bridged_device = 0; /* This device is on a PCI bridge */ + u32 i = 0; + + if (pirq_data_ptr == NULL) { + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" + " 'mainboard_pirq_data' structure does not exist\n"); + return; + } + + /* Populate the PCI cfg space header with the IRQ assignment */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); + + for (dev = all_devices; dev; dev = dev->next) { + /* + * Step 1: Get the INT_PIN and device structure to look for in the + * PCI_INTR table pirq_data + */ + target_dev = NULL; + target_pin = get_pci_irq_pins(dev, &target_dev); + if (target_dev == NULL) + continue; + + if (target_pin < 1) + continue; + + /* Get the original INT_PIN for record keeping */ + int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); + if (int_pin < 1 || int_pin > 4) + continue; /* Device has invalid INT_PIN so skip it */ + + bus = target_dev->bus->secondary; + devfn = target_dev->path.pci.devfn; + + /* + * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR + * register (0xC00) index for this device + */ + pci_intr_idx = 0xBAD; /* Will check to make sure it changed */ + for (i = 0; i < pirq_data_size; i++) { + if (pirq_data_ptr[i].devfn != devfn) + continue; + + /* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */ + pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1]; + printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i); + break; + } + + /* + * Step 3: Make sure we got a valid index and use it to get + * the IRQ number from the PCI_INTR register table + */ + if (pci_intr_idx == 0xBAD) { /* Not on a bridge or in pirq_data table, skip it */ + printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn); + continue; + } else if (pci_intr_idx == 0x1F) { /* Index found is not defined */ + printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n"); + continue; + } else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) { /* Index out of bounds */ + printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n", + __func__, pci_intr_idx, FCH_INT_TABLE_SIZE); + continue; + } + + /* Find the value to program into the INT_LINE register from the PCI_INTR registers */ + int_line = read_pci_int_idx(pci_intr_idx, 0); + if (int_line == PIRQ_NC) { /* The IRQ found is disabled */ + printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n"); + continue; + } + + /* + * Step 4: Program the INT_LINE register in this device's + * PCI config space with the IRQ number we found in step 3 + * and make it Level Triggered + */ + pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line); + + /* Set this IRQ to level triggered since it is used by a PCI device */ + i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); + + /* + * Step 5: Print out debug info and move on to next device + */ + printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", + int_pin, pin_to_str(int_pin)); + if (bridged_device) + printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", + target_pin, pin_to_str(target_pin)); + printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" + "\tINT_LINE\t: 0x%X (IRQ %d)\n", + pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line); + } /* for (dev = all_devices) */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); +} +#endif /* __PRE_RAM__ */ diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h new file mode 100644 index 0000000..1d1e52b --- /dev/null +++ b/src/southbridge/amd/common/amd_pci_util.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef AMD_PCI_UTIL_H +#define AMD_PCI_UTIL_H + +#include <stdint.h> +#include "amd_pci_int_defs.h" + +/* FCH index/data registers */ +#define PCI_INTR_INDEX 0xc00 +#define PCI_INTR_DATA 0xc01 + +#ifndef __PRE_RAM__ + +struct pirq_struct { + u8 devfn; + u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ +}; + +extern const struct pirq_struct * pirq_data_ptr; +extern u32 pirq_data_size; +extern const u8 * intr_data_ptr; +extern const u8 * picr_data_ptr; + +u8 read_pci_int_idx(u8 index, int mode); +void write_pci_int_idx(u8 index, int mode, u8 data); +void write_pci_cfg_irqs(void); +void write_pci_int_table (void); +#endif /* __PRE_RAM */ + +#endif /* AMD_PCI_UTIL_H */ diff --git a/src/southbridge/amd/cs5535/Makefile.inc b/src/southbridge/amd/cs5535/Makefile.inc index 6f65e2e..3785cd4 100644 --- a/src/southbridge/amd/cs5535/Makefile.inc +++ b/src/southbridge/amd/cs5535/Makefile.inc @@ -1,4 +1,8 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5535),y) + ramstage-y += cs5535.c #ramstage-y += pci.c #ramstage-y += ide.c ramstage-y += chipsetinit.c + +endif diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc index f36dcc5..2da076e 100644 --- a/src/southbridge/amd/cs5536/Makefile.inc +++ b/src/southbridge/amd/cs5536/Makefile.inc @@ -17,8 +17,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y) + ramstage-y += cs5536.c ramstage-y += ide.c ramstage-y += pirq.c ramstage-y += smbus.c -romstage-y += smbus.c \ No newline at end of file +romstage-y += smbus.c + +endif diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index 70e2c18..5e71b4b 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "hudson.h" -#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <bootstate.h> static void pci_init(struct device *dev) diff --git a/src/southbridge/amd/rs690/Makefile.inc b/src/southbridge/amd/rs690/Makefile.inc index e0cf927..c80ed9b 100644 --- a/src/southbridge/amd/rs690/Makefile.inc +++ b/src/southbridge/amd/rs690/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y) + ramstage-y += rs690.c ramstage-y += cmn.c ramstage-y += pcie.c ramstage-y += ht.c ramstage-y += gfx.c + +endif diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc index bf51d83..1a8a17a 100644 --- a/src/southbridge/amd/rs780/Makefile.inc +++ b/src/southbridge/amd/rs780/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS790),y) + ramstage-y += rs780.c ramstage-y += cmn.c ramstage-y += pcie.c ramstage-y += ht.c ramstage-y += gfx.c + +endif diff --git a/src/southbridge/amd/sb600/Makefile.inc b/src/southbridge/amd/sb600/Makefile.inc index 37fe57d..cd5bb61 100644 --- a/src/southbridge/amd/sb600/Makefile.inc +++ b/src/southbridge/amd/sb600/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y) + ramstage-y += sb600.c ramstage-y += usb.c ramstage-y += lpc.c @@ -10,3 +12,5 @@ ramstage-y += pci.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c + +endif diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 6e772fe..5ec8431 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB700),y) + ramstage-y += sb700.c ramstage-y += usb.c ramstage-y += lpc.c @@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c romstage-y += smbus.c + +endif diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc index d665af4..fca4a98 100644 --- a/src/southbridge/amd/sb800/Makefile.inc +++ b/src/southbridge/amd/sb800/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB800),y) + ramstage-y += sb800.c ramstage-y += usb.c ramstage-y += lpc.c @@ -11,3 +13,5 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c + +endif diff --git a/src/southbridge/amd/sr5650/Makefile.inc b/src/southbridge/amd/sr5650/Makefile.inc index 3c17be0..f695a11 100644 --- a/src/southbridge/amd/sr5650/Makefile.inc +++ b/src/southbridge/amd/sr5650/Makefile.inc @@ -1,5 +1,9 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SR5650),y) + ramstage-y += sr5650.c ramstage-y += pcie.c ramstage-y += ht.c romstage-y += early_setup.c + +endif diff --git a/src/southbridge/broadcom/Makefile.inc b/src/southbridge/broadcom/Makefile.inc deleted file mode 100644 index c9de93d..0000000 --- a/src/southbridge/broadcom/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM21000) += bcm21000 -subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5780) += bcm5780 -subdirs-$(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785) += bcm5785 diff --git a/src/southbridge/broadcom/bcm21000/Makefile.inc b/src/southbridge/broadcom/bcm21000/Makefile.inc index f85aeb1..d298c8e 100644 --- a/src/southbridge/broadcom/bcm21000/Makefile.inc +++ b/src/southbridge/broadcom/bcm21000/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM21000),y) + ramstage-y += pcie.c + +endif diff --git a/src/southbridge/broadcom/bcm5780/Makefile.inc b/src/southbridge/broadcom/bcm5780/Makefile.inc index 4eb834a..d4f83ed 100644 --- a/src/southbridge/broadcom/bcm5780/Makefile.inc +++ b/src/southbridge/broadcom/bcm5780/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5870),y) + ramstage-y += nic.c ramstage-y += pcix.c ramstage-y += pcie.c + +endif diff --git a/src/southbridge/broadcom/bcm5785/Makefile.inc b/src/southbridge/broadcom/bcm5785/Makefile.inc index b8427c4..70fba1f 100644 --- a/src/southbridge/broadcom/bcm5785/Makefile.inc +++ b/src/southbridge/broadcom/bcm5785/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_BROADCOM_BCM5785),y) + ramstage-y += bcm5785.c ramstage-y += usb.c ramstage-y += lpc.c @@ -5,3 +7,5 @@ ramstage-y += sb_pci_main.c ramstage-y += ide.c ramstage-y += sata.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/dmp/Makefile.inc b/src/southbridge/dmp/Makefile.inc deleted file mode 100644 index a94e935..0000000 --- a/src/southbridge/dmp/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 DMP Electronics Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOUTHBRIDGE_DMP_VORTEX86EX) += vortex86ex diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc index 5471faa..968930b 100644 --- a/src/southbridge/dmp/vortex86ex/Makefile.inc +++ b/src/southbridge/dmp/vortex86ex/Makefile.inc @@ -17,7 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_DMP_VORTEX86EX),y) + ramstage-y += southbridge.c ramstage-y += hard_reset.c ramstage-y += ide_sd_sata.c ramstage-y += audio.c + +endif diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc deleted file mode 100644 index dd20d46..0000000 --- a/src/southbridge/intel/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON) += common -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_ESB6300) += esb6300 -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I3100) += i3100 -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801AX) += i82801ax -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801BX) += i82801bx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) += i82801ix -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870 -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += bd82x6x -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += bd82x6x -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) += ibexpeak -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) += lynxpoint -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) += fsp_bd82x6x -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_rangeley diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 83de051..234c009 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -107,3 +109,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) endif PHONY += bd82x6x_add_me + +endif diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 4374ebc..5c613eb 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -17,5 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) + romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c + +endif diff --git a/src/southbridge/intel/esb6300/Makefile.inc b/src/southbridge/intel/esb6300/Makefile.inc index bb70fdc..fba8c23 100644 --- a/src/southbridge/intel/esb6300/Makefile.inc +++ b/src/southbridge/intel/esb6300/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_ESB6300),y) + ramstage-y += esb6300.c ramstage-y += reset.c ramstage-y += uhci.c @@ -10,3 +12,5 @@ ramstage-y += pci.c ramstage-y += pic.c ramstage-y += bridge1c.c ramstage-y += ac97.c + +endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc index 208611b..1bfed23 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -71,3 +73,5 @@ endif PHONY += bd82x6x_add_me CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x + +endif diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index 48ac522..1d33052 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -48,3 +50,5 @@ rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL) endif PHONY += rangeley_add_descriptor + +endif diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc index dc3d039..bcc6d06 100644 --- a/src/southbridge/intel/i3100/Makefile.inc +++ b/src/southbridge/intel/i3100/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I3100),y) + ramstage-y += i3100.c ramstage-y += uhci.c ramstage-y += lpc.c @@ -8,3 +10,5 @@ ramstage-y += pci.c ramstage-y += ioapic.c ramstage-y += reset.c ramstage-y += pciexp_portb.c + +endif diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 0aae455..0ab2531 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) + ramstage-y += i82371eb.c ramstage-y += isa.c ramstage-y += ide.c @@ -30,3 +32,5 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c romstage-y += early_pm.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801ax/Makefile.inc b/src/southbridge/intel/i82801ax/Makefile.inc index aeb1e54..48eadf3 100644 --- a/src/southbridge/intel/i82801ax/Makefile.inc +++ b/src/southbridge/intel/i82801ax/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801AX),y) + ramstage-y += i82801ax.c ramstage-y += ac97.c ramstage-y += ide.c @@ -30,3 +32,5 @@ ramstage-y += reset.c ramstage-y += watchdog.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801bx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc index f070f05..44a2ac8 100644 --- a/src/southbridge/intel/i82801bx/Makefile.inc +++ b/src/southbridge/intel/i82801bx/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801BX),y) + ramstage-y += i82801bx.c ramstage-y += ac97.c ramstage-y += ide.c @@ -31,3 +33,5 @@ ramstage-y += reset.c ramstage-y += watchdog.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801cx/Makefile.inc b/src/southbridge/intel/i82801cx/Makefile.inc index c375476..ab95982 100644 --- a/src/southbridge/intel/i82801cx/Makefile.inc +++ b/src/southbridge/intel/i82801cx/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801CX),y) + ramstage-y += i82801cx.c ramstage-y += usb.c ramstage-y += lpc.c @@ -6,3 +8,5 @@ ramstage-y += ac97.c #ramstage-y += nic.c ramstage-y += pci.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index e412ef9..d10383c 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -19,6 +19,8 @@ ## MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y) + ramstage-y += i82801dx.c ramstage-y += ac97.c ramstage-y += ide.c @@ -33,3 +35,5 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c + +endif diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc index fb76a98..240eaf0 100644 --- a/src/southbridge/intel/i82801ex/Makefile.inc +++ b/src/southbridge/intel/i82801ex/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801EX),y) + ramstage-y += i82801ex.c ramstage-y += uhci.c ramstage-y += lpc.c @@ -9,3 +11,5 @@ ramstage-y += pci.c ramstage-y += ac97.c ramstage-y += watchdog.c ramstage-y += reset.c + +endif diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 6e4d42e..fa1721f 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) + ramstage-y += i82801gx.c ramstage-y += ac97.c ramstage-y += azalia.c @@ -39,3 +41,5 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c early_lpc.c + +endif diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index a6580c4..19f5bb4 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y) + ramstage-y += i82801ix.c ramstage-y += pci.c ramstage-y += lpc.c @@ -40,3 +42,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_init.c romstage-y += early_smbus.c romstage-y += dmi_setup.c + +endif diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc index 190aa4f..790bd01 100644 --- a/src/southbridge/intel/i82870/Makefile.inc +++ b/src/southbridge/intel/i82870/Makefile.inc @@ -1,3 +1,7 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y) + ramstage-y += ioapic.c ramstage-y += pcibridge.c #ramstage-y += pci_parity.c + +endif diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 393655d..f09db1a 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -100,3 +102,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) endif PHONY += bd82x6x_add_me + +endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 3b7663e..df68db2 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) + # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS @@ -104,3 +106,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) endif PHONY += lynxpoint_add_me + +endif diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc index 0bdd475..bfdbe04 100644 --- a/src/southbridge/intel/sch/Makefile.inc +++ b/src/southbridge/intel/sch/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_SCH),y) + ramstage-y += south.c ramstage-y += audio.c ramstage-y += lpc.c @@ -39,3 +41,5 @@ cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin cmc.bin-file := $(call strip_quotes,$(CONFIG_CMC_FILE)) cmc.bin-type := raw cmc.bin-position := 0xfffd0000 + +endif diff --git a/src/southbridge/nvidia/Makefile.inc b/src/southbridge/nvidia/Makefile.inc deleted file mode 100644 index 13bf3e4..0000000 --- a/src/southbridge/nvidia/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) += ck804 -subdirs-$(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) += mcp55 diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index c88da39..de1162a 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_CK804),y) + ramstage-y += ck804.c ramstage-y += usb.c ramstage-y += lpc.c @@ -21,3 +23,5 @@ romstage-y += early_smbus.c chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index e2f8553..3e24f1c 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y) + ramstage-y += mcp55.c ramstage-y += azalia.c ramstage-y += ht.c @@ -20,3 +22,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/rdc/Makefile.inc b/src/southbridge/rdc/Makefile.inc deleted file mode 100644 index 34f3efd..0000000 --- a/src/southbridge/rdc/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_RDC_R8610) += r8610 diff --git a/src/southbridge/rdc/r8610/Makefile.inc b/src/southbridge/rdc/r8610/Makefile.inc index 3484c95..c6866bc 100644 --- a/src/southbridge/rdc/r8610/Makefile.inc +++ b/src/southbridge/rdc/r8610/Makefile.inc @@ -17,4 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_RDC_R8610),y) + ramstage-y += r8610.c + +endif diff --git a/src/southbridge/ricoh/Makefile.inc b/src/southbridge/ricoh/Makefile.inc deleted file mode 100644 index 3969392..0000000 --- a/src/southbridge/ricoh/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_RICOH_RL5C476) += rl5c476 diff --git a/src/southbridge/ricoh/rl5c476/Makefile.inc b/src/southbridge/ricoh/rl5c476/Makefile.inc index 3156706..3fa232f 100644 --- a/src/southbridge/ricoh/rl5c476/Makefile.inc +++ b/src/southbridge/ricoh/rl5c476/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_RICOH_RL5C476),y) + ramstage-y += rl5c476.c + +endif diff --git a/src/southbridge/sis/Makefile.inc b/src/southbridge/sis/Makefile.inc deleted file mode 100644 index 45332ca..0000000 --- a/src/southbridge/sis/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_SIS_SIS966) += sis966 diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index 5cf5954..71fff02 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_SIS_SIS966),y) + ramstage-y += sis761.c ramstage-y += sis966.c ramstage-y += lpc.c @@ -15,3 +17,5 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/ti/Makefile.inc b/src/southbridge/ti/Makefile.inc deleted file mode 100644 index 2bd00e7..0000000 --- a/src/southbridge/ti/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI7420) += pci7420 -subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCIXX12) += pcixx12 -subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x diff --git a/src/southbridge/ti/pci1x2x/Makefile.inc b/src/southbridge/ti/pci1x2x/Makefile.inc index 7c0e4aa..4f2a3d3 100644 --- a/src/southbridge/ti/pci1x2x/Makefile.inc +++ b/src/southbridge/ti/pci1x2x/Makefile.inc @@ -1 +1,5 @@ -ramstage-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x.c +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI1X2X),y) + +ramstage-y += pci1x2x.c + +endif diff --git a/src/southbridge/ti/pci7420/Makefile.inc b/src/southbridge/ti/pci7420/Makefile.inc index d919258..66cfa90 100644 --- a/src/southbridge/ti/pci7420/Makefile.inc +++ b/src/southbridge/ti/pci7420/Makefile.inc @@ -17,5 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI7420),y) + ramstage-y += cardbus.c ramstage-y += firewire.c + +endif diff --git a/src/southbridge/ti/pcixx12/Makefile.inc b/src/southbridge/ti/pcixx12/Makefile.inc index bdd2cf3..6ab571b 100644 --- a/src/southbridge/ti/pcixx12/Makefile.inc +++ b/src/southbridge/ti/pcixx12/Makefile.inc @@ -17,4 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCIXX12),y) + ramstage-y += pcixx12.c + +endif diff --git a/src/southbridge/via/Makefile.inc b/src/southbridge/via/Makefile.inc deleted file mode 100644 index db19438..0000000 --- a/src/southbridge/via/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890 -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8237R) += vt8237r diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 634ccd1..18cb5aa 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -1,3 +1,5 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y) + ramstage-y += ctrl.c ramstage-y += dram.c ramstage-y += bridge.c @@ -10,3 +12,5 @@ ramstage-y += chrome.c chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc bootblock-y += romstrap.ld + +endif diff --git a/src/southbridge/via/vt8237r/Makefile.inc b/src/southbridge/via/vt8237r/Makefile.inc index de69ffd..2630602 100644 --- a/src/southbridge/via/vt8237r/Makefile.inc +++ b/src/southbridge/via/vt8237r/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(CONFIG_SOUTHBRIDGE_VIA_VT8237R),y) + ramstage-y += vt8237r.c ramstage-y += ctrl.c ramstage-y += ide.c @@ -27,3 +29,5 @@ ramstage-$(CONFIG_PIRQ_ROUTE) += pirq.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +endif

1 0

New patch to review for coreboot: 0c79513 RTC cleanup
by Stefan Reinauer 27 Apr '15

27 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10013 -gerrit commit 0c79513c4057151de2ff725c1cf83f1d764bf049 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 27 13:40:54 2015 -0700 RTC cleanup Change-Id: I6d11167a4f309811a4d1efdaa04b16850d907bd8 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/pc80/rtc/Makefile.inc | 3 +++ src/include/pc80/mc146818rtc.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index 4dee348..d3b3344 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -2,7 +2,10 @@ ifeq ($(CONFIG_ARCH_X86),y) romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_early.c romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c + +ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_early.c ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c + cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool cmos.default-type = 0xaa diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index c74af66..22f0d5f 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -177,7 +177,7 @@ enum cb_err get_option(void *dest, const char *name); unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); #else /* defined(__ROMCC__) */ -#include <drivers/pc80/mc146818rtc_early.c> +#include <drivers/pc80/rtc/mc146818rtc_early.c> #endif /* !defined(__ROMCC__) */ #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))

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New patch to review for coreboot: d629374 Kconfig cleanups
by Stefan Reinauer 27 Apr '15

27 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10012 -gerrit commit d629374564d0e0a50cfc2aabfa51e9dee1b58678 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 27 13:40:16 2015 -0700 Kconfig cleanups Change-Id: I25ea327ed151e18ccb5d13626d44925d2a253d08 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/Kconfig | 1 + src/cpu/x86/Kconfig | 23 ++++++++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index a6032c7..e77db23 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -305,6 +305,7 @@ source "src/device/Kconfig" menu "Generic Drivers" source "src/drivers/*/Kconfig" +source "src/drivers/*/*/Kconfig" endmenu config TPM diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 41c2288..689170b 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,7 +1,16 @@ +# TODO These two options look too similar config PARALLEL_CPU_INIT bool default n +config PARALLEL_MP + def_bool n + help + This option uses common MP infrastructure for bringing up APs + in parallel. It additionally provides a more flexible mechanism + for sequencing the steps of bringing up the APs. + + config UDELAY_IO bool default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2 @@ -39,11 +48,14 @@ config TSC_MONOTONIC_TIMER help Expose monotonic time using the TSC. -config UDELAY_TIMER2 +# This option is used in code but never selected. +config TSC_CALIBRATE_WITH_IO bool + depends on UDELAY_TSC default n -config TSC_CALIBRATE_WITH_IO +# This option is used in code but never selected. +config UDELAY_TIMER2 bool default n @@ -112,13 +124,6 @@ config PLATFORM_USES_FSP Selected for Intel processors/platform combinations that use the Intel Firmware Support Package (FSP) for initialization. -config PARALLEL_MP - def_bool n - help - This option uses common MP infrastructure for bringing up APs - in parallel. It additionally provides a more flexible mechanism - for sequencing the steps of bringing up the APs. - config BACKUP_DEFAULT_SMM_REGION def_bool n help

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New patch to review for coreboot: fa87965 some timer cleanups
by Stefan Reinauer 27 Apr '15

27 Apr '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10011 -gerrit commit fa879653d10670da1323f982032564a9904c3c3e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 27 13:38:50 2015 -0700 some timer cleanups Change-Id: Ic6915743b7c948a57478744777fdbc31163c48f6 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/via/c7/Kconfig | 4 +++- src/drivers/pc80/pc/Makefile.inc | 1 + src/mainboard/abit/be6-ii_v2_0/Kconfig | 2 +- src/mainboard/abit/be6-ii_v2_0/romstage.c | 1 - src/mainboard/asus/mew-am/romstage.c | 1 - src/mainboard/asus/mew-vm/romstage.c | 1 - src/mainboard/asus/p2b-f/romstage.c | 1 - src/mainboard/emulation/qemu-i440fx/romstage.c | 1 - src/mainboard/jetway/j7f2/romstage.c | 1 - src/mainboard/via/vt8454c/romstage.c | 1 - 10 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig index 3507713..b71178d 100644 --- a/src/cpu/via/c7/Kconfig +++ b/src/cpu/via/c7/Kconfig @@ -9,7 +9,9 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select UDELAY_TSC + # Missing tsc_freq_mhz and TSC_CONSTANT_RATE + #select UDELAY_TSC + select UDELAY_IO select MMX select SSE2 diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 550ca12..b7eda19 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_ARCH_X86),y) ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c +romstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c diff --git a/src/mainboard/abit/be6-ii_v2_0/Kconfig b/src/mainboard/abit/be6-ii_v2_0/Kconfig index 5dc1ca0..3800e28 100644 --- a/src/mainboard/abit/be6-ii_v2_0/Kconfig +++ b/src/mainboard/abit/be6-ii_v2_0/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC + select UDELAY_IO select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 73fef6e..eac5448 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 213d480..0712eec 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index f6032ef..44d3c58 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -28,7 +28,6 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index a93b743..62e121a 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index b9f0dea..35b9ac9 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <timestamp.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 8a17113..24bdc6e 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -27,7 +27,6 @@ #include <console/console.h> #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/fintek/common/fintek.h> diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 5a74255..4b7bf08 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -28,7 +28,6 @@ #include <lib.h> #include <northbridge/via/cx700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include "northbridge/via/cx700/early_smbus.c" #include "lib/debug.c"

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coreboot-gerrit April 2015