coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 0fd3e79 libpayload arm64: update mmu translation table granule size, logic and macros
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit 0fd3e79d0d9d3e5607a57a899333ddb1ef6a927e Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Mon Apr 13 20:28:38 2015 +0800 libpayload arm64: update mmu translation table granule size, logic and macros 1. change mmu granule size from 64KB to 4KB 2. correct level 1 translation table creation logic 3. automatically calculate granule size related macros BRANCH=none BUG=none TEST=boot to kernel on oak board Change-Id: Ic62c7863dff53f566b82b68ff1d1ad9ec5d0698d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e5de7d942e42a8202fb879ce64b871864b1b9d38 Original-Change-Id: I78d7838921fa82a670e18ddc2de6d766dc7a2146 Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/266010 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Reviewed-on: http://review.coreboot.org/10010 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10010 for details. -gerrit

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Patch merged into coreboot/master: dea4597 arch/arm64: update mmu translation table granule size, logic and macros
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit dea4597bd4e35d8421b1cf8816a3c9dc045b9b36 Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Mon Apr 13 20:28:38 2015 +0800 arch/arm64: update mmu translation table granule size, logic and macros 1. change mmu granule size from 64KB to 4KB 2. correct level 1 translation table creation logic 3. automatically calculate granule size related macros BRANCH=none BUG=none TEST=boot to kernel on oak board Change-Id: I9e99a3017033f6870b1735ac8faabb267c7be0a4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2f18c4d5d9902f2830db82720c5543af270a7e3c Original-Change-Id: Ia27a414ab7578d70b00c36f9c063983397ba7927 Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265603 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Reviewed-on: http://review.coreboot.org/10009 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10009 for details. -gerrit

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Patch merged into coreboot/master: 16fb9b9 chromeec: ec_mec: Fix misaligned data access
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit 16fb9b9f81d0535a2125779e955ada77b40340e1 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Apr 21 09:30:10 2015 -0700 chromeec: ec_mec: Fix misaligned data access Long auto-increment access cannot be used when our initial address is misaligned or when our terminal address is misaligned on write operations. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on cyan. BRANCH=None Change-Id: Ieba0e8e05dabd44a28c63d5d56a2a634c2d349bf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a7237c8df027ae70a38478846ff3d5ce97543ff1 Original-Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Change-Id: Id709ca92cc386f9ea5b2a1139733961e1bc59354 Original-Reviewed-on: https://chromium-review.googlesource.com/266653 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/9987 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9987 for details. -gerrit

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Patch merged into coreboot/master: 8603680 storm: enable CBMEM console dump
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit 8603680c4a5ca3a718e2c21331be6d12fe9de147 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Apr 10 19:23:16 2015 -0700 storm: enable CBMEM console dump This patch enables on storm the recently introduced 'console buffer dump on reboot' capability. BRANCH=none BUG=chromium:475347 TEST=generated storm image with serial console disabled and both rw firmware A and B sections corrupted. Programmed the new image on an SP5 device and rebooted it. Observed the device dump cbmem console buffer to the serial output, terminating with VB2:vb2_fail() Need recovery, reason: 0x3 / 0xa Reboot requested (1008000a) Saving nvdata SF: Detected S25FL128S_256K with page size 10000, total 2000000 and the LED ring started flashing indicating recovery mode. Change-Id: Idb50c86f59f393c783ccbc15de8f5564e2a1b38e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0ec88001b152bb9f1d7268b83367131b004816f8 Original-Change-Id: I9345eeb4d375f42fb1e4c617495b63b308ce51d9 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265295 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9986 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9986 for details. -gerrit

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Patch merged into coreboot/master: 189bec5 Cygnus: add TrustZone functions and set everything non-secure in bootblock
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit 189bec59f01fc959dde7a9f29142adcad2a43cbe Author: Corneliu Doban <cdoban(a)broadcom.com> Date: Fri Apr 10 15:51:55 2015 -0700 Cygnus: add TrustZone functions and set everything non-secure in bootblock To allow an OS to run in non-secure mode: - Set all peripherals and system components non-secure except SOTP and TZPC. - Set all memory non-secure (ROM, SRAM, DDR, flash). - Enable A9 access to entire M0 address space except M0 ROM. BUG=chrome-os-partner:37533 BRANCH=broadcom-firmware TEST=boot kernel from usb stick Change-Id: I3bbd288863923011ff1413be353ac4b178ffdd07 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6de56bbe73ed8d87ad572da711a193985ee68e3a Original-Signed-off-by: Corneliu Doban <cdoban(a)broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212735 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)google.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)google.com> Original-Tested-by: Daisuke Nojiri <dnojiri(a)google.com> Original-Change-Id: Ibac7de03a72a98fbd95659d0113833049b4871a5 Original-Reviewed-on: https://chromium-review.googlesource.com/266593 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri(a)chromium.org> Reviewed-on: http://review.coreboot.org/9985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9985 for details. -gerrit

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Patch merged into coreboot/master: 6e20e2f cbmem: add and use a function to dump console buffer
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit 6e20e2f16872a276c9af18b7ca11b1ea62bfb820 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Apr 10 18:04:04 2015 -0700 cbmem: add and use a function to dump console buffer The new function can be compiled in only when serial console is disabled. When invoked, this function initializes the serial interface and dumps the contents of the CBMEM console buffer to serial output. BRANCH=none BUG=chromium:475347 TEST=compiled for different platforms with and without serial console enabled. No actual test of this function yet. Change-Id: Ia8d16649dc9d09798fa6970f2cfd893438e00dc5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a38a8254dd788ad188ba2509b9ae117d6f699579 Original-Change-Id: Ib85759a2727e31ba1ca21da7e6c346e434f83b52 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265293 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9984 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9984 for details. -gerrit

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Patch merged into coreboot/master: 5bdbd00 lib/tlcl: Provide mock implementation
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit 5bdbd004e689157588c01b9689611b826d2382c9 Author: Yen Lin <yelin(a)nvidia.com> Date: Wed Apr 8 16:55:17 2015 -0700 lib/tlcl: Provide mock implementation It returns TPM_E_NO_DEVICE for all calls. BRANCH=None BUG=None TEST=manual MOCK_TPM=1 emerge-foster coreboot, and coreboot can boot to kernel Change-Id: Id7e79b58fabeac929b874385064b2417db49a708 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a9a91a65af115657e7317754eda931120750c56d Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Change-Id: I8dcf0db14cf2bc76c67a3bd7f06114e70e08764d Original-Reviewed-on: https://chromium-review.googlesource.com/264946 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9983 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9983 for details. -gerrit

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New patch to review for coreboot: dff3fef libpayload arm64: update mmu translation table granule size, logic and macros
by Patrick Georgi 27 Apr '15

27 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10010 -gerrit commit dff3fef992f49393a9730922250290dd730f7d94 Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Mon Apr 13 20:28:38 2015 +0800 libpayload arm64: update mmu translation table granule size, logic and macros 1. change mmu granule size from 64KB to 4KB 2. correct level 1 translation table creation logic 3. automatically calculate granule size related macros BRANCH=none BUG=none TEST=boot to kernel on oak board Change-Id: Ic62c7863dff53f566b82b68ff1d1ad9ec5d0698d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e5de7d942e42a8202fb879ce64b871864b1b9d38 Original-Change-Id: I78d7838921fa82a670e18ddc2de6d766dc7a2146 Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/266010 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> --- payloads/libpayload/arch/arm64/mmu.c | 29 ++++++++++---- payloads/libpayload/include/arm64/arch/mmu.h | 59 +++++++++------------------- payloads/libpayload/include/stdlib.h | 1 + 3 files changed, 40 insertions(+), 49 deletions(-) diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index 204412e..f0781f5 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -200,12 +200,24 @@ static uint64_t init_xlat_table(uint64_t base_addr, /* * L1 table lookup - * If VA has bits more than 41, lookup starts at L1 + * If VA has bits more than L2 can resolve, lookup starts at L1 + * Assumption: we don't need L0 table in coreboot */ - if (l1_index) { - table = get_next_level_table(&table[l1_index]); - if (!table) - return 0; + if (BITS_PER_VA > L1_ADDR_SHIFT) { + if ((size >= L1_XLAT_SIZE) && + IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) { + /* If block address is aligned and size is greater than + * or equal to size addressed by each L1 entry, we can + * directly store a block desc */ + desc = base_addr | BLOCK_DESC | attr; + table[l1_index] = desc; + /* L2 lookup is not required */ + return L1_XLAT_SIZE; + } else { + table = get_next_level_table(&table[l1_index]); + if (!table) + return 0; + } } /* @@ -213,10 +225,11 @@ static uint64_t init_xlat_table(uint64_t base_addr, * If lookup was performed at L1, L2 table addr is obtained from L1 desc * else, lookup starts at ttbr address */ - if (!l3_index && (size >= L2_XLAT_SIZE)) { + if ((size >= L2_XLAT_SIZE) && + IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) { /* * If block address is aligned and size is greater than or equal - * to 512MiB i.e. size addressed by each L2 entry, we can + * to size addressed by each L2 entry, we can * directly store a block desc */ desc = base_addr | BLOCK_DESC | attr; @@ -369,7 +382,7 @@ void mmu_enable(void) /* Initialize TCR flags */ raw_write_tcr_current(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC | - TCR_SH0_IS | TCR_TG0_64KB | TCR_PS_64GB | + TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_64GB | TCR_TBI_USED); /* Initialize TTBR */ diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h index e241d75..79bc783 100644 --- a/payloads/libpayload/include/arm64/arch/mmu.h +++ b/payloads/libpayload/include/arm64/arch/mmu.h @@ -49,14 +49,6 @@ struct mmu_ranges { */ extern char _start[], _end[]; -/* IMPORTANT!!!!!!! - * Assumptions made: - * Granule size is 64KiB - * BITS per Virtual address is 33 - * All the calculations for tables L1,L2 and L3 are based on these assumptions - * If these values are changed, recalculate the other macros as well - */ - /* Memory attributes for mmap regions * These attributes act as tag values for memrange regions */ @@ -89,47 +81,32 @@ extern char _start[], _end[]; /* XLAT Table Init Attributes */ #define VA_START 0x0 -/* If BITS_PER_VA or GRANULE_SIZE are changed, recalculate and change the - macros following them */ #define BITS_PER_VA 33 -/* Granule size of 64KB is being used */ #define MIN_64_BIT_ADDR (1UL << 32) -#define XLAT_TABLE_MASK ~(0xffffUL) -#define GRANULE_SIZE_SHIFT 16 +/* Granule size of 4KB is being used */ +#define GRANULE_SIZE_SHIFT 12 #define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT) -#define GRANULE_SIZE_MASK ((1 << 16) - 1) - -#define L1_ADDR_SHIFT 42 -#define L2_ADDR_SHIFT 29 -#define L3_ADDR_SHIFT 16 - -#define L1_ADDR_MASK (0UL << L1_ADDR_SHIFT) -#define L2_ADDR_MASK (0xfUL << L2_ADDR_SHIFT) -#define L3_ADDR_MASK (0x1fffUL << L3_ADDR_SHIFT) - -/* Dependent on BITS_PER_VA and GRANULE_SIZE */ -#define INIT_LEVEL 2 -#define XLAT_MAX_LEVEL 3 - -/* Each entry in XLAT table is 8 bytes */ -#define XLAT_ENTRY_SHIFT 3 -#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SHIFT) +#define XLAT_TABLE_MASK (~(0UL) << GRANULE_SIZE_SHIFT) +#define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1) -#define XLAT_TABLE_SHIFT GRANULE_SIZE_SHIFT -#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SHIFT) +#define BITS_RESOLVED_PER_LVL (GRANULE_SIZE_SHIFT - 3) +#define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 2) +#define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 1) +#define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 0) -#define XLAT_NUM_ENTRIES_SHIFT (XLAT_TABLE_SHIFT - XLAT_ENTRY_SHIFT) -#define XLAT_NUM_ENTRIES (1 << XLAT_NUM_ENTRIES_SHIFT) +#if BITS_PER_VA > L1_ADDR_SHIFT + BITS_RESOLVED_PER_LVL + #error "BITS_PER_VA too large (we don't have L0 table support)" +#endif -#define L3_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT) -#define L2_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT + XLAT_NUM_ENTRIES_SHIFT) -#define L1_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT + XLAT_NUM_ENTRIES_SHIFT) +#define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT) +#define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT) +#define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT) /* These macros give the size of the region addressed by each entry of a xlat table at any given level */ -#define L3_XLAT_SIZE (1 << L3_XLAT_SIZE_SHIFT) -#define L2_XLAT_SIZE (1 << L2_XLAT_SIZE_SHIFT) -#define L1_XLAT_SIZE (1 << L1_XLAT_SIZE_SHIFT) +#define L3_XLAT_SIZE (1UL << L3_ADDR_SHIFT) +#define L2_XLAT_SIZE (1UL << L2_ADDR_SHIFT) +#define L1_XLAT_SIZE (1UL << L1_ADDR_SHIFT) /* Block indices required for MAIR */ #define BLOCK_INDEX_MEM_DEV_NGNRNE 0 @@ -184,7 +161,7 @@ extern char _start[], _end[]; #define TCR_TBI_USED (0x0 << TCR_TBI_SHIFT) #define TCR_TBI_IGNORED (0x1 << TCR_TBI_SHIFT) -#define DMA_DEFAULT_SIZE (0x200 * GRANULE_SIZE) +#define DMA_DEFAULT_SIZE (32 * MiB) #define TTB_DEFAULT_SIZE 0x100000 #define MB_SIZE (1UL << 20) diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index deb5e3d..08c7d06 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -39,6 +39,7 @@ #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) #define ALIGN_UP(x,a) ALIGN((x),(a)) #define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL)) +#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0) /** * @defgroup malloc Memory allocation functions

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New patch to review for coreboot: 2f452b4 arch/arm64: update mmu translation table granule size, logic and macros
by Patrick Georgi 27 Apr '15

27 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10009 -gerrit commit 2f452b4492df58f7e7f1ca556fed9b1a6c0b88c4 Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Mon Apr 13 20:28:38 2015 +0800 arch/arm64: update mmu translation table granule size, logic and macros 1. change mmu granule size from 64KB to 4KB 2. correct level 1 translation table creation logic 3. automatically calculate granule size related macros BRANCH=none BUG=none TEST=boot to kernel on oak board Change-Id: I9e99a3017033f6870b1735ac8faabb267c7be0a4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2f18c4d5d9902f2830db82720c5543af270a7e3c Original-Change-Id: Ia27a414ab7578d70b00c36f9c063983397ba7927 Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265603 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> --- src/arch/arm64/armv8/mmu.c | 33 +++++++++++++------ src/arch/arm64/include/armv8/arch/mmu.h | 58 ++++++++++----------------------- 2 files changed, 40 insertions(+), 51 deletions(-) diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 84b9935..99c97fb 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -164,20 +164,33 @@ static uint64_t init_xlat_table(uint64_t base_addr, uint64_t attr = get_block_attr(tag); /* L1 table lookup */ - /* If VA has bits more than 41, lookup starts at L1 */ - if (l1_index) { - table = get_next_level_table(&table[l1_index]); - if (!table) - return 0; + /* If VA has bits more than L2 can resolve, lookup starts at L1 + Assumption: we don't need L0 table in coreboot */ + if (BITS_PER_VA > L1_ADDR_SHIFT) { + if ((size >= L1_XLAT_SIZE) && + IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) { + /* If block address is aligned and size is greater than + * or equal to size addressed by each L1 entry, we can + * directly store a block desc */ + desc = base_addr | BLOCK_DESC | attr; + table[l1_index] = desc; + /* L2 lookup is not required */ + return L1_XLAT_SIZE; + } else { + table = get_next_level_table(&table[l1_index]); + if (!table) + return 0; + } } /* L2 table lookup */ /* If lookup was performed at L1, L2 table addr is obtained from L1 desc else, lookup starts at ttbr address */ - if (!l3_index && (size >= L2_XLAT_SIZE)) { - /* If block address is aligned and size is greater than or equal - to 512MiB i.e. size addressed by each L2 entry, we can - directly store a block desc */ + if ((size >= L2_XLAT_SIZE) && + IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) { + /* If block address is aligned and size is greater than + * or equal to size addressed by each L2 entry, we can + * directly store a block desc */ desc = base_addr | BLOCK_DESC | attr; table[l2_index] = desc; /* L3 lookup is not required */ @@ -279,7 +292,7 @@ void mmu_enable(void) /* Initialize TCR flags */ raw_write_tcr_el3(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC | - TCR_SH0_IS | TCR_TG0_64KB | TCR_PS_64GB | + TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_64GB | TCR_TBI_USED); /* Initialize TTBR */ diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h index 564d6af..59d2158 100644 --- a/src/arch/arm64/include/armv8/arch/mmu.h +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -22,15 +22,6 @@ #include <memrange.h> -/* IMPORTANT!!!!!!! - * Assumptions made: - * Granule size is 64KiB - * BITS per Virtual address is 33 - * All the calculations for tables L1,L2 and L3 are based on these assumptions - * If these values are changed, recalculate the other macros as well - */ - - /* Memory attributes for mmap regions * These attributes act as tag values for memrange regions */ @@ -74,46 +65,31 @@ /* XLAT Table Init Attributes */ #define VA_START 0x0 -/* If BITS_PER_VA or GRANULE_SIZE are changed, recalculate and change the - macros following them */ #define BITS_PER_VA 33 -/* Granule size of 64KB is being used */ -#define GRANULE_SIZE_SHIFT 16 +/* Granule size of 4KB is being used */ +#define GRANULE_SIZE_SHIFT 12 #define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT) -#define XLAT_TABLE_MASK ~(0xffffUL) -#define GRANULE_SIZE_MASK ((1 << 16) - 1) - -#define L1_ADDR_SHIFT 42 -#define L2_ADDR_SHIFT 29 -#define L3_ADDR_SHIFT 16 - -#define L1_ADDR_MASK (0UL << L1_ADDR_SHIFT) -#define L2_ADDR_MASK (0xfUL << L2_ADDR_SHIFT) -#define L3_ADDR_MASK (0x1fffUL << L3_ADDR_SHIFT) - -/* Dependent on BITS_PER_VA and GRANULE_SIZE */ -#define INIT_LEVEL 2 -#define XLAT_MAX_LEVEL 3 - -/* Each entry in XLAT table is 8 bytes */ -#define XLAT_ENTRY_SHIFT 3 -#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SHIFT) +#define XLAT_TABLE_MASK (~(0UL) << GRANULE_SIZE_SHIFT) +#define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1) -#define XLAT_TABLE_SHIFT GRANULE_SIZE_SHIFT -#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SHIFT) +#define BITS_RESOLVED_PER_LVL (GRANULE_SIZE_SHIFT - 3) +#define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 2) +#define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 1) +#define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 0) -#define XLAT_NUM_ENTRIES_SHIFT (XLAT_TABLE_SHIFT - XLAT_ENTRY_SHIFT) -#define XLAT_NUM_ENTRIES (1 << XLAT_NUM_ENTRIES_SHIFT) +#if BITS_PER_VA > L1_ADDR_SHIFT + BITS_RESOLVED_PER_LVL + #error "BITS_PER_VA too large (we don't have L0 table support)" +#endif -#define L3_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT) -#define L2_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT + XLAT_NUM_ENTRIES_SHIFT) -#define L1_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT + XLAT_NUM_ENTRIES_SHIFT) +#define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT) +#define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT) +#define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT) /* These macros give the size of the region addressed by each entry of a xlat table at any given level */ -#define L3_XLAT_SIZE (1 << L3_XLAT_SIZE_SHIFT) -#define L2_XLAT_SIZE (1 << L2_XLAT_SIZE_SHIFT) -#define L1_XLAT_SIZE (1 << L1_XLAT_SIZE_SHIFT) +#define L3_XLAT_SIZE (1UL << L3_ADDR_SHIFT) +#define L2_XLAT_SIZE (1UL << L2_ADDR_SHIFT) +#define L1_XLAT_SIZE (1UL << L1_ADDR_SHIFT) /* Block indices required for MAIR */ #define BLOCK_INDEX_MEM_DEV_NGNRNE 0

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Patch merged into coreboot/master: cd4165a vboot: #include "fmap.h" for declarations
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit cd4165acaba095d03575d35e8a7458cd950f1087 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 22 12:08:55 2015 -0500 vboot: #include "fmap.h" for declarations In the spirit of include what you use actually #include the header necessary for fmap calls. Change-Id: I7acede51d7139234c0520281799dad3a8d33454f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9968 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9968 for details. -gerrit

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coreboot-gerrit April 2015