coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 53a2f60 arm64: perform early setup in secmon too
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit 53a2f6078ac28738b6b52148eb8d90b2fc4132b5 Author: Joseph Lo <josephl(a)nvidia.com> Date: Wed Apr 15 14:30:55 2015 +0800 arm64: perform early setup in secmon too Same as commit fe0eac5f416e "arm64: Allow cpu specific early setup", we need the same in secmon too. BRANCH=none BUG=none TEST=boot on smaug/foster Change-Id: I5b1347880306a95f99233db12cb99547bad4aa8c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1f70fd940ff92eb5b8991cd777c2894b7a9633cf Original-Change-Id: Ifce5a6d636051e7a447d055c8e09ed4e29e091c7 Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265825 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> Reviewed-on: http://review.coreboot.org/9978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9978 for details. -gerrit

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Patch merged into coreboot/master: 36d3586 arm64: Allow cpu specific early setup
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit 36d3586e787addff57bb835c3aa1664b6c8ece94 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Mar 27 22:55:59 2015 -0700 arm64: Allow cpu specific early setup Call arm64_cpu_early_setup to allow cpu-specific initialization to be performed. Also, add support for setting SMPEN bit for cortex a57 within arm64_cpu_early_setup. BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully and SMP works for foster Change-Id: Ifa4e6134dbce3ad63046b3dd9b947c3d9134d5e7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fe0eac5f416efcf9f7b05388a17444205a8352c0 Original-Change-Id: I28a05a20e6adf084cd0bf94bdd0c3b492632107c Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/262993 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9977 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9977 for details. -gerrit

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Patch set updated for coreboot: 1455832 mainboard/intel: Drop unused onboard.h files
by Kyösti Mälkki 27 Apr '15

27 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9991 -gerrit commit 145583289ed2a63075da11a21e0262d6e7f0480a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 24 15:41:18 2015 +0300 mainboard/intel: Drop unused onboard.h files Change-Id: I0851375f419202f62ddc8c80fa77e1d8c95ed50f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/baskingridge/onboard.h | 37 ------------------------------ src/mainboard/intel/emeraldlake2/onboard.h | 37 ------------------------------ 2 files changed, 74 deletions(-) diff --git a/src/mainboard/intel/baskingridge/onboard.h b/src/mainboard/intel/baskingridge/onboard.h deleted file mode 100644 index 52f53e0..0000000 --- a/src/mainboard/intel/baskingridge/onboard.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef LUMPY_ONBOARD_H -#define LUMPY_ONBOARD_H - -#include <arch/smp/mpspec.h> - -#define LUMPY_LIGHTSENSOR_NAME "lightsensor" -#define LUMPY_LIGHTSENSOR_I2C_ADDR 0x44 -#define LUMPY_LIGHTSENSOR_GSI 20 -#define LUMPY_LIGHTSENSOR_IRQ 14 -#define LUMPY_LIGHTSENSOR_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW) - -#define LUMPY_TRACKPAD_NAME "trackpad" -#define LUMPY_TRACKPAD_I2C_ADDR 0x67 -#define LUMPY_TRACKPAD_GSI 21 -#define LUMPY_TRACKPAD_IRQ 15 -#define LUMPY_TRACKPAD_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW) - -#endif diff --git a/src/mainboard/intel/emeraldlake2/onboard.h b/src/mainboard/intel/emeraldlake2/onboard.h deleted file mode 100644 index 52f53e0..0000000 --- a/src/mainboard/intel/emeraldlake2/onboard.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef LUMPY_ONBOARD_H -#define LUMPY_ONBOARD_H - -#include <arch/smp/mpspec.h> - -#define LUMPY_LIGHTSENSOR_NAME "lightsensor" -#define LUMPY_LIGHTSENSOR_I2C_ADDR 0x44 -#define LUMPY_LIGHTSENSOR_GSI 20 -#define LUMPY_LIGHTSENSOR_IRQ 14 -#define LUMPY_LIGHTSENSOR_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW) - -#define LUMPY_TRACKPAD_NAME "trackpad" -#define LUMPY_TRACKPAD_I2C_ADDR 0x67 -#define LUMPY_TRACKPAD_GSI 21 -#define LUMPY_TRACKPAD_IRQ 15 -#define LUMPY_TRACKPAD_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW) - -#endif

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Patch set updated for coreboot: 9070d09 sandy/ivy/nehalem: Fix interrupt handling [NOTFORMERGE]
by Kyösti Mälkki 27 Apr '15

27 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9993 -gerrit commit 9070d09fedc318a18533508302a7e5b39a4eb8cc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Apr 25 18:29:28 2015 +0300 sandy/ivy/nehalem: Fix interrupt handling [NOTFORMERGE] This partially reverts commit 33b535f1. PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive for the GPIO to use. They cannot be used for PCI devices at the same time. Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- .../google/butterfly/acpi/sandybridge_pci_irqs.asl | 64 ++++++++++++++++ src/mainboard/google/butterfly/romstage.c | 42 ++++++++++- .../google/link/acpi/sandybridge_pci_irqs.asl | 68 +++++++++++++++++ src/mainboard/google/link/romstage.c | 39 +++++++++- .../google/parrot/acpi/sandybridge_pci_irqs.asl | 68 +++++++++++++++++ src/mainboard/google/parrot/romstage.c | 43 ++++++++++- .../google/stout/acpi/sandybridge_pci_irqs.asl | 72 ++++++++++++++++++ src/mainboard/google/stout/romstage.c | 43 ++++++++++- .../emeraldlake2/acpi/sandybridge_pci_irqs.asl | 68 +++++++++++++++++ src/mainboard/intel/emeraldlake2/romstage.c | 38 +++++++++- .../kontron/ktqm77/acpi/sandybridge_pci_irqs.asl | 87 ++++++++++++++++++++++ src/mainboard/kontron/ktqm77/romstage.c | 58 ++++++++++++++- .../lenovo/t520/acpi/sandybridge_pci_irqs.asl | 64 ++++++++++++++++ src/mainboard/lenovo/t520/romstage.c | 42 +++++++++++ .../lenovo/t530/acpi/sandybridge_pci_irqs.asl | 64 ++++++++++++++++ src/mainboard/lenovo/t530/romstage.c | 42 +++++++++++ .../lenovo/x201/acpi/nehalem_pci_irqs.asl | 86 +++++++++++++++++++++ src/mainboard/lenovo/x201/romstage.c | 40 +++++++++- .../lenovo/x220/acpi/sandybridge_pci_irqs.asl | 64 ++++++++++++++++ src/mainboard/lenovo/x220/romstage.c | 42 +++++++++++ .../lenovo/x230/acpi/sandybridge_pci_irqs.asl | 64 ++++++++++++++++ src/mainboard/lenovo/x230/romstage.c | 42 +++++++++++ .../packardbell/ms2290/acpi/nehalem_pci_irqs.asl | 86 +++++++++++++++++++++ src/mainboard/packardbell/ms2290/romstage.c | 41 ++++++++-- .../samsung/lumpy/acpi/sandybridge_pci_irqs.asl | 68 +++++++++++++++++ src/mainboard/samsung/lumpy/romstage.c | 36 ++++++++- .../samsung/stumpy/acpi/sandybridge_pci_irqs.asl | 68 +++++++++++++++++ src/mainboard/samsung/stumpy/romstage.c | 38 +++++++++- src/northbridge/intel/nehalem/acpi/hostbridge.asl | 3 + .../intel/sandybridge/acpi/hostbridge.asl | 3 + src/southbridge/intel/bd82x6x/acpi/irq.asl | 72 ------------------ src/southbridge/intel/bd82x6x/acpi/pch.asl | 2 - 32 files changed, 1566 insertions(+), 91 deletions(-) diff --git a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..6c1c695 --- /dev/null +++ b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 1753cd5..eda54a5 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -60,7 +60,47 @@ void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..a4267bb --- /dev/null +++ b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, + Package() { 0x001fffff, 1, 0, 23 }, + Package() { 0x001fffff, 2, 0, 16 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 5844aa6..e814a24 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -78,7 +78,44 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P3IP WLAN INTA -> PIRQB + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * TRACKPAD -> PIRQE (Edge Triggered) + * TOUCHSCREEN -> PIRQG (Edge Triggered) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..a4267bb --- /dev/null +++ b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, + Package() { 0x001fffff, 1, 0, 23 }, + Package() { 0x001fffff, 2, 0, 16 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index ab82bde..fc50a87 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -62,7 +62,48 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P2IP WLAN INTA -> PIRQB + * D28IP_P3IP ETH0 INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQE + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQH + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * + * Trackpad DVT PIRQA (16) + * Trackpad DVT PIRQE (20) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | + (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) | + (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) | + (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..cf3d82a --- /dev/null +++ b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 19 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, + Package() { 0x001fffff, 1, 0, 23 }, + Package() { 0x001fffff, 2, 0, 16 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 6a6aa48..5e6db50 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -68,7 +68,48 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D20IP_XHCI XHCI INTA -> PIRQD (MSI) + * D26IP_E2P EHCI #2 INTA -> PIRQF + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * D28IP_P2IP WLAN INTA -> PIRQD + * D28IP_P3IP Card Reader INTB -> PIRQE + * D28IP_P6IP LAN INTC -> PIRQB + * D29IP_E1P EHCI #1 INTA -> PIRQD + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | + (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | + (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | + (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCIIP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC); + DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl b/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..a57f9f1 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 18 }, + Package() { 0x001cffff, 2, 0, 19 }, + Package() { 0x001cffff, 3, 0, 20 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 20 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 21 }, + Package() { 0x001fffff, 1, 0, 22 }, + Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 3, 0, 16 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 45d92d8..8344a6c 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -74,7 +74,43 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P4IP ETH0 INTB -> PIRQC + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQH + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..ceb40be --- /dev/null +++ b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Ivybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // LPC devices 0:1f.x + // D31IP_TTIP THRT INTC -> PIRQC + Package() { 0x001fffff, 2, 0, 18 },// D31IP_SMIP SMBUS INTC -> PIRQC + Package() { 0x001fffff, 1, 0, 19 },// D31IP_SIP SATA INTB -> PIRQD (MSI) + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 23 },// D29IP_E1P EHCI1 INTA -> PIRQH + // PCIe Root Ports 0:1c.x + // D28IP_P8IP Slot? INTD -> PIRQD + Package() { 0x001cffff, 3, 0, 19 },// D28IP_P4IP ETH2 INTD -> PIRQD (MSI) + // D28IP_P7IP PCIEx1 INTC -> PIRQC + Package() { 0x001cffff, 2, 0, 18 },// D28IP_P3IP ETH1 INTC -> PIRQC (MSI) + // D28IP_P6IP 1394 INTB -> PIRQB (MSI) + Package() { 0x001cffff, 1, 0, 17 },// D28IP_P2IP Slot? INTB -> PIRQB + // D28IP_P5IP GbEPHY INTA -> PIRQA + Package() { 0x001cffff, 0, 0, 16 },// D28IP_P1IP Slot? INTA -> PIRQA + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 },// D27IP_ZIP HDA INTA -> PIRQG (MSI) + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 16 },// D26IP_E2P EHCI2 INTA -> PIRQA + // ETH0 0:19.0 + Package() { 0x0019ffff, 0, 0, 20 },// D25IP_LIP ETH0 INTA -> PIRQE (MSI) + // xHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 16 },// D20IP_XHCIIP xHCI INTA -> PIRQA (MSI) + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // PCIe PEG x16 0:1.0 + Package() { 0x0001ffff, 3, 0, 19 },// PEGx16 INTD -> PIRQD + Package() { 0x0001ffff, 2, 0, 18 },// PEGx16 INTC -> PIRQC + Package() { 0x0001ffff, 1, 0, 17 },// PEGx16 INTB -> PIRQB + Package() { 0x0001ffff, 0, 0, 16 },// PEGx16 INTA -> PIRQA + }) + } Else { + Return (Package() { + // LPC devices 0:1f.x + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // ETH0 0:19.0 + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // xHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe PEG x16 0:1.0 + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 22dc33d..a4bc3a2 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -60,7 +60,63 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * D31IP_TTIP THRT INTC -> PIRQC + * D31IP_SIP2 SATA2 NOINT + * D31IP_SMIP SMBUS INTC -> PIRQC + * D31IP_SIP SATA INTB -> PIRQD (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQH + * D28IP_P8IP Slot? INTD -> PIRQD + * D28IP_P7IP PCIEx1 INTC -> PIRQC + * D28IP_P6IP 1394 INTB -> PIRQB (MSI) + * D28IP_P5IP GbEPHY INTA -> PIRQA + * D28IP_P4IP ETH2 INTD -> PIRQD (MSI) + * D28IP_P3IP ETH1 INTC -> PIRQC (MSI) + * D28IP_P2IP Slot? INTB -> PIRQB + * D28IP_P1IP Slot? INTA -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D26IP_E2P EHCI2 INTA -> PIRQA + * D25IP_LIP ETH0 INTA -> PIRQE (MSI) + * D22IP_KTIP MEI NOINT + * D22IP_IDERIP MEI NOINT + * D22IP_MEI2IP MEI NOINT + * D22IP_MEI1IP MEI NOINT + * D20IP_XHCIIP XHCI INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) + * PEGx16 INTA -> PIRQA + * INTB -> PIRQB + * INTC -> PIRQC + * INTD -> PIRQD + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTC << D31IP_SMIP) | (INTB << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) | + (INTA << D28IP_P5IP) | (INTB << D28IP_P6IP) | + (INTC << D28IP_P7IP) | (INTD << D28IP_P8IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (INTA << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCIIP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); + DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); + DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD); + DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); + DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..b4b81a2 --- /dev/null +++ b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P2IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P4IP EXC INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P5IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index f7866a8..83be0c7 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -60,6 +60,48 @@ void pch_enable_lpc(void) void rcba_config(void) { + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P2IP WLAN INTA -> PIRQB + * D28IP_P4IP EXC INTB -> PIRQF + * D28IP_P5IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P2IP) | (INTB << D28IP_P4IP) | + (INTC << D28IP_P5IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1ee51fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..6c1c695 --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index f29d375..970ee97 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -47,6 +47,48 @@ void pch_enable_lpc(void) void rcba_config(void) { + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl b/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl new file mode 100644 index 0000000..3e9e1b3 --- /dev/null +++ b/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing. + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 0x10 }, + Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA + Package() { 0x0003ffff, 0, 0, 0x10 }, + Package() { 0x0016ffff, 0, 0, 0x10 }, // ME + Package() { 0x0016ffff, 1, 0, 0x11 }, // ME + Package() { 0x0016ffff, 2, 0, 0x12 }, // ME + Package() { 0x0016ffff, 3, 0, 0x13 }, // ME + Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet + Package() { 0x001affff, 0, 0, 0x14 }, // USB + Package() { 0x001affff, 1, 0, 0x15 }, // USB + Package() { 0x001affff, 2, 0, 0x16 }, // USB + Package() { 0x001affff, 3, 0, 0x17 }, // USB + Package() { 0x001bffff, 1, 0, 0x11 }, // Audio + Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge + Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge + Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge + Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge + Package() { 0x001dffff, 0, 0, 0x10 }, // USB + Package() { 0x001dffff, 1, 0, 0x11 }, // USB + Package() { 0x001dffff, 2, 0, 0x12 }, // USB + Package() { 0x001dffff, 3, 0, 0x13 }, // USB + Package() { 0x001fffff, 0, 0, 0x17 }, // LPC + Package() { 0x001fffff, 1, 0, 0x10 }, // IDE + Package() { 0x001fffff, 2, 0, 0x11 }, // SATA + Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS + }) + } Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME + Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME + Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME + Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB + Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB + Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB + Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB + Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus + }) + } +} diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 624440a..3ae8a3b 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -75,9 +75,41 @@ static void pch_enable_lpc(void) static void rcba_config(void) { - southbridge_configure_default_intmap(); - static const u32 rcba_dump3[] = { + /* 30fc */ 0x00000000, + /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321, + /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002, + /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000, + /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654, + /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210, + /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000, + /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -147,8 +179,8 @@ static void rcba_config(void) }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x30fc) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x30fc); } } diff --git a/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..6c1c695 --- /dev/null +++ b/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index d0fb8e6..cf25703 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -57,6 +57,48 @@ void pch_enable_lpc(void) void rcba_config(void) { + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1fe41fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..6c1c695 --- /dev/null +++ b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 4ea272d..ef47b54 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -60,6 +60,48 @@ void pch_enable_lpc(void) void rcba_config(void) { + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl b/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl new file mode 100644 index 0000000..1f782c8 --- /dev/null +++ b/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing. + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 0x10 }, + Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA + Package() { 0x0003ffff, 0, 0, 0x10 }, + Package() { 0x0016ffff, 0, 0, 0x10 }, // ME + Package() { 0x0016ffff, 1, 0, 0x11 }, // ME + Package() { 0x0016ffff, 2, 0, 0x12 }, // ME + Package() { 0x0016ffff, 3, 0, 0x13 }, // ME + Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet + Package() { 0x001affff, 0, 0, 0x14 }, // USB + Package() { 0x001affff, 1, 0, 0x15 }, // USB + Package() { 0x001affff, 2, 0, 0x16 }, // USB + Package() { 0x001affff, 3, 0, 0x17 }, // USB + Package() { 0x001bffff, 1, 0, 0x11 }, // Audio + Package() { 0x001cffff, 0, 0, 0x10 }, // PCI bridge + Package() { 0x001cffff, 1, 0, 0x11 }, // PCI bridge + Package() { 0x001cffff, 2, 0, 0x12 }, // PCI bridge + Package() { 0x001cffff, 3, 0, 0x13 }, // PCI bridge + Package() { 0x001dffff, 0, 0, 0x10 }, // USB + Package() { 0x001dffff, 1, 0, 0x11 }, // USB + Package() { 0x001dffff, 2, 0, 0x12 }, // USB + Package() { 0x001dffff, 3, 0, 0x13 }, // USB + Package() { 0x001fffff, 0, 0, 0x17 }, // LPC + Package() { 0x001fffff, 1, 0, 0x10 }, // IDE + Package() { 0x001fffff, 2, 0, 0x11 }, // SATA + Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS + }) + } Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME + Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME + Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME + Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB + Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB + Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB + Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB + Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // PCI + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // PCI + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // PCI + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // PCI + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus + }) + } +} diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index f702e9f..0d65e66 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -70,9 +70,41 @@ static void pch_enable_lpc(void) static void rcba_config(void) { - southbridge_configure_default_intmap(); - static const u32 rcba_dump3[] = { + /* 30fc */ 0x00000000, + /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321, + /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002, + /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000, + /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654, + /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210, + /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000, + /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -141,10 +173,9 @@ static void rcba_config(void) /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000, }; unsigned i; - for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x30fc) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x30fc); } } diff --git a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..aff2351 --- /dev/null +++ b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 18 }, + Package() { 0x001cffff, 2, 0, 19 }, + Package() { 0x001cffff, 3, 0, 16 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 17 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 16 }, + Package() { 0x001fffff, 1, 0, 22 }, + Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 3, 0, 17 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }, + }) + } +} diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 29a238a..27be119 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -74,7 +74,41 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P4IP ETH0 INTB -> PIRQC (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQB + * D31IP_SIP SATA INTA -> PIRQA (MSI) + * D31IP_SMIP SMBUS INTC -> PIRQH + * D31IP_TTIP THRT INTB -> PIRQG + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * + * LIGHTSENSOR -> PIRQE (Edge Triggered) + * TRACKPAD -> PIRQF (Edge Triggered) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTC << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; diff --git a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..2636f13 --- /dev/null +++ b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 18 }, + Package() { 0x001cffff, 2, 0, 19 }, + Package() { 0x001cffff, 3, 0, 20 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 20 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 21 }, + Package() { 0x001fffff, 1, 0, 22 }, + Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 3, 0, 16 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 346026f..3c2308a 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -86,7 +86,43 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P4IP ETH0 INTB -> PIRQC + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQH + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index d210a95..aeb4c29 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -343,3 +343,6 @@ Method (_CRS, 0, Serialized) Return (MCRS) } + +/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ +#include "acpi/nehalem_pci_irqs.asl" diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 26f7514..d9fc171 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -378,3 +378,6 @@ Method (_CRS, 0, Serialized) Return (MCRS) } + +/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ +#include "acpi/sandybridge_pci_irqs.asl" diff --git a/src/southbridge/intel/bd82x6x/acpi/irq.asl b/src/southbridge/intel/bd82x6x/acpi/irq.asl deleted file mode 100644 index 61e3335..0000000 --- a/src/southbridge/intel/bd82x6x/acpi/irq.asl +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* PCI Interrupt Routing */ -Method(_PRT) -{ - If (PICM) { - Return (Package() { - /* Onboard graphics (IGD) 0:2.0 */ - Package() { 0x0002ffff, 0, 0, 16 },/* GFX INTA -> PIRQA (MSI) */ - /* XHCI 0:14.0 (ivy only) */ - Package() { 0x0014ffff, 0, 0, 19 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */ - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 17 },/* D28IP_P1IP PCIe INTA -> PIRQB */ - Package() { 0x001cffff, 1, 0, 21 },/* D28IP_P2IP PCIe INTB -> PIRQF */ - Package() { 0x001cffff, 2, 0, 19 },/* D28IP_P3IP PCIe INTC -> PIRQD */ - Package() { 0x001cffff, 3, 0, 20 },/* D28IP_P3IP PCIe INTD -> PIRQE */ - /* EHCI #1 0:1d.0 */ - Package() { 0x001dffff, 0, 0, 19 },/* D29IP_E1P EHCI1 INTA -> PIRQD */ - /* EHCI #2 0:1a.0 */ - Package() { 0x001affff, 0, 0, 21 },/* D26IP_E2P EHCI2 INTA -> PIRQF */ - /* LPC devices 0:1f.0 */ - Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */ - Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */ - Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */ - Package() { 0x001fffff, 3, 0, 18 }, - }) - } Else { - Return (Package() { - /* Onboard graphics (IGD) 0:2.0 */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* XHCI 0:14.0 (ivy only) */ - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, - /* EHCI #1 0:1d.0 */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - /* EHCI #2 0:1a.0 */ - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - /* LPC device 0:1f.0 */ - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, - }) - } -} diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 73fcfcc..27f08e2 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -257,8 +257,6 @@ Scope(\) // SMBus 0:1f.3 #include "smbus.asl" -#include "irq.asl" - Method (_OSC, 4) { /* Check for XHCI */

1 0

Patch set updated for coreboot: 7d7fcb2 sandy/ivy boards: Rename defines from onboard.h for ACPI
by Kyösti Mälkki 27 Apr '15

27 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9992 -gerrit commit 7d7fcb2d48955a2ebd3f855dd0975754f7878080 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 24 16:05:58 2015 +0300 sandy/ivy boards: Rename defines from onboard.h for ACPI Adopted style from later Chromebooks. Change-Id: I4993b8f40489b6bf5d08e00089f36f293853629e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/butterfly/acpi/mainboard.asl | 11 ++++++++--- src/mainboard/google/butterfly/mainboard.c | 6 +++--- src/mainboard/google/butterfly/onboard.h | 7 ++++--- src/mainboard/google/link/acpi/mainboard.asl | 11 ++++++++--- src/mainboard/google/link/mainboard.c | 18 +++++++++--------- src/mainboard/google/link/onboard.h | 19 ++++++++++--------- src/mainboard/google/parrot/acpi/mainboard.asl | 16 ++++++++++++---- src/mainboard/google/parrot/mainboard.c | 12 ++++++------ src/mainboard/google/parrot/onboard.h | 10 ++++++---- src/mainboard/samsung/lumpy/acpi/mainboard.asl | 18 +++++++++++++----- src/mainboard/samsung/lumpy/mainboard.c | 12 ++++++------ src/mainboard/samsung/lumpy/onboard.h | 13 +++++++------ 12 files changed, 92 insertions(+), 61 deletions(-) diff --git a/src/mainboard/google/butterfly/acpi/mainboard.asl b/src/mainboard/google/butterfly/acpi/mainboard.asl index c6e35e8..342193f 100644 --- a/src/mainboard/google/butterfly/acpi/mainboard.asl +++ b/src/mainboard/google/butterfly/acpi/mainboard.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <mainboard/google/butterfly/onboard.h> + Scope (\_SB) { Device (LID0) { @@ -45,15 +47,18 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0E")) // Trackpad Wake is GPIO11, wake from S3 - Name(_PRW, Package(){0x1b, 0x03}) + Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) Name(_CRS, ResourceTemplate() { // PIRQG -> GSI22 - Interrupt (ResourceConsumer, EDGE, ActiveLow) {22} + Interrupt (ResourceConsumer, EDGE, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } // SMBUS Address 0x67 - VendorShort (ADDR) {0x67} + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } }) } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 655fc2f..f83b33b 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -265,10 +265,10 @@ static int butterfly_onboard_smbios_data(device_t dev, int *handle, len += smbios_write_type41( current, handle, - BUTTERFLY_TRACKPAD_NAME, /* name */ - BUTTERFLY_TRACKPAD_IRQ, /* instance */ + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ, /* instance */ 0, /* segment */ - BUTTERFLY_TRACKPAD_I2C_ADDR, /* bus */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h index e32e023..f7db29e 100644 --- a/src/mainboard/google/butterfly/onboard.h +++ b/src/mainboard/google/butterfly/onboard.h @@ -23,9 +23,10 @@ #include <arch/smp/mpspec.h> /* uses 7-bit I2C address */ /* must be set to edge triggered */ -#define BUTTERFLY_TRACKPAD_NAME "trackpad" -#define BUTTERFLY_TRACKPAD_I2C_ADDR 0x67 -#define BUTTERFLY_TRACKPAD_IRQ 22 /* PIRQG - 22 Edge triggered */ +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_I2C_ADDR 0x67 +#define BOARD_TRACKPAD_IRQ 22 /* PIRQG - 22 Edge triggered */ +#define BOARD_TRACKPAD_WAKE_GPIO 0x1b /* defines for programming the MAC address */ #define BUTTERFLY_NIC_VENDOR_ID 0x10EC diff --git a/src/mainboard/google/link/acpi/mainboard.asl b/src/mainboard/google/link/acpi/mainboard.asl index a2778a0..ee727e0 100644 --- a/src/mainboard/google/link/acpi/mainboard.asl +++ b/src/mainboard/google/link/acpi/mainboard.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <mainboard/google/link/onboard.h> + Scope (\_SB) { Device (LID0) { @@ -48,15 +50,18 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0E")) // Trackpad Wake is GPIO12 - Name(_PRW, Package(){0x1c, 0x03}) + Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } ) Name(_CRS, ResourceTemplate() { // PIRQE -> GSI20 - Interrupt (ResourceConsumer, Edge, ActiveLow) {20} + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } // SMBUS Address 0x4b - VendorShort (ADDR) {0x4b} + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } }) } diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index ed40f8f..a3a98fc 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -173,28 +173,28 @@ static int link_onboard_smbios_data(device_t dev, int *handle, len += smbios_write_type41( current, handle, - LINK_LIGHTSENSOR_NAME, /* name */ - LINK_LIGHTSENSOR_IRQ, /* instance */ + BOARD_LIGHTSENSOR_NAME, /* name */ + BOARD_LIGHTSENSOR_IRQ, /* instance */ 0, /* segment */ - LINK_LIGHTSENSOR_I2C_ADDR, /* bus */ + BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ len += smbios_write_type41( current, handle, - LINK_TRACKPAD_NAME, /* name */ - LINK_TRACKPAD_IRQ, /* instance */ + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ, /* instance */ 0, /* segment */ - LINK_TRACKPAD_I2C_ADDR, /* bus */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ len += smbios_write_type41( current, handle, - LINK_TOUCHSCREEN_NAME, /* name */ - LINK_TOUCHSCREEN_IRQ, /* instance */ + BOARD_TOUCHSCREEN_NAME, /* name */ + BOARD_TOUCHSCREEN_IRQ, /* instance */ 0, /* segment */ - LINK_TOUCHSCREEN_I2C_ADDR, /* bus */ + BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h index eaac383..78cc85f 100644 --- a/src/mainboard/google/link/onboard.h +++ b/src/mainboard/google/link/onboard.h @@ -22,16 +22,17 @@ #include <arch/smp/mpspec.h> -#define LINK_LIGHTSENSOR_NAME "lightsensor" -#define LINK_LIGHTSENSOR_I2C_ADDR 0x44 -#define LINK_LIGHTSENSOR_IRQ 0 +#define BOARD_LIGHTSENSOR_NAME "lightsensor" +#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 +#define BOARD_LIGHTSENSOR_IRQ 0 -#define LINK_TRACKPAD_NAME "trackpad" -#define LINK_TRACKPAD_I2C_ADDR 0x4b -#define LINK_TRACKPAD_IRQ 20 +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_I2C_ADDR 0x4b +#define BOARD_TRACKPAD_IRQ 20 +#define BOARD_TRACKPAD_WAKE_GPIO 0x1c -#define LINK_TOUCHSCREEN_NAME "touchscreen" -#define LINK_TOUCHSCREEN_I2C_ADDR 0x4a -#define LINK_TOUCHSCREEN_IRQ 22 +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a +#define BOARD_TOUCHSCREEN_IRQ 22 #endif diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 503e44b..9116c69 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <mainboard/google/parrot/onboard.h> + Scope (\_GPE) { Method(_L1F, 0x0, NotSerialized) { @@ -59,19 +61,25 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0E")) // Trackpad Wake is GPIO12, wake from S3 - Name(_PRW, Package(){0x1c, 0x03}) + Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) Name(_CRS, ResourceTemplate() { // PIRQA -> GSI16 - Interrupt (ResourceConsumer, Level, ActiveLow) {16} + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TRACKPAD_IRQ_DVT + } // PIRQE -> GSI20 - Interrupt (ResourceConsumer, Edge, ActiveLow) {20} + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ_PVT + } // SMBUS Address 0x67 - VendorShort (ADDR) {0x67} + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } }) } diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 547680e..39d2c84 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -62,19 +62,19 @@ static int parrot_onboard_smbios_data(device_t dev, int *handle, if (hardware_version < 0x2) { /* DVT vs PVT */ len += smbios_write_type41( current, handle, - PARROT_TRACKPAD_NAME, /* name */ - PARROT_TRACKPAD_IRQ_DVT, /* instance */ + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ_DVT, /* instance */ 0, /* segment */ - PARROT_TRACKPAD_I2C_ADDR, /* bus */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ } else { len += smbios_write_type41( current, handle, - PARROT_TRACKPAD_NAME, /* name */ - PARROT_TRACKPAD_IRQ_PVT, /* instance */ + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ_PVT, /* instance */ 0, /* segment */ - PARROT_TRACKPAD_I2C_ADDR, /* bus */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ } diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h index f3d200d..4ed341e 100644 --- a/src/mainboard/google/parrot/onboard.h +++ b/src/mainboard/google/parrot/onboard.h @@ -22,8 +22,10 @@ #include <arch/smp/mpspec.h> -#define PARROT_TRACKPAD_NAME "trackpad" -#define PARROT_TRACKPAD_I2C_ADDR 0x67 -#define PARROT_TRACKPAD_IRQ_DVT 16 -#define PARROT_TRACKPAD_IRQ_PVT 20 +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_I2C_ADDR 0x67 +#define BOARD_TRACKPAD_IRQ_DVT 16 +#define BOARD_TRACKPAD_IRQ_PVT 20 +#define BOARD_TRACKPAD_WAKE_GPIO 0x1c + #endif diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl index b1ab678..435dd51 100644 --- a/src/mainboard/samsung/lumpy/acpi/mainboard.asl +++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <mainboard/samsung/lumpy/onboard.h> + Scope (\_SB) { Device (LID0) { @@ -45,15 +47,18 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0E")) // Trackpad Wake is GPIO11 - Name(_PRW, Package(){0x1b, 0x03}) + Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) Name(_CRS, ResourceTemplate() { // PIRQF -> GSI21 - Interrupt (ResourceConsumer, Edge, ActiveLow) {21} + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } // SMBUS Address 0x67 - VendorShort (ADDR) {0x67} + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } }) } @@ -65,10 +70,13 @@ Scope (\_SB) { Name(_CRS, ResourceTemplate() { // PIRQE -> GSI20 - Interrupt (ResourceConsumer, Edge, ActiveLow) {20} + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_LIGHTSENSOR_IRQ + } // SMBUS Address 0x44 - VendorShort (ADDR) {0x44} + VendorShort (ADDR) { BOARD_LIGHTSENSOR_I2C_ADDR } }) } } diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 3bdd4d9..6967a2b 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -86,14 +86,14 @@ static int lumpy_onboard_smbios_data(device_t dev, int *handle, int len = 0; len += lumpy_smbios_type41_irq(handle, current, - LUMPY_LIGHTSENSOR_NAME, - LUMPY_LIGHTSENSOR_IRQ, - LUMPY_LIGHTSENSOR_I2C_ADDR); + BOARD_LIGHTSENSOR_NAME, + BOARD_LIGHTSENSOR_IRQ, + BOARD_LIGHTSENSOR_I2C_ADDR); len += lumpy_smbios_type41_irq(handle, current, - LUMPY_TRACKPAD_NAME, - LUMPY_TRACKPAD_IRQ, - LUMPY_TRACKPAD_I2C_ADDR); + BOARD_TRACKPAD_NAME, + BOARD_TRACKPAD_IRQ, + BOARD_TRACKPAD_I2C_ADDR); return len; } diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h index 6bdf057..0237003 100644 --- a/src/mainboard/samsung/lumpy/onboard.h +++ b/src/mainboard/samsung/lumpy/onboard.h @@ -22,12 +22,13 @@ #include <arch/smp/mpspec.h> -#define LUMPY_LIGHTSENSOR_NAME "lightsensor" -#define LUMPY_LIGHTSENSOR_I2C_ADDR 0x44 -#define LUMPY_LIGHTSENSOR_IRQ 20 +#define BOARD_LIGHTSENSOR_NAME "lightsensor" +#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 +#define BOARD_LIGHTSENSOR_IRQ 20 -#define LUMPY_TRACKPAD_NAME "trackpad" -#define LUMPY_TRACKPAD_I2C_ADDR 0x67 -#define LUMPY_TRACKPAD_IRQ 21 +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_I2C_ADDR 0x67 +#define BOARD_TRACKPAD_IRQ 21 +#define BOARD_TRACKPAD_WAKE_GPIO 0x1b #endif

1 0

Patch merged into coreboot/master: de8c780 Build system: Fix "dd: invalid number `0x800000'"
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit de8c78083454a30628d8d67c970535790adcff01 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed Apr 22 15:22:00 2015 +0800 Build system: Fix "dd: invalid number `0x800000'" dd doesn't recognise hex number. the commit introducing this: f21b657 build system: improve portability by not relying on extraordinary dd options Change-Id: Ie0df3eb00fa2ba5d7bbb8218e24b864cbdd07c3a Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Reviewed-on: http://review.coreboot.org/9944 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/9944 for details. -gerrit

1 0

Patch set updated for coreboot: 3a5b36d Build system: Fix "dd: invalid number `0x800000'"
by WANG Siyuan 27 Apr '15

27 Apr '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9944 -gerrit commit 3a5b36d14b685f6ed9e1b2169a3febde7cae40bc Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed Apr 22 15:22:00 2015 +0800 Build system: Fix "dd: invalid number `0x800000'" dd doesn't recognise hex number. the commit introducing this: f21b657 build system: improve portability by not relying on extraordinary dd options Change-Id: Ie0df3eb00fa2ba5d7bbb8218e24b864cbdd07c3a Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 04e8085..b67f145 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -560,7 +560,7 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(c @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty # file (filled with \377 = 0xff) and copy the CBFS image over it. - dd if=/dev/zero bs=$(CONFIG_ROM_SIZE) count=1 | tr '\000' '\377' > $@.tmp + dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y)

1 0

Patch set updated for coreboot: 7cf1652 amd/pi/hudson: Add AMD Avalon BLOBs to CBFS
by WANG Siyuan 27 Apr '15

27 Apr '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9416 -gerrit commit 7cf1652774dd2109f77ce31de447d01af22b9975 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed Apr 8 18:51:15 2015 +0800 amd/pi/hudson: Add AMD Avalon BLOBs to CBFS trustlets.bin and Trustlet.tkn.cert are necessary for AGESA.bin <Change-Id: I7c413c>. Otherwise it does not boot. I have tested on OliveHill plus. This change depends on the BLOBs added to the 3rdparty/BLOBs repository in <Change-Id: I7c413c> : AMD FT3b binary PI: fix Windows 7 graphics driver issue and <If81c2285269> : amd/avalon: Add PSP firmware Change-Id: I03c612fc49ddc77777a70cc7a1a8d297b9786bc8 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 32 +++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c66d541..de172fb 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -207,10 +207,22 @@ SMUFWM_POS=$(call int-align, \ $(call int-add,$(PSPNVRAM_POS) $(PSPNVRAM_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUFWM_SIZE=$(call file-size,$(CONFIG_SMUFWM_FILE)) +## 12 +CONFIG_TRUSTLET_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +TRUSTLET_POS=$(call int-align, \ + $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +TRUSTLET_SIZE=$(call file-size,$(CONFIG_TRUSTLET_FILE)) +## 13 +CONFIG_TRUSTLET_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +TRUSTLET_KEY_POS=$(call int-align, \ + $(call int-add,$(TRUSTLET_POS) $(TRUSTLET_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +TRUSTLET_KEY_SIZE=$(call file-size,$(CONFIG_TRUSTLET_KEY_FILE)) CONFIG_SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin SMUSCS_POS=$(call int-align, \ - $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(TRUSTLET_KEY_POS) $(TRUSTLET_KEY_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUSCS_SIZE=$(call file-size,$(CONFIG_SMUSCS_FILE)) @@ -241,6 +253,12 @@ $(obj)/coreboot_psp_directory.bin: $(obj)/config.h $(FLETCHER) $(RTM_FILE) for fwm in 4 $(PSPNVRAM_SIZE) $(PSPNVRAM_POS) 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $(a)_tail.tmp + for fwm in 12 $(TRUSTLET_SIZE) $(TRUSTLET_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $(a)_tail.tmp + for fwm in 13 $(TRUSTLET_KEY_SIZE) $(TRUSTLET_KEY_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $(a)_tail.tmp for fwm in 95 $(SMUSCS_SIZE) $(SMUSCS_POS) 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $(a)_tail.tmp @@ -300,6 +318,18 @@ apu/smufwm-file := $(CONFIG_SMUFWM_FILE) apu/smufwm-position := $(SMUFWM_POS) apu/smufwm-type := raw +#12 +cbfs-files-y += apu/trustlet +apu/trustlet-file := $(CONFIG_TRUSTLET_FILE) +apu/trustlet-position := $(TRUSTLET_POS) +apu/trustlet-type := raw + +#13 +cbfs-files-y += apu/trustlet_key +apu/trustlet_key-file := $(CONFIG_TRUSTLET_KEY_FILE) +apu/trustlet_key-position := $(TRUSTLET_KEY_POS) +apu/trustlet_key-type := raw + cbfs-files-y += apu/smuscs apu/smuscs-file := $(CONFIG_SMUSCS_FILE) apu/smuscs-position := $(SMUSCS_POS)

1 0

Patch set updated for coreboot: 3cc3d07 fsp platforms: consolidate FspNotify calls
by Martin Roth 27 Apr '15

27 Apr '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9780 -gerrit commit 3cc3d075a641ff37c0a2ed790a6a9e81c8f05376 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Apr 16 21:20:34 2015 -0600 fsp platforms: consolidate FspNotify calls Consolidate the FspNotify calls into the FSP driver directory, using BOOT_STATE_INIT_ENTRY to set up the call times. Change-Id: I184ab234ebb9dcdeb8eece1537c12d03f227c25e Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp1_0/fsp_util.c | 29 ++++++++++++++++++++++ src/northbridge/intel/fsp_rangeley/northbridge.c | 22 ---------------- .../intel/fsp_sandybridge/northbridge.c | 23 ----------------- src/soc/intel/fsp_baytrail/chip.c | 20 --------------- 4 files changed, 29 insertions(+), 65 deletions(-) diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index ab67147..3147b67 100755 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -317,6 +317,35 @@ static void find_fsp_hob_update_mrc(void *unused) } } +/** @brief Notify FSP for PostPciEnumeration + * + * @param unused + */ +static void fsp_after_pci_enum(void *unused) +{ + /* This call needs to be done before resource allocation. */ + printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); + FspNotify(EnumInitPhaseAfterPciEnumeration); + printk(BIOS_DEBUG, + "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); +} + +/** @brief Notify FSP for ReadyToBoot + * + * @param unused + */ +static void fsp_finalize(void *unused) +{ + printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); + print_fsp_info(); + FspNotify(EnumInitPhaseReadyToBoot); + printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); +} + +/* Set up for the ramstage FSP calls */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL); + /* Update the MRC/fast boot cache as part of the late table writing stage */ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 14d0853..306bb89 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -112,17 +112,6 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void finalize_dev (device_t dev) -{ - /* - * Notify FSP for PostPciEnumeration. - * Northbridge APIC init should be early and late enough... - */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); - FspNotify(EnumInitPhaseAfterPciEnumeration); - printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); -} - static void mc_add_dram_resources(device_t dev) { u32 tomlow, bmbound, bsmmrrl, bsmmrrh; @@ -233,7 +222,6 @@ static struct device_operations pci_domain_ops = { .set_resources = pci_domain_set_resources, .enable_resources = NULL, .init = NULL, - .final = finalize_dev, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, }; @@ -294,17 +282,7 @@ static void enable_dev(device_t dev) } } -static void finalize_chip(void *chip_info) -{ - /* Notify FSP for ReadyToBoot */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); - print_fsp_info(); - FspNotify(EnumInitPhaseReadyToBoot); - printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); -} - struct chip_operations northbridge_intel_fsp_rangeley_ops = { CHIP_NAME("Intel Rangeley Northbridge") .enable_dev = enable_dev, - .final = finalize_chip, }; diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index fac635d..17e7723 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -39,7 +39,6 @@ #include <fsp_util.h> static int bridge_revision_id = -1; -static u8 finished_FSP_after_pci = 0; /* IGD UMA memory */ static uint64_t uma_memory_base = 0; @@ -372,31 +371,9 @@ static void enable_dev(device_t dev) } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } - - /* - * Notify FSP for PostPciEnumeration. - * This call needs to be done before resource allocation. - */ - if (!finished_FSP_after_pci) { - finished_FSP_after_pci = 1; - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); - FspNotify(EnumInitPhaseAfterPciEnumeration); - printk(BIOS_DEBUG, - "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n\n"); - } -} - -static void finalize_chip(void *chip_info) -{ - /* Notify FSP for ReadyToBoot */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); - print_fsp_info(); - FspNotify(EnumInitPhaseReadyToBoot); - printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); } struct chip_operations northbridge_intel_fsp_sandybridge_ops = { CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge") .enable_dev = enable_dev, - .final = finalize_chip, }; diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index d26b64a..991e851 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -30,22 +30,11 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void finalize_dev (device_t dev) -{ - /* - * Notify FSP for PostPciEnumeration. - * Northbridge APIC init should be early and late enough... - */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); - FspNotify(EnumInitPhaseAfterPciEnumeration); -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = NULL, .init = NULL, - .final = &finalize_dev, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, }; @@ -77,14 +66,6 @@ static void enable_dev(device_t dev) } } -static void finalize_chip(void *chip_info) -{ - /* Notify FSP for ReadyToBoot */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); - FspNotify(EnumInitPhaseReadyToBoot); - -} - /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ static void soc_init(void *chip_info) { @@ -95,7 +76,6 @@ struct chip_operations soc_intel_fsp_baytrail_ops = { CHIP_NAME("Intel BayTrail SoC") .enable_dev = enable_dev, .init = soc_init, - .final = &finalize_chip, }; static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)

1 0

New patch to review for coreboot: 6e35812 Kconfig whitespace fixes
by Martin Roth 27 Apr '15

27 Apr '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10000 -gerrit commit 6e358125dada16cc226a3bef539a9421b2b65720 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Apr 26 18:53:26 2015 -0600 Kconfig whitespace fixes trivial whitespace fixes. Mostly changing leading spaces to tabs. Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/Kconfig | 22 +++++++++--------- src/cpu/amd/agesa/family10/Kconfig | 10 ++++---- src/cpu/amd/agesa/family15/Kconfig | 10 ++++---- src/cpu/amd/socket_S1G1/Kconfig | 2 +- src/cpu/intel/socket_LGA771/Kconfig | 2 +- src/drivers/intel/i210/Kconfig | 4 ++-- src/drivers/ipmi/Kconfig | 4 ++-- src/drivers/lenovo/Kconfig | 4 ++-- src/drivers/ricoh/rce822/Kconfig | 4 ++-- src/mainboard/advansus/a785e-i/Kconfig | 4 ++-- src/mainboard/amd/tilapia_fam10/Kconfig | 10 ++++---- src/mainboard/aopen/Kconfig | 2 +- src/mainboard/asus/m5a88-v/Kconfig | 4 ++-- src/mainboard/avalue/eax-785e/Kconfig | 4 ++-- src/mainboard/dmp/vortex86ex/Kconfig | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 36 ++++++++++++++--------------- src/mainboard/gigabyte/ga-b75m-d3v/Kconfig | 36 ++++++++++++++--------------- src/mainboard/google/urara/Kconfig | 4 ++-- src/mainboard/google/veyron_brain/Kconfig | 4 ++-- src/mainboard/google/veyron_danger/Kconfig | 4 ++-- src/mainboard/google/veyron_jerry/Kconfig | 4 ++-- src/mainboard/google/veyron_mighty/Kconfig | 4 ++-- src/mainboard/google/veyron_pinky/Kconfig | 4 ++-- src/mainboard/google/veyron_rialto/Kconfig | 4 ++-- src/mainboard/google/veyron_speedy/Kconfig | 4 ++-- src/mainboard/hp/dl165_g6_fam10/Kconfig | 2 +- src/mainboard/supermicro/h8scm/Kconfig.name | 2 +- src/mainboard/traverse/geos/Kconfig | 4 ++-- src/mainboard/tyan/s8226/Kconfig.name | 2 +- src/northbridge/amd/amdfam10/Kconfig | 10 ++++---- src/northbridge/amd/amdk8/Kconfig | 4 ++-- src/northbridge/amd/cimx/rd890/Kconfig | 2 +- src/northbridge/amd/pi/Kconfig | 4 ++-- src/northbridge/intel/i855/Kconfig | 36 ++++++++++++++--------------- src/southbridge/amd/cimx/sb800/Kconfig | 18 +++++++-------- src/southbridge/amd/cimx/sb900/Kconfig | 24 +++++++++---------- src/southbridge/amd/sb600/Kconfig | 4 ++-- src/southbridge/intel/bd82x6x/Kconfig | 4 ++-- src/southbridge/intel/i3100/Kconfig | 4 ++-- src/southbridge/intel/i82801gx/Kconfig | 2 +- src/southbridge/intel/i82801ix/Kconfig | 2 +- src/southbridge/intel/ibexpeak/Kconfig | 4 ++-- src/southbridge/intel/lynxpoint/Kconfig | 4 ++-- src/southbridge/intel/sch/Kconfig | 4 ++-- 44 files changed, 164 insertions(+), 164 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f531f07..df4e320 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -56,14 +56,14 @@ config COMMON_CBFS_SPI_WRAPPER Use common wrapper to interface CBFS to SPI bootrom. config MULTIPLE_CBFS_INSTANCES - bool "Multiple CBFS instances in the bootrom" - default n - depends on !ARCH_X86 - help - Account for the firmware image containing more than one CBFS - instance. Locations of instances are known at build time and are - communicated between coreboot stages to make sure the next stage is - loaded from the appropriate instance. + bool "Multiple CBFS instances in the bootrom" + default n + depends on !ARCH_X86 + help + Account for the firmware image containing more than one CBFS + instance. Locations of instances are known at build time and are + communicated between coreboot stages to make sure the next stage is + loaded from the appropriate instance. choice prompt "Compiler to use" @@ -317,8 +317,8 @@ source "src/arch/*/Kconfig" source "src/vendorcode/*/Kconfig" config SYSTEM_TYPE_LAPTOP - default n - bool + default n + bool menu "Chipset" @@ -578,7 +578,7 @@ config MAINBOARD_SERIAL_NUMBER string "SMBIOS Serial Number" depends on GENERATE_SMBIOS_TABLES default "123456789" - help + help The Serial Number to store in SMBIOS structures. config MAINBOARD_VERSION diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index ec8521c..f5b77ef 100644 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -42,11 +42,11 @@ config XIP_ROM_SIZE default 0x80000 config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - Warning: Only enable this option when debuging or tracing AMD AGESA code. + Warning: Only enable this option when debuging or tracing AMD AGESA code. endif #CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 7fe7d19..b292b90 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -63,11 +63,11 @@ config XIP_ROM_SIZE default 0x80000 config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - Warning: Only enable this option when debuging or tracing AMD AGESA code. + Warning: Only enable this option when debuging or tracing AMD AGESA code. endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index e714200..f88f64a 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -1,5 +1,5 @@ config CPU_AMD_SOCKET_S1G1 - bool + bool if CPU_AMD_SOCKET_S1G1 diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig index 62bd17b..1df55e6 100644 --- a/src/cpu/intel/socket_LGA771/Kconfig +++ b/src/cpu/intel/socket_LGA771/Kconfig @@ -1,6 +1,6 @@ config CPU_INTEL_SOCKET_LGA771 bool - select CPU_INTEL_MODEL_6FX + select CPU_INTEL_MODEL_6FX select SSE2 select MMX select AP_IN_SIPI_WAIT diff --git a/src/drivers/intel/i210/Kconfig b/src/drivers/intel/i210/Kconfig index 0191169..264cca8 100644 --- a/src/drivers/intel/i210/Kconfig +++ b/src/drivers/intel/i210/Kconfig @@ -1,3 +1,3 @@ config DRIVER_INTEL_I210 - bool - default n + bool + default n diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 55c85ea..5851438 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -1,3 +1,3 @@ config IPMI_KCS - bool - default n + bool + default n diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 30bacb9..f20f3b2 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -1,6 +1,6 @@ config DRIVERS_LENOVO_WACOM - bool - default n + bool + default n if DRIVERS_LENOVO_WACOM diff --git a/src/drivers/ricoh/rce822/Kconfig b/src/drivers/ricoh/rce822/Kconfig index 6b0c7905..ef11383 100644 --- a/src/drivers/ricoh/rce822/Kconfig +++ b/src/drivers/ricoh/rce822/Kconfig @@ -1,3 +1,3 @@ config DRIVERS_RICOH_RCE822 - bool - default n + bool + default n diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index e76a312..388249f 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -69,7 +69,7 @@ config IRQ_SLOT_COUNT default 11 config VGA_BIOS_ID - string - default "1002,9712" + string + default "1002,9712" endif #BOARD_ADVANSUS_A785E_I diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index dd46f6a..901d6b1 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -57,12 +57,12 @@ config IRQ_SLOT_COUNT default 11 config VGA_BIOS - bool - default n + bool + default n config VGA_BIOS_ID - string - depends on VGA_BIOS - default "1002,9615" + string + depends on VGA_BIOS + default "1002,9615" endif # BOARD_AMD_TILAPIA_FAM10 diff --git a/src/mainboard/aopen/Kconfig b/src/mainboard/aopen/Kconfig index 7ea4e54..2208e62 100644 --- a/src/mainboard/aopen/Kconfig +++ b/src/mainboard/aopen/Kconfig @@ -1,7 +1,7 @@ if VENDOR_AOPEN choice - prompt "Mainboard model" + prompt "Mainboard model" source "src/mainboard/aopen/*/Kconfig.name" diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index bded839..1430189 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -67,7 +67,7 @@ config IRQ_SLOT_COUNT default 11 config VGA_BIOS_ID - string - default "1002,9715" + string + default "1002,9715" endif #BOARD_ASUS_M5A88_V diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 84f3523..38a3aa3 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -69,7 +69,7 @@ config IRQ_SLOT_COUNT default 11 config VGA_BIOS_ID - string - default "1002,9712" + string + default "1002,9712" endif #BOARD_AVALUE_EAX_785E diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig index d76799e..5adb52d 100644 --- a/src/mainboard/dmp/vortex86ex/Kconfig +++ b/src/mainboard/dmp/vortex86ex/Kconfig @@ -187,7 +187,7 @@ config IDE_COMPATIBLE_SELECTION depends on IDE_STANDARD_COMPATIBLE hex "IDE Compatible Selection" default 0x808624db - help + help IDE controller PCI vendor/device ID value setting. Higher 16-bit is vendor ID, lower 16-bit is device ID. diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index a804fd3..39c04c6 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -17,43 +17,43 @@ config BOARD_SPECIFIC_OPTIONS select VGA select INTEL_EDID select UDELAY_TSC - select SERIRQ_CONTINUOUS_MODE + select SERIRQ_CONTINUOUS_MODE config MMCONF_BASE_ADDRESS hex default 0xf0000000 config DRAM_RESET_GATE_GPIO - int + int default 25 config USBDEBUG_HCD_INDEX - int - default 2 + int + default 2 config MAINBOARD_DIR - string - default gigabyte/ga-b75m-d3h + string + default gigabyte/ga-b75m-d3h config MAINBOARD_PART_NUMBER - string - default "GA-B75M-D3H" + string + default "GA-B75M-D3H" config IRQ_SLOT_COUNT - int - default 18 + int + default 18 config MAX_CPUS - int - default 8 + int + default 8 config VGA_BIOS_ID string default "8086,0162" config VGA_BIOS_FILE - string - default "pci8086,0162.rom" + string + default "pci8086,0162.rom" config HAVE_IFD_BIN bool @@ -64,11 +64,11 @@ config HAVE_ME_BIN default n config IFD_BIOS_SECTION - string - default "0x00600000:0x007fffff" + string + default "0x00600000:0x007fffff" config IFD_ME_SECTION - string - default "0x00001000:0x004fffff" + string + default "0x00001000:0x004fffff" endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig index cffc7f0..20db0c0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig @@ -18,43 +18,43 @@ config BOARD_SPECIFIC_OPTIONS select VGA select INTEL_EDID select UDELAY_TSC - select SERIRQ_CONTINUOUS_MODE + select SERIRQ_CONTINUOUS_MODE config MMCONF_BASE_ADDRESS hex default 0xf8000000 config DRAM_RESET_GATE_GPIO - int + int default 25 config USBDEBUG_HCD_INDEX - int - default 2 + int + default 2 config MAINBOARD_DIR - string - default gigabyte/ga-b75m-d3v + string + default gigabyte/ga-b75m-d3v config MAINBOARD_PART_NUMBER - string - default "GA-B75M-D3V" + string + default "GA-B75M-D3V" config IRQ_SLOT_COUNT - int - default 18 + int + default 18 config MAX_CPUS - int - default 8 + int + default 8 config VGA_BIOS_ID string default "8086,0102" config VGA_BIOS_FILE - string - default "pci8086,0102.rom" + string + default "pci8086,0102.rom" config HAVE_IFD_BIN bool @@ -65,11 +65,11 @@ config HAVE_ME_BIN default n config IFD_BIOS_SECTION - string - default "0x00600000:0x007fffff" + string + default "0x00600000:0x007fffff" config IFD_ME_SECTION - string - default "0x00001000:0x004fffff" + string + default "0x00001000:0x004fffff" endif # BOARD_GIGABYTE_GA_B75M_D3V diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index e1004cd..00a00f8 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -28,8 +28,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select SPI_FLASH_WINBOND select CPU_IMGTEC_PISTACHIO - select COMMON_CBFS_SPI_WRAPPER - select MAINBOARD_HAS_BOOTBLOCK_INIT + select COMMON_CBFS_SPI_WRAPPER + select MAINBOARD_HAS_BOOTBLOCK_INIT select SPI_FLASH config MAINBOARD_DIR diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index bea618c..2f48abd 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -61,8 +61,8 @@ config VBOOT_ROMSTAGE_INDEX default 0x1 config BOOT_MEDIA_SPI_BUS - int - default 2 + int + default 2 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index f6e0060..876e387 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -61,8 +61,8 @@ config VBOOT_ROMSTAGE_INDEX default 0x1 config BOOT_MEDIA_SPI_BUS - int - default 2 + int + default 2 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig index be0b736..c00f526 100644 --- a/src/mainboard/google/veyron_jerry/Kconfig +++ b/src/mainboard/google/veyron_jerry/Kconfig @@ -65,8 +65,8 @@ config VBOOT_RAMSTAGE_INDEX default 0x3 config BOOT_MEDIA_SPI_BUS - int - default 2 + int + default 2 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig index 58972ad..919a546 100644 --- a/src/mainboard/google/veyron_mighty/Kconfig +++ b/src/mainboard/google/veyron_mighty/Kconfig @@ -65,8 +65,8 @@ config VBOOT_RAMSTAGE_INDEX default 0x3 config BOOT_MEDIA_SPI_BUS - int - default 2 + int + default 2 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index 87d24f0..7e3838f 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -65,8 +65,8 @@ config VBOOT_RAMSTAGE_INDEX default 0x3 config BOOT_MEDIA_SPI_BUS - int - default 2 + int + default 2 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 597dd19..f11098f 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -60,8 +60,8 @@ config VBOOT_ROMSTAGE_INDEX default 0x1 config BOOT_MEDIA_SPI_BUS - int - default 2 + int + default 2 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig index 6a51457..6dabe34 100644 --- a/src/mainboard/google/veyron_speedy/Kconfig +++ b/src/mainboard/google/veyron_speedy/Kconfig @@ -65,8 +65,8 @@ config VBOOT_RAMSTAGE_INDEX default 0x3 config BOOT_MEDIA_SPI_BUS - int - default 2 + int + default 2 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index bbf5e07..8376d89 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -1,7 +1,7 @@ if BOARD_HP_DL165_G6_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y + def_bool y select CPU_AMD_SOCKET_F_1207 select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 diff --git a/src/mainboard/supermicro/h8scm/Kconfig.name b/src/mainboard/supermicro/h8scm/Kconfig.name index d502234..4c5cbd9 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig.name +++ b/src/mainboard/supermicro/h8scm/Kconfig.name @@ -1,2 +1,2 @@ config BOARD_SUPERMICRO_H8SCM - bool "H8SCM" + bool "H8SCM" diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index 945ab09..354ca81 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -26,7 +26,7 @@ config IRQ_SLOT_COUNT default 6 config PLLMSRlo - hex - default 0x00de602e + hex + default 0x00de602e endif # BOARD_TRAVERSE_GEOS diff --git a/src/mainboard/tyan/s8226/Kconfig.name b/src/mainboard/tyan/s8226/Kconfig.name index 78de0d2..881e56f 100644 --- a/src/mainboard/tyan/s8226/Kconfig.name +++ b/src/mainboard/tyan/s8226/Kconfig.name @@ -1,2 +1,2 @@ config BOARD_TYAN_S8226 - bool "S8226" + bool "S8226" diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 37993aa..e094286 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -58,8 +58,8 @@ config RAMTOP default 0x400000 config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdfam10/bootblock.c" + string + default "northbridge/amd/amdfam10/bootblock.c" config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool @@ -112,9 +112,9 @@ endif config SVI_HIGH_FREQ bool default n - help - Select this for boards with a Voltage Regulator able to operate - at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. + help + Select this for boards with a Voltage Regulator able to operate + at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 65dc173..23fa390 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -58,8 +58,8 @@ config HW_MEM_HOLE_SIZE_AUTO_INC default n config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdk8/bootblock.c" + string + default "northbridge/amd/amdk8/bootblock.c" config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig index 9642416..04e9950 100644 --- a/src/northbridge/amd/cimx/rd890/Kconfig +++ b/src/northbridge/amd/cimx/rd890/Kconfig @@ -31,6 +31,6 @@ config REDIRECT_NBCIMX_TRACE_TO_SERIAL This Option allows you to redirect the AMD Northbridge CIMX Trace debug information to the serial console. - Warning: Only enable this option when debuging or tracing AMD CIMX code. + Warning: Only enable this option when debuging or tracing AMD CIMX code. endif # NORTHBRIDGE_AMD_CIMX_RD890 diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index d071334..62bd880 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -18,8 +18,8 @@ # config NORTHBRIDGE_AMD_PI - bool - default CPU_AMD_PI + bool + default CPU_AMD_PI select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI diff --git a/src/northbridge/intel/i855/Kconfig b/src/northbridge/intel/i855/Kconfig index 44becf6..25a1fd5 100644 --- a/src/northbridge/intel/i855/Kconfig +++ b/src/northbridge/intel/i855/Kconfig @@ -1,34 +1,34 @@ config NORTHBRIDGE_INTEL_I855 bool - select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT choice - prompt "Onboard graphics" - default I855_VIDEO_MB_8MB - depends on NORTHBRIDGE_INTEL_I855 + prompt "Onboard graphics" + default I855_VIDEO_MB_8MB + depends on NORTHBRIDGE_INTEL_I855 config I855_VIDEO_MB_OFF - bool "Disabled, 0KB" + bool "Disabled, 0KB" config I855_VIDEO_MB_1MB - bool "Enabled, 1MB" + bool "Enabled, 1MB" config I855_VIDEO_MB_4MB - bool "Enabled, 4MB" + bool "Enabled, 4MB" config I855_VIDEO_MB_8MB - bool "Enabled, 8MB" + bool "Enabled, 8MB" config I855_VIDEO_MB_16MB - bool "Enabled, 16MB" + bool "Enabled, 16MB" config I855_VIDEO_MB_32MB - bool "Enabled, 32MB" + bool "Enabled, 32MB" endchoice config VIDEO_MB - int - default 0 if I855_VIDEO_MB_OFF - default 1 if I855_VIDEO_MB_1MB - default 4 if I855_VIDEO_MB_4MB - default 8 if I855_VIDEO_MB_8MB - default 16 if I855_VIDEO_MB_16MB - default 32 if I855_VIDEO_MB_32MB - depends on NORTHBRIDGE_INTEL_I855 + int + default 0 if I855_VIDEO_MB_OFF + default 1 if I855_VIDEO_MB_1MB + default 4 if I855_VIDEO_MB_4MB + default 8 if I855_VIDEO_MB_8MB + default 16 if I855_VIDEO_MB_16MB + default 32 if I855_VIDEO_MB_32MB + depends on NORTHBRIDGE_INTEL_I855 diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index ac25e89..891a8e0 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -27,8 +27,8 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb800/bootblock.c" + string + default "southbridge/amd/cimx/sb800/bootblock.c" config ENABLE_IDE_COMBINED_MODE bool "Enable SATA IDE combined mode" @@ -72,15 +72,15 @@ config SB800_SATA_RAID endchoice config SB800_SATA_MODE - hex + hex depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) default "0x0" if SB800_SATA_IDE default "0x1" if SB800_SATA_RAID default "0x2" if SB800_SATA_AHCI config SB_SUPERIO_HWM - bool - default n + bool + default n if SB800_SATA_AHCI config AHCI_ROM_ID @@ -100,8 +100,8 @@ if SB800_SATA_RAID config RAID_ROM_ID string "RAID device PCI IDs" default "1002,4393" - help - 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode + help + 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode config RAID_ROM_FILE string "RAID ROM path and filename" @@ -109,8 +109,8 @@ config RAID_ROM_FILE default "site-local/sb800/raid.bin" config RAID_MISC_ROM_FILE - string "RAID Misc ROM path and filename" - default "site-local/sb800/misc.bin" + string "RAID Misc ROM path and filename" + default "site-local/sb800/misc.bin" depends on SB800_SATA_RAID config RAID_MISC_ROM_POSITION diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 3bef95a..be94c69 100644 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -29,30 +29,30 @@ config SATA_CONTROLLER_MODE hex default 0x0 help - 0x0 = Native IDE mode. - 0x1 = RAID mode. - 0x2 = AHCI mode. - 0x3 = Legacy IDE mode. - 0x4 = IDE->AHCI mode. - 0x5 = AHCI mode as 7804 ID (AMD driver). - 0x6 = IDE->AHCI mode as 7804 ID (AMD driver). + 0x0 = Native IDE mode. + 0x1 = RAID mode. + 0x2 = AHCI mode. + 0x3 = Legacy IDE mode. + 0x4 = IDE->AHCI mode. + 0x5 = AHCI mode as 7804 ID (AMD driver). + 0x6 = IDE->AHCI mode as 7804 ID (AMD driver). config PCIB_ENABLE bool default n help - n = Disable PCI Bridge Device 14 Function 4. - y = Enable PCI Bridge Device 14 Function 4. + n = Disable PCI Bridge Device 14 Function 4. + y = Enable PCI Bridge Device 14 Function 4. config ACPI_SCI_IRQ hex default 0x9 help - Set SCI IRQ to 9. + Set SCI IRQ to 9. config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb900/bootblock.c" + string + default "southbridge/amd/cimx/sb900/bootblock.c" endif #SOUTHBRIDGE_AMD_CIMX_SB900 diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 4d5fff4..1276bbb 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -52,7 +52,7 @@ config SATA_MODE default 0 if SATA_MODE_AHCI config HPET_MIN_TICKS - hex - default 0x14 + hex + default 0x14 endif diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 767193e..970605c 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -79,9 +79,9 @@ config BUILD_WITH_FAKE_IFD support this yet. But there is a patch pending [1]. WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. + was built with a fake IFD. It just won't work. - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html config IFD_BIOS_SECTION depends on BUILD_WITH_FAKE_IFD diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig index 9a535d7..9dd8a38 100644 --- a/src/southbridge/intel/i3100/Kconfig +++ b/src/southbridge/intel/i3100/Kconfig @@ -7,8 +7,8 @@ config SOUTHBRIDGE_INTEL_I3100 if SOUTHBRIDGE_INTEL_I3100 config HPET_MIN_TICKS - hex - default 0x90 + hex + default 0x90 endif diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index d8c73be..f845d1d 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -34,7 +34,7 @@ config EHCI_BAR default 0xfef00000 config BOOTBLOCK_SOUTHBRIDGE_INIT - string + string default "southbridge/intel/i82801gx/bootblock.c" config HPET_MIN_TICKS diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index d8a32e5..7428d00 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -40,7 +40,7 @@ config HPET_MIN_TICKS default 0x80 config BOOTBLOCK_SOUTHBRIDGE_INIT - string + string default "southbridge/intel/i82801ix/bootblock.c" endif diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 07a5ac2..b47bf99 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -69,9 +69,9 @@ config BUILD_WITH_FAKE_IFD support this yet. But there is a patch pending [1]. WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. + was built with a fake IFD. It just won't work. - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html config IFD_BIOS_SECTION diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 0f52011..4797e96 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -71,9 +71,9 @@ config BUILD_WITH_FAKE_IFD support this yet. But there is a patch pending [1]. WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. + was built with a fake IFD. It just won't work. - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html config IFD_BIOS_SECTION depends on BUILD_WITH_FAKE_IFD diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig index d320a53..1c0f6f0 100644 --- a/src/southbridge/intel/sch/Kconfig +++ b/src/southbridge/intel/sch/Kconfig @@ -47,8 +47,8 @@ config CMC_FILE binary. config HPET_MIN_TICKS - hex - default 0x80 + hex + default 0x80 endif

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coreboot-gerrit April 2015