coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 824e2c4 lib/tlcl: Provide mock implementation
by Patrick Georgi 27 Apr '15

27 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9983 -gerrit commit 824e2c4c7558cec99856b09e6a222ef44e678a8d Author: Yen Lin <yelin(a)nvidia.com> Date: Wed Apr 8 16:55:17 2015 -0700 lib/tlcl: Provide mock implementation It returns TPM_E_NO_DEVICE for all calls. BRANCH=None BUG=None TEST=manual MOCK_TPM=1 emerge-foster coreboot, and coreboot can boot to kernel Change-Id: Id7e79b58fabeac929b874385064b2417db49a708 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a9a91a65af115657e7317754eda931120750c56d Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Change-Id: I8dcf0db14cf2bc76c67a3bd7f06114e70e08764d Original-Reviewed-on: https://chromium-review.googlesource.com/264946 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/lib/Makefile.inc | 6 +++ src/lib/mocked_tlcl.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 142 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f0fb02874..78b16d9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -35,7 +35,13 @@ verstage-y += cbfs.c verstage-y += memcmp.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c + +ifeq ($(MOCK_TPM),1) +verstage-y += mocked_tlcl.c +else verstage-y += tlcl.c +endif + verstage-$(CONFIG_GENERIC_UDELAY) += timer.c verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c diff --git a/src/lib/mocked_tlcl.c b/src/lib/mocked_tlcl.c new file mode 100644 index 0000000..628afc2 --- /dev/null +++ b/src/lib/mocked_tlcl.c @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <tpm_lite/tlcl.h> + +#ifdef FOR_TEST +#include <stdio.h> +#define VBDEBUG(format, args...) printf(format, ## args) +#else +#include <console/console.h> +#define VBDEBUG(format, args...) printk(BIOS_DEBUG, format, ## args) +#endif + +uint32_t tlcl_lib_init(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_startup(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_resume(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_self_test_full(void) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_continue_self_test(void) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_write(uint32_t index, const void* data, uint32_t length) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + + +uint32_t tlcl_assert_physical_presence(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_physical_presence_cmd_enable(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_finalize_physical_presence(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_set_nv_locked(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_force_clear(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_set_enable(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_set_deactivated(uint8_t flag) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS* pflags) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, + uint8_t *nvlocked) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_set_global_lock(void) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_extend(int pcr_num, const uint8_t* in_digest, + uint8_t* out_digest) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +}

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Patch set updated for coreboot: bd92fe7 chromeec: ec_mec: Fix misaligned data access
by Patrick Georgi 27 Apr '15

27 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9987 -gerrit commit bd92fe79eebd04cdcd0d65a93c8e03b513543b3a Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Apr 21 09:30:10 2015 -0700 chromeec: ec_mec: Fix misaligned data access Long auto-increment access cannot be used when our initial address is misaligned or when our terminal address is misaligned on write operations. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on cyan. BRANCH=None Change-Id: Ieba0e8e05dabd44a28c63d5d56a2a634c2d349bf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a7237c8df027ae70a38478846ff3d5ce97543ff1 Original-Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Change-Id: Id709ca92cc386f9ea5b2a1139733961e1bc59354 Original-Reviewed-on: https://chromium-review.googlesource.com/266653 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/ec/google/chromeec/ec_mec.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/ec_mec.c b/src/ec/google/chromeec/ec_mec.c index 9836eda..264a256 100644 --- a/src/ec/google/chromeec/ec_mec.c +++ b/src/ec/google/chromeec/ec_mec.c @@ -76,12 +76,22 @@ void mec_io_bytes(int write, u16 port, unsigned int length, u8 *buf, u8 *csum) { int i = 0; int io_addr; + u8 access_mode, new_access_mode; if (length == 0) return; + /* + * Long access cannot be used on misaligned data since reading B0 loads + * the data register and writing B3 flushes it. + */ + if (port & 0x3) + access_mode = ACCESS_TYPE_BYTE; + else + access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT; + /* Initialize I/O at desired address */ - mec_emi_write_address(port, ACCESS_TYPE_LONG_AUTO_INCREMENT); + mec_emi_write_address(port, access_mode); /* Skip bytes in case of misaligned port */ io_addr = MEC_EMI_EC_DATA_B0 + (port & 0x3); @@ -94,11 +104,26 @@ void mec_io_bytes(int write, u16 port, unsigned int length, u8 *buf, u8 *csum) if (csum) *csum += buf[i]; + port++; /* Extra bounds check in case of misaligned length */ if (++i == length) return; } + /* + * Use long auto-increment access except for misaligned write, + * since writing B3 triggers the flush. + */ + if (length - i < 4 && write) + new_access_mode = ACCESS_TYPE_BYTE; + else + new_access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT; + if (new_access_mode != access_mode || + access_mode != ACCESS_TYPE_LONG_AUTO_INCREMENT) { + access_mode = new_access_mode; + mec_emi_write_address(port, access_mode); + } + /* Access [B0, B3] on each loop pass */ io_addr = MEC_EMI_EC_DATA_B0; }

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Patch set updated for coreboot: 1314bce storm: enable CBMEM console dump
by Patrick Georgi 27 Apr '15

27 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9986 -gerrit commit 1314bce33b2e04665913d28f66d35ed786d14c0e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Apr 10 19:23:16 2015 -0700 storm: enable CBMEM console dump This patch enables on storm the recently introduced 'console buffer dump on reboot' capability. BRANCH=none BUG=chromium:475347 TEST=generated storm image with serial console disabled and both rw firmware A and B sections corrupted. Programmed the new image on an SP5 device and rebooted it. Observed the device dump cbmem console buffer to the serial output, terminating with VB2:vb2_fail() Need recovery, reason: 0x3 / 0xa Reboot requested (1008000a) Saving nvdata SF: Detected S25FL128S_256K with page size 10000, total 2000000 and the LED ring started flashing indicating recovery mode. Change-Id: Idb50c86f59f393c783ccbc15de8f5564e2a1b38e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0ec88001b152bb9f1d7268b83367131b004816f8 Original-Change-Id: I9345eeb4d375f42fb1e4c617495b63b308ce51d9 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265295 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/storm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index d2c011b..dfa00cc 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_8192 select COMMON_CBFS_SPI_WRAPPER - select VBOOT_DISABLE_DEV_ON_RECOVERY + select CONSOLE_CBMEM_DUMP_TO_UART select DRIVERS_I2C_WW_RING select HAVE_HARD_RESET select MAINBOARD_HAS_BOOTBLOCK_INIT @@ -34,6 +34,7 @@ config BOARD_SPECIFIC_OPTIONS select SPI_FLASH select SPI_FLASH_SPANSION select SPI_FLASH_STMICRO + select VBOOT_DISABLE_DEV_ON_RECOVERY select VIRTUAL_DEV_SWITCH select WIPEOUT_SUPPORTED

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Patch set updated for coreboot: 8a4a9c4 Cygnus: add TrustZone functions and set everything non-secure in bootblock
by Patrick Georgi 27 Apr '15

27 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9985 -gerrit commit 8a4a9c45916aa692e0440540e2b7b1654cba6a1f Author: Corneliu Doban <cdoban(a)broadcom.com> Date: Fri Apr 10 15:51:55 2015 -0700 Cygnus: add TrustZone functions and set everything non-secure in bootblock To allow an OS to run in non-secure mode: - Set all peripherals and system components non-secure except SOTP and TZPC. - Set all memory non-secure (ROM, SRAM, DDR, flash). - Enable A9 access to entire M0 address space except M0 ROM. BUG=chrome-os-partner:37533 BRANCH=broadcom-firmware TEST=boot kernel from usb stick Change-Id: I3bbd288863923011ff1413be353ac4b178ffdd07 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6de56bbe73ed8d87ad572da711a193985ee68e3a Original-Signed-off-by: Corneliu Doban <cdoban(a)broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212735 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)google.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)google.com> Original-Tested-by: Daisuke Nojiri <dnojiri(a)google.com> Original-Change-Id: Ibac7de03a72a98fbd95659d0113833049b4871a5 Original-Reviewed-on: https://chromium-review.googlesource.com/266593 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/soc/broadcom/cygnus/Makefile.inc | 1 + src/soc/broadcom/cygnus/hw_init.c | 228 +++++++++++++----------- src/soc/broadcom/cygnus/include/soc/tz.h | 226 ++++++++++++++++++++++++ src/soc/broadcom/cygnus/tz.c | 287 +++++++++++++++++++++++++++++++ 4 files changed, 643 insertions(+), 99 deletions(-) diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc index edeb687..4e09bed 100644 --- a/src/soc/broadcom/cygnus/Makefile.inc +++ b/src/soc/broadcom/cygnus/Makefile.inc @@ -21,6 +21,7 @@ bootblock-y += bootblock.c bootblock-y += cbmem.c bootblock-y += i2c.c bootblock-y += timer.c +bootblock-y += tz.c bootblock-y += hw_init.c bootblock-$(CONFIG_SPI_FLASH) += spi.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) diff --git a/src/soc/broadcom/cygnus/hw_init.c b/src/soc/broadcom/cygnus/hw_init.c index 12adf66..610ec6c 100644 --- a/src/soc/broadcom/cygnus/hw_init.c +++ b/src/soc/broadcom/cygnus/hw_init.c @@ -18,75 +18,139 @@ #include <arch/io.h> #include <delay.h> #include <console/console.h> +#include <soc/tz.h> #include <soc/hw_init.h> /***************************************************************************** * TrustZone *****************************************************************************/ -#define TZPC_TZPCDECPROT0SET 0x18034804 -#define TZPC_TZPCDECPROT0CLR 0x18034808 -#define TZPC_TZPCDECPROT1SET 0x18034810 -#define TZPC_TZPCDECPROT1CLR 0x18034814 -#define TZPC_TZPCDECPROT2SET 0x1803481c -#define TZPC_TZPCDECPROT2CLR 0x18034820 - -#define TZPCDECPROT0_MASK 0x000000FF -#define TZPCDECPROT1_MASK 0x000000FF -#define TZPCDECPROT2_MASK 0x000000FF - -#define TZ_STATE_SECURE 0 -#define TZ_STATE_NON_SECURE 1 - -#define CYGNUS_M_PCIE0_M0 0x00000003 -#define CYGNUS_M_PCIE1_M0 0x0000000c -#define CYGNUS_M_CMICD_M0 0x00000030 -#define CYGNUS_M_EXT_M0 0x000000c0 - -#define CYGNUS_M_EXT_M1 (0x00000003 << 8) -#define CYGNUS_M_SDIO_M0 (0x0000000c << 8) -#define CYGNUS_M_SDIO_M1 (0x00000030 << 8) -#define CYGNUS_M_AMAC_M0 (0x000000c0 << 8) - -#define CYGNUS_M_AMAC_M1 (0x00000003 << 16) -#define CYGNUS_M_USB2H_M0 (0x0000000c << 16) -#define CYGNUS_M_USB2D_M0 (0x00000030 << 16) -#define CYGNUS_M_A9JTAG_M0 (0x000000c0 << 16) - -#define IPROC_M_PCIE (CYGNUS_M_PCIE0_M0 | CYGNUS_M_PCIE1_M0) -#define IPROC_M_EXT (CYGNUS_M_EXT_M0 | CYGNUS_M_EXT_M1) -#define IPROC_M_SDIO (CYGNUS_M_SDIO_M0 | CYGNUS_M_SDIO_M1) -#define IPROC_M_AMAC (CYGNUS_M_AMAC_M0 | CYGNUS_M_AMAC_M1) -#define IPROC_M_USB (CYGNUS_M_USB2H_M0 | CYGNUS_M_USB2D_M0) -#define IPROC_M_CMICD (CYGNUS_M_CMICD_M0) - -static void tz_set_masters_security(uint32_t masters, uint32_t ns_bit) +#define IHOST_SCU_SECURE_ACCESS 0x19020054 + +#define SMAU_NIC_IDM_TZ_BASE 0x180150a0 +#define SMAU_DDR_TZ_BASE 0x18015200 +#define SMAU_FLASH0_TZ_BASE 0x18015300 +#define SMAU_FLASH1_TZ_BASE 0x18015308 +#define SMAU_FLASH2_TZ_BASE 0x18015310 +#define SMAU_FLASH3_TZ_BASE 0x18015318 +#define SMAU_TZ_BASE_ENABLE 0x00000001 + +#define CRMU_IPROC_ADDR_RANGE0_LOW 0x03024c30 +#define CRMU_IPROC_ADDR_RANGE0_HIGH 0x03024c34 +#define CRMU_ADDR_MASK 0xffffff00 +#define CRMU_ADDR_VALID 0x00000001 +#define CRMU_ADDR_START 0x03010000 +#define CRMU_ADDR_END 0x03100000 + +static void scu_ns_config(void) { - uint32_t val = 0; - - /* Check any TZPCDECPROT0 is set and then write to TZPCDECPROT0 */ - if (masters & TZPCDECPROT0_MASK) { - val = masters & TZPCDECPROT0_MASK; - if (ns_bit) - write32((void *)TZPC_TZPCDECPROT0SET, val); - else - write32((void *)TZPC_TZPCDECPROT0CLR, val); - } - /* Check any TZPCDECPROT1 is set and then write to TZPCDECPROT1 */ - if ((masters >> 8) & TZPCDECPROT1_MASK) { - val = (masters >> 8) & TZPCDECPROT1_MASK; - if (ns_bit) - write32((void *)TZPC_TZPCDECPROT1SET, val); - else - write32((void *)TZPC_TZPCDECPROT1CLR, val); - } - /* Check any TZPCDECPROT2 is set and then write to TZPCDECPROT2 */ - if ((masters >> 16) & TZPCDECPROT2_MASK) { - val = (masters >> 16) & TZPCDECPROT2_MASK; - if (ns_bit) - write32((void *)TZPC_TZPCDECPROT2SET, val); - else - write32((void *)TZPC_TZPCDECPROT2CLR, val); - } + /* + * Enable NS SCU access to ARM global timer, private timer, and + * components + */ + write32((void *)IHOST_SCU_SECURE_ACCESS, 0xFFF); +} + +static void smau_ns_config(void) +{ + unsigned int val; + + /* Disable SMAU NIC IDM TZ */ + val = read32((void *)SMAU_NIC_IDM_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_NIC_IDM_TZ_BASE, val); + + /* + * Disable DDR TZ base + * + * This means the entire DDR is marked as NONSECURE (NS) + * + * NOTE: In the future, multiple regions of DDR may need to be marked + * as SECURE for secure OS and other TZ usages + */ + val = read32((void *)SMAU_DDR_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_DDR_TZ_BASE, val); + + + /* + * Disable flash TZ support + * + * The entire flash is currently marked as NS + * + * NOTE: In the future, multiple regions of flash may need to be marked + * as SECURE for secure OS and other TZ firmware/data storage + */ + + /* Flash 0: ROM */ + val = read32((void *)SMAU_FLASH0_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_FLASH0_TZ_BASE, val); + + /* Flash 1: QSPI */ + val = read32((void *)SMAU_FLASH1_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_FLASH1_TZ_BASE, val); + + /* Flash 2: NAND */ + val = read32((void *)SMAU_FLASH2_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_FLASH2_TZ_BASE, val); + + /* Flash 3: PNOR */ + val = read32((void *)SMAU_FLASH3_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_FLASH3_TZ_BASE, val); +} + +static void crmu_ns_config(void) +{ + + /* + * Currently opens up the entire CRMU to allow iPROC NS access + * + * NOTE: In the future, we might want to protect particular CRMU + * sub-blocks to allow SECURE access only. That can be done by + * programing the CRMU IPROC address range registers. Up to 4 access + * windows can be created + */ + write32((void *)CRMU_IPROC_ADDR_RANGE0_LOW, + (CRMU_ADDR_START & CRMU_ADDR_MASK) | CRMU_ADDR_VALID); + write32((void *)CRMU_IPROC_ADDR_RANGE0_HIGH, + (CRMU_ADDR_END & CRMU_ADDR_MASK) | CRMU_ADDR_VALID); +} + +static void tz_init(void) +{ + /* Configure the Cygnus for non-secure access */ + /* ARM Cortex A9 SCU NS access configuration */ + scu_ns_config(); + + /* SMAU NS related configurations */ + smau_ns_config(); + + /* CRMU NS related configurations */ + crmu_ns_config(); + + /* + * Configure multiple masters and slaves to run in NS + */ + tz_set_non_virtual_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE); + tz_set_periph_security(0xFFFFFFFF, TZ_STATE_NON_SECURE); + tz_set_masters_security(0xFFFFFFFF, TZ_STATE_NON_SECURE); + tz_set_wrapper_security(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + TZ_STATE_NON_SECURE); + tz_set_cfg_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE); + + tz_set_ext_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE); + + /* configure sec peripherals to be accessed from non-secure world */ + tz_set_sec_periphs_security(0xFFFFFFFF & + ~(CYGNUS_sec_periph_APBz_sotp | + CYGNUS_sec_periph_APBz_tzpc), + TZ_STATE_NON_SECURE); + + /* default sram to non-secure */ + tz_set_sram_sec_region(0); } /***************************************************************************** @@ -350,10 +414,6 @@ static void ccu_init(void) /***************************************************************************** * LCD *****************************************************************************/ -#define ASIU_TOP_LCD_AXI_SB_CTRL 0x180aa02c -#define ASIU_TOP_LCD_AXI_SB_CTRL_LCD_ARPROT_MASK 0x03800000 -#define ASIU_TOP_LCD_AXI_SB_CTRL_LCD_HPROT_NON_SECURE 0x40000000 - #define ASIU_TOP_CLK_GATING_CTRL 0x180aa024 #define ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN 0x00000010 #define ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN 0x00000008 @@ -364,12 +424,6 @@ static void lcd_init(void) { unsigned int val; - val = read32((void *)ASIU_TOP_LCD_AXI_SB_CTRL); - /* set LCD_ARPROT and LCD_HPROT_NON_SECURE to 0 */ - val &= ~(ASIU_TOP_LCD_AXI_SB_CTRL_LCD_ARPROT_MASK | - ASIU_TOP_LCD_AXI_SB_CTRL_LCD_HPROT_NON_SECURE); - write32((void *)ASIU_TOP_LCD_AXI_SB_CTRL, val); - /* make sure the LCD clock is ungated */ val = read32((void *)ASIU_TOP_CLK_GATING_CTRL); val |= ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN; @@ -423,22 +477,10 @@ static void lcd_qos_init(unsigned int qos) /***************************************************************************** * V3D *****************************************************************************/ -#define ASIU_TOP_GFX_AXI_SB_CTRL 0x180aa034 -#define ASIU_TOP_GFX_AXI_SB_CTRL_GFX_ARPROT_MASK 0x03800000 -#define ASIU_TOP_GFX_AXI_SB_CTRL_GFX_AWPROT_MASK 0x00700000 - static void v3d_init(void) { unsigned int val; - val = read32((void *)ASIU_TOP_GFX_AXI_SB_CTRL); - /* - * set both GFX_ARPROT and GFX_AWPROT to 0 - */ - val &= ~(ASIU_TOP_GFX_AXI_SB_CTRL_GFX_ARPROT_MASK | - ASIU_TOP_GFX_AXI_SB_CTRL_GFX_AWPROT_MASK); - write32((void *)ASIU_TOP_GFX_AXI_SB_CTRL, val); - /* make sure the V3D clock is ungated */ val = read32((void *)ASIU_TOP_CLK_GATING_CTRL); val |= ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN | @@ -455,10 +497,6 @@ static void v3d_init(void) #define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_LDO 0x00000200 #define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN 0x00000100 -#define ASIU_TOP_AUD_AXI_SB_CTRL 0x180aa028 -#define ASIU_TOP_AUD_AXI_SB_CTRL_AUD_ARPROT_MASK 0x03800000 -#define ASIU_TOP_AUD_AXI_SB_CTRL_AUD_AWPROT_MASK 0x00700000 - static void audio_init(void) { unsigned int val; @@ -475,12 +513,6 @@ static void audio_init(void) val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_PLL; val &= ~CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN; write32((void *)CRMU_PLL_AON_CTRL, val); - - /* Clear AWPROT and ARPROT signals to audio block. */ - val = read32((void *)ASIU_TOP_AUD_AXI_SB_CTRL); - val &= ~(ASIU_TOP_AUD_AXI_SB_CTRL_AUD_AWPROT_MASK | - ASIU_TOP_AUD_AXI_SB_CTRL_AUD_ARPROT_MASK); - write32((void *)ASIU_TOP_AUD_AXI_SB_CTRL, val); } /***************************************************************************** @@ -707,12 +739,10 @@ static void sdio_init(void) void hw_init(void) { - tz_set_masters_security(IPROC_M_PCIE | IPROC_M_EXT | IPROC_M_SDIO | - IPROC_M_AMAC | IPROC_M_USB | IPROC_M_CMICD, - TZ_STATE_SECURE); + tz_init(); printk(BIOS_INFO, "trustzone initialized\n"); dmac_init(); - printk(BIOS_INFO, "PL022 DMAC initialized\n"); + printk(BIOS_INFO, "PL330 DMAC initialized\n"); lcd_init(); lcd_qos_init(15); printk(BIOS_INFO, "LCD initialized\n"); diff --git a/src/soc/broadcom/cygnus/include/soc/tz.h b/src/soc/broadcom/cygnus/include/soc/tz.h new file mode 100644 index 0000000..cb9ae63 --- /dev/null +++ b/src/soc/broadcom/cygnus/include/soc/tz.h @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2015 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_BROADCOM_CYGNUS_TZ_H__ +#define __SOC_BROADCOM_CYGNUS_TZ_H__ + +#define TZ_STATE_SECURE 0 +#define TZ_STATE_NON_SECURE 1 + +/* + * Masters (for parameter masters in "tz_set_masters_security") + */ +#define CYGNUS_M_Pcie0_m0 0x00000003 +#define CYGNUS_M_Pcie1_m0 0x0000000c +#define CYGNUS_M_cmicd_m0 0x00000030 +#define CYGNUS_M_ext_m0 0x000000c0 + +#define CYGNUS_M_ext_m1 (0x00000003 << 8) +#define CYGNUS_M_sdio_m0 (0x0000000c << 8) +#define CYGNUS_M_sdio_m1 (0x00000030 << 8) +#define CYGNUS_M_amac_m0 (0x000000c0 << 8) + +#define CYGNUS_M_amac_m1 (0x00000003 << 16) +#define CYGNUS_M_usb2h_m0 (0x0000000c << 16) +#define CYGNUS_M_usb2d_m0 (0x00000030 << 16) +#define CYGNUS_M_a9jtag_m0 (0x000000c0 << 16) + +/* + * Non virtual slaves (for parameter slave_vector in "tz_set_non_virtual_slaves_security") + * Note: the order has to match the order in non_virtual_slave_regs[] array from tz.c + */ +#define CYGNUS_S_Ihost_acp (0x1 << 0) +#define CYGNUS_S_PCIe0_s0 (0x1 << 1) +#define CYGNUS_S_PCIe1_s0 (0x1 << 2) +#define CYGNUS_S_ihost_s0 (0x1 << 3) +#define CYGNUS_S_A9jtag_s0 (0x1 << 4) +#define CYGNUS_S_CMICd_s0 (0x1 << 5) +#define CYGNUS_S_mhost0_s0 (0x1 << 6) +#define CYGNUS_S_mhost1_s0 (0x1 << 7) +#define CYGNUS_S_Crypto_s0 (0x1 << 8) +#define CYGNUS_S_DMU_s0 (0x1 << 9) + +/* + * Peripherals (for parameter slave_vector in "tz_set_periph_security") + */ +#define CYGNUS_periph_APBx_DMU 0x00008000 +#define CYGNUS_periph_APBx_cru 0x00004000 +#define CYGNUS_periph_APBx_ccg_smbus1 0x00000800 +#define CYGNUS_periph_APBx_ccg_gpio 0x00000400 +#define CYGNUS_periph_APBx_ccg_watchdog 0x00000200 +#define CYGNUS_periph_APBx_ccg_smbus0 0x00000100 +#define CYGNUS_periph_APBx_ccg_srab 0x00000080 +#define CYGNUS_periph_APBx_ccg_timer3 0x00000040 +#define CYGNUS_periph_APBx_ccg_timer2 0x00000020 +#define CYGNUS_periph_APBx_ccg_timer1 0x00000010 +#define CYGNUS_periph_APBx_ccg_timer0 0x00000008 +#define CYGNUS_periph_APBx_ccg_mdio 0x00000004 +#define CYGNUS_periph_APBx_ccg_pwm 0x00000002 +#define CYGNUS_periph_APBx_icfg 0x00000001 + +#define CYGNUS_periph_APBy_ccg_spi5 (0x00002000 << 16) +#define CYGNUS_periph_APBy_ccg_spi4 (0x00001000 << 16) +#define CYGNUS_periph_APBy_ccg_spi3 (0x00000800 << 16) +#define CYGNUS_periph_APBy_ccg_spi2 (0x00000400 << 16) +#define CYGNUS_periph_APBy_ccg_spi1 (0x00000200 << 16) +#define CYGNUS_periph_APBy_ccg_spi0 (0x00000100 << 16) +#define CYGNUS_periph_APBy_ccg_uart4 (0x00000010 << 16) +#define CYGNUS_periph_APBy_ccg_uart3 (0x00000008 << 16) +#define CYGNUS_periph_APBy_ccg_uart2 (0x00000004 << 16) +#define CYGNUS_periph_APBy_ccg_uart1 (0x00000002 << 16) +#define CYGNUS_periph_APBy_ccg_uart0 (0x00000001 << 16) + +/* + * Sececure Peripherals (for parameter slave_vector in "tz_set_sec_periphs_security") + */ +#define CYGNUS_sec_periph_APBz_sotp 0x00000020 +#define CYGNUS_sec_periph_APBz_tzpc 0x00000010 +#define CYGNUS_sec_periph_APBz_ccg_wdog 0x00000008 +#define CYGNUS_sec_periph_APBz_ccs_rng 0x00000004 +#define CYGNUS_sec_periph_APBz_ccs_pka 0x00000002 +#define CYGNUS_sec_periph_APBz_ccs_gpio 0x00000001 + +/* + * Cfg Slaves (for parameter slave_vector in "tz_set_cfg_slaves_security") + */ +#define CYGNUS_cfg_slv_APBr_mhost0 0x00004000 +#define CYGNUS_cfg_slv_APBr_dma_s1 0x00000200 +#define CYGNUS_cfg_slv_APBr_dma_s0 0x00000100 +#define CYGNUS_cfg_slv_APBr_acpal 0x00000040 +#define CYGNUS_cfg_slv_APBr_smau 0x00000020 +#define CYGNUS_cfg_slv_APBr_pcie1 0x00000008 +#define CYGNUS_cfg_slv_APBr_pcie0 0x00000004 +#define CYGNUS_cfg_slv_APBr_ddr 0x00000001 + +#define CYGNUS_cfg_slv_APBs_sram (0x00004000 << 16) +#define CYGNUS_cfg_slv_APBs_usb2d (0x00001000 << 16) +#define CYGNUS_cfg_slv_APBs_amac1 (0x00000400 << 16) +#define CYGNUS_cfg_slv_APBs_usb2h_apb2 (0x00000200 << 16) +#define CYGNUS_cfg_slv_APBs_usb2h_apb1 (0x00000100 << 16) +#define CYGNUS_cfg_slv_APBs_qspi (0x00000080 << 16) +#define CYGNUS_cfg_slv_APBs_nand (0x00000040 << 16) +#define CYGNUS_cfg_slv_APBs_nor (0x00000020 << 16) +#define CYGNUS_cfg_slv_APBs_sdio1 (0x00000008 << 16) +#define CYGNUS_cfg_slv_APBs_amac0 (0x00000004 << 16) +#define CYGNUS_cfg_slv_APBs_sdio0 (0x00000002 << 16) + +/* + * Wrapper1 (for parameter wrapper1 in "tz_set_wrapper_security") + */ +#define CYGNUS_APB_W1_wrp_master_ihost_m0 0x00000001 +#define CYGNUS_APB_W1_wrp_master_pcie0_m0 0x00000002 +#define CYGNUS_APB_W1_wrp_master_pcie1_m0 0x00000004 +#define CYGNUS_APB_W1_wrp_master_cmicd_m0 0x00000008 +#define CYGNUS_APB_W1_wrp_master_mhost0_m0 0x00000010 +#define CYGNUS_APB_W1_wrp_master_mhost1_m0 0x00000020 +#define CYGNUS_APB_W1_wrp_slave_ihost_acp 0x00000040 +#define CYGNUS_APB_W1_wrp_slave_ihost_s0 0x00000080 +#define CYGNUS_APB_W1_wrp_slave_pcie0_s0 0x00000100 +#define CYGNUS_APB_W1_wrp_slave_pcie1_s0 0x00000200 +#define CYGNUS_APB_W1_wrp_slave_cmicd_s0 0x00000400 +#define CYGNUS_APB_W1_wrp_slave_smau_s0 0x00000800 +#define CYGNUS_APB_W1_wrp_slave_mhost0_s0 0x00001000 +#define CYGNUS_APB_W1_wrp_slave_mhost1_s0 0x00002000 +#define CYGNUS_APB_W1_wrp_slave_apbr 0x00004000 +#define CYGNUS_APB_W1_wrp_master_dma_m0 0x00008000 + +/* + * Wrapper2 (for parameter wrapper2 in "tz_set_wrapper_security") + */ +#define CYGNUS_APB_W2_wrp_ds_ds_2 0x00000008 +#define CYGNUS_APB_W2_sdrom 0x00000004 +#define CYGNUS_APB_W2_wrp_ds_ds_1 0x00000002 +#define CYGNUS_APB_W2_wrp_ds_ds_0 0x00000001 + +/* + * Wrapper3 (for parameter wrapper3 in "tz_set_wrapper_security") + */ +#define CYGNUS_APB_W3_wrp_master_amac_m1 0x00002000 +#define CYGNUS_APB_W3_wrp_ds_ds_3 0x00001000 +#define CYGNUS_APB_W3_wrp_slave_apbs 0x00000800 +#define CYGNUS_APB_W3_wrp_slave_sram_s0 0x00000400 +#define CYGNUS_APB_W3_wrp_master_sdio_m1 0x00000200 +#define CYGNUS_APB_W3_wrp_slave_a9jtag_s0 0x00000100 +#define CYGNUS_APB_W3_wrp_slave_crypto_s0 0x00000080 +#define CYGNUS_APB_W3_wrp_master_usb2h_m0 0x00000040 +#define CYGNUS_APB_W3_wrp_master_a9jtag_m0 0x00000020 +#define CYGNUS_APB_W3_wrp_master_ext_m1 0x00000010 +#define CYGNUS_APB_W3_wrp_master_sdio_m0 0x00000008 +#define CYGNUS_APB_W3_wrp_master_ext_m0 0x00000004 +#define CYGNUS_APB_W3_wrp_master_usb2d_m0 0x00000002 +#define CYGNUS_APB_W3_wrp_master_amac_m0 0x00000001 + +/* + * Wrapper4 (for parameter wrapper4 in "tz_set_wrapper_security") + */ +#define CYGNUS_APB_W4_wrp_slave_ext_s1 0x00000040 +#define CYGNUS_APB_W4_wrp_slave_dmu_s0 0x00000020 +#define CYGNUS_APB_W4_wrp_slave_ext_s0 0x00000010 +#define CYGNUS_APB_W4_wrp_master_dmu_m0 0x00000008 +#define CYGNUS_APB_W4_wrp_slave_apbz 0x00000004 +#define CYGNUS_APB_W4_wrp_slave_apby 0x00000002 +#define CYGNUS_APB_W4_wrp_slave_apbx 0x00000001 + +/* + * Ext Slaves (for parameter slave_vector in "tz_set_ext_slaves_security") + */ +#define CYGNUS_AXIIC_ext_s0_slave_0 0x00000001 /* LCD */ +#define CYGNUS_AXIIC_ext_s0_slave_1 0x00000002 /* Camera */ +#define CYGNUS_AXIIC_ext_s0_slave_2 0x00000004 +#define CYGNUS_AXIIC_ext_s0_slave_3 0x00000008 /* Smartcard */ +#define CYGNUS_AXIIC_ext_s0_slave_4 0x00000010 /* S-GPIO */ +#define CYGNUS_AXIIC_ext_s0_slave_5 0x00000020 /* GPIO */ +#define CYGNUS_AXIIC_ext_s0_slave_6 0x00000040 /* ADC_APB */ +#define CYGNUS_AXIIC_ext_s0_slave_7 0x00000080 +#define CYGNUS_AXIIC_ext_s0_slave_8 0x00000100 /* GFX_S0 */ +#define CYGNUS_AXIIC_ext_s0_slave_9 0x00000200 /* MIPI */ +#define CYGNUS_AXIIC_ext_s0_slave_10 0x00000400 /* ASIU_TOP */ +#define CYGNUS_AXIIC_ext_s0_slave_11 0x00000800 /* D1W */ +#define CYGNUS_AXIIC_ext_s0_slave_12 0x00001000 /* Keypad */ +#define CYGNUS_AXIIC_ext_s0_slave_13 0x00002000 /* Keypad */ +#define CYGNUS_AXIIC_ext_s0_slave_14 0x00004000 /* Audio */ +#define CYGNUS_AXIIC_ext_s0_slave_15 0x00008000 + +#define CYGNUS_AXIIC_ext_s1_slave_0 (0x00000001 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_1 (0x00000002 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_2 (0x00000004 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_3 (0x00000008 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_4 (0x00000010 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_5 (0x00000020 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_6 (0x00000040 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_7 (0x00000080 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_8 (0x00000100 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_9 (0x00000200 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_10 (0x00000400 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_11 (0x00000800 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_12 (0x00001000 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_13 (0x00002000 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_14 (0x00004000 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_15 (0x00008000 << 16) + +void tz_set_masters_security(uint32_t masters, uint32_t ns_bit); +void tz_set_wrapper_security(uint32_t wrapper1, uint32_t wrapper2, + uint32_t wrapper3, uint32_t wrapper4, + uint32_t ns_bit); +void tz_set_cfg_slaves_security(uint32_t slave_vector, uint32_t ns_bit); +void tz_set_sec_periphs_security(uint32_t slave_vector, uint32_t ns_bit); +void tz_set_periph_security(uint32_t slave_vector, uint32_t ns_bit); +void tz_set_non_virtual_slaves_security(uint32_t slave_vector, uint32_t ns_bit); +void tz_set_sram_sec_region(uint32_t r0size); +void tz_set_ext_slaves_security(uint32_t slave_vector, uint32_t ns_bit); + +#endif diff --git a/src/soc/broadcom/cygnus/tz.c b/src/soc/broadcom/cygnus/tz.c new file mode 100644 index 0000000..e35669b --- /dev/null +++ b/src/soc/broadcom/cygnus/tz.c @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2015 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/tz.h> + +#define TZPC_TZPCR0SIZE 0x18034000 +#define TZPC_TZPCR0SIZE_MASK 0x000003ff + +#define TZPC_TZPCDECPROT0SET 0x18034804 +#define TZPC_TZPCDECPROT0CLR 0x18034808 +#define TZPC_TZPCDECPROT1SET 0x18034810 +#define TZPC_TZPCDECPROT1CLR 0x18034814 +#define TZPC_TZPCDECPROT2SET 0x1803481c +#define TZPC_TZPCDECPROT2CLR 0x18034820 + +#define TZPCDECPROT0_MASK 0x000000FF +#define TZPCDECPROT1_MASK 0x000000FF +#define TZPCDECPROT2_MASK 0x000000FF + +#define AXIIC_Ihost_acp_security 0x1a000008 +#define AXIIC_PCIe0_s0_security 0x1a000010 +#define AXIIC_PCIe1_s0_security 0x1a000014 +#define AXIIC_APBY_s0_security 0x1a00002c +#define AXIIC_APBZ_s0_security 0x1a000030 +#define AXIIC_APBX_s0_security 0x1a000034 +#define AXIIC_ihost_s0_security 0x1a000038 +#define AXIIC_A9jtag_s0_security 0x1a00003c +#define AXIIC_APB_W1_security 0x1a000040 +#define AXIIC_APB_W2_security 0x1a000044 +#define AXIIC_APB_W3_security 0x1a000048 +#define AXIIC_APB_W4_security 0x1a00004c +#define AXIIC_APBR_s0_security 0x1a00006c +#define AXIIC_APBS_s0_security 0x1a000070 +#define AXIIC_CMICd_s0_security 0x1a000074 +#define AXIIC_mhost0_s0_security 0x1a000078 +#define AXIIC_mhost1_s0_security 0x1a00007c +#define AXIIC_Crypto_s0_security 0x1a000080 +#define AXIIC_DMU_s0_security 0x1a000084 +#define AXIIC_ext_s0_security 0x1a000088 +#define AXIIC_ext_s1_security 0x1a00008c + +#define AXIIC_APBY_s0_security_MASK 0x00003f1f +#define AXIIC_APBZ_s0_security_MASK 0x0000003f +#define AXIIC_APBX_s0_security_MASK 0x0000cfff +#define AXIIC_ext_s0_security_MASK 0xffffffff +#define AXIIC_ext_s1_security_MASK 0xffffffff +#define AXIIC_APBR_s0_security_MASK 0x0000436d +#define AXIIC_APBS_s0_security_MASK 0x000057ee +#define AXIIC_APB_W1_security_MASK 0x0000ffff +#define AXIIC_APB_W2_security_MASK 0x0000000f +#define AXIIC_APB_W3_security_MASK 0x00003fff +#define AXIIC_APB_W4_security_MASK 0x0000007f + +/* + * Note: the order need to match corresponding definitions for + * non virtual slave slave_vector in tz.h + */ +static uint32_t non_virtual_slave_regs[] = { + AXIIC_Ihost_acp_security, + AXIIC_PCIe0_s0_security, + AXIIC_PCIe1_s0_security, + AXIIC_ihost_s0_security, + AXIIC_A9jtag_s0_security, + AXIIC_CMICd_s0_security, + AXIIC_mhost0_s0_security, + AXIIC_mhost1_s0_security, + AXIIC_Crypto_s0_security, + AXIIC_DMU_s0_security +}; + +/* + * Set master security. + * Use defines in tz.h for both parameters. + */ +void tz_set_masters_security(uint32_t masters, uint32_t ns_bit) +{ + uint32_t val; + + /* Check any TZPCDECPROT0 is set and then write to TZPCDECPROT0 */ + if (masters & TZPCDECPROT0_MASK) { + val = masters & TZPCDECPROT0_MASK; + if (ns_bit) + write32((void *)TZPC_TZPCDECPROT0SET, val); + else + write32((void *)TZPC_TZPCDECPROT0CLR, val); + } + /* Check any TZPCDECPROT1 is set and then write to TZPCDECPROT1 */ + if ((masters >> 8) & TZPCDECPROT1_MASK) { + val = (masters >> 8) & TZPCDECPROT1_MASK; + if (ns_bit) + write32((void *)TZPC_TZPCDECPROT1SET, val); + else + write32((void *)TZPC_TZPCDECPROT1CLR, val); + } + /* Check any TZPCDECPROT2 is set and then write to TZPCDECPROT2 */ + if ((masters >> 16) & TZPCDECPROT2_MASK) { + val = (masters >> 16) & TZPCDECPROT2_MASK; + if (ns_bit) + write32((void *)TZPC_TZPCDECPROT2SET, val); + else + write32((void *)TZPC_TZPCDECPROT2CLR, val); + } +} + +/* + * Set non virtual slave security. + * Use defines in tz.h for both parameters. + */ +void tz_set_non_virtual_slaves_security(uint32_t slave_vector, uint32_t ns_bit) +{ + uint32_t i; + uint32_t total = sizeof(non_virtual_slave_regs) / + sizeof(non_virtual_slave_regs[0]); + uint32_t mask = ~(0xffffffff << total); + + ns_bit &= 0x1; + slave_vector = slave_vector & mask; + for (i = 0; i < total; i++) { + if (slave_vector & (0x1 << i)) + write32((void *)(non_virtual_slave_regs[i]), ns_bit); + } +} + +/* + * Set peripheral security. + * Use defines in tz.h for both parameters. + */ +void tz_set_periph_security(uint32_t slave_vector, uint32_t ns_bit) +{ + uint32_t val; + uint32_t mask_x = AXIIC_APBX_s0_security_MASK; + uint32_t mask_y = AXIIC_APBY_s0_security_MASK; + uint32_t tz_periphs_sec_status = + (mask_x & read32((void *)AXIIC_APBX_s0_security)) | + ((mask_y & read32((void *)AXIIC_APBY_s0_security)) << 16); + + if (ns_bit == TZ_STATE_SECURE) + tz_periphs_sec_status &= ~slave_vector; + else + tz_periphs_sec_status |= slave_vector; + + val = tz_periphs_sec_status & mask_x; + write32((void *)AXIIC_APBX_s0_security, val); + + val = (tz_periphs_sec_status >> 16) & mask_y; + write32((void *)AXIIC_APBY_s0_security, val); +} + +/* + * Set sec peripheral security. + * Use defines in tz.h for both parameters. + */ +void tz_set_sec_periphs_security(uint32_t slave_vector, uint32_t ns_bit) +{ + uint32_t val; + uint32_t mask = AXIIC_APBZ_s0_security_MASK; + uint32_t tz_sec_periphs_sec_status = + read32((void *)AXIIC_APBZ_s0_security); + + if (ns_bit == TZ_STATE_SECURE) + tz_sec_periphs_sec_status &= ~slave_vector; + else + tz_sec_periphs_sec_status |= slave_vector; + + val = tz_sec_periphs_sec_status & mask; + write32((void *)AXIIC_APBZ_s0_security, val); +} + +/* + * Set external slave security. + * Use defines in tz.h for both parameters. + */ +void tz_set_ext_slaves_security(uint32_t slave_vector, uint32_t ns_bit) +{ + uint32_t val; + uint32_t mask_s0 = AXIIC_ext_s0_security_MASK; + uint32_t mask_s1 = AXIIC_ext_s1_security_MASK; + uint32_t tz_ext_slaves_sec_status = + (mask_s0 & read32((void *)AXIIC_ext_s0_security)) | + ((mask_s1 & read32((void *)AXIIC_ext_s0_security)) << 16); + + if (ns_bit == TZ_STATE_SECURE) + tz_ext_slaves_sec_status &= ~slave_vector; + else + tz_ext_slaves_sec_status |= slave_vector; + + val = tz_ext_slaves_sec_status & mask_s0; + write32((void *)AXIIC_ext_s0_security, val); + + val = (tz_ext_slaves_sec_status >> 16) & mask_s1; + write32((void *)AXIIC_ext_s1_security, val); +} + +/* + * Set cfg slave security + * Use defines in tz.h for both parameters. + */ +void tz_set_cfg_slaves_security(uint32_t slave_vector, uint32_t ns_bit) +{ + uint32_t val; + uint32_t mask_r = AXIIC_APBR_s0_security_MASK; + uint32_t mask_s = AXIIC_APBS_s0_security_MASK; + uint32_t tz_cfg_slaves_sec_status = + (mask_r & read32((void *)AXIIC_APBR_s0_security)) | + ((mask_s & read32((void *)AXIIC_APBS_s0_security)) << 16); + + if (ns_bit == TZ_STATE_SECURE) + tz_cfg_slaves_sec_status &= ~slave_vector; + else + tz_cfg_slaves_sec_status |= slave_vector; + + val = tz_cfg_slaves_sec_status & mask_r; + write32((void *)AXIIC_APBR_s0_security, val); + + val = (tz_cfg_slaves_sec_status >> 16) & mask_s; + write32((void *)AXIIC_APBS_s0_security, val); +} + +/* + * Set SRAM secure region + * parameter 'r0size' specify the secure RAM region in 4KB steps: + * 0x00000000 = no secure region + * 0x00000001 = 4KB secure region + * 0x00000002 = 8KB secure region + * ....... + * 0x000001FF = 2044KB secure region. + * 0x00000200 or above sets the entire SRAM to secure regardless of size + */ +void tz_set_sram_sec_region(uint32_t r0size) +{ + uint32_t mask = TZPC_TZPCR0SIZE_MASK; + + write32((void *)TZPC_TZPCR0SIZE, r0size & mask); +} + +/* + * Set wrapper security + * Use defines in tz.h for all parameters. + */ +void tz_set_wrapper_security(uint32_t wrapper1, uint32_t wrapper2, + uint32_t wrapper3, uint32_t wrapper4, + uint32_t ns_bit) +{ + uint32_t mask_w4 = AXIIC_APB_W4_security_MASK; + uint32_t mask_w3 = AXIIC_APB_W3_security_MASK; + uint32_t mask_w2 = AXIIC_APB_W2_security_MASK; + uint32_t mask_w1 = AXIIC_APB_W1_security_MASK; + uint32_t tz_wrapper1_sec_status = read32((void *)AXIIC_APB_W1_security); + uint32_t tz_wrapper2_sec_status = read32((void *)AXIIC_APB_W2_security); + uint32_t tz_wrapper3_sec_status = read32((void *)AXIIC_APB_W3_security); + uint32_t tz_wrapper4_sec_status = read32((void *)AXIIC_APB_W4_security); + + if (ns_bit == TZ_STATE_SECURE) { + tz_wrapper1_sec_status &= ~wrapper1; + tz_wrapper2_sec_status &= ~wrapper2; + tz_wrapper3_sec_status &= ~wrapper3; + tz_wrapper4_sec_status &= ~wrapper4; + } else { + tz_wrapper1_sec_status |= wrapper1; + tz_wrapper2_sec_status |= wrapper2; + tz_wrapper3_sec_status |= wrapper3; + tz_wrapper4_sec_status |= wrapper4; + } + write32((void *)AXIIC_APB_W1_security, + tz_wrapper1_sec_status & mask_w1); + write32((void *)AXIIC_APB_W2_security, + tz_wrapper2_sec_status & mask_w2); + write32((void *)AXIIC_APB_W3_security, + tz_wrapper3_sec_status & mask_w3); + write32((void *)AXIIC_APB_W4_security, + tz_wrapper4_sec_status & mask_w4); +}

1 0

Patch set updated for coreboot: 4cdae41 cbmem: add and use a function to dump console buffer
by Patrick Georgi 27 Apr '15

27 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9984 -gerrit commit 4cdae41f2c02c33df752721984d371fc91bac0ff Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Apr 10 18:04:04 2015 -0700 cbmem: add and use a function to dump console buffer The new function can be compiled in only when serial console is disabled. When invoked, this function initializes the serial interface and dumps the contents of the CBMEM console buffer to serial output. BRANCH=none BUG=chromium:475347 TEST=compiled for different platforms with and without serial console enabled. No actual test of this function yet. Change-Id: Ia8d16649dc9d09798fa6970f2cfd893438e00dc5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a38a8254dd788ad188ba2509b9ae117d6f699579 Original-Change-Id: Ib85759a2727e31ba1ca21da7e6c346e434f83b52 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265293 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/console/Kconfig | 9 +++++++++ src/include/console/cbmem_console.h | 1 + src/lib/cbmem_console.c | 17 +++++++++++++++++ src/vendorcode/google/chromeos/vboot.c | 2 ++ src/vendorcode/google/chromeos/vboot_common.c | 2 ++ 5 files changed, 31 insertions(+) diff --git a/src/console/Kconfig b/src/console/Kconfig index 2807039..7d6fa0e 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -184,6 +184,15 @@ config CONSOLE_CBMEM_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. +config CONSOLE_CBMEM_DUMP_TO_UART + depends on !CONSOLE_SERIAL + bool "Dump CBMEM console on resets" + default n + help + Enable this to have CBMEM console buffer contents dumped on the + serial output in case serial console is disabled and the device + resets itself while trying to boot the payload. + endif config CONSOLE_QEMU_DEBUGCON diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 3431459..8f7fcb2 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -43,4 +43,5 @@ static inline void __cbmemc_init(void) {} static inline void __cbmemc_tx_byte(u8 data) {} #endif +void cbmem_dump_console(void); #endif diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 628d3b9..9d292bf 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <console/cbmem_console.h> +#include <console/uart.h> #include <cbmem.h> #include <arch/early_variables.h> #include <symbols.h> @@ -236,5 +237,21 @@ void cbmemc_reinit(void) init_console_ptr(cbm_cons_p, size, flags); } +#if IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART) +void cbmem_dump_console(void) +{ + struct cbmem_console *cbm_cons_p; + int cursor; + + cbm_cons_p = current_console(); + if (!cbm_cons_p) + return; + + uart_init(0); + for (cursor = 0; cursor < cbm_cons_p->buffer_cursor; cursor++) + uart_tx_byte(0, cbm_cons_p->buffer_body[cursor]); +} +#endif + /* Call cbmemc_reinit() at CAR migration time. */ CAR_MIGRATE(cbmemc_reinit) diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c index 44fe9e3..a151f54 100644 --- a/src/vendorcode/google/chromeos/vboot.c +++ b/src/vendorcode/google/chromeos/vboot.c @@ -234,6 +234,8 @@ static void init_vboot(int bootmode) #if !MOCK_TPM printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result); post_code(POST_TPM_FAILURE); + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) + cbmem_dump_console(); hard_reset(); #endif } diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index 3c1a9c3..2e38563 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -129,6 +129,8 @@ void *vboot_get_payload(int *len) void vboot_reboot(void) { + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) + cbmem_dump_console(); hard_reset(); die("failed to reboot"); }

1 0

Patch set updated for coreboot: 6b16a69 sandy/ivy/nehalem: Fix interrupt handling [NOTFORMERGE]
by Kyösti Mälkki 27 Apr '15

27 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9993 -gerrit commit 6b16a69be8314fe41a4d97b473e76e97088e4e1f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Apr 25 18:29:28 2015 +0300 sandy/ivy/nehalem: Fix interrupt handling [NOTFORMERGE] This partially reverts commit 33b535f1. PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive for the GPIO to use. They cannot be used for PCI devices at the same time. Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- .../google/butterfly/acpi/sandybridge_pci_irqs.asl | 64 ++++++++++++++++ src/mainboard/google/butterfly/romstage.c | 42 ++++++++++- .../google/link/acpi/sandybridge_pci_irqs.asl | 68 +++++++++++++++++ src/mainboard/google/link/romstage.c | 39 +++++++++- .../google/parrot/acpi/sandybridge_pci_irqs.asl | 68 +++++++++++++++++ src/mainboard/google/parrot/romstage.c | 43 ++++++++++- .../google/stout/acpi/sandybridge_pci_irqs.asl | 72 ++++++++++++++++++ src/mainboard/google/stout/romstage.c | 43 ++++++++++- .../emeraldlake2/acpi/sandybridge_pci_irqs.asl | 68 +++++++++++++++++ src/mainboard/intel/emeraldlake2/romstage.c | 38 +++++++++- .../kontron/ktqm77/acpi/sandybridge_pci_irqs.asl | 87 ++++++++++++++++++++++ src/mainboard/kontron/ktqm77/romstage.c | 58 ++++++++++++++- .../lenovo/t520/acpi/sandybridge_pci_irqs.asl | 64 ++++++++++++++++ src/mainboard/lenovo/t520/romstage.c | 42 +++++++++++ .../lenovo/t530/acpi/sandybridge_pci_irqs.asl | 64 ++++++++++++++++ src/mainboard/lenovo/t530/romstage.c | 42 +++++++++++ .../lenovo/x201/acpi/nehalem_pci_irqs.asl | 86 +++++++++++++++++++++ src/mainboard/lenovo/x201/romstage.c | 40 +++++++++- .../lenovo/x220/acpi/sandybridge_pci_irqs.asl | 64 ++++++++++++++++ src/mainboard/lenovo/x220/romstage.c | 42 +++++++++++ .../lenovo/x230/acpi/sandybridge_pci_irqs.asl | 64 ++++++++++++++++ src/mainboard/lenovo/x230/romstage.c | 42 +++++++++++ .../packardbell/ms2290/acpi/nehalem_pci_irqs.asl | 86 +++++++++++++++++++++ src/mainboard/packardbell/ms2290/romstage.c | 41 ++++++++-- .../samsung/lumpy/acpi/sandybridge_pci_irqs.asl | 68 +++++++++++++++++ src/mainboard/samsung/lumpy/romstage.c | 36 ++++++++- .../samsung/stumpy/acpi/sandybridge_pci_irqs.asl | 68 +++++++++++++++++ src/mainboard/samsung/stumpy/romstage.c | 38 +++++++++- src/northbridge/intel/nehalem/acpi/hostbridge.asl | 3 + .../intel/sandybridge/acpi/hostbridge.asl | 3 + src/southbridge/intel/bd82x6x/acpi/irq.asl | 72 ------------------ src/southbridge/intel/bd82x6x/acpi/pch.asl | 2 - 32 files changed, 1566 insertions(+), 91 deletions(-) diff --git a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..6c1c695 --- /dev/null +++ b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 1753cd5..eda54a5 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -60,7 +60,47 @@ void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..a4267bb --- /dev/null +++ b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, + Package() { 0x001fffff, 1, 0, 23 }, + Package() { 0x001fffff, 2, 0, 16 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 5844aa6..e814a24 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -78,7 +78,44 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P3IP WLAN INTA -> PIRQB + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * TRACKPAD -> PIRQE (Edge Triggered) + * TOUCHSCREEN -> PIRQG (Edge Triggered) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..a4267bb --- /dev/null +++ b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, + Package() { 0x001fffff, 1, 0, 23 }, + Package() { 0x001fffff, 2, 0, 16 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index ab82bde..fc50a87 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -62,7 +62,48 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P2IP WLAN INTA -> PIRQB + * D28IP_P3IP ETH0 INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQE + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQH + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * + * Trackpad DVT PIRQA (16) + * Trackpad DVT PIRQE (20) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | + (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) | + (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) | + (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..cf3d82a --- /dev/null +++ b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 19 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, + Package() { 0x001fffff, 1, 0, 23 }, + Package() { 0x001fffff, 2, 0, 16 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 6a6aa48..5e6db50 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -68,7 +68,48 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D20IP_XHCI XHCI INTA -> PIRQD (MSI) + * D26IP_E2P EHCI #2 INTA -> PIRQF + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * D28IP_P2IP WLAN INTA -> PIRQD + * D28IP_P3IP Card Reader INTB -> PIRQE + * D28IP_P6IP LAN INTC -> PIRQB + * D29IP_E1P EHCI #1 INTA -> PIRQD + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | + (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | + (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | + (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCIIP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC); + DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl b/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..a57f9f1 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 18 }, + Package() { 0x001cffff, 2, 0, 19 }, + Package() { 0x001cffff, 3, 0, 20 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 20 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 21 }, + Package() { 0x001fffff, 1, 0, 22 }, + Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 3, 0, 16 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 45d92d8..8344a6c 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -74,7 +74,43 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P4IP ETH0 INTB -> PIRQC + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQH + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..ceb40be --- /dev/null +++ b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Ivybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // LPC devices 0:1f.x + // D31IP_TTIP THRT INTC -> PIRQC + Package() { 0x001fffff, 2, 0, 18 },// D31IP_SMIP SMBUS INTC -> PIRQC + Package() { 0x001fffff, 1, 0, 19 },// D31IP_SIP SATA INTB -> PIRQD (MSI) + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 23 },// D29IP_E1P EHCI1 INTA -> PIRQH + // PCIe Root Ports 0:1c.x + // D28IP_P8IP Slot? INTD -> PIRQD + Package() { 0x001cffff, 3, 0, 19 },// D28IP_P4IP ETH2 INTD -> PIRQD (MSI) + // D28IP_P7IP PCIEx1 INTC -> PIRQC + Package() { 0x001cffff, 2, 0, 18 },// D28IP_P3IP ETH1 INTC -> PIRQC (MSI) + // D28IP_P6IP 1394 INTB -> PIRQB (MSI) + Package() { 0x001cffff, 1, 0, 17 },// D28IP_P2IP Slot? INTB -> PIRQB + // D28IP_P5IP GbEPHY INTA -> PIRQA + Package() { 0x001cffff, 0, 0, 16 },// D28IP_P1IP Slot? INTA -> PIRQA + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 },// D27IP_ZIP HDA INTA -> PIRQG (MSI) + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 16 },// D26IP_E2P EHCI2 INTA -> PIRQA + // ETH0 0:19.0 + Package() { 0x0019ffff, 0, 0, 20 },// D25IP_LIP ETH0 INTA -> PIRQE (MSI) + // xHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 16 },// D20IP_XHCIIP xHCI INTA -> PIRQA (MSI) + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // PCIe PEG x16 0:1.0 + Package() { 0x0001ffff, 3, 0, 19 },// PEGx16 INTD -> PIRQD + Package() { 0x0001ffff, 2, 0, 18 },// PEGx16 INTC -> PIRQC + Package() { 0x0001ffff, 1, 0, 17 },// PEGx16 INTB -> PIRQB + Package() { 0x0001ffff, 0, 0, 16 },// PEGx16 INTA -> PIRQA + }) + } Else { + Return (Package() { + // LPC devices 0:1f.x + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // ETH0 0:19.0 + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // xHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe PEG x16 0:1.0 + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 22dc33d..a4bc3a2 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -60,7 +60,63 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * D31IP_TTIP THRT INTC -> PIRQC + * D31IP_SIP2 SATA2 NOINT + * D31IP_SMIP SMBUS INTC -> PIRQC + * D31IP_SIP SATA INTB -> PIRQD (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQH + * D28IP_P8IP Slot? INTD -> PIRQD + * D28IP_P7IP PCIEx1 INTC -> PIRQC + * D28IP_P6IP 1394 INTB -> PIRQB (MSI) + * D28IP_P5IP GbEPHY INTA -> PIRQA + * D28IP_P4IP ETH2 INTD -> PIRQD (MSI) + * D28IP_P3IP ETH1 INTC -> PIRQC (MSI) + * D28IP_P2IP Slot? INTB -> PIRQB + * D28IP_P1IP Slot? INTA -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D26IP_E2P EHCI2 INTA -> PIRQA + * D25IP_LIP ETH0 INTA -> PIRQE (MSI) + * D22IP_KTIP MEI NOINT + * D22IP_IDERIP MEI NOINT + * D22IP_MEI2IP MEI NOINT + * D22IP_MEI1IP MEI NOINT + * D20IP_XHCIIP XHCI INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) + * PEGx16 INTA -> PIRQA + * INTB -> PIRQB + * INTC -> PIRQC + * INTD -> PIRQD + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTC << D31IP_SMIP) | (INTB << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) | + (INTA << D28IP_P5IP) | (INTB << D28IP_P6IP) | + (INTC << D28IP_P7IP) | (INTD << D28IP_P8IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (INTA << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCIIP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); + DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); + DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD); + DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); + DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..b4b81a2 --- /dev/null +++ b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P2IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P4IP EXC INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P5IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index f7866a8..83be0c7 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -60,6 +60,48 @@ void pch_enable_lpc(void) void rcba_config(void) { + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P2IP WLAN INTA -> PIRQB + * D28IP_P4IP EXC INTB -> PIRQF + * D28IP_P5IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P2IP) | (INTB << D28IP_P4IP) | + (INTC << D28IP_P5IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1ee51fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..6c1c695 --- /dev/null +++ b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index f29d375..970ee97 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -47,6 +47,48 @@ void pch_enable_lpc(void) void rcba_config(void) { + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl b/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl new file mode 100644 index 0000000..3e9e1b3 --- /dev/null +++ b/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing. + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 0x10 }, + Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA + Package() { 0x0003ffff, 0, 0, 0x10 }, + Package() { 0x0016ffff, 0, 0, 0x10 }, // ME + Package() { 0x0016ffff, 1, 0, 0x11 }, // ME + Package() { 0x0016ffff, 2, 0, 0x12 }, // ME + Package() { 0x0016ffff, 3, 0, 0x13 }, // ME + Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet + Package() { 0x001affff, 0, 0, 0x14 }, // USB + Package() { 0x001affff, 1, 0, 0x15 }, // USB + Package() { 0x001affff, 2, 0, 0x16 }, // USB + Package() { 0x001affff, 3, 0, 0x17 }, // USB + Package() { 0x001bffff, 1, 0, 0x11 }, // Audio + Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge + Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge + Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge + Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge + Package() { 0x001dffff, 0, 0, 0x10 }, // USB + Package() { 0x001dffff, 1, 0, 0x11 }, // USB + Package() { 0x001dffff, 2, 0, 0x12 }, // USB + Package() { 0x001dffff, 3, 0, 0x13 }, // USB + Package() { 0x001fffff, 0, 0, 0x17 }, // LPC + Package() { 0x001fffff, 1, 0, 0x10 }, // IDE + Package() { 0x001fffff, 2, 0, 0x11 }, // SATA + Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS + }) + } Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME + Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME + Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME + Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB + Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB + Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB + Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB + Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus + }) + } +} diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 624440a..3ae8a3b 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -75,9 +75,41 @@ static void pch_enable_lpc(void) static void rcba_config(void) { - southbridge_configure_default_intmap(); - static const u32 rcba_dump3[] = { + /* 30fc */ 0x00000000, + /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321, + /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002, + /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000, + /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654, + /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210, + /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000, + /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -147,8 +179,8 @@ static void rcba_config(void) }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x30fc) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x30fc); } } diff --git a/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..6c1c695 --- /dev/null +++ b/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index d0fb8e6..cf25703 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -57,6 +57,48 @@ void pch_enable_lpc(void) void rcba_config(void) { + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1fe41fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..6c1c695 --- /dev/null +++ b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 4ea272d..ef47b54 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -60,6 +60,48 @@ void pch_enable_lpc(void) void rcba_config(void) { + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl b/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl new file mode 100644 index 0000000..1f782c8 --- /dev/null +++ b/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing. + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 0x10 }, + Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA + Package() { 0x0003ffff, 0, 0, 0x10 }, + Package() { 0x0016ffff, 0, 0, 0x10 }, // ME + Package() { 0x0016ffff, 1, 0, 0x11 }, // ME + Package() { 0x0016ffff, 2, 0, 0x12 }, // ME + Package() { 0x0016ffff, 3, 0, 0x13 }, // ME + Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet + Package() { 0x001affff, 0, 0, 0x14 }, // USB + Package() { 0x001affff, 1, 0, 0x15 }, // USB + Package() { 0x001affff, 2, 0, 0x16 }, // USB + Package() { 0x001affff, 3, 0, 0x17 }, // USB + Package() { 0x001bffff, 1, 0, 0x11 }, // Audio + Package() { 0x001cffff, 0, 0, 0x10 }, // PCI bridge + Package() { 0x001cffff, 1, 0, 0x11 }, // PCI bridge + Package() { 0x001cffff, 2, 0, 0x12 }, // PCI bridge + Package() { 0x001cffff, 3, 0, 0x13 }, // PCI bridge + Package() { 0x001dffff, 0, 0, 0x10 }, // USB + Package() { 0x001dffff, 1, 0, 0x11 }, // USB + Package() { 0x001dffff, 2, 0, 0x12 }, // USB + Package() { 0x001dffff, 3, 0, 0x13 }, // USB + Package() { 0x001fffff, 0, 0, 0x17 }, // LPC + Package() { 0x001fffff, 1, 0, 0x10 }, // IDE + Package() { 0x001fffff, 2, 0, 0x11 }, // SATA + Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS + }) + } Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME + Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME + Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME + Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB + Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB + Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB + Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB + Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // PCI + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // PCI + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // PCI + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // PCI + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus + }) + } +} diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index f702e9f..0d65e66 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -70,9 +70,41 @@ static void pch_enable_lpc(void) static void rcba_config(void) { - southbridge_configure_default_intmap(); - static const u32 rcba_dump3[] = { + /* 30fc */ 0x00000000, + /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321, + /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002, + /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000, + /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654, + /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210, + /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000, + /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -141,10 +173,9 @@ static void rcba_config(void) /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000, }; unsigned i; - for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3310) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3310); + RCBA32(4 * i + 0x30fc) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x30fc); } } diff --git a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..aff2351 --- /dev/null +++ b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 18 }, + Package() { 0x001cffff, 2, 0, 19 }, + Package() { 0x001cffff, 3, 0, 16 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 17 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 16 }, + Package() { 0x001fffff, 1, 0, 22 }, + Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 3, 0, 17 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }, + }) + } +} diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 29a238a..27be119 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -74,7 +74,41 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P4IP ETH0 INTB -> PIRQC (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQB + * D31IP_SIP SATA INTA -> PIRQA (MSI) + * D31IP_SMIP SMBUS INTC -> PIRQH + * D31IP_TTIP THRT INTB -> PIRQG + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * + * LIGHTSENSOR -> PIRQE (Edge Triggered) + * TRACKPAD -> PIRQF (Edge Triggered) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTC << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; diff --git a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..2636f13 --- /dev/null +++ b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 18 }, + Package() { 0x001cffff, 2, 0, 19 }, + Package() { 0x001cffff, 3, 0, 20 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 20 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 21 }, + Package() { 0x001fffff, 1, 0, 22 }, + Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 3, 0, 16 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 346026f..3c2308a 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -86,7 +86,43 @@ static void rcba_config(void) { u32 reg32; - southbridge_configure_default_intmap(); + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P4IP ETH0 INTB -> PIRQC + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQH + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index d210a95..aeb4c29 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -343,3 +343,6 @@ Method (_CRS, 0, Serialized) Return (MCRS) } + +/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ +#include "acpi/nehalem_pci_irqs.asl" diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 26f7514..d9fc171 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -378,3 +378,6 @@ Method (_CRS, 0, Serialized) Return (MCRS) } + +/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ +#include "acpi/sandybridge_pci_irqs.asl" diff --git a/src/southbridge/intel/bd82x6x/acpi/irq.asl b/src/southbridge/intel/bd82x6x/acpi/irq.asl deleted file mode 100644 index 61e3335..0000000 --- a/src/southbridge/intel/bd82x6x/acpi/irq.asl +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* PCI Interrupt Routing */ -Method(_PRT) -{ - If (PICM) { - Return (Package() { - /* Onboard graphics (IGD) 0:2.0 */ - Package() { 0x0002ffff, 0, 0, 16 },/* GFX INTA -> PIRQA (MSI) */ - /* XHCI 0:14.0 (ivy only) */ - Package() { 0x0014ffff, 0, 0, 19 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */ - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 17 },/* D28IP_P1IP PCIe INTA -> PIRQB */ - Package() { 0x001cffff, 1, 0, 21 },/* D28IP_P2IP PCIe INTB -> PIRQF */ - Package() { 0x001cffff, 2, 0, 19 },/* D28IP_P3IP PCIe INTC -> PIRQD */ - Package() { 0x001cffff, 3, 0, 20 },/* D28IP_P3IP PCIe INTD -> PIRQE */ - /* EHCI #1 0:1d.0 */ - Package() { 0x001dffff, 0, 0, 19 },/* D29IP_E1P EHCI1 INTA -> PIRQD */ - /* EHCI #2 0:1a.0 */ - Package() { 0x001affff, 0, 0, 21 },/* D26IP_E2P EHCI2 INTA -> PIRQF */ - /* LPC devices 0:1f.0 */ - Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */ - Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */ - Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */ - Package() { 0x001fffff, 3, 0, 18 }, - }) - } Else { - Return (Package() { - /* Onboard graphics (IGD) 0:2.0 */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* XHCI 0:14.0 (ivy only) */ - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, - /* EHCI #1 0:1d.0 */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - /* EHCI #2 0:1a.0 */ - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - /* LPC device 0:1f.0 */ - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, - }) - } -} diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 73fcfcc..27f08e2 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -257,8 +257,6 @@ Scope(\) // SMBus 0:1f.3 #include "smbus.asl" -#include "irq.asl" - Method (_OSC, 4) { /* Check for XHCI */

1 0

Patch set updated for coreboot: 8d27699 sandy/ivy boards: Rename defines from onboard.h for ACPI
by Kyösti Mälkki 27 Apr '15

27 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9992 -gerrit commit 8d27699df33c856f70014f2a317193c67bac69d7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 24 16:05:58 2015 +0300 sandy/ivy boards: Rename defines from onboard.h for ACPI Adopted style from later Chromebooks. Change-Id: I4993b8f40489b6bf5d08e00089f36f293853629e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/butterfly/acpi/mainboard.asl | 11 ++++++++--- src/mainboard/google/butterfly/mainboard.c | 6 +++--- src/mainboard/google/butterfly/onboard.h | 8 ++++---- src/mainboard/google/link/acpi/mainboard.asl | 11 ++++++++--- src/mainboard/google/link/mainboard.c | 18 +++++++++--------- src/mainboard/google/link/onboard.h | 21 ++++++++++----------- src/mainboard/google/parrot/acpi/mainboard.asl | 16 ++++++++++++---- src/mainboard/google/parrot/mainboard.c | 12 ++++++------ src/mainboard/google/parrot/onboard.h | 10 +++++----- src/mainboard/samsung/lumpy/acpi/mainboard.asl | 18 +++++++++++++----- src/mainboard/samsung/lumpy/mainboard.c | 12 ++++++------ src/mainboard/samsung/lumpy/onboard.h | 15 +++++++-------- 12 files changed, 91 insertions(+), 67 deletions(-) diff --git a/src/mainboard/google/butterfly/acpi/mainboard.asl b/src/mainboard/google/butterfly/acpi/mainboard.asl index c6e35e8..342193f 100644 --- a/src/mainboard/google/butterfly/acpi/mainboard.asl +++ b/src/mainboard/google/butterfly/acpi/mainboard.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <mainboard/google/butterfly/onboard.h> + Scope (\_SB) { Device (LID0) { @@ -45,15 +47,18 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0E")) // Trackpad Wake is GPIO11, wake from S3 - Name(_PRW, Package(){0x1b, 0x03}) + Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) Name(_CRS, ResourceTemplate() { // PIRQG -> GSI22 - Interrupt (ResourceConsumer, EDGE, ActiveLow) {22} + Interrupt (ResourceConsumer, EDGE, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } // SMBUS Address 0x67 - VendorShort (ADDR) {0x67} + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } }) } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 655fc2f..f83b33b 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -265,10 +265,10 @@ static int butterfly_onboard_smbios_data(device_t dev, int *handle, len += smbios_write_type41( current, handle, - BUTTERFLY_TRACKPAD_NAME, /* name */ - BUTTERFLY_TRACKPAD_IRQ, /* instance */ + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ, /* instance */ 0, /* segment */ - BUTTERFLY_TRACKPAD_I2C_ADDR, /* bus */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h index e32e023..08ba806 100644 --- a/src/mainboard/google/butterfly/onboard.h +++ b/src/mainboard/google/butterfly/onboard.h @@ -20,12 +20,12 @@ #ifndef BUTTERFLY_ONBOARD_H #define BUTTERFLY_ONBOARD_H -#include <arch/smp/mpspec.h> /* uses 7-bit I2C address */ /* must be set to edge triggered */ -#define BUTTERFLY_TRACKPAD_NAME "trackpad" -#define BUTTERFLY_TRACKPAD_I2C_ADDR 0x67 -#define BUTTERFLY_TRACKPAD_IRQ 22 /* PIRQG - 22 Edge triggered */ +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_I2C_ADDR 0x67 +#define BOARD_TRACKPAD_IRQ 22 /* PIRQG - 22 Edge triggered */ +#define BOARD_TRACKPAD_WAKE_GPIO 0x1b /* defines for programming the MAC address */ #define BUTTERFLY_NIC_VENDOR_ID 0x10EC diff --git a/src/mainboard/google/link/acpi/mainboard.asl b/src/mainboard/google/link/acpi/mainboard.asl index a2778a0..ee727e0 100644 --- a/src/mainboard/google/link/acpi/mainboard.asl +++ b/src/mainboard/google/link/acpi/mainboard.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <mainboard/google/link/onboard.h> + Scope (\_SB) { Device (LID0) { @@ -48,15 +50,18 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0E")) // Trackpad Wake is GPIO12 - Name(_PRW, Package(){0x1c, 0x03}) + Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } ) Name(_CRS, ResourceTemplate() { // PIRQE -> GSI20 - Interrupt (ResourceConsumer, Edge, ActiveLow) {20} + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } // SMBUS Address 0x4b - VendorShort (ADDR) {0x4b} + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } }) } diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index ed40f8f..a3a98fc 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -173,28 +173,28 @@ static int link_onboard_smbios_data(device_t dev, int *handle, len += smbios_write_type41( current, handle, - LINK_LIGHTSENSOR_NAME, /* name */ - LINK_LIGHTSENSOR_IRQ, /* instance */ + BOARD_LIGHTSENSOR_NAME, /* name */ + BOARD_LIGHTSENSOR_IRQ, /* instance */ 0, /* segment */ - LINK_LIGHTSENSOR_I2C_ADDR, /* bus */ + BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ len += smbios_write_type41( current, handle, - LINK_TRACKPAD_NAME, /* name */ - LINK_TRACKPAD_IRQ, /* instance */ + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ, /* instance */ 0, /* segment */ - LINK_TRACKPAD_I2C_ADDR, /* bus */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ len += smbios_write_type41( current, handle, - LINK_TOUCHSCREEN_NAME, /* name */ - LINK_TOUCHSCREEN_IRQ, /* instance */ + BOARD_TOUCHSCREEN_NAME, /* name */ + BOARD_TOUCHSCREEN_IRQ, /* instance */ 0, /* segment */ - LINK_TOUCHSCREEN_I2C_ADDR, /* bus */ + BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h index eaac383..2ecbdc4 100644 --- a/src/mainboard/google/link/onboard.h +++ b/src/mainboard/google/link/onboard.h @@ -20,18 +20,17 @@ #ifndef LINK_ONBOARD_H #define LINK_ONBOARD_H -#include <arch/smp/mpspec.h> +#define BOARD_LIGHTSENSOR_NAME "lightsensor" +#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 +#define BOARD_LIGHTSENSOR_IRQ 0 -#define LINK_LIGHTSENSOR_NAME "lightsensor" -#define LINK_LIGHTSENSOR_I2C_ADDR 0x44 -#define LINK_LIGHTSENSOR_IRQ 0 +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_I2C_ADDR 0x4b +#define BOARD_TRACKPAD_IRQ 20 +#define BOARD_TRACKPAD_WAKE_GPIO 0x1c -#define LINK_TRACKPAD_NAME "trackpad" -#define LINK_TRACKPAD_I2C_ADDR 0x4b -#define LINK_TRACKPAD_IRQ 20 - -#define LINK_TOUCHSCREEN_NAME "touchscreen" -#define LINK_TOUCHSCREEN_I2C_ADDR 0x4a -#define LINK_TOUCHSCREEN_IRQ 22 +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a +#define BOARD_TOUCHSCREEN_IRQ 22 #endif diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 503e44b..9116c69 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <mainboard/google/parrot/onboard.h> + Scope (\_GPE) { Method(_L1F, 0x0, NotSerialized) { @@ -59,19 +61,25 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0E")) // Trackpad Wake is GPIO12, wake from S3 - Name(_PRW, Package(){0x1c, 0x03}) + Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) Name(_CRS, ResourceTemplate() { // PIRQA -> GSI16 - Interrupt (ResourceConsumer, Level, ActiveLow) {16} + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TRACKPAD_IRQ_DVT + } // PIRQE -> GSI20 - Interrupt (ResourceConsumer, Edge, ActiveLow) {20} + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ_PVT + } // SMBUS Address 0x67 - VendorShort (ADDR) {0x67} + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } }) } diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 547680e..39d2c84 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -62,19 +62,19 @@ static int parrot_onboard_smbios_data(device_t dev, int *handle, if (hardware_version < 0x2) { /* DVT vs PVT */ len += smbios_write_type41( current, handle, - PARROT_TRACKPAD_NAME, /* name */ - PARROT_TRACKPAD_IRQ_DVT, /* instance */ + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ_DVT, /* instance */ 0, /* segment */ - PARROT_TRACKPAD_I2C_ADDR, /* bus */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ } else { len += smbios_write_type41( current, handle, - PARROT_TRACKPAD_NAME, /* name */ - PARROT_TRACKPAD_IRQ_PVT, /* instance */ + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ_PVT, /* instance */ 0, /* segment */ - PARROT_TRACKPAD_I2C_ADDR, /* bus */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ 0); /* function */ } diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h index f3d200d..1f878af 100644 --- a/src/mainboard/google/parrot/onboard.h +++ b/src/mainboard/google/parrot/onboard.h @@ -20,10 +20,10 @@ #ifndef PARROT_ONBOARD_H #define PARROT_ONBOARD_H -#include <arch/smp/mpspec.h> +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_I2C_ADDR 0x67 +#define BOARD_TRACKPAD_IRQ_DVT 16 +#define BOARD_TRACKPAD_IRQ_PVT 20 +#define BOARD_TRACKPAD_WAKE_GPIO 0x1c -#define PARROT_TRACKPAD_NAME "trackpad" -#define PARROT_TRACKPAD_I2C_ADDR 0x67 -#define PARROT_TRACKPAD_IRQ_DVT 16 -#define PARROT_TRACKPAD_IRQ_PVT 20 #endif diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl index b1ab678..435dd51 100644 --- a/src/mainboard/samsung/lumpy/acpi/mainboard.asl +++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <mainboard/samsung/lumpy/onboard.h> + Scope (\_SB) { Device (LID0) { @@ -45,15 +47,18 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0E")) // Trackpad Wake is GPIO11 - Name(_PRW, Package(){0x1b, 0x03}) + Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) Name(_CRS, ResourceTemplate() { // PIRQF -> GSI21 - Interrupt (ResourceConsumer, Edge, ActiveLow) {21} + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } // SMBUS Address 0x67 - VendorShort (ADDR) {0x67} + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } }) } @@ -65,10 +70,13 @@ Scope (\_SB) { Name(_CRS, ResourceTemplate() { // PIRQE -> GSI20 - Interrupt (ResourceConsumer, Edge, ActiveLow) {20} + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_LIGHTSENSOR_IRQ + } // SMBUS Address 0x44 - VendorShort (ADDR) {0x44} + VendorShort (ADDR) { BOARD_LIGHTSENSOR_I2C_ADDR } }) } } diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 3bdd4d9..6967a2b 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -86,14 +86,14 @@ static int lumpy_onboard_smbios_data(device_t dev, int *handle, int len = 0; len += lumpy_smbios_type41_irq(handle, current, - LUMPY_LIGHTSENSOR_NAME, - LUMPY_LIGHTSENSOR_IRQ, - LUMPY_LIGHTSENSOR_I2C_ADDR); + BOARD_LIGHTSENSOR_NAME, + BOARD_LIGHTSENSOR_IRQ, + BOARD_LIGHTSENSOR_I2C_ADDR); len += lumpy_smbios_type41_irq(handle, current, - LUMPY_TRACKPAD_NAME, - LUMPY_TRACKPAD_IRQ, - LUMPY_TRACKPAD_I2C_ADDR); + BOARD_TRACKPAD_NAME, + BOARD_TRACKPAD_IRQ, + BOARD_TRACKPAD_I2C_ADDR); return len; } diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h index 6bdf057..5001612 100644 --- a/src/mainboard/samsung/lumpy/onboard.h +++ b/src/mainboard/samsung/lumpy/onboard.h @@ -20,14 +20,13 @@ #ifndef LUMPY_ONBOARD_H #define LUMPY_ONBOARD_H -#include <arch/smp/mpspec.h> +#define BOARD_LIGHTSENSOR_NAME "lightsensor" +#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 +#define BOARD_LIGHTSENSOR_IRQ 20 -#define LUMPY_LIGHTSENSOR_NAME "lightsensor" -#define LUMPY_LIGHTSENSOR_I2C_ADDR 0x44 -#define LUMPY_LIGHTSENSOR_IRQ 20 - -#define LUMPY_TRACKPAD_NAME "trackpad" -#define LUMPY_TRACKPAD_I2C_ADDR 0x67 -#define LUMPY_TRACKPAD_IRQ 21 +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_I2C_ADDR 0x67 +#define BOARD_TRACKPAD_IRQ 21 +#define BOARD_TRACKPAD_WAKE_GPIO 0x1b #endif

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Patch merged into coreboot/master: d8a5017 arm64: save/restore cptr_el3 and cpacr_el1 registers
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit d8a5017ee0d47e860148d139bc5329083ac06515 Author: Joseph Lo <josephl(a)nvidia.com> Date: Fri Apr 17 15:31:59 2015 +0800 arm64: save/restore cptr_el3 and cpacr_el1 registers CPTR_EL3 and CPACR_EL1 are the registers for controlling the trap level and access right of the FPU/SIMD instructions. Need to save/restore them in every power cycle to keep the settings consistent. BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well Change-Id: I96fc0e0d2620e72b6ae2ffe4d073c9328047dc01 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 73e8cc8f25922e7bc218d24fbf4f7c67e15e3057 Original-Change-Id: I51eed07b1bb8f6eb2715622ec5d5c3f80c3c8bdd Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/266073 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> Reviewed-on: http://review.coreboot.org/9981 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9981 for details. -gerrit

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Patch merged into coreboot/master: c38d3e8 arm64: implement CPU power down sequence as per A57/A53/A72 TRM
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit c38d3e8131b0f6ed7e576d1a66ac9513b1810f27 Author: Joseph Lo <josephl(a)nvidia.com> Date: Wed Apr 15 10:09:50 2015 +0800 arm64: implement CPU power down sequence as per A57/A53/A72 TRM Implement the individual core powerdown sequence as per Cortex-A57/A53/A72 TRM. Based-on-the-work-by: Varun Wadekar <vwadekar(a)nvidia.com> BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well Change-Id: I4719fcbe86b35f9b448d274e1732da5fc75346b0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b6bdcc12150820dfad28cef3af3d8220847c5d74 Original-Change-Id: I65abab8cda55cfe7a0c424f3175677ed5e3c2a1c Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265827 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9980 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9980 for details. -gerrit

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Patch merged into coreboot/master: c4301f7 arm64: introduce data cache ops by set/way to the level specified
by gerrit＠coreboot.org 27 Apr '15

27 Apr '15

the following patch was just integrated into master: commit c4301f79691995dfedb56cb3e20adea3ecd8f596 Author: Joseph Lo <josephl(a)nvidia.com> Date: Tue Apr 14 16:03:58 2015 +0800 arm64: introduce data cache ops by set/way to the level specified This patchs introduces level specific data cache maintenance operations to cache_helpers.S. It's derived form ARM trusted firmware repository. Please reference here. https://github.com/ARM-software/arm-trusted-firmware/blob/master/ lib/aarch64/cache_helpers.S BRANCH=none BUG=none TEST=boot on smaug/foster Change-Id: Ib58a6d6f95eb51ce5d80749ff51d9d389b0d1343 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b3d1a16bd0089740f1f2257146c771783beece82 Original-Change-Id: Ifcd1dbcd868331107d0d47af73545a3a159fdff6 Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265826 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9979 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9979 for details. -gerrit

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coreboot-gerrit April 2015