coreboot-gerrit April 2015

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Patch set updated for coreboot: 2be7917 cbmem: Identify the FSP areas in CBMEM
by Leroy P Leahy 29 Apr '15

29 Apr '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10026 -gerrit commit 2be7917829404a832af2fd710ab08e478cc632f8 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Apr 28 18:21:25 2015 -0700 cbmem: Identify the FSP areas in CBMEM Add identifers and descriptions for the FSP areas within CBMEM. BRANCH=none BUG=None TEST=Build for Braswell and Skylake boards using FSP 1.1. Change-Id: I4d58f7f08cfbc17f3aef261c835b92d8d65f6622 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/cbmem.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 936fdf6..c5cd52a 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -54,6 +54,8 @@ #define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 #define CBMEM_ID_ELOG 0x454c4f47 #define CBMEM_ID_FREESPACE 0x46524545 +#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052 +#define CBMEM_ID_FSP_RUNTIME 0x52505346 #define CBMEM_ID_GDT 0x4c474454 #define CBMEM_ID_HOB_POINTER 0x484f4221 #define CBMEM_ID_IGD_OPREGION 0x4f444749 @@ -101,6 +103,8 @@ { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \ { CBMEM_ID_ELOG, "ELOG " }, \ { CBMEM_ID_FREESPACE, "FREE SPACE " }, \ + { CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \ + { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \ { CBMEM_ID_GDT, "GDT " }, \ { CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \ { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \

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Patch set updated for coreboot: 768e0a9 chromeos: Add missing headers
by Patrick Georgi 29 Apr '15

29 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10029 -gerrit commit 768e0a9107670d228fe3b843c1cefcad2e617349 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 18:59:04 2015 +0200 chromeos: Add missing headers Builds with CHROMEOS fail due to missing includes. Change-Id: I8c88bca8f8cc3247d3f3311777f794c4fdfee3c1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/romstage/romstage.c | 1 + src/vendorcode/google/chromeos/vboot.c | 1 + src/vendorcode/google/chromeos/vboot_common.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 1741ae6..c026004 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -38,6 +38,7 @@ #include <soc/reset.h> #include <soc/romstage.h> #include <soc/spi.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c index a151f54..7216373 100644 --- a/src/vendorcode/google/chromeos/vboot.c +++ b/src/vendorcode/google/chromeos/vboot.c @@ -18,6 +18,7 @@ */ #include <types.h> +#include <console/cbmem_console.h> #include <console/console.h> #include <arch/acpi.h> #include <tpm.h> diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index 2e0ab2b..68aa314 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -20,6 +20,7 @@ #include <boot/coreboot_tables.h> #include <cbfs.h> #include <cbmem.h> +#include <console/cbmem_console.h> #include <console/console.h> #include <reset.h> #include <stddef.h>

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Patch set updated for coreboot: 3ad459f cbmem: Add FSP timestamps
by Leroy P Leahy 29 Apr '15

29 Apr '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10025 -gerrit commit 3ad459f3cf9e79607169ad8bfadbe3128b8f3508 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Feb 24 11:30:38 2015 -0800 cbmem: Add FSP timestamps Add additional FSP timestamp values to cbmem.h and specify values for the existing ones. Update cbmem.c with the FSP timestamp values and descriptions. BRANCH=none BUG=None TEST=Build for Braswell and Skylake boards using FSP 1.1. Change-Id: I835bb090ff5877a108e48cb60f8e80260773771b Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/timestamp.h | 16 ++++++++++++---- util/cbmem/cbmem.c | 15 ++++++++++++++- 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/src/include/timestamp.h b/src/include/timestamp.h index cd648ea..a6bfced 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -51,16 +51,12 @@ enum timestamp_id { TS_START_ULZMA = 15, TS_END_ULZMA = 16, TS_DEVICE_ENUMERATE = 30, - TS_FSP_BEFORE_ENUMERATE, - TS_FSP_AFTER_ENUMERATE, TS_DEVICE_CONFIGURE = 40, TS_DEVICE_ENABLE = 50, TS_DEVICE_INITIALIZE = 60, TS_DEVICE_DONE = 70, TS_CBMEM_POST = 75, TS_WRITE_TABLES = 80, - TS_FSP_BEFORE_FINALIZE, - TS_FSP_AFTER_FINALIZE, TS_LOAD_PAYLOAD = 90, TS_ACPI_WAKE_JUMP = 98, TS_SELFBOOT_JUMP = 99, @@ -77,6 +73,18 @@ enum timestamp_id { TS_DONE_HASHING = 509, TS_END_HASH_BODY = 510, + /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ + TS_FSP_MEMORY_INIT_START = 950, + TS_FSP_MEMORY_INIT_END = 951, + TS_FSP_TEMP_RAM_EXIT_START = 952, + TS_FSP_TEMP_RAM_EXIT_END = 953, + TS_FSP_SILICON_INIT_START = 954, + TS_FSP_SILICON_INIT_END = 955, + TS_FSP_BEFORE_ENUMERATE = 956, + TS_FSP_AFTER_ENUMERATE = 957, + TS_FSP_BEFORE_FINALIZE = 958, + TS_FSP_AFTER_FINALIZE = 959, + /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */ }; diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 7007354..e342d69 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -413,7 +413,20 @@ static const struct timestamp_id_to_name { { TS_RW_VB_SELECT_AND_LOAD_KERNEL, "RW vboot select&load kernel" }, { TS_VB_SELECT_AND_LOAD_KERNEL, "vboot select&load kernel" }, { TS_CROSSYSTEM_DATA, "crossystem data" }, - { TS_START_KERNEL, "start kernel" } + { TS_START_KERNEL, "start kernel" }, + + /* FSP related timestamps */ + { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" }, + { TS_FSP_MEMORY_INIT_END, "returning from FspMemoryInit" }, + { TS_FSP_TEMP_RAM_EXIT_START, "calling FspTempRamExit" }, + { TS_FSP_TEMP_RAM_EXIT_END, "returning from FspTempRamExit" }, + { TS_FSP_SILICON_INIT_START, "calling FspSiliconInit" }, + { TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit" }, + { TS_FSP_BEFORE_ENUMERATE, "calling FspNotify(AfterPciEnumeration)" }, + { TS_FSP_AFTER_ENUMERATE, + "returning from FspNotify(AfterPciEnumeration)" }, + { TS_FSP_BEFORE_FINALIZE, "calling FspNotify(ReadyToBoot)" }, + { TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" } }; void timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp)

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New patch to review for coreboot: 29191e0 chromeos: Add missing headers
by Patrick Georgi 29 Apr '15

29 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10029 -gerrit commit 29191e021e5a8ccf09849f4e879c0dbf098d4697 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 18:59:04 2015 +0200 chromeos: Add missing headers Builds with CHROMEOS fail due to missing includes. Change-Id: I8c88bca8f8cc3247d3f3311777f794c4fdfee3c1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/romstage/romstage.c | 1 + src/vendorcode/google/chromeos/vboot.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 1741ae6..c026004 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -38,6 +38,7 @@ #include <soc/reset.h> #include <soc/romstage.h> #include <soc/spi.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c index a151f54..6f5534a 100644 --- a/src/vendorcode/google/chromeos/vboot.c +++ b/src/vendorcode/google/chromeos/vboot.c @@ -19,6 +19,7 @@ #include <types.h> #include <console/console.h> +#include <console/cbmem_console.h> #include <arch/acpi.h> #include <tpm.h> #include <reset.h>

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Patch merged into coreboot/master: e1133b7 kbuild: automatically include northbridges
by gerrit＠coreboot.org 29 Apr '15

29 Apr '15

the following patch was just integrated into master: commit e1133b7d7d353480e135bf0f94e4d0f94a617360 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 27 14:04:38 2015 -0700 kbuild: automatically include northbridges This change switches all northbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in northbridge/Makefile.inc or in northbridge/<vendor>/Makefile.inc. This means, vendor and northbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I8468154dbfaaaffcba9fda27ba2d7b9049ad5c19 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/9800 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9800 for details. -gerrit

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Patch merged into coreboot/master: aae53ab kbuild: automatically include SOCs
by gerrit＠coreboot.org 29 Apr '15

29 Apr '15

the following patch was just integrated into master: commit aae53ab76aa818bcf3a7df1e44a80289a2ac6018 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 27 14:03:57 2015 -0700 kbuild: automatically include SOCs This change switches all SOC vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in soc/Makefile.inc or in soc/<vendor>/Makefile.inc. This means, vendor and SOC directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/9799 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9799 for details. -gerrit

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Patch merged into coreboot/master: 77c04e9 kbuild: automatically include ECs
by gerrit＠coreboot.org 29 Apr '15

29 Apr '15

the following patch was just integrated into master: commit 77c04e95bac0b56ced7deec1f41c0c5b6b9f8ee5 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 27 14:03:47 2015 -0700 kbuild: automatically include ECs This change switches all ECs and the generic EC ACPI code to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in ec/Makefile.inc or in ec/<vendor>/Makefile.inc. This means, vendor and ec directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I29d757d1f8c10a1d0167a76fd0d0f97bac576f6d Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/9798 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9798 for details. -gerrit

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Patch merged into coreboot/master: e2c2bb9 dmp/vortex86: move PLL config to cpu Kconfig
by gerrit＠coreboot.org 29 Apr '15

29 Apr '15

the following patch was just integrated into master: commit e2c2bb944717f808de47a9c473a1885086c64425 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Mar 26 22:33:31 2015 -0600 dmp/vortex86: move PLL config to cpu Kconfig This moves the vortex86ex cpu's pll configuration out of the mainboard and into the cpu's Kconfig. Change-Id: I72ee1baa3a96586fceff03ff43c5f61e2498667e Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/9058 Tested-by: build bot (Jenkins) Reviewed-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/9058 for details. -gerrit

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Patch merged into coreboot/master: f20046f mainboard/intel: Drop unused onboard.h files
by gerrit＠coreboot.org 29 Apr '15

29 Apr '15

the following patch was just integrated into master: commit f20046f5cf682ea0318d4c6d69c2cf05e3a72e76 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 24 15:41:18 2015 +0300 mainboard/intel: Drop unused onboard.h files Change-Id: I0851375f419202f62ddc8c80fa77e1d8c95ed50f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/9991 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9991 for details. -gerrit

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Patch merged into coreboot/master: 1b7c959 crossgcc: don't use libdl while building GDB on FreeBSD
by gerrit＠coreboot.org 29 Apr '15

29 Apr '15

the following patch was just integrated into master: commit 1b7c9590f4bcbb82cbea7cdbbf9d423086c96b35 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Thu Apr 9 15:34:07 2015 +0200 crossgcc: don't use libdl while building GDB on FreeBSD Since FreeBSD doesn't have libdl, these errors are shown: - config.log: /usr/bin/ld: cannot find -ldl - crossgcc-build.log: configure: error: C compiler cannot create executables Conditionally pass the presence of libdl in LDFLAGS. Change-Id: I79c48da7e6700a4606c9e0c1314241db8997d3f3 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-on: http://review.coreboot.org/2342 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/2342 for details. -gerrit

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coreboot-gerrit April 2015