coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: d38a72f program loading: add optional is_loader_active() callback
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10022 -gerrit commit d38a72fba740f3aaed455088564d3a245efe00f5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 28 15:59:12 2015 -0500 program loading: add optional is_loader_active() callback Add a way for a loader to indicate if it is active. Such users of this callback would be vboot which can indicate to the rest of the system that it isn't active. is_loader_active() also gives vboot a chance to perform the necessary work to make said decision. Change-Id: I6679ac75b19bb1bfff9c2b709da5591986f752ff Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/program_loading.h | 3 +++ src/lib/loaders/load_and_run_payload.c | 17 +++++++++++++++++ src/lib/loaders/load_and_run_ramstage.c | 19 ++++++++++++++++++- src/lib/loaders/load_and_run_romstage.c | 17 ++++++++++++++++- 4 files changed, 54 insertions(+), 2 deletions(-) diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 02e6f5f..ca80b0e 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -103,6 +103,9 @@ void platform_prog_run(struct prog *prog); struct prog_loader_ops { const char *name; + /* Determine if the loader is the active one. If so returns 1 else 0 + * or < 0 on error. */ + int (*is_loader_active)(struct prog *prog); /* Returns < 0 on error or 0 on success. This function needs to do * different things depending on the prog type. See definition * of struct prog above. */ diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 0e08d88..7a08097 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -54,7 +54,24 @@ void payload_load(void) struct prog *payload = &global_payload; for (i = 0; i < ARRAY_SIZE(payload_ops); i++) { + /* Default loader state is active. */ + int ret = 1; + ops = payload_ops[i]; + + if (ops->is_loader_active != NULL) + ret = ops->is_loader_active(payload); + + if (ret == 0) { + printk(BIOS_DEBUG, "%s payload loader inactive.\n", + ops->name); + continue; + } else if (ret < 0) { + printk(BIOS_DEBUG, "%s payload loader failure.\n", + ops->name); + continue; + } + if (ops->prepare(payload) < 0) { printk(BIOS_DEBUG, "%s: could not locate payload.\n", ops->name); diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c index 153e38e..fddea4d 100644 --- a/src/lib/loaders/load_and_run_ramstage.c +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -83,8 +83,25 @@ void run_ramstage(void) run_ramstage_from_resume(romstage_handoff_find_or_add(), &ramstage); for (i = 0; i < ARRAY_SIZE(loaders); i++) { + /* Default loader state is active. */ + int ret = 1; + ops = loaders[i]; - printk(BIOS_DEBUG, "Trying %s ramstage loader.\n", ops->name); + + if (ops->is_loader_active != NULL) + ret = ops->is_loader_active(&ramstage); + + if (ret == 0) { + printk(BIOS_DEBUG, "%s ramstage loader inactive.\n", + ops->name); + continue; + } else if (ret < 0) { + printk(BIOS_DEBUG, "%s ramstage loader failure.\n", + ops->name); + continue; + } + + printk(BIOS_DEBUG, "%s ramstage loader active.\n", ops->name); load_ramstage(ops, &ramstage); } diff --git a/src/lib/loaders/load_and_run_romstage.c b/src/lib/loaders/load_and_run_romstage.c index 1c2ed77..b54bfc7 100644 --- a/src/lib/loaders/load_and_run_romstage.c +++ b/src/lib/loaders/load_and_run_romstage.c @@ -41,11 +41,26 @@ void run_romstage(void) }; for (i = 0; i < ARRAY_SIZE(loaders); i++) { + /* Default loader state is active. */ + int ret = 1; const struct prog_loader_ops *ops; ops = loaders[i]; - printk(BIOS_DEBUG, "Trying %s romstage loader.\n", ops->name); + if (ops->is_loader_active != NULL) + ret = ops->is_loader_active(&romstage); + + if (ret == 0) { + printk(BIOS_DEBUG, "%s romstage loader inactive.\n", + ops->name); + continue; + } else if (ret < 0) { + printk(BIOS_DEBUG, "%s romstage loader failure.\n", + ops->name); + continue; + } + + printk(BIOS_DEBUG, "%s romstage loader active.\n", ops->name); timestamp_add_now(TS_START_COPYROM);

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Patch set updated for coreboot: 20c2bf5 vboot: add and rejuggle Kconfig options
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10024 -gerrit commit 20c2bf5cd60f515a132863e487b4532202bfd3b6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 28 16:17:25 2015 -0500 vboot: add and rejuggle Kconfig options The ChromeOS machines employing vboot verfication require different combinations of support: 1. When vboot verification starts. 2. Is the vboot code a separate stage or program? 3. If a separate stage, does the that vboot program (verstage) return to the stage that loaded the verstage? For the above, #1 is dependent on when to load/run vboot logic which is orthogonal to #2. However, #3 is dependent on #2. The logic to act on the combinations follows in subsequent patches. Change-Id: I39ef7a7c2858e7de43aa99c38121e85a57f1f2f6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/marvell/bg4cd/Kconfig | 2 +- src/vendorcode/google/chromeos/vboot2/Kconfig | 37 ++++++++++++++-------- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 4 +++ 3 files changed, 28 insertions(+), 15 deletions(-) diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig index 96fd8ef..9c0dc14 100644 --- a/src/soc/marvell/bg4cd/Kconfig +++ b/src/soc/marvell/bg4cd/Kconfig @@ -32,7 +32,7 @@ config SOC_MARVELL_BG4CD select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select GENERIC_GPIO_LIB - select VERSTAGE_IN_BOOTBLOCK + select VBOOT_STARTS_IN_BOOTBLOCK if SOC_MARVELL_BG4CD diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig index 3b5c594..8396113 100644 --- a/src/vendorcode/google/chromeos/vboot2/Kconfig +++ b/src/vendorcode/google/chromeos/vboot2/Kconfig @@ -16,6 +16,20 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +config VBOOT_STARTS_IN_BOOTBLOCK + bool + default n + depends on VBOOT_VERIFY_FIRMWARE + help + Firmware verification happens during or at the end of bootblock. + +config VBOOT_STARTS_IN_ROMSTAGE + bool + default n + depends on VBOOT_VERIFY_FIRMWARE && !VBOOT_STARTS_IN_BOOTBLOCK + help + Firmware verification happens during or at the end of romstage. + config VBOOT2_MOCK_SECDATA bool "Mock secdata for firmware verification" default n @@ -27,16 +41,6 @@ config VBOOT2_MOCK_SECDATA can be used during development when a TPM is not present or broken. THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES. -config RETURN_FROM_VERSTAGE - bool "return from verstage" - default n - depends on VBOOT_VERIFY_FIRMWARE - help - If this is set, the verstage returns back to the bootblock instead of - exits to the romstage so that the verstage space can be reused by the - romstage. Useful if a ram space is too small to fit both the verstage - and the romstage. - config VBOOT_DISABLE_DEV_ON_RECOVERY bool "Disable dev mode on recovery requests" default n @@ -46,15 +50,20 @@ config VBOOT_DISABLE_DEV_ON_RECOVERY developer mode as soon as recovery request is detected. This is handy on embedded devices with limited input capabilities. -config VERSTAGE_IN_BOOTBLOCK +config SEPARATE_VERSTAGE bool default n depends on VBOOT_VERIFY_FIRMWARE -config SEPARATE_VERSTAGE +config RETURN_FROM_VERSTAGE bool - default !VERSTAGE_IN_BOOTBLOCK - depends on VBOOT_VERIFY_FIRMWARE + default n + depends on SEPARATE_VERSTAGE + help + If this is set, the verstage returns back to the calling stage instead + of exiting to the succeeding stage so that the verstage space can be + reused by the succeeding stage. This is useful if a ram space is too + small to fit both the verstage and the succeeding stage. # These VBOOT_X_INDEX are the position of X in FW_MAIN_A/B region. The index # table is created by cros_bundle_firmware at build time based on the positions diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index b2d2dc1..4c53aed 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -63,5 +63,9 @@ fallback/verstage-file = $(objcbfs)/verstage.elf fallback/verstage-type = stage fallback/verstage-compression = none else +ifeq ($(VBOOT_STARTS_IN_BOOTBLOCK),y) bootblock-srcs += $(objgenerated)/libverstage.a +else +romstage-srcs += $(objgenerated)/libverstage.a endif +endif # CONFIG_SEPARATE_VERSTAGE

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Patch set updated for coreboot: 652d421 cpu/intel/haswell: remove dependency on socket_rpga989
by Matt DeVillier 30 Apr '15

30 Apr '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10037 -gerrit commit 652d421834e9e61494bcdd2d80f152aaa907d319 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Apr 30 01:19:16 2015 -0500 cpu/intel/haswell: remove dependency on socket_rpga989 Remove dependency of Haswell on cpu/intel/socket_rpga989 code, which is a carry-over from Sandy Bridge/Ivy Bridge and older coreboot conventions where features were structured around socket types. Add CPU-specific options to Kconfig and required subdirs to Makefile.inc which are curently included with socket_rpga989. TEST=successfully built and booted on google/panther Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/intel/haswell/Kconfig | 2 ++ src/cpu/intel/haswell/Makefile.inc | 8 ++++++++ src/mainboard/google/bolt/Kconfig | 2 +- src/mainboard/google/bolt/devicetree.cb | 4 +--- src/mainboard/google/falco/Kconfig | 2 +- src/mainboard/google/falco/devicetree.cb | 4 +--- src/mainboard/google/panther/Kconfig | 2 +- src/mainboard/google/panther/devicetree.cb | 8 +++----- src/mainboard/google/peppy/Kconfig | 2 +- src/mainboard/google/peppy/devicetree.cb | 4 +--- src/mainboard/google/slippy/Kconfig | 2 +- src/mainboard/google/slippy/devicetree.cb | 4 +--- src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/baskingridge/devicetree.cb | 4 +--- 14 files changed, 24 insertions(+), 26 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 741b677..00fb1d7 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -12,6 +12,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select SMP + select MMX + select SSE select SSE2 select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 82d3bec..0db0475 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -14,3 +14,11 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index c901b8f..1ec399e 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_BOLT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/bolt/devicetree.cb b/src/mainboard/google/bolt/devicetree.cb index f514bb4..1d1eab5 100644 --- a/src/mainboard/google/bolt/devicetree.cb +++ b/src/mainboard/google/bolt/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index c836110..0f020f5 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_FALCO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index 428a060..7a8e757 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 6fdb46c..f172166 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_PANTHER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index d37b622..ad39edc 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -10,11 +10,9 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell # Magic APIC ID to locate this chip + device lapic 0 on end device lapic 0xACAC off end register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) @@ -123,12 +121,12 @@ chip northbridge/intel/haswell io 0x60 = 0x720 io 0x62 = 0x730 end - device pnp 2e.5 on + device pnp 2e.5 off io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end # Keyboard - device pnp 2e.6 on + device pnp 2e.6 off irq 0x70 = 12 end # Mouse device pnp 2e.a off end # IR diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 05234d0..6affd34 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_PEPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb index 4c0d02d..894d3ef 100644 --- a/src/mainboard/google/peppy/devicetree.cb +++ b/src/mainboard/google/peppy/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 48e5825..2857c0a 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_SLIPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 06ca93c..f50882c 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 485ff75..b636e5b 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -2,7 +2,7 @@ if BOARD_INTEL_BASKING_RIDGE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index a173aaa..cd341d1 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -10,10 +10,8 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end

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Patch set updated for coreboot: 13e72f5 dmp/vortex86: fix missing if CPU_DMP_VORTEX86EX / endif
by Matt DeVillier 30 Apr '15

30 Apr '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10038 -gerrit commit 13e72f5a3008502a5880416b0945cba002df128e Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Apr 30 01:35:57 2015 -0500 dmp/vortex86: fix missing if CPU_DMP_VORTEX86EX / endif e2c2bb9 moved a config selection from the mainboard to the associated CPU, but neglected to properly restrict it, resulting the the selection option being present/requried for all CPUs Change-Id: Ifecf291b985ab9d0d13d6b1264d3bc9a314b8546 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/dmp/vortex86ex/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index b14be7d..733de8b 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -19,6 +19,10 @@ config CPU_DMP_VORTEX86EX bool + +if CPU_DMP_VORTEX86EX + +config CPU_SPECIFIC_OPTIONS select ARCH_BOOTBLOCK_X86_32 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 @@ -71,3 +75,5 @@ config PLL_500_375_33 bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz" endchoice + +endif

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New patch to review for coreboot: 08cebba dmp/vortex86ex: fix missing if CPU_DMP_VORTEX86EX / endif
by Matt DeVillier 30 Apr '15

30 Apr '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10038 -gerrit commit 08cebba23c6b7e312aa3d3324288d3b9eddce49d Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Apr 30 01:35:57 2015 -0500 dmp/vortex86ex: fix missing if CPU_DMP_VORTEX86EX / endif Change-Id: Ifecf291b985ab9d0d13d6b1264d3bc9a314b8546 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/dmp/vortex86ex/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index b14be7d..733de8b 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -19,6 +19,10 @@ config CPU_DMP_VORTEX86EX bool + +if CPU_DMP_VORTEX86EX + +config CPU_SPECIFIC_OPTIONS select ARCH_BOOTBLOCK_X86_32 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 @@ -71,3 +75,5 @@ config PLL_500_375_33 bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz" endchoice + +endif

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New patch to review for coreboot: 82b2291 cpu/intel/haswell: remove dependency on socket_rpga989
by Matt DeVillier 30 Apr '15

30 Apr '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10037 -gerrit commit 82b2291b99cfeb4d3841a12e6836234c7a8e9240 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Apr 30 01:19:16 2015 -0500 cpu/intel/haswell: remove dependency on socket_rpga989 Remove dependency of Haswell on cpu/intel/socket_rpga989 code, which is a carry-over from SandyBridge/IvyBridge and older coreboot conventions where features were structured around socket types. Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/intel/haswell/Kconfig | 2 ++ src/cpu/intel/haswell/Makefile.inc | 8 ++++++++ src/mainboard/google/bolt/Kconfig | 2 +- src/mainboard/google/bolt/devicetree.cb | 4 +--- src/mainboard/google/falco/Kconfig | 2 +- src/mainboard/google/falco/devicetree.cb | 4 +--- src/mainboard/google/panther/Kconfig | 2 +- src/mainboard/google/panther/devicetree.cb | 8 +++----- src/mainboard/google/peppy/Kconfig | 2 +- src/mainboard/google/peppy/devicetree.cb | 4 +--- src/mainboard/google/slippy/Kconfig | 2 +- src/mainboard/google/slippy/devicetree.cb | 4 +--- src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/baskingridge/devicetree.cb | 4 +--- 14 files changed, 24 insertions(+), 26 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 741b677..00fb1d7 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -12,6 +12,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select SMP + select MMX + select SSE select SSE2 select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 82d3bec..0db0475 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -14,3 +14,11 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index c901b8f..1ec399e 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_BOLT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/bolt/devicetree.cb b/src/mainboard/google/bolt/devicetree.cb index f514bb4..1d1eab5 100644 --- a/src/mainboard/google/bolt/devicetree.cb +++ b/src/mainboard/google/bolt/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index c836110..0f020f5 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_FALCO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index 428a060..7a8e757 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 6fdb46c..f172166 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_PANTHER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index d37b622..ad39edc 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -10,11 +10,9 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell # Magic APIC ID to locate this chip + device lapic 0 on end device lapic 0xACAC off end register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) @@ -123,12 +121,12 @@ chip northbridge/intel/haswell io 0x60 = 0x720 io 0x62 = 0x730 end - device pnp 2e.5 on + device pnp 2e.5 off io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end # Keyboard - device pnp 2e.6 on + device pnp 2e.6 off irq 0x70 = 12 end # Mouse device pnp 2e.a off end # IR diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 05234d0..6affd34 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_PEPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb index 4c0d02d..894d3ef 100644 --- a/src/mainboard/google/peppy/devicetree.cb +++ b/src/mainboard/google/peppy/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 48e5825..2857c0a 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -2,7 +2,7 @@ if BOARD_GOOGLE_SLIPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 06ca93c..f50882c 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -22,10 +22,8 @@ chip northbridge/intel/haswell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 485ff75..b636e5b 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -2,7 +2,7 @@ if BOARD_INTEL_BASKING_RIDGE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 + select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index a173aaa..cd341d1 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -10,10 +10,8 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end chip cpu/intel/haswell + device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end

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Patch set updated for coreboot: b5593ab crossgcc: Re-download the archive if it is incomplete
by Zheng Bao 30 Apr '15

30 Apr '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4511 -gerrit commit b5593ab170c7935db077ac849f7595b2e9f418dc Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 30 04:44:07 2015 +0800 crossgcc: Re-download the archive if it is incomplete If the buildgcc is interrupt by Ctrl-C, probably part of an archive is downloaded. If we run buildgcc again, the incomplete archive would be considered as cached file and skipped. We check file hashes to see if the file is complete. If test is failed, we need to delete the partially-downloaded file and download it again. sha1sum is quite different among the distributions. Only Linux, Cygwin, Darwin have been tested. Once new archive is deployed, a new checksum would be created, which should be uploaded along with the script buildgcc. Change-Id: Ibb1aa25a0374f774e1e643fe5e698de7bf7cc418 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/crossgcc/buildgcc | 41 +++++++++++++++++++++- .../crossgcc/sum/acpica-unix-20150204.tar.gz.cksum | 1 + util/crossgcc/sum/binutils-2.25.tar.bz2.cksum | 1 + util/crossgcc/sum/gcc-4.9.2.tar.bz2.cksum | 1 + util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum | 1 + util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum | 1 + util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum | 1 + util/crossgcc/sum/mpfr-3.1.2.tar.bz2.cksum | 1 + 8 files changed, 47 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a29a338..02a7d82 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -125,6 +125,26 @@ searchtool() fi fi fi + if [ "`echo $1 | cut -b -3`" = "sha" ]; then + if [ $UNAME = "FreeBSD" ]; then + if test -x "`which sha1 2>/dev/null`"; then + echo sha1 + return + fi + fi + if [ $UNAME = "NetBSD" ]; then + if test -x "`which cksum 2>/dev/null`"; then + echo cksum -a `echo $1 | sed -e 's,sum,,'` + return + fi + fi + if [ $UNAME = "Darwin" ]; then + if test -x "`which openssl 2>/dev/null`"; then + echo openssl `echo $1 | sed -e 's,sum,,'` + return + fi + fi + fi printf "${RED}ERROR:${red} Missing tool: Please install $1 (eg using your OS packaging system)${NC}\n" >&2 [ -z "$3" ] && exit 1 false @@ -151,6 +171,10 @@ wait_for_build() { true } +SHA1SUM=`searchtool sha1sum` +SHA512SUM=`searchtool sha512sum` +CHECKSUM=$SHA1SUM + cleanup() { printf "Cleaning up temporary files... " @@ -295,10 +319,25 @@ for ARCHIVE in $GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE \ $IASL_ARCHIVE $PYTHON_ARCHIVE $EXPAT_ARCHIVE; do FILE=`basename $ARCHIVE` printf " * $FILE " - test -f tarballs/$FILE && printf "(cached)" || ( + + ##create the sum + #test -f sum/$FILE.cksum || ( + # $CHECKSUM tarballs/$FILE > sum/$FILE.cksum + # continue + #) + + test -f tarballs/$FILE && \ + (test -z "$CHECKSUM" || \ + test "`cat sum/$FILE.cksum 2>/dev/null | sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,'`" = "`$CHECKSUM tarballs/$FILE 2>/dev/null | sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,'`" ) && \ + printf "(cached)" || ( printf "(downloading)" + rm -f tarballs/$FILE cd tarballs wget --no-check-certificate -q $ARCHIVE + cd .. + test ! -f sum/$FILE.cksum && test -f tarballs/$FILE && \ + (test -z "$CHECKSUM" || $CHECKSUM tarballs/$FILE > sum/$FILE.cksum ) && \ + printf "(checksum created. ${RED}Note. Please upload sum/$FILE.cksum if the corresponding archive is upgraded.${NC})" ) test -f tarballs/$FILE || \ printf "\n${RED}Failed to download $FILE.${NC}\n" diff --git a/util/crossgcc/sum/acpica-unix-20150204.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20150204.tar.gz.cksum new file mode 100644 index 0000000..c2f201f --- /dev/null +++ b/util/crossgcc/sum/acpica-unix-20150204.tar.gz.cksum @@ -0,0 +1 @@ +e8ab49a9cd47ec1f3542b4185852bb49814c7694 tarballs/acpica-unix-20150204.tar.gz diff --git a/util/crossgcc/sum/binutils-2.25.tar.bz2.cksum b/util/crossgcc/sum/binutils-2.25.tar.bz2.cksum new file mode 100644 index 0000000..1f339d4 --- /dev/null +++ b/util/crossgcc/sum/binutils-2.25.tar.bz2.cksum @@ -0,0 +1 @@ +b46cc90ebaba7ffcf6c6d996d60738881b14e50d tarballs/binutils-2.25.tar.bz2 diff --git a/util/crossgcc/sum/gcc-4.9.2.tar.bz2.cksum b/util/crossgcc/sum/gcc-4.9.2.tar.bz2.cksum new file mode 100644 index 0000000..b1d8c46 --- /dev/null +++ b/util/crossgcc/sum/gcc-4.9.2.tar.bz2.cksum @@ -0,0 +1 @@ +79dbcb09f44232822460d80b033c962c0237c6d8 tarballs/gcc-4.9.2.tar.bz2 diff --git a/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum b/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum new file mode 100644 index 0000000..67d60bf --- /dev/null +++ b/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum @@ -0,0 +1 @@ +360802e3541a3da08ab4b55268c80f799939fddc tarballs/gmp-6.0.0a.tar.bz2 diff --git a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum new file mode 100644 index 0000000..daa27c6 --- /dev/null +++ b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum @@ -0,0 +1 @@ +c1d6ac5f182d19dd685c4dfd74eedbfe3992425d tarballs/libelf-0.8.13.tar.gz diff --git a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum new file mode 100644 index 0000000..c7ca1ac --- /dev/null +++ b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum @@ -0,0 +1 @@ +b8be66396c726fdc36ebb0f692ed8a8cca3bcc66 tarballs/mpc-1.0.3.tar.gz diff --git a/util/crossgcc/sum/mpfr-3.1.2.tar.bz2.cksum b/util/crossgcc/sum/mpfr-3.1.2.tar.bz2.cksum new file mode 100644 index 0000000..d62e243 --- /dev/null +++ b/util/crossgcc/sum/mpfr-3.1.2.tar.bz2.cksum @@ -0,0 +1 @@ +46d5a11a59a4e31f74f73dd70c5d57a59de2d0b4 tarballs/mpfr-3.1.2.tar.bz2

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Patch merged into coreboot/master: ae5ab60 crossgcc: improve error message on missing tools
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit ae5ab604d51815bfed964017fad815c002aca9fe Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 23:30:15 2015 +0200 crossgcc: improve error message on missing tools People were confused about the 'missing toolchain', so improve the error message. Change-Id: Icaee338aeedce2255bcfdafe5407c9df02ad9c4a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10036 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/10036 for details. -gerrit

1 0

Patch merged into coreboot/master: b817908 cbmem: Add FSP timestamps
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit b8179087afea63bc10c950eb3406b4fc94a3997f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Feb 24 11:30:38 2015 -0800 cbmem: Add FSP timestamps Add additional FSP timestamp values to cbmem.h and specify values for the existing ones. Update cbmem.c with the FSP timestamp values and descriptions. BRANCH=none BUG=None TEST=Build for Braswell and Skylake boards using FSP 1.1. Change-Id: I835bb090ff5877a108e48cb60f8e80260773771b Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10025 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10025 for details. -gerrit

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Patch merged into coreboot/master: bdd9825 cbmem: Identify the FSP areas in CBMEM
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit bdd98254abf964692f193fe42ebffbd01d0b22b8 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Apr 28 18:21:25 2015 -0700 cbmem: Identify the FSP areas in CBMEM Add identifers and descriptions for the FSP areas within CBMEM. BRANCH=none BUG=None TEST=Build for Braswell and Skylake boards using FSP 1.1. Change-Id: I4d58f7f08cfbc17f3aef261c835b92d8d65f6622 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10026 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10026 for details. -gerrit

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