coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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3044 discussions

Patch merged into coreboot/master: 3e18aca chromeos: Add missing headers
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 3e18acabd3ea49133fcd507f09ff44aba7d92fe2 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 18:59:04 2015 +0200 chromeos: Add missing headers Builds with CHROMEOS fail due to missing includes. Change-Id: I8c88bca8f8cc3247d3f3311777f794c4fdfee3c1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10029 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10029 for details. -gerrit

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New patch to review for coreboot: 56a11d2 chromeos: Use __attribute__ normal form
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10044 -gerrit commit 56a11d2672d609bb0ad197de13722218926daf39 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 14:30:51 2015 +0200 chromeos: Use __attribute__ normal form Change-Id: Idf99c1491386578ac2471ca5cc8a153d2b5225e4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/vendorcode/google/chromeos/chromeos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index 1da9676..fb72673 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -50,7 +50,7 @@ void __attribute__((weak)) save_chromeos_gpios(void) // Can be implemented by a mainboard } -int __attribute((weak)) vboot_get_sw_write_protect(void) +int __attribute__((weak)) vboot_get_sw_write_protect(void) { // Can be implemented by a platform / mainboard return 0;

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New patch to review for coreboot: 77ab71f i2c/tpm: add final newline
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10043 -gerrit commit 77ab71f78ec2f8bcb4c9e9da90e0e46c3efc39b5 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 14:30:28 2015 +0200 i2c/tpm: add final newline Change-Id: I0024c4d56f93eb6c9a54103e79c9d8a8b7d8d6fb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/drivers/i2c/tpm/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/i2c/tpm/Makefile.inc b/src/drivers/i2c/tpm/Makefile.inc index 55c01de..e601136 100644 --- a/src/drivers/i2c/tpm/Makefile.inc +++ b/src/drivers/i2c/tpm/Makefile.inc @@ -1,3 +1,3 @@ ramstage-$(CONFIG_I2C_TPM) += tis.c tpm.c romstage-$(CONFIG_I2C_TPM) += tis.c tpm.c -verstage-$(CONFIG_I2C_TPM) += tis.c tpm.c \ No newline at end of file +verstage-$(CONFIG_I2C_TPM) += tis.c tpm.c

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New patch to review for coreboot: 140c273 arm/armv7: drop merge left-over
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10042 -gerrit commit 140c2733154075f3c7b0712adc147a29cef763b6 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 14:30:08 2015 +0200 arm/armv7: drop merge left-over Change-Id: Ie0b6c90e9ce89d564e3345d2746297f39ba9121d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/arm/armv7/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 3a71d98..3d1043f 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -91,8 +91,6 @@ verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ## ROM stage ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y) ->>>>>>> 34b838e... armv7-m: add armv7-m configuration - romstage-y += cache.c romstage-y += cpu.S romstage-y += exception.c

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New patch to review for coreboot: c576ef2 vboot: split class in library and stage
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10041 -gerrit commit c576ef236e6b1b44b67eaf03da7a201b77f8e70d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 14:25:14 2015 +0200 vboot: split class in library and stage The build system includes a bunch of files into verstage that also exist in romstage - generic drivers etc. These create link time conflicts when trying to link both the verstage copy and romstage copy together in a combined configuration, so separate "stage" parts (that allow things to run) from "library" parts (that contain the vboot specifics) Change-Id: Ieed910fcd642693e5e89e55f3e6801887d94462f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 5 +++-- src/arch/arm/Makefile.inc | 4 ++-- src/arch/arm/armv4/Makefile.inc | 2 ++ src/arch/arm/armv7/Makefile.inc | 4 ++++ src/arch/arm64/Makefile.inc | 4 ++-- src/arch/arm64/armv8/Makefile.inc | 2 ++ src/drivers/i2c/ww_ring/Makefile.inc | 4 ++-- src/lib/Makefile.inc | 4 ++-- src/soc/qualcomm/ipq806x/Makefile.inc | 8 ++++---- src/soc/rockchip/rk3288/Makefile.inc | 2 +- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 14 +++++++------- toolchain.inc | 6 ++++-- 12 files changed, 35 insertions(+), 24 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 8c32c08..6403977 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -64,7 +64,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock smm smmstub cpu_microcode verstage secmon +classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage verstage secmon # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ @@ -138,6 +138,7 @@ endif ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) +libverstage-c-deps:=$$(OPTION_TABLE_H) verstage-c-deps:=$$(OPTION_TABLE_H) bootblock-c-deps:=$$(OPTION_TABLE_H) @@ -362,7 +363,7 @@ $(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) -MMD $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) $(bootblock-c-ccopts) -c -o $@ $< -$(objgenerated)/libverstage.a: $$(verstage-objs) +$(objgenerated)/libverstage.a: $$(libverstage-objs) rm -f $@ ar rcsT $@ $^ diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index afb8d20..c05b33e 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -73,9 +73,9 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) -$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld +$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(objgenerated)/libverstage.a --end-group + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group verstage-y += div0.c verstage-y += eabi_compat.c diff --git a/src/arch/arm/armv4/Makefile.inc b/src/arch/arm/armv4/Makefile.inc index 5f12a6a..6b01056 100644 --- a/src/arch/arm/armv4/Makefile.inc +++ b/src/arch/arm/armv4/Makefile.inc @@ -45,6 +45,8 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARMV4 ################################################################################ ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV4),y) +libverstage-c-ccopts += $(armv4_flags) +libverstage-S-ccopts += $(armv4_flags) verstage-c-ccopts += $(armv4_flags) verstage-S-ccopts += $(armv4_flags) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index e9daf11..3a71d98 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -66,6 +66,8 @@ bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ################################################################################ ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7),y) +libverstage-c-ccopts += $(armv7-a_flags) +libverstage-S-ccopts += $(armv7-a_asm_flags) verstage-c-ccopts += $(armv7-a_flags) verstage-S-ccopts += $(armv7-a_asm_flags) @@ -76,6 +78,8 @@ verstage-y += exception_asm.S verstage-y += mmu.c else ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7_M),y) +libverstage-c-ccopts += $(armv7-m_flags) +libverstage-S-ccopts += $(armv7-m_asm_flags) verstage-c-ccopts += $(armv7-m_flags) verstage-S-ccopts += $(armv7-m_asm_flags) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index adaba8e..3791ae7 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -84,9 +84,9 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM64 ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) -$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h +$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(verstage-objs)--end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c verstage-y += div0.c diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index d043921..19684b2 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -56,6 +56,8 @@ verstage-y += cpu.S verstage-y += cache_helpers.S verstage-y += exception.c +libverstage-c-ccopts += $(armv8_flags) +libverstage-S-ccopts += $(armv8_asm_flags) verstage-c-ccopts += $(armv8_flags) verstage-S-ccopts += $(armv8_asm_flags) diff --git a/src/drivers/i2c/ww_ring/Makefile.inc b/src/drivers/i2c/ww_ring/Makefile.inc index 56de190..eabd3bf 100644 --- a/src/drivers/i2c/ww_ring/Makefile.inc +++ b/src/drivers/i2c/ww_ring/Makefile.inc @@ -1,2 +1,2 @@ -verstage-$(CONFIG_DRIVERS_I2C_WW_RING) += ww_ring.c -verstage-$(CONFIG_DRIVERS_I2C_WW_RING) += ww_ring_programs.c +libverstage-$(CONFIG_DRIVERS_I2C_WW_RING) += ww_ring.c +libverstage-$(CONFIG_DRIVERS_I2C_WW_RING) += ww_ring_programs.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 318fe4d..82dd5c5 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -39,9 +39,9 @@ verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ifeq ($(MOCK_TPM),1) -verstage-y += mocked_tlcl.c +libverstage-y += mocked_tlcl.c else -verstage-y += tlcl.c +libverstage-y += tlcl.c endif verstage-$(CONFIG_GENERIC_UDELAY) += timer.c diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 3eb070e..8cf8d7a 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -27,10 +27,10 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += clock.c verstage-y += gpio.c -verstage-y += gsbi.c -verstage-y += i2c.c -verstage-y += qup.c -verstage-y += spi.c +libverstage-y += gsbi.c +libverstage-y += i2c.c +libverstage-y += qup.c +libverstage-y += spi.c verstage-y += timer.c verstage-$(CONFIG_CONSOLE_SERIAL_IPQ806X) += uart.c diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index be41327..0c7585a 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -39,7 +39,7 @@ verstage-y += timer.c verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += gpio.c verstage-y += clock.c -verstage-y += crypto.c +libverstage-y += crypto.c verstage-y += i2c.c verstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index 4c53aed..29115de 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -17,7 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ +libverstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ bootblock-y += ../vboot_common.c verstage-y += ../vboot_common.c @@ -25,14 +25,14 @@ romstage-y += ../vboot_common.c ramstage-y += ../vboot_common.c bootblock-y += verstub.c -verstage-y += verstub.c +libverstage-y += verstub.c bootblock-y += common.c -verstage-y += verstage.c +libverstage-y += verstage.c verstage-y += common.c ifeq (${CONFIG_VBOOT2_MOCK_SECDATA},y) -verstage-y += secdata_mock.c +libverstage-y += secdata_mock.c else -verstage-y += antirollback.c +libverstage-y += antirollback.c endif romstage-y += vboot_handoff.c common.c @@ -41,7 +41,7 @@ verstage-y += verstage.ld VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y)) VB2_LIB = $(obj)/external/vboot_reference/vboot_fw20.a VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%,$(filter-out -include $(src)/include/kconfig.h, $(CPPFLAGS_verstage))) -VBOOT_CFLAGS += $(verstage-c-ccopts) +VBOOT_CFLAGS += $(libverstage-c-ccopts) VBOOT_CFLAGS += -include $(top)/src/include/kconfig.h -Wno-missing-prototypes VBOOT_CFLAGS += -DVBOOT_DEBUG @@ -55,7 +55,7 @@ $(VB2_LIB): $(obj)/config.h V=$(V) \ fwlib20 -verstage-srcs += $(VB2_LIB) +libverstage-srcs += $(VB2_LIB) ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/verstage diff --git a/toolchain.inc b/toolchain.inc index 9820fa2..36402fe 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -51,7 +51,8 @@ HOSTCXX:=CCC_CXX="$(HOSTCXX)" $(CXX) ROMCC=CCC_CC="$(ROMCC_BIN)" $(CC) endif -COREBOOT_STANDARD_STAGES := bootblock verstage romstage ramstage +COREBOOT_STANDARD_STAGES := bootblock libverstage verstage romstage ramstage +MAP-libverstage := verstage ARCHDIR-i386 := x86 ARCHDIR-x86_32 := x86 @@ -81,8 +82,9 @@ toolchain_to_dir = \ # This step is essential for initializing the toolchain for coreboot standard # stages i.e. bootblock, romstage and ramstage, since it acts as the second # parameter to create_class_compiler below in init_standard_toolchain +map_stage = $(strip $(if $(MAP-$(1)),$(MAP-$(1)),$(1))) set_stage_toolchain= \ - $(foreach arch,$(ARCH_SUPPORTED),$(eval ARCH-$(1)-$($(shell echo CONFIG_ARCH_$(1)_$(arch) | tr '[:lower:]' '[:upper:]')) := $(arch))) + $(foreach arch,$(ARCH_SUPPORTED),$(eval ARCH-$(1)-$($(shell echo CONFIG_ARCH_$(call map_stage,$(1))_$(arch) | tr '[:lower:]' '[:upper:]')) := $(arch))) # create_class_compiler: Used to create compiler tool set for # special classes

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Patch set updated for coreboot: d20f528 arch/arm: only include subdirectories for ARM builds
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10032 -gerrit commit d20f5287810d560f3115fe3c2561c3fdf4f00eab Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 20:28:03 2015 +0200 arch/arm: only include subdirectories for ARM builds Change-Id: Ieac02fcc4508f7c1b194802453d6222b902a38a2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/arm/Makefile.inc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 272a495..afb8d20 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -20,11 +20,6 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -############################################################################### -# Take care of subdirectories -############################################################################### -subdirs-y += libgcc/ -subdirs-y += armv4/ armv7/ ############################################################################### # ARM specific options @@ -36,6 +31,9 @@ CBFSTOOL_PRE_OPTS = -b 0 endif ifeq ($(CONFIG_ARCH_ARM),y) +subdirs-y += libgcc/ +subdirs-y += armv4/ armv7/ + stages_c = $(src)/arch/arm/stages.c stages_o = $(obj)/arch/arm/stages.o

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Patch set updated for coreboot: 2f8e918 intel/broadwell: Build monotonic timer driver for SMM
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10033 -gerrit commit 2f8e91809b11b479ecbd26cc007699da8457aab8 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 20:43:44 2015 +0200 intel/broadwell: Build monotonic timer driver for SMM SPI flash drivers need it. Change-Id: I63d79472d70d75f7907e7620755c228d5a4918e1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 8b4a0c1..d7845e6 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -33,6 +33,7 @@ ramstage-y += memmap.c romstage-y += memmap.c ramstage-y += minihd.c ramstage-y += monotonic_timer.c +smm-y += monotonic_timer.c ramstage-y += pch.c romstage-y += pch.c ramstage-y += pcie.c

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Patch set updated for coreboot: 5485b3f intel/broadwell: Don't select MONOTONIC_TIMER_MSR
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10034 -gerrit commit 5485b3fe6284d1e9e535cce780ea7a1be1942578 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 20:44:06 2015 +0200 intel/broadwell: Don't select MONOTONIC_TIMER_MSR That's a Haswell exclusive, used nowhere else, but confusing when hunting for the monotonic timer used on that SoC. Change-Id: I60ec523e54e5af0d2a418bcb9145de452a3a4ea9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/samus/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 6 ------ 3 files changed, 8 deletions(-) diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index 664faf1..f655b29 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select MONOTONIC_TIMER_MSR select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 98b2790..5a064d1 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT - select MONOTONIC_TIMER_MSR select INTEL_INT15 select CHROMEOS_RAMOOPS_DYNAMIC diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 91249ee..695e495 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -174,12 +174,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs. -config MONOTONIC_TIMER_MSR - def_bool y - select HAVE_MONOTONIC_TIMER - help - Provide a monotonic timer using the 24MHz MSR counter. - config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n

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Patch set updated for coreboot: a5e062d build system: Drop another vboot1 remnant
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10040 -gerrit commit a5e062de70f1d6748be321acffad414424a45a23 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 11:47:07 2015 +0200 build system: Drop another vboot1 remnant The vboot stage is now done totally different, as a real stage, and handled in the right location (src/vendorcode/google/chromeos/vboot2/Makefile.inc), so drop this vboot1 file. Change-Id: Ie9a4ae257c2702ddcd217f5b4ef8d8f22b5099f4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 3 --- 1 file changed, 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index f1c9f15..8c32c08 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -604,9 +604,6 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " REVISION build.h\n" if [ -f $(obj)/build.h ]; then $(CBFSTOOL) $@.tmp add -f $(obj)/build.h -n revision -t raw; fi endif -ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) - $(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG) -endif ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y) $(CBFSTOOL) $@.tmp add-stage -f $(REFCODE_BLOB) -n $(CONFIG_CBFS_PREFIX)/refcode -c $(CBFS_COMPRESS_FLAG) endif

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Patch set updated for coreboot: b8bf5f8 chromeos: Add missing headers
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10029 -gerrit commit b8bf5f808429a190d137ef66726720142407b610 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 18:59:04 2015 +0200 chromeos: Add missing headers Builds with CHROMEOS fail due to missing includes. Change-Id: I8c88bca8f8cc3247d3f3311777f794c4fdfee3c1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/romstage/romstage.c | 1 + src/vendorcode/google/chromeos/vboot.c | 1 + src/vendorcode/google/chromeos/vboot_common.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 1741ae6..c026004 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -38,6 +38,7 @@ #include <soc/reset.h> #include <soc/romstage.h> #include <soc/spi.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c index a151f54..7216373 100644 --- a/src/vendorcode/google/chromeos/vboot.c +++ b/src/vendorcode/google/chromeos/vboot.c @@ -18,6 +18,7 @@ */ #include <types.h> +#include <console/cbmem_console.h> #include <console/console.h> #include <arch/acpi.h> #include <tpm.h> diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index 2e0ab2b..68aa314 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -20,6 +20,7 @@ #include <boot/coreboot_tables.h> #include <cbfs.h> #include <cbmem.h> +#include <console/cbmem_console.h> #include <console/console.h> #include <reset.h> #include <stddef.h>

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coreboot-gerrit April 2015