coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: c41fd4b arm/armv7: drop merge left-over
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit c41fd4b75c223d1ef44e8b7820a94801752790fc Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 14:30:08 2015 +0200 arm/armv7: drop merge left-over Fixes up commit 93d8e3c4 (armv7-m: add armv7-m configuration). Change-Id: Ie0b6c90e9ce89d564e3345d2746297f39ba9121d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10042 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10042 for details. -gerrit

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Patch set updated for coreboot: 88108c9 arm/armv7: drop merge left-over
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10042 -gerrit commit 88108c9e268b411681c1d36b8f53089220c375ad Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 14:30:08 2015 +0200 arm/armv7: drop merge left-over Fixes up commit 93d8e3c4 (armv7-m: add armv7-m configuration). Change-Id: Ie0b6c90e9ce89d564e3345d2746297f39ba9121d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/arm/armv7/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 3a71d98..3d1043f 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -91,8 +91,6 @@ verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ## ROM stage ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y) ->>>>>>> 34b838e... armv7-m: add armv7-m configuration - romstage-y += cache.c romstage-y += cpu.S romstage-y += exception.c

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Patch merged into coreboot/master: 27ef602 vboot: split class in library and stage
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 27ef602fab2074a5e524f9448b61f5b7c5a7b2d5 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 14:25:14 2015 +0200 vboot: split class in library and stage The build system includes a bunch of files into verstage that also exist in romstage - generic drivers etc. These create link time conflicts when trying to link both the verstage copy and romstage copy together in a combined configuration, so separate "stage" parts (that allow things to run) from "library" parts (that contain the vboot specifics). Change-Id: Ieed910fcd642693e5e89e55f3e6801887d94462f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10041 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10041 for details. -gerrit

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Patch merged into coreboot/master: 8ef8afb arch/arm: only include subdirectories for ARM builds
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 8ef8afbb38734fea50b926c94e994b2682328a0d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 20:28:03 2015 +0200 arch/arm: only include subdirectories for ARM builds Change-Id: Ieac02fcc4508f7c1b194802453d6222b902a38a2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10032 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10032 for details. -gerrit

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Patch merged into coreboot/master: b5e1984 intel/broadwell: Don't select MONOTONIC_TIMER_MSR
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit b5e1984594525878172fb17abf3939e71963a5ff Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 20:44:06 2015 +0200 intel/broadwell: Don't select MONOTONIC_TIMER_MSR That's a Haswell exclusive, used nowhere else, but confusing when hunting for the monotonic timer used on that SoC. Change-Id: I60ec523e54e5af0d2a418bcb9145de452a3a4ea9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10034 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10034 for details. -gerrit

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Patch merged into coreboot/master: e3f880e intel/broadwell: Build monotonic timer driver for SMM
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit e3f880e4d8c0a9c29451e08a1c30e4135af96076 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 20:43:44 2015 +0200 intel/broadwell: Build monotonic timer driver for SMM SPI flash drivers need it. Change-Id: I63d79472d70d75f7907e7620755c228d5a4918e1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10033 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10033 for details. -gerrit

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Patch merged into coreboot/master: fd5ed6b build system: Drop another vboot1 remnant
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit fd5ed6b7add4a3035a5c2be743a3783a88204d6a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 11:47:07 2015 +0200 build system: Drop another vboot1 remnant The vboot stage is now done totally different, as a real stage, and handled in the right location (src/vendorcode/google/chromeos/vboot2/Makefile.inc), so drop this vboot1 file. Change-Id: Ie9a4ae257c2702ddcd217f5b4ef8d8f22b5099f4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10040 for details. -gerrit

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Patch set updated for coreboot: 7c2094c vboot: split class in library and stage
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10041 -gerrit commit 7c2094c36670be79096f09aa7493e7faec08ef87 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 14:25:14 2015 +0200 vboot: split class in library and stage The build system includes a bunch of files into verstage that also exist in romstage - generic drivers etc. These create link time conflicts when trying to link both the verstage copy and romstage copy together in a combined configuration, so separate "stage" parts (that allow things to run) from "library" parts (that contain the vboot specifics). Change-Id: Ieed910fcd642693e5e89e55f3e6801887d94462f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 5 +++-- src/arch/arm/Makefile.inc | 4 ++-- src/arch/arm/armv4/Makefile.inc | 2 ++ src/arch/arm/armv7/Makefile.inc | 4 ++++ src/arch/arm64/Makefile.inc | 4 ++-- src/arch/arm64/armv8/Makefile.inc | 2 ++ src/drivers/i2c/ww_ring/Makefile.inc | 4 ++-- src/lib/Makefile.inc | 4 ++-- src/soc/qualcomm/ipq806x/Makefile.inc | 8 ++++---- src/soc/rockchip/rk3288/Makefile.inc | 2 +- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 14 +++++++------- toolchain.inc | 6 ++++-- 12 files changed, 35 insertions(+), 24 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 8c32c08..6403977 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -64,7 +64,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock smm smmstub cpu_microcode verstage secmon +classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage verstage secmon # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ @@ -138,6 +138,7 @@ endif ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) +libverstage-c-deps:=$$(OPTION_TABLE_H) verstage-c-deps:=$$(OPTION_TABLE_H) bootblock-c-deps:=$$(OPTION_TABLE_H) @@ -362,7 +363,7 @@ $(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) -MMD $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) $(bootblock-c-ccopts) -c -o $@ $< -$(objgenerated)/libverstage.a: $$(verstage-objs) +$(objgenerated)/libverstage.a: $$(libverstage-objs) rm -f $@ ar rcsT $@ $^ diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index afb8d20..c05b33e 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -73,9 +73,9 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) -$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld +$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(objgenerated)/libverstage.a --end-group + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group verstage-y += div0.c verstage-y += eabi_compat.c diff --git a/src/arch/arm/armv4/Makefile.inc b/src/arch/arm/armv4/Makefile.inc index 5f12a6a..6b01056 100644 --- a/src/arch/arm/armv4/Makefile.inc +++ b/src/arch/arm/armv4/Makefile.inc @@ -45,6 +45,8 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARMV4 ################################################################################ ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV4),y) +libverstage-c-ccopts += $(armv4_flags) +libverstage-S-ccopts += $(armv4_flags) verstage-c-ccopts += $(armv4_flags) verstage-S-ccopts += $(armv4_flags) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index e9daf11..3a71d98 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -66,6 +66,8 @@ bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ################################################################################ ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7),y) +libverstage-c-ccopts += $(armv7-a_flags) +libverstage-S-ccopts += $(armv7-a_asm_flags) verstage-c-ccopts += $(armv7-a_flags) verstage-S-ccopts += $(armv7-a_asm_flags) @@ -76,6 +78,8 @@ verstage-y += exception_asm.S verstage-y += mmu.c else ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7_M),y) +libverstage-c-ccopts += $(armv7-m_flags) +libverstage-S-ccopts += $(armv7-m_asm_flags) verstage-c-ccopts += $(armv7-m_flags) verstage-S-ccopts += $(armv7-m_asm_flags) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index adaba8e..3791ae7 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -84,9 +84,9 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM64 ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) -$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h +$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(verstage-objs)--end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c verstage-y += div0.c diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index d043921..19684b2 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -56,6 +56,8 @@ verstage-y += cpu.S verstage-y += cache_helpers.S verstage-y += exception.c +libverstage-c-ccopts += $(armv8_flags) +libverstage-S-ccopts += $(armv8_asm_flags) verstage-c-ccopts += $(armv8_flags) verstage-S-ccopts += $(armv8_asm_flags) diff --git a/src/drivers/i2c/ww_ring/Makefile.inc b/src/drivers/i2c/ww_ring/Makefile.inc index 56de190..eabd3bf 100644 --- a/src/drivers/i2c/ww_ring/Makefile.inc +++ b/src/drivers/i2c/ww_ring/Makefile.inc @@ -1,2 +1,2 @@ -verstage-$(CONFIG_DRIVERS_I2C_WW_RING) += ww_ring.c -verstage-$(CONFIG_DRIVERS_I2C_WW_RING) += ww_ring_programs.c +libverstage-$(CONFIG_DRIVERS_I2C_WW_RING) += ww_ring.c +libverstage-$(CONFIG_DRIVERS_I2C_WW_RING) += ww_ring_programs.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 318fe4d..82dd5c5 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -39,9 +39,9 @@ verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ifeq ($(MOCK_TPM),1) -verstage-y += mocked_tlcl.c +libverstage-y += mocked_tlcl.c else -verstage-y += tlcl.c +libverstage-y += tlcl.c endif verstage-$(CONFIG_GENERIC_UDELAY) += timer.c diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 3eb070e..8cf8d7a 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -27,10 +27,10 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += clock.c verstage-y += gpio.c -verstage-y += gsbi.c -verstage-y += i2c.c -verstage-y += qup.c -verstage-y += spi.c +libverstage-y += gsbi.c +libverstage-y += i2c.c +libverstage-y += qup.c +libverstage-y += spi.c verstage-y += timer.c verstage-$(CONFIG_CONSOLE_SERIAL_IPQ806X) += uart.c diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index be41327..0c7585a 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -39,7 +39,7 @@ verstage-y += timer.c verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += gpio.c verstage-y += clock.c -verstage-y += crypto.c +libverstage-y += crypto.c verstage-y += i2c.c verstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index 4c53aed..29115de 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -17,7 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ +libverstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ bootblock-y += ../vboot_common.c verstage-y += ../vboot_common.c @@ -25,14 +25,14 @@ romstage-y += ../vboot_common.c ramstage-y += ../vboot_common.c bootblock-y += verstub.c -verstage-y += verstub.c +libverstage-y += verstub.c bootblock-y += common.c -verstage-y += verstage.c +libverstage-y += verstage.c verstage-y += common.c ifeq (${CONFIG_VBOOT2_MOCK_SECDATA},y) -verstage-y += secdata_mock.c +libverstage-y += secdata_mock.c else -verstage-y += antirollback.c +libverstage-y += antirollback.c endif romstage-y += vboot_handoff.c common.c @@ -41,7 +41,7 @@ verstage-y += verstage.ld VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y)) VB2_LIB = $(obj)/external/vboot_reference/vboot_fw20.a VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%,$(filter-out -include $(src)/include/kconfig.h, $(CPPFLAGS_verstage))) -VBOOT_CFLAGS += $(verstage-c-ccopts) +VBOOT_CFLAGS += $(libverstage-c-ccopts) VBOOT_CFLAGS += -include $(top)/src/include/kconfig.h -Wno-missing-prototypes VBOOT_CFLAGS += -DVBOOT_DEBUG @@ -55,7 +55,7 @@ $(VB2_LIB): $(obj)/config.h V=$(V) \ fwlib20 -verstage-srcs += $(VB2_LIB) +libverstage-srcs += $(VB2_LIB) ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/verstage diff --git a/toolchain.inc b/toolchain.inc index 9820fa2..36402fe 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -51,7 +51,8 @@ HOSTCXX:=CCC_CXX="$(HOSTCXX)" $(CXX) ROMCC=CCC_CC="$(ROMCC_BIN)" $(CC) endif -COREBOOT_STANDARD_STAGES := bootblock verstage romstage ramstage +COREBOOT_STANDARD_STAGES := bootblock libverstage verstage romstage ramstage +MAP-libverstage := verstage ARCHDIR-i386 := x86 ARCHDIR-x86_32 := x86 @@ -81,8 +82,9 @@ toolchain_to_dir = \ # This step is essential for initializing the toolchain for coreboot standard # stages i.e. bootblock, romstage and ramstage, since it acts as the second # parameter to create_class_compiler below in init_standard_toolchain +map_stage = $(strip $(if $(MAP-$(1)),$(MAP-$(1)),$(1))) set_stage_toolchain= \ - $(foreach arch,$(ARCH_SUPPORTED),$(eval ARCH-$(1)-$($(shell echo CONFIG_ARCH_$(1)_$(arch) | tr '[:lower:]' '[:upper:]')) := $(arch))) + $(foreach arch,$(ARCH_SUPPORTED),$(eval ARCH-$(1)-$($(shell echo CONFIG_ARCH_$(call map_stage,$(1))_$(arch) | tr '[:lower:]' '[:upper:]')) := $(arch))) # create_class_compiler: Used to create compiler tool set for # special classes

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Patch merged into coreboot/master: ba2b1e3 i2c/tpm: add final newline
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit ba2b1e32b01c37950ca89e7e1533f6ba0834e3cf Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 14:30:28 2015 +0200 i2c/tpm: add final newline Change-Id: I0024c4d56f93eb6c9a54103e79c9d8a8b7d8d6fb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10043 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10043 for details. -gerrit

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Patch merged into coreboot/master: e360df0 chromeos: Use __attribute__ normal form
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit e360df0fe2cc5fa0e632573891cab5c4c617a576 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 14:30:51 2015 +0200 chromeos: Use __attribute__ normal form Change-Id: Idf99c1491386578ac2471ca5cc8a153d2b5225e4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10044 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10044 for details. -gerrit

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coreboot-gerrit April 2015