coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: d362d2d intel/broadwell: bootstate mechanism doesn't exist in SMM
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10030 -gerrit commit d362d2d63be55f9366a80f601286e2e5ab7e0101 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Apr 29 19:11:30 2015 +0200 intel/broadwell: bootstate mechanism doesn't exist in SMM So don't try to use it. Change-Id: Ia600ba654bde36d3ea8a0f3185afae00fe50bfe9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/intel/broadwell/spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 0fca059..44285a9 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -312,12 +312,14 @@ void spi_init(void) pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } +#ifndef __SMM__ static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); +#endif int spi_claim_bus(struct spi_slave *slave) {

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Patch merged into coreboot/master: 57e3728 vboot: add and rejuggle Kconfig options
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 57e37287f45cc4911accbea21cc9a9ac0f0adde7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 28 16:17:25 2015 -0500 vboot: add and rejuggle Kconfig options The ChromeOS machines employing vboot verfication require different combinations of support: 1. When vboot verification starts. 2. Is the vboot code a separate stage or program? 3. If a separate stage, does the that vboot program (verstage) return to the stage that loaded the verstage? For the above, #1 is dependent on when to load/run vboot logic which is orthogonal to #2. However, #3 is dependent on #2. The logic to act on the combinations follows in subsequent patches. Change-Id: I39ef7a7c2858e7de43aa99c38121e85a57f1f2f6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10024 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10024 for details. -gerrit

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Patch merged into coreboot/master: 5abcba7 vboot: move Kconfig options for stage indicies
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 5abcba71212bf162661b22aec7f8ad7141547668 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 28 16:02:17 2015 -0500 vboot: move Kconfig options for stage indicies With vboot1 out of the way place all the associated Kconfig options in vboot2's Kconfig file (excluding main vboot verify option). More options will be added to accomodate vboot's various combinations of use cases. Change-Id: I17b06d741a36a5e2fefb2757651a61bfed61ae1e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10023 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10023 for details. -gerrit

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Patch merged into coreboot/master: 5e8286b program loading: add optional is_loader_active() callback
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 5e8286bed6f18cd2a85b029911f97da21b38394d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 28 15:59:12 2015 -0500 program loading: add optional is_loader_active() callback Add a way for a loader to indicate if it is active. Such users of this callback would be vboot which can indicate to the rest of the system that it isn't active. is_loader_active() also gives vboot a chance to perform the necessary work to make said decision. Change-Id: I6679ac75b19bb1bfff9c2b709da5591986f752ff Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10022 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10022 for details. -gerrit

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Patch merged into coreboot/master: 16110e7 i945/gma: Fix wrong comment about the documentation.
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 16110e7ffaf417f98bef2a359ec522f6fc160ee5 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue Oct 14 07:33:53 2014 +0200 i945/gma: Fix wrong comment about the documentation. The GTT location is documented in the "309219" datasheet. For instance it can be found in the TOLUD register description. The 309219 datasheet is for the "Mobile Intel® 945 Express Chipset Family". It was published in 2008. Change-Id: I75ac095ebc577e031af566963ebffe9ed2587c96 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: http://review.coreboot.org/9622 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9622 for details. -gerrit

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Patch set updated for coreboot: acdcdf0 i945/gma: Fix wrong comment about the documentation.
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9622 -gerrit commit acdcdf0cc612c2dd0722cf8c2866cf8da9401258 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue Oct 14 07:33:53 2014 +0200 i945/gma: Fix wrong comment about the documentation. The GTT location is documented in the "309219" datasheet. For instance it can be found in the TOLUD register description. The 309219 datasheet is for the "Mobile Intel® 945 Express Chipset Family". It was published in 2008. Change-Id: I75ac095ebc577e031af566963ebffe9ed2587c96 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/northbridge/intel/i945/gma.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index cee0640..e5974c9 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -58,12 +58,7 @@ static int gtt_setup(void *mmiobase) /* * The Video BIOS places the GTT right below top of memory. - * - * It is not documented in the Intel 945 datasheet, but the Intel - * developers said that it is normally placed there. - * - * TODO: Add option to make the GTT size runtime configurable - */ + */ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; PGETBL_save = tom - 256 * KiB; PGETBL_save |= PGETBL_ENABLED;

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Patch merged into coreboot/master: 9616f3c kbuild: Don't require intel/common changes for every soc
by gerrit＠coreboot.org 30 Apr '15

30 Apr '15

the following patch was just integrated into master: commit 9616f3ceb7e6bb2a55b0de01a5364fca011a1ecb Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 29 10:45:22 2015 -0700 kbuild: Don't require intel/common changes for every soc In the true spirit of separating components more strictly and allowing to add new components to coreboot without touching existing code, move Intel common code selection to the soc Kconfig and out of src/soc/intel/common/Makefile.inc Change-Id: I0a70656bb9f4550b6088e9f45e68b5106c0eb9af Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10031 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10031 for details. -gerrit

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New patch to review for coreboot: a59d682 build system: Drop another vboot1 remnant
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10040 -gerrit commit a59d682489e2b736ea73046a483d6087958a0a30 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 11:47:07 2015 +0200 build system: Drop another vboot1 remnant The vboot stage is now done totally different, as a real stage, and handled in the right location (src/vendorcode/google/chromeos/vboot2/Makefile.inc), so drop this vboot1 file. Change-Id: Ie9a4ae257c2702ddcd217f5b4ef8d8f22b5099f4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 3 --- 1 file changed, 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index f1c9f15..8c32c08 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -604,9 +604,6 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " REVISION build.h\n" if [ -f $(obj)/build.h ]; then $(CBFSTOOL) $@.tmp add -f $(obj)/build.h -n revision -t raw; fi endif -ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) - $(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG) -endif ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y) $(CBFSTOOL) $@.tmp add-stage -f $(REFCODE_BLOB) -n $(CONFIG_CBFS_PREFIX)/refcode -c $(CBFS_COMPRESS_FLAG) endif

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New patch to review for coreboot: 8966917 imgtec/pistachio: Add comment on the unusual memory layout
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10039 -gerrit commit 8966917f5b412f235c0f97d91347f887dfdbbff2 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 11:38:13 2015 +0200 imgtec/pistachio: Add comment on the unusual memory layout To avoid having to dig up the constraints again, document the memory layout right in memlayout.ld. Change-Id: I298cc880ae462f5b197ab2f64beb2f0e0d9f5a7d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index e9f6c59..bc67447 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -42,7 +42,10 @@ SECTIONS PRERAM_CBFS_CACHE(0x1a00e000, 72K) SRAM_END(0x1a020000) - /* Bootblock executes out of KSEG0 and sets up the identity mapping. */ + /* Bootblock executes out of KSEG0 and sets up the identity mapping. + * This is identical to SRAM above, and thus also limited 64K and + * needs to avoid conflicts with items set up above. + */ BOOTBLOCK(0x9a000000, 20K) /*

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Patch set updated for coreboot: cf590c1 vboot: move Kconfig options for stage indicies
by Patrick Georgi 30 Apr '15

30 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10023 -gerrit commit cf590c1e944070c6389144b14fbe2a196e4b34cd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 28 16:02:17 2015 -0500 vboot: move Kconfig options for stage indicies With vboot1 out of the way place all the associated Kconfig options in vboot2's Kconfig file (excluding main vboot verify option). More options will be added to accomodate vboot's various combinations of use cases. Change-Id: I17b06d741a36a5e2fefb2757651a61bfed61ae1e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/Kconfig | 37 --------------------------- src/vendorcode/google/chromeos/vboot2/Kconfig | 37 +++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index a75237e..90e3505 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -140,43 +140,6 @@ config VBOOT_VERIFY_FIRMWARE Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the components of the firmware (stages, payload, etc). -# These VBOOT_X_INDEX are the position of X in FW_MAIN_A/B region. The index -# table is created by cros_bundle_firmware at build time based on the positions -# of the blobs listed in fmap.dts and stored at the top of FW_MAIN_A/B region. -# Unfortunately, there is no programmatical link between the blob list and the -# index number here. -config VBOOT_BOOT_LOADER_INDEX - hex "Bootloader component index" - default 0 - depends on VBOOT_VERIFY_FIRMWARE - help - This is the index of the bootloader component in the verified - firmware block. - -config VBOOT_REFCODE_INDEX - hex "Reference code firmware index" - default 1 - depends on VBOOT_VERIFY_FIRMWARE - help - This is the index of the reference code component in the verified - firmware block. - -config VBOOT_RAMSTAGE_INDEX - hex "Ramstage component index" - default 1 - depends on VBOOT_VERIFY_FIRMWARE - help - This is the index of the ramstage component in the verified - firmware block. - -config VBOOT_ROMSTAGE_INDEX - hex "Romstage component index" - default 2 - depends on VBOOT_VERIFY_FIRMWARE - help - This is the index of the romstage component in the verified - firmware block. - config NO_TPM_RESUME bool default n diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig index b27b5b7..3b5c594 100644 --- a/src/vendorcode/google/chromeos/vboot2/Kconfig +++ b/src/vendorcode/google/chromeos/vboot2/Kconfig @@ -55,3 +55,40 @@ config SEPARATE_VERSTAGE bool default !VERSTAGE_IN_BOOTBLOCK depends on VBOOT_VERIFY_FIRMWARE + +# These VBOOT_X_INDEX are the position of X in FW_MAIN_A/B region. The index +# table is created by cros_bundle_firmware at build time based on the positions +# of the blobs listed in fmap.dts and stored at the top of FW_MAIN_A/B region. +# Unfortunately, there is no programmatical link between the blob list and the +# index number here. +config VBOOT_ROMSTAGE_INDEX + hex "Romstage component index" + default 2 + depends on VBOOT_VERIFY_FIRMWARE + help + This is the index of the romstage component in the verified + firmware block. + +config VBOOT_RAMSTAGE_INDEX + hex "Ramstage component index" + default 1 + depends on VBOOT_VERIFY_FIRMWARE + help + This is the index of the ramstage component in the verified + firmware block. + +config VBOOT_REFCODE_INDEX + hex "Reference code firmware index" + default 1 + depends on VBOOT_VERIFY_FIRMWARE + help + This is the index of the reference code component in the verified + firmware block. + +config VBOOT_BOOT_LOADER_INDEX + hex "Bootloader component index" + default 0 + depends on VBOOT_VERIFY_FIRMWARE + help + This is the index of the bootloader component in the verified + firmware block.

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coreboot-gerrit April 2015