coreboot-gerrit March 2015

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Patch set updated for coreboot: c3026d0 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit
by Timothy Pearson 16 Mar '15

16 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8489 -gerrit commit c3026d016414e206fced099e80a3b6d930d9d90d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:27:58 2015 -0500 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. The CBMEM location code implicitly assumes TOM does not change between romstage and ramstage. TOM is set by romstage raminit, and is never changed by romstage or ramstage afterward. As the CBMEM location is positioned at a specific offset from TOM that is known to both romstage and ramstage early CBMEM is safe on Fam10h systems. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/ram_calc.c | 11 +++++++++++ src/mainboard/advansus/a785e-i/romstage.c | 1 + src/mainboard/amd/bimini_fam10/romstage.c | 1 + src/mainboard/amd/mahogany_fam10/romstage.c | 1 + src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 1 + src/mainboard/amd/tilapia_fam10/romstage.c | 1 + src/mainboard/asus/kfsn4-dre/romstage.c | 1 + src/mainboard/asus/m4a78-em/romstage.c | 1 + src/mainboard/asus/m4a785-m/romstage.c | 1 + src/mainboard/asus/m5a88-v/romstage.c | 1 + src/mainboard/avalue/eax-785e/romstage.c | 1 + src/mainboard/gigabyte/ma785gm/romstage.c | 1 + src/mainboard/gigabyte/ma785gmt/romstage.c | 1 + src/mainboard/gigabyte/ma78gm/romstage.c | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 + src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 + src/mainboard/jetway/pa78vm5/romstage.c | 1 + src/mainboard/msi/ms9652_fam10/romstage.c | 1 + src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 + src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 + src/mainboard/supermicro/h8scm_fam10/romstage.c | 1 + src/mainboard/tyan/s2912_fam10/romstage.c | 1 + src/northbridge/amd/amdfam10/Kconfig | 1 - src/northbridge/amd/amdfam10/northbridge.c | 3 --- src/southbridge/amd/sb700/early_setup.c | 5 +++++ src/southbridge/amd/sb700/lpc.c | 5 +++++ src/southbridge/amd/sb800/early_setup.c | 5 +++++ 27 files changed, 47 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c index 98b80e9..dcf4300 100644 --- a/src/cpu/amd/model_10xxx/ram_calc.c +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -22,6 +22,8 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#include <cbmem.h> + #include "ram_calc.h" uint64_t get_uma_memory_size(uint64_t topmem) @@ -41,3 +43,12 @@ uint64_t get_uma_memory_size(uint64_t topmem) return uma_size; } + +void *cbmem_top(void) +{ + uint32_t topmem = rdmsr(TOP_MEM).lo; + + topmem = topmem - get_uma_memory_size(topmem); + + return (void *) topmem; +} diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 19ce53e..c1c9a1b 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index d8a38d7..6d03685 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -198,6 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e6d7f2e..e53c64d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 76bc73f..ef15e83 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -312,6 +312,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index b7f6869..7d2f272 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 0dab8e8..44864f6 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -343,6 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); printk(BIOS_DEBUG, "disable_spd()\n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 7c93767..47b9c83 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 328955a..7ebec29 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index baa38ac..2339478 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index b586198..c1dbaa7 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -201,6 +201,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4ad3d2c..7b0168d 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 590bb93..d0d6c94 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a7b6b1b..8861ab6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index d7e8447..4aefcd2 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -204,6 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); bcm5785_early_setup(); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index b88baa3..991cd55 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 08b6398..df30a69 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -205,6 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 45f05a5..0bdcd38 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -231,6 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index bc1ca24..4615465 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -228,6 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 2be09bc..c8ed2df 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -292,6 +292,7 @@ post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index eb38a29..4c6292f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -212,6 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 74c0aaa..7dcca17 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -227,6 +227,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index ff7fb9c..37993aa 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES - select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 68c6e35..9206de7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -897,10 +897,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 94f33b7..0c37840 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -728,6 +728,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -742,5 +746,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 658e954..a5f11a6 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -88,6 +88,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; @@ -98,6 +102,7 @@ void backup_top_of_ram(uint64_t ramtop) nvram_pos++; } } +#endif static void sb700_lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 69bc3bd..300b54e 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -673,6 +673,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -687,5 +691,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif

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Patch set updated for coreboot: b7a925d northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA
by Timothy Pearson 16 Mar '15

16 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8664 -gerrit commit b7a925d80d9c2202e2ac11e7d7e38a42623142f2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:10:29 2015 -0500 northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA is enabled, however when GFXUMA is disabled an attempt was made to locate the CBMEM memory segment above the I/O hole in certain rare cases. Removing this special case does not impact functionality, and paves the way for early CBMEM support. Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e2b1441..68c6e35 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -756,7 +756,6 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -879,8 +878,6 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -897,15 +894,13 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } #if CONFIG_GFXUMA set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else - set_top_of_ram(ramtop); + set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) {

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Patch merged into coreboot/master: 87200e2 Makefile.inc: Use -Og when compiling with GDB support
by gerrit＠coreboot.org 16 Mar '15

16 Mar '15

the following patch was just integrated into master: commit 87200e2aa327bb53b7594e058aa42f7aba693109 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 15 00:21:17 2015 +0100 Makefile.inc: Use -Og when compiling with GDB support From GCC's documentation: Optimize debugging experience. -Og enables optimizations that do not interfere with debugging. It should be the optimization level of choice for the standard edit-compile-debug cycle, offering a reasonable level of optimization while maintaining fast compilation and a good debugging experience. Change-Id: I9a3dadbf8e894cb28e29d7b2f4e9add252e7bbb3 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/8689 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8689 for details. -gerrit

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Patch merged into coreboot/master: 24f9cb9 crossgcc: Add x86_64 to list of supported architectures
by gerrit＠coreboot.org 16 Mar '15

16 Mar '15

the following patch was just integrated into master: commit 24f9cb91d0c4d55fe1cadaa3a913a14506412cdd Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 13 22:50:22 2015 +0100 crossgcc: Add x86_64 to list of supported architectures You can build your new toolchain with: $ cd util/crossgcc/ $ ./buildgcc -d /opt/cross -p x86_64-elf -j 16 or $ make crossgcc-x64 Change-Id: I8eb584166294578d2b33c63e94ed3aca9b5de4f4 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/8668 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8668 for details. -gerrit

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New patch to review for coreboot: 1cb2c6e Chrome OS vendorcode: Fix vboot_reference compilation
by Stefan Reinauer 16 Mar '15

16 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8703 -gerrit commit 1cb2c6e81d846ace4385b86e89f349b69606fbf8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 16 17:01:52 2015 -0700 Chrome OS vendorcode: Fix vboot_reference compilation Oddly, the include paths are no longer passed in, and FIRMWARE_ARCH wants to be passed as a parameter. Change-Id: I5aee9935ab36ad571fbcf9f6fa8d8ace2bac16b3 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/vendorcode/google/chromeos/Makefile.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index cb3d9a6..c6b9887 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -83,11 +83,11 @@ $(eval $(call rmodule_link,$(VBOOT_STUB_ELF), $(VBOOT_STUB_DOTO), 0x10000,$(ARCH # Build vboot library without the default includes from coreboot proper. $(VB_LIB): @printf " MAKE $(subst $(obj)/,,$(@))\n" - $(Q)FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ - CC="$(CC_romstage)" \ - CFLAGS="$(VBOOT_CFLAGS)" \ + $(Q)CC="$(CC_romstage)" \ + CFLAGS="$(VBOOT_CFLAGS) -I../$(src)/include -I../$(src)/arch/$(ARCHDIR-$(ARCH-romstage-y))/include" \ make -C $(VB_SOURCE) \ $(VBOOT_MAKEFLAGS) \ + FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ BUILD=../$(dir $(VB_LIB)) \ V=$(V) \ fwlib

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New patch to review for coreboot: b33836b haswell: Fix monotonic timer integration
by Stefan Reinauer 16 Mar '15

16 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8702 -gerrit commit b33836b17cfe95f012017fc4081749ebd3ece15d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 16 16:53:27 2015 -0700 haswell: Fix monotonic timer integration In some previous attempt to enable monotonic timers on all platforms, the LAPIC monotonic timer was selected for Haswell devices, despite the fact that LAPIC timers are not used in coreboot on Haswell (See haswell Kconfig) and there already was a monotonic timer implementation enabled that just needed to be added for SMM as well. Change-Id: I6beb2977864e507956636860ed463e1991cea1ed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/haswell/Makefile.inc | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 4732623..741b677 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -25,7 +25,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP - select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 2518e9a..82d3bec 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -11,5 +11,6 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc

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New patch to review for coreboot: 93025da Intel common SPI: Fix compilation breakage from refactoring
by Stefan Reinauer 16 Mar '15

16 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8701 -gerrit commit 93025dad106767ac2f1d2cb3082cd8a66fc3648c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 16 16:50:27 2015 -0700 Intel common SPI: Fix compilation breakage from refactoring When the Intel SPI drivers were refactored, compilation for Chrome OS devices broke, because ELOG uses the SPI driver in SMM. Change-Id: If2b2da5d526196ed742e17409b01a381417d0ce8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/common/spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index d6ab01a..1780fc0 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -360,6 +360,7 @@ void spi_init(void) bios_cntl &= ~(1 << 5); pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } +#ifndef __SMM__ static void spi_init_cb(void *unused) { spi_init(); @@ -368,6 +369,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +#endif int spi_claim_bus(struct spi_slave *slave) {

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New patch to review for coreboot: 97e235b elog: Fix compilation with CONFIG_CHROMEOS enabled
by Stefan Reinauer 16 Mar '15

16 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8700 -gerrit commit 97e235b477aa7537b4261a96c3aa189e03d047a9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 16 16:47:39 2015 -0700 elog: Fix compilation with CONFIG_CHROMEOS enabled On ChromeOS devices the ELOG section size and offset are provided by the FMAP, rather than KConfig. Some upstream refactoring broke compilation in that case. Change-Id: I8b08daa327726218815855c7c2be45f44fcffeed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/elog/elog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 7701906..8bc8a07 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -37,7 +37,7 @@ #include <vendorcode/google/chromeos/fmap.h> -#if CONFIG_ELOG_FLASH_BASE == 0 +#if !IS_ENABLED(CONFIG_CHROMEOS) && CONFIG_ELOG_FLASH_BASE == 0 #error "CONFIG_ELOG_FLASH_BASE is invalid" #endif #if CONFIG_ELOG_FULL_THRESHOLD >= CONFIG_ELOG_AREA_SIZE

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New patch to review for coreboot: 790a425 boostate: use function pointers for scheduling callbacks
by Aaron Durbin 16 Mar '15

16 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8699 -gerrit commit 790a42562941ef3dc94621d2f9be600f73c08302 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 16 17:30:09 2015 -0500 boostate: use function pointers for scheduling callbacks Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/ramstage.ld | 1 + src/arch/arm64/ramstage.ld | 2 ++ src/arch/riscv/ramstage.ld | 1 + src/arch/x86/ramstage.ld | 1 + src/cpu/amd/agesa/amd_late_init.c | 1 + src/cpu/amd/pi/amd_late_init.c | 1 + src/drivers/intel/fsp/fsp_util.c | 1 + src/include/bootstate.h | 17 ++++++++++++++++- src/lib/dynamic_cbmem.c | 2 ++ src/lib/hardwaremain.c | 24 +++++++++++++++++------- src/lib/rmodule.ld | 2 ++ src/mainboard/google/rambi/mainboard.c | 1 + src/northbridge/intel/haswell/mrccache.c | 1 + src/northbridge/intel/sandybridge/mrccache.c | 1 + src/soc/intel/baytrail/dptf.c | 1 + src/soc/intel/baytrail/perf_power.c | 1 + src/soc/intel/baytrail/southcluster.c | 1 + src/soc/intel/baytrail/spi.c | 1 + src/soc/intel/broadwell/elog.c | 1 + src/soc/intel/broadwell/finalize.c | 1 + src/soc/intel/broadwell/spi.c | 1 + src/soc/intel/common/mrc_cache.c | 1 + src/southbridge/amd/agesa/hudson/pci.c | 1 + src/southbridge/amd/cimx/sb800/late.c | 1 + src/southbridge/amd/pi/hudson/pci.c | 1 + src/southbridge/intel/common/spi.c | 1 + src/southbridge/intel/lynxpoint/smi.c | 1 + 27 files changed, 61 insertions(+), 8 deletions(-) diff --git a/src/arch/arm/ramstage.ld b/src/arch/arm/ramstage.ld index 5469509..5e0607d 100644 --- a/src/arch/arm/ramstage.ld +++ b/src/arch/arm/ramstage.ld @@ -64,6 +64,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index de13fcc..784e62d 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -69,6 +69,8 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/riscv/ramstage.ld b/src/arch/riscv/ramstage.ld index 5d9ba3e..2e97a7e 100644 --- a/src/arch/riscv/ramstage.ld +++ b/src/arch/riscv/ramstage.ld @@ -69,6 +69,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 1c8e8dc..cf60dda 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -62,6 +62,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 53c2759..02eb19c 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -46,3 +46,4 @@ BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesawrapper_post_device, NULL), }; +BOOT_STATE_SCHED_ENTRIES(agesa_bscb); diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c index 4b08d1b..d69cb98 100644 --- a/src/cpu/amd/pi/amd_late_init.c +++ b/src/cpu/amd/pi/amd_late_init.c @@ -44,3 +44,4 @@ BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesawrapper_post_device, NULL), }; +BOOT_STATE_SCHED_ENTRIES(agesa_bscb); diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 2a53c25..3c74496 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -322,4 +322,5 @@ BOOT_STATE_INIT_ENTRIES(fsp_hob_find) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL), }; +BOOT_STATE_SCHED_ENTRIES(fsp_hob_find); #endif /* #ifndef __PRE_RAM__ */ diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 202acf7..0738cda 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -22,6 +22,9 @@ #if !defined(__SMM__) && !defined(__PRE_RAM__) #include <string.h> +#include <stdlib.h> +#include <stddef.h> +#include <stdint.h> /* Control debugging of the boot state machine. */ #define BOOT_STATE_DEBUG 0 @@ -157,6 +160,10 @@ int boot_state_sched_on_entry(struct boot_state_callback *bscb, boot_state_t state); int boot_state_sched_on_exit(struct boot_state_callback *bscb, boot_state_t state); +/* Schedule an array of entries of size num. */ +struct boot_state_init_entry; +void boot_state_sched_entries(struct boot_state_init_entry *entries, + size_t num); /* Block/Unblock the (state, seq) pair from transitioning. Returns 0 on * success < 0 when the phase of the (state,seq) has already ran. */ @@ -181,7 +188,7 @@ struct boot_state_init_entry { #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init"))) #define BOOT_STATE_INIT_ENTRIES(name_) \ - static struct boot_state_init_entry name_[] BOOT_STATE_INIT_ATTR + static struct boot_state_init_entry name_[] #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ { \ @@ -190,5 +197,13 @@ struct boot_state_init_entry { .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ } +#define BOOT_STATE_SCHED_ENTRIES(name_) \ + static void _bscb_sched_ ## name_(void) \ + { \ + boot_state_sched_entries(name_, ARRAY_SIZE(name_)); \ + } \ + static void (*_bscb_sched_ptr_ ## name_)(void) \ + BOOT_STATE_INIT_ATTR = _bscb_sched_ ## name_ + #endif #endif /* BOOTSTATE_H */ diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index daa3717..527ce81 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -456,6 +456,8 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { }; #endif +BOOT_STATE_SCHED_ENTRIES(cbmem_bscb); + void cbmem_add_bootmem(void) { uintptr_t base; diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 32162eb..96fb64f 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -430,20 +430,30 @@ int boot_state_sched_on_exit(struct boot_state_callback *bscb, return boot_state_sched_callback(state, bscb, BS_ON_EXIT); } -static void boot_state_schedule_static_entries(void) +void boot_state_sched_entries(struct boot_state_init_entry *entries, size_t num) { - extern struct boot_state_init_entry _bs_init_begin; - extern struct boot_state_init_entry _bs_init_end; - struct boot_state_init_entry *cur; + size_t i; - cur = &_bs_init_begin; + for (i = 0; i < num; i++) { + struct boot_state_init_entry *cur = &entries[i]; - while (cur != &_bs_init_end) { if (cur->when == BS_ON_ENTRY) boot_state_sched_on_entry(&cur->bscb, cur->state); else boot_state_sched_on_exit(&cur->bscb, cur->state); - cur++; + } +} + +static void boot_state_schedule_static_entries(void) +{ + extern void (*_bs_init_begin[])(void); + void (**f)(void); + + f = &_bs_init_begin[0]; + + while (*f != NULL) { + (*f)(); + f++; } } diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f3e7cba..0124c44 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -47,6 +47,8 @@ SECTIONS . = ALIGN(8); _bs_init_begin = .; *(.bs_init) + LONG(0); + LONG(0); _bs_init_end = .; . = ALIGN(8); diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 1290a15..685c92b 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -185,3 +185,4 @@ static void edp_vdden_cb(void *unused) BOOT_STATE_INIT_ENTRIES(edp_vdden_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(edp_vdden_bscb); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 540bbf6..08d7d89 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -226,6 +226,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; +BOOT_STATE_SCHED_ENTRIES(mrc_cache_update); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..dd36ad6 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -227,6 +227,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; +BOOT_STATE_SCHED_ENTRIES(mrc_cache_update); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index 044a807..b05ccbc 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -52,3 +52,4 @@ static void dptf_init(void *unused) BOOT_STATE_INIT_ENTRIES(dptf_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL), }; +BOOT_STATE_SCHED_ENTRIES(dptf_init_bscb); diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 2cde77f..9491617 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -292,3 +292,4 @@ BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL), BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL), }; +BOOT_STATE_SCHED_ENTRIES(disable_rom_cache_bscb); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index d0569b4..ba61ca4 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -575,3 +575,4 @@ BOOT_STATE_INIT_ENTRIES(finalize_bscb) = { BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL), }; +BOOT_STATE_SCHED_ENTRIES(finalize_bscb); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index a83fb8e..6861803 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -326,6 +326,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(spi_init_bscb); #endif int spi_claim_bus(struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index a6a2813..a31a82e 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -136,3 +136,4 @@ static void pch_log_state(void *unused) BOOT_STATE_INIT_ENTRIES(pch_log) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL) }; +BOOT_STATE_SCHED_ENTRIES(pch_log); diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 67cba66..24b7d6c 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -125,3 +125,4 @@ BOOT_STATE_INIT_ENTRIES(finalize) = { BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL), }; +BOOT_STATE_SCHED_ENTRIES(finalize); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 4710271..4636349 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -318,6 +318,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(spi_init_bscb); int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 8f0d18f..99d4a22 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -307,5 +307,6 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; +BOOT_STATE_SCHED_ENTRIES(mrc_cache_update); #endif /* defined(__PRE_RAM__) */ diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 49e2ba6..aa841dd 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -49,6 +49,7 @@ BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL), }; +BOOT_STATE_SCHED_ENTRIES(pci_irq_update); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 2125027..dfcf167 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -330,6 +330,7 @@ BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL), }; +BOOT_STATE_SCHED_ENTRIES(pci_irq_update); /** * @brief SB Cimx entry point sbBeforePciInit wrapper diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index e8836e4..3188155 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -52,6 +52,7 @@ BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL), }; +BOOT_STATE_SCHED_ENTRIES(pci_irq_update); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index d6ab01a..1a75241 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -368,6 +368,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(spi_init_bscb); int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 94abf5f..7424cb3 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -139,5 +139,6 @@ BOOT_STATE_INIT_ENTRIES(finalize) = { BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL), }; +BOOT_STATE_SCHED_ENTRIES(finalize); #endif

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Patch set updated for coreboot: 2824e1a cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function
by Timothy Pearson 16 Mar '15

16 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8663 -gerrit commit 2824e1a7e65890a8ba292f299975d15b9a8b81ec Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 12:48:31 2015 -0500 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function This is required for early CBMEM support. Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/Makefile.inc | 2 ++ src/cpu/amd/model_10xxx/ram_calc.c | 43 ++++++++++++++++++++++++++++++ src/cpu/amd/model_10xxx/ram_calc.h | 25 +++++++++++++++++ src/northbridge/amd/amdfam10/northbridge.c | 17 ++---------- 4 files changed, 72 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index ba12dcd..c17e66c 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -3,6 +3,8 @@ ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c romstage-y += update_microcode.c +romstage-y += ram_calc.c +ramstage-y += ram_calc.c ramstage-y += monotonic_timer.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c new file mode 100644 index 0000000..98b80e9 --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +#include "ram_calc.h" + +uint64_t get_uma_memory_size(uint64_t topmem) +{ + uint64_t uma_size = 0; + if (IS_ENABLED(CONFIG_GFXUMA)) { + /* refer to UMA Size Consideration in 780 BDG. */ + if (topmem > 0x40000000) /* 1GB and above system memory */ + uma_size = 0x10000000; /* 256M recommended UMA */ + + else if (topmem > 0x20000000) /* 512M - 1023M system memory */ + uma_size = 0x8000000; /* 128M recommended UMA */ + + else if (topmem > 0x10000000) /* 256M - 511M system memory */ + uma_size = 0x4000000; /* 64M recommended UMA */ + } + + return uma_size; +} diff --git a/src/cpu/amd/model_10xxx/ram_calc.h b/src/cpu/amd/model_10xxx/ram_calc.h new file mode 100644 index 0000000..7ece338 --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_MODEL_10XXX_MEM_CALC_H_ +#define _AMD_MODEL_10XXX_MEM_CALC_H_ + +uint64_t get_uma_memory_size(uint64_t topmem); + +#endif diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5ce7ae6..e2b1441 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -33,6 +33,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> +#include <cpu/amd/model_10xxx/ram_calc.h> #if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> @@ -740,21 +741,7 @@ static void setup_uma_memory(void) { #if CONFIG_GFXUMA uint32_t topmem = (uint32_t) bsp_topmem(); - /* refer to UMA Size Consideration in 780 BDG. */ - switch (topmem) { - case 0x10000000: /* 256M system memory */ - uma_memory_size = 0x4000000; /* 64M recommended UMA */ - break; - - case 0x20000000: /* 512M system memory */ - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - break; - - default: /* 1GB and above system memory */ - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - break; - } - + uma_memory_size = get_uma_memory_size(topmem); uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base);

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coreboot-gerrit March 2015