coreboot-gerrit March 2015

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New patch to review for coreboot: 7c15290 PCI subsystem: Drop PCI_64BIT_PREF_MEM option
by Kyösti Mälkki 16 Mar '15

16 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8705 -gerrit commit 7c15290687864dd82e0a717107c737d9813ff5e4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Mar 17 06:42:54 2015 +0200 PCI subsystem: Drop PCI_64BIT_PREF_MEM option No board in the tree selects this at it looks like the implementation was done at chipset level while it should be part of PCI subsystem. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 5 -- src/device/device.c | 2 +- src/mainboard/asus/kfsn4-dre/Kconfig | 4 -- src/mainboard/asus/m2n-e/Kconfig | 4 -- src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 4 -- src/mainboard/gigabyte/m57sli/Kconfig | 4 -- src/mainboard/msi/ms7260/Kconfig | 4 -- src/mainboard/msi/ms9282/Kconfig | 4 -- src/mainboard/nvidia/l1_2pvv/Kconfig | 4 -- src/mainboard/tyan/s2912/Kconfig | 4 -- src/mainboard/tyan/s2912_fam10/Kconfig | 4 -- src/northbridge/amd/agesa/family10/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family12/northbridge.c | 81 +-------------------- src/northbridge/amd/agesa/family14/northbridge.c | 82 ---------------------- src/northbridge/amd/agesa/family15/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family15rl/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family15tn/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family16kb/northbridge.c | 77 -------------------- src/northbridge/amd/amdfam10/northbridge.c | 76 -------------------- src/northbridge/amd/amdk8/northbridge.c | 68 ------------------ src/northbridge/amd/pi/00630F01/northbridge.c | 77 +------------------- src/northbridge/amd/pi/00730F01/northbridge.c | 78 -------------------- 22 files changed, 3 insertions(+), 887 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 7f43888..ddfcdce 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -205,11 +205,6 @@ config PCI bool default n -config PCI_64BIT_PREF_MEM - bool - depends on PCI - default n - config HYPERTRANSPORT_PLUGIN_SUPPORT bool depends on PCI diff --git a/src/device/device.c b/src/device/device.c index 00e323a..34edcb7 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -610,7 +610,7 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, } } -#if CONFIG_PCI_64BIT_PREF_MEM +#if 0 /* was: CONFIG_PCI_64BIT_PREF_MEM */ #define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM) #else #define MEM_MASK (IORESOURCE_MEM) diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index a7ac369..5957028 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZEK hex default 0x100000 -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 12 diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index 7292bf3..c86de2d 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -65,10 +65,6 @@ config MAINBOARD_PART_NUMBER string default "M2N-E" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index a79c28f..660ac1c 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -45,10 +45,6 @@ config MAINBOARD_PART_NUMBER string default "GA-2761GXDK" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 6ef94ce..3132d37 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -49,10 +49,6 @@ config MAINBOARD_PART_NUMBER string default "GA-M57SLI-S4" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 0e7e592..60ea9ea 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -47,10 +47,6 @@ config MAINBOARD_PART_NUMBER string default "MS-7260" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index f109375..e88f36f 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -41,10 +41,6 @@ config MAINBOARD_PART_NUMBER string default "MS-9282" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 57911f7..7694492 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -51,10 +51,6 @@ config MAINBOARD_PART_NUMBER string default "l1_2pvv" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 26d9a53..8b59eb5 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -46,10 +46,6 @@ config MAINBOARD_PART_NUMBER string default "S2912" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 1dd74ca..1e0d4d0 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -43,10 +43,6 @@ config MAINBOARD_PART_NUMBER string default "S2912 (Fam10)" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 12 diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 8e47c1a..6b2ff63 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -635,29 +635,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void amdfam10_domain_enable_resources(device_t dev) @@ -737,10 +715,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -751,57 +725,6 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index a3b3493..4cd9156 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -509,9 +509,6 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM -//- pci_domain_read_resources(dev); - struct resource *resource; /* Initialize the system-wide I/O space constraints. */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -526,27 +523,7 @@ static void domain_read_resources(device_t dev) resource->limit = 0xdfffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -#else - struct bus *link; - struct resource *resource; - for(link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -556,10 +533,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -570,58 +543,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - -printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); - for(link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for(res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index ff669ef..852780b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -498,29 +498,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for (link = dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0 | (link->link_num << 2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1 | (link->link_num << 2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2 | (link->link_num << 2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void setup_uma_memory(void) @@ -553,10 +531,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -567,62 +541,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1 | (link->link_num << 2)); - mem2 = find_resource(dev, 2 | (link->link_num << 2)); - - printk(BIOS_DEBUG, - "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - (u32) (mem1->base), (u32) (mem1->limit), - (u32) (mem1->size), u32) (mem1->align)); - printk(BIOS_DEBUG, - "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - (u32) (mem2->base), (u32) (mem2->limit), - (u32) (mem2->size), (u32) (mem2->align)); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) - || ((mem1->limit > 0xffffffff) - && (mem2->limit > 0xffffffff))) { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, - "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, - "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 89e1644..aaa63bb 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -668,30 +668,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -792,10 +769,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -806,56 +779,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index f83ff2d..4e77758 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -663,30 +663,7 @@ static void domain_read_resources(struct device *dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(struct device *dev) @@ -787,10 +764,6 @@ static void setup_uma_memory(void) static void domain_set_resources(struct device *dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -801,56 +774,6 @@ static void domain_set_resources(struct device *dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index d878b4f..9eb502a 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -661,30 +661,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -785,10 +762,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -799,56 +772,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index badec55..5178065 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -677,30 +677,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -803,10 +780,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -817,56 +790,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e2b1441..bf8fc7b 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -632,29 +632,8 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for(link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif #if CONFIG_MMCONF_SUPPORT struct resource *res = new_resource(dev, 0xc0010058); res->base = CONFIG_MMCONF_BASE_ADDRESS; @@ -750,10 +729,6 @@ static void setup_uma_memory(void) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -764,57 +739,6 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for(link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for(res = dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a17aa65..b42b6bf 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -667,13 +667,6 @@ static void amdk8_domain_read_resources(device_t dev) } pci_domain_read_resources(dev); - -#if CONFIG_PCI_64BIT_PREF_MEM - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 2); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; -#endif } static void my_tolm_test(void *gp, struct device *dev, struct resource *new) @@ -904,10 +897,6 @@ static void setup_uma_memory(void) static void amdk8_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -917,63 +906,6 @@ static void amdk8_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if 0 - /* Place the IO devices somewhere safe */ - io = find_resource(dev, 0); - io->base = DEVICE_IO_START; -#endif -#if CONFIG_PCI_64BIT_PREF_MEM - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1); - mem2 = find_resource(dev, 2); - -#if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); -#endif - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - -#if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); -#endif - - for(res = dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = my_find_pci_tolm(dev->link_list); // FIXME handle interleaved nodes. If you fix this here, please fix diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index f8b3246..e5fa0cb 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -654,29 +654,8 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ - if (!IS_ENABLED(CONFIG_PCI_64BIT_PREF_MEM)) pci_domain_read_resources(dev); - else { - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } - } + } static void domain_enable_resources(device_t dev) @@ -780,10 +759,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -794,56 +769,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index b10da3d..d33f021 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -663,31 +663,7 @@ static void domain_read_resources(device_t dev) } /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ - -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -796,10 +772,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -810,56 +782,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link);

1 0

New patch to review for coreboot: 1b751a1 rockchip/rk3288: Fix whitespace
by Kyösti Mälkki 16 Mar '15

16 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8704 -gerrit commit 1b751a14f88c54ea03be3bc1df5ded21bbc6e230 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Mar 17 07:11:26 2015 +0200 rockchip/rk3288: Fix whitespace Change-Id: I6c3c1e871de33b4d0e968b254bbcf125cee9fddb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/soc/rockchip/rk3288/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 51cf74c..0fadefd 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -30,7 +30,7 @@ config SOC_ROCKCHIP_RK3288 select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select DYNAMIC_CBMEM - + if SOC_ROCKCHIP_RK3288 config BOOTBLOCK_CPU_INIT

1 0

Patch merged into coreboot/master: 3d78ece haswell: Fix monotonic timer integration
by gerrit＠coreboot.org 16 Mar '15

16 Mar '15

the following patch was just integrated into master: commit 3d78ece7d02797187a56ada8ba8ae379df4a5b95 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 16 16:53:27 2015 -0700 haswell: Fix monotonic timer integration In some previous attempt to enable monotonic timers on all platforms, the LAPIC monotonic timer was selected for Haswell devices, despite the fact that LAPIC timers are not used in coreboot on Haswell (See haswell Kconfig) and there already was a monotonic timer implementation enabled that just needed to be added for SMM as well. Change-Id: I6beb2977864e507956636860ed463e1991cea1ed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/8702 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8702 for details. -gerrit

1 0

Patch merged into coreboot/master: c3d15a7 Intel common SPI: Fix compilation breakage from refactoring
by gerrit＠coreboot.org 16 Mar '15

16 Mar '15

the following patch was just integrated into master: commit c3d15a72104b844baab6f99a32c74c09c49335b6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 16 16:50:27 2015 -0700 Intel common SPI: Fix compilation breakage from refactoring When the Intel SPI drivers were refactored, compilation for Chrome OS devices broke, because ELOG uses the SPI driver in SMM. Change-Id: If2b2da5d526196ed742e17409b01a381417d0ce8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/8701 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8701 for details. -gerrit

1 0

Patch merged into coreboot/master: 45a225b elog: Fix compilation with CONFIG_CHROMEOS enabled
by gerrit＠coreboot.org 16 Mar '15

16 Mar '15

the following patch was just integrated into master: commit 45a225b05dbc22c5aff3c8baf927a68142f6be86 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 16 16:47:39 2015 -0700 elog: Fix compilation with CONFIG_CHROMEOS enabled On ChromeOS devices the ELOG section size and offset are provided by the FMAP, rather than KConfig. Some upstream refactoring broke compilation in that case. Change-Id: I8b08daa327726218815855c7c2be45f44fcffeed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/8700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8700 for details. -gerrit

1 0

Patch merged into coreboot/master: 4916880 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function
by gerrit＠coreboot.org 16 Mar '15

16 Mar '15

the following patch was just integrated into master: commit 49168805112d021f8715cab3abded8ab384860ac Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 12:48:31 2015 -0500 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function This is required for early CBMEM support. Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8663 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8663 for details. -gerrit

1 0

Patch merged into coreboot/master: 4472408 lib: Add Kconfig option to enable/disable auto fallback control
by gerrit＠coreboot.org 16 Mar '15

16 Mar '15

the following patch was just integrated into master: commit 447240808c62cb877e343c40802a35d01ed198fb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 16 11:47:45 2015 -0500 lib: Add Kconfig option to enable/disable auto fallback control Under certain conditions, e.g. automated testing, it is useful to have the payload (e.g. Linux) reset the reboot_bits CMOS value. This allows automated recovery in the case of coreboot starting properly but the payload failing to start due to bad configuration data provided by the coreboot image under test. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Change-Id: Ifc8f565f8292941d90b2e520cc9c5993b41e9cdd Reviewed-on: http://review.coreboot.org/8698 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8698 for details. -gerrit

1 0

Patch set updated for coreboot: efec4ec boostate: use structure pointers for scheduling callbacks
by Aaron Durbin 16 Mar '15

16 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8699 -gerrit commit efec4ecb7147a9042366bfb7f12e2d50434b7710 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 16 17:30:09 2015 -0500 boostate: use structure pointers for scheduling callbacks The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/ramstage.ld | 1 + src/arch/arm64/ramstage.ld | 2 ++ src/arch/riscv/ramstage.ld | 1 + src/arch/x86/ramstage.ld | 1 + src/cpu/amd/agesa/amd_late_init.c | 6 ++---- src/cpu/amd/pi/amd_late_init.c | 6 ++---- src/drivers/intel/fsp/fsp_util.c | 6 ++---- src/include/bootstate.h | 26 +++++++++++++++++--------- src/lib/dynamic_cbmem.c | 12 +++--------- src/lib/gcov-glue.c | 8 +++----- src/lib/hardwaremain.c | 10 ++++------ src/lib/rmodule.ld | 2 ++ src/mainboard/google/rambi/mainboard.c | 4 +--- src/northbridge/intel/haswell/mrccache.c | 5 +---- src/northbridge/intel/sandybridge/mrccache.c | 5 +---- src/soc/intel/baytrail/dptf.c | 4 +--- src/soc/intel/baytrail/perf_power.c | 6 ++---- src/soc/intel/baytrail/southcluster.c | 8 ++------ src/soc/intel/baytrail/spi.c | 4 +--- src/soc/intel/broadwell/elog.c | 4 +--- src/soc/intel/broadwell/finalize.c | 8 ++------ src/soc/intel/broadwell/spi.c | 4 +--- src/soc/intel/common/mrc_cache.c | 5 +---- src/southbridge/amd/agesa/hudson/pci.c | 5 +---- src/southbridge/amd/cimx/sb800/late.c | 5 +---- src/southbridge/amd/pi/hudson/pci.c | 5 +---- src/southbridge/intel/common/spi.c | 4 +--- src/southbridge/intel/lynxpoint/smi.c | 5 +---- 28 files changed, 59 insertions(+), 103 deletions(-) diff --git a/src/arch/arm/ramstage.ld b/src/arch/arm/ramstage.ld index 5469509..5e0607d 100644 --- a/src/arch/arm/ramstage.ld +++ b/src/arch/arm/ramstage.ld @@ -64,6 +64,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index de13fcc..784e62d 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -69,6 +69,8 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/riscv/ramstage.ld b/src/arch/riscv/ramstage.ld index 5d9ba3e..2e97a7e 100644 --- a/src/arch/riscv/ramstage.ld +++ b/src/arch/riscv/ramstage.ld @@ -69,6 +69,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 1c8e8dc..cf60dda 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -62,6 +62,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 53c2759..b41fa5c 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -42,7 +42,5 @@ static void agesawrapper_post_device(void *unused) agesawrapper_amdS3Save(); } -BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + agesawrapper_post_device, NULL); diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c index 4b08d1b..7ef4c63 100644 --- a/src/cpu/amd/pi/amd_late_init.c +++ b/src/cpu/amd/pi/amd_late_init.c @@ -40,7 +40,5 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdS3Save); } -BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + agesawrapper_post_device, NULL); diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 2a53c25..a00cb81 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -318,8 +318,6 @@ static void find_fsp_hob_update_mrc(void *unused) } /* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRIES(fsp_hob_find) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - find_fsp_hob_update_mrc, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + find_fsp_hob_update_mrc, NULL); #endif /* #ifndef __PRE_RAM__ */ diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 202acf7..8b5e4be 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -22,6 +22,9 @@ #if !defined(__SMM__) && !defined(__PRE_RAM__) #include <string.h> +#include <stdlib.h> +#include <stddef.h> +#include <stdint.h> /* Control debugging of the boot state machine. */ #define BOOT_STATE_DEBUG 0 @@ -157,6 +160,10 @@ int boot_state_sched_on_entry(struct boot_state_callback *bscb, boot_state_t state); int boot_state_sched_on_exit(struct boot_state_callback *bscb, boot_state_t state); +/* Schedule an array of entries of size num. */ +struct boot_state_init_entry; +void boot_state_sched_entries(struct boot_state_init_entry *entries, + size_t num); /* Block/Unblock the (state, seq) pair from transitioning. Returns 0 on * success < 0 when the phase of the (state,seq) has already ran. */ @@ -180,15 +187,16 @@ struct boot_state_init_entry { #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init"))) -#define BOOT_STATE_INIT_ENTRIES(name_) \ - static struct boot_state_init_entry name_[] BOOT_STATE_INIT_ATTR - -#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ - { \ - .state = state_, \ - .when = when_, \ - .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ - } +#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ + static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \ + { \ + .state = state_, \ + .when = when_, \ + .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ + }; \ + static struct boot_state_init_entry * \ + bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \ + & func_ ##_## state_ ##_## when_; #endif #endif /* BOOTSTATE_H */ diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index daa3717..3b008c7 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -435,11 +435,7 @@ static void init_cbmem_pre_device(void *unused) cbmem_initialize(); } -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, - init_cbmem_pre_device, NULL), -}; - +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, init_cbmem_pre_device, NULL); #else static void init_cbmem_post_device(void *unused) @@ -450,10 +446,8 @@ static void init_cbmem_post_device(void *unused) cbmem_initialize_empty(); } -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, - init_cbmem_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, + init_cbmem_post_device, NULL); #endif void cbmem_add_bootmem(void) diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index ab9062b..615624f 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -150,8 +150,6 @@ static void coverage_exit(void *unused) __gcov_flush(); } -BOOT_STATE_INIT_ENTRIES(gcov_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, coverage_init, NULL), - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, coverage_exit, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, coverage_exit, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, coverage_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, coverage_exit, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, coverage_exit, NULL); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 32162eb..d16aa09 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -432,18 +432,16 @@ int boot_state_sched_on_exit(struct boot_state_callback *bscb, static void boot_state_schedule_static_entries(void) { - extern struct boot_state_init_entry _bs_init_begin; - extern struct boot_state_init_entry _bs_init_end; - struct boot_state_init_entry *cur; + extern struct boot_state_init_entry *_bs_init_begin[]; + struct boot_state_init_entry **slot; - cur = &_bs_init_begin; + for (slot = &_bs_init_begin[0]; *slot != NULL; slot++) { + struct boot_state_init_entry *cur = *slot; - while (cur != &_bs_init_end) { if (cur->when == BS_ON_ENTRY) boot_state_sched_on_entry(&cur->bscb, cur->state); else boot_state_sched_on_exit(&cur->bscb, cur->state); - cur++; } } diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f3e7cba..0124c44 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -47,6 +47,8 @@ SECTIONS . = ALIGN(8); _bs_init_begin = .; *(.bs_init) + LONG(0); + LONG(0); _bs_init_end = .; . = ALIGN(8); diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 1290a15..7128448 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -182,6 +182,4 @@ static void edp_vdden_cb(void *unused) ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2); } -BOOT_STATE_INIT_ENTRIES(edp_vdden_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 540bbf6..b66e9fd 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -222,10 +222,7 @@ static void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..127ca3d 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -223,10 +223,7 @@ static void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index 044a807..e875319 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -49,6 +49,4 @@ static void dptf_init(void *unused) reg_script_run(dptf_init_settings); } -BOOT_STATE_INIT_ENTRIES(dptf_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL); diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 2cde77f..dade339 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -288,7 +288,5 @@ static void perf_power(void *unused) reg_script_run(perf_power_settings); } -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index d0569b4..84052d8 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -569,9 +569,5 @@ static void finalize_chipset(void *unused) outb(APM_CNT_FINALIZE, APM_CNT); } -BOOT_STATE_INIT_ENTRIES(finalize_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - finalize_chipset, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - finalize_chipset, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index a83fb8e..cf40140 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -323,9 +323,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); #endif int spi_claim_bus(struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index a6a2813..79484a9 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -133,6 +133,4 @@ static void pch_log_state(void *unused) pch_log_wake_source(ps); } -BOOT_STATE_INIT_ENTRIES(pch_log) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL) -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL); diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 67cba66..4f7a518 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -119,9 +119,5 @@ static void broadwell_finalize(void *unused) post_code(POST_OS_BOOT); } -BOOT_STATE_INIT_ENTRIES(finalize) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - broadwell_finalize, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - broadwell_finalize, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 4710271..0069d10 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -315,9 +315,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 8f0d18f..5860201 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -303,9 +303,6 @@ static void update_mrc_cache(void *unused) } } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif /* defined(__PRE_RAM__) */ diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 49e2ba6..5858cd2 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -45,10 +45,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 2125027..f4a7aa3 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -326,10 +326,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); /** * @brief SB Cimx entry point sbBeforePciInit wrapper diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index e8836e4..70e2c18 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -48,10 +48,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index d6ab01a..0aee3a0 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -365,9 +365,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 94abf5f..18a55f6 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -135,9 +135,6 @@ static void finalize_boot(void *unused) outb(0xcb, 0xb2); } -BOOT_STATE_INIT_ENTRIES(finalize) = { - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, - finalize_boot, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); #endif

1 0

Patch set updated for coreboot: 8691adf boostate: use structure pointers for scheduling callbacks
by Aaron Durbin 16 Mar '15

16 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8699 -gerrit commit 8691adf794e2668c9763e63f2ff05cc4d6f2e508 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 16 17:30:09 2015 -0500 boostate: use structure pointers for scheduling callbacks The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/ramstage.ld | 1 + src/arch/arm64/ramstage.ld | 2 ++ src/arch/riscv/ramstage.ld | 1 + src/arch/x86/ramstage.ld | 1 + src/cpu/amd/agesa/amd_late_init.c | 1 + src/cpu/amd/pi/amd_late_init.c | 1 + src/drivers/intel/fsp/fsp_util.c | 1 + src/include/bootstate.h | 17 ++++++++++++++++- src/lib/dynamic_cbmem.c | 2 ++ src/lib/hardwaremain.c | 24 +++++++++++++++++------- src/lib/rmodule.ld | 2 ++ src/mainboard/google/rambi/mainboard.c | 1 + src/northbridge/intel/haswell/mrccache.c | 1 + src/northbridge/intel/sandybridge/mrccache.c | 1 + src/soc/intel/baytrail/dptf.c | 1 + src/soc/intel/baytrail/perf_power.c | 1 + src/soc/intel/baytrail/southcluster.c | 1 + src/soc/intel/baytrail/spi.c | 1 + src/soc/intel/broadwell/elog.c | 1 + src/soc/intel/broadwell/finalize.c | 1 + src/soc/intel/broadwell/spi.c | 1 + src/soc/intel/common/mrc_cache.c | 1 + src/southbridge/amd/agesa/hudson/pci.c | 1 + src/southbridge/amd/cimx/sb800/late.c | 1 + src/southbridge/amd/pi/hudson/pci.c | 1 + src/southbridge/intel/common/spi.c | 1 + src/southbridge/intel/lynxpoint/smi.c | 1 + 27 files changed, 61 insertions(+), 8 deletions(-) diff --git a/src/arch/arm/ramstage.ld b/src/arch/arm/ramstage.ld index 5469509..5e0607d 100644 --- a/src/arch/arm/ramstage.ld +++ b/src/arch/arm/ramstage.ld @@ -64,6 +64,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index de13fcc..784e62d 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -69,6 +69,8 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/riscv/ramstage.ld b/src/arch/riscv/ramstage.ld index 5d9ba3e..2e97a7e 100644 --- a/src/arch/riscv/ramstage.ld +++ b/src/arch/riscv/ramstage.ld @@ -69,6 +69,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 1c8e8dc..cf60dda 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -62,6 +62,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 53c2759..02eb19c 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -46,3 +46,4 @@ BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesawrapper_post_device, NULL), }; +BOOT_STATE_SCHED_ENTRIES(agesa_bscb); diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c index 4b08d1b..d69cb98 100644 --- a/src/cpu/amd/pi/amd_late_init.c +++ b/src/cpu/amd/pi/amd_late_init.c @@ -44,3 +44,4 @@ BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesawrapper_post_device, NULL), }; +BOOT_STATE_SCHED_ENTRIES(agesa_bscb); diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 2a53c25..3c74496 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -322,4 +322,5 @@ BOOT_STATE_INIT_ENTRIES(fsp_hob_find) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL), }; +BOOT_STATE_SCHED_ENTRIES(fsp_hob_find); #endif /* #ifndef __PRE_RAM__ */ diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 202acf7..0738cda 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -22,6 +22,9 @@ #if !defined(__SMM__) && !defined(__PRE_RAM__) #include <string.h> +#include <stdlib.h> +#include <stddef.h> +#include <stdint.h> /* Control debugging of the boot state machine. */ #define BOOT_STATE_DEBUG 0 @@ -157,6 +160,10 @@ int boot_state_sched_on_entry(struct boot_state_callback *bscb, boot_state_t state); int boot_state_sched_on_exit(struct boot_state_callback *bscb, boot_state_t state); +/* Schedule an array of entries of size num. */ +struct boot_state_init_entry; +void boot_state_sched_entries(struct boot_state_init_entry *entries, + size_t num); /* Block/Unblock the (state, seq) pair from transitioning. Returns 0 on * success < 0 when the phase of the (state,seq) has already ran. */ @@ -181,7 +188,7 @@ struct boot_state_init_entry { #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init"))) #define BOOT_STATE_INIT_ENTRIES(name_) \ - static struct boot_state_init_entry name_[] BOOT_STATE_INIT_ATTR + static struct boot_state_init_entry name_[] #define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ { \ @@ -190,5 +197,13 @@ struct boot_state_init_entry { .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ } +#define BOOT_STATE_SCHED_ENTRIES(name_) \ + static void _bscb_sched_ ## name_(void) \ + { \ + boot_state_sched_entries(name_, ARRAY_SIZE(name_)); \ + } \ + static void (*_bscb_sched_ptr_ ## name_)(void) \ + BOOT_STATE_INIT_ATTR = _bscb_sched_ ## name_ + #endif #endif /* BOOTSTATE_H */ diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index daa3717..527ce81 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -456,6 +456,8 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { }; #endif +BOOT_STATE_SCHED_ENTRIES(cbmem_bscb); + void cbmem_add_bootmem(void) { uintptr_t base; diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 32162eb..96fb64f 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -430,20 +430,30 @@ int boot_state_sched_on_exit(struct boot_state_callback *bscb, return boot_state_sched_callback(state, bscb, BS_ON_EXIT); } -static void boot_state_schedule_static_entries(void) +void boot_state_sched_entries(struct boot_state_init_entry *entries, size_t num) { - extern struct boot_state_init_entry _bs_init_begin; - extern struct boot_state_init_entry _bs_init_end; - struct boot_state_init_entry *cur; + size_t i; - cur = &_bs_init_begin; + for (i = 0; i < num; i++) { + struct boot_state_init_entry *cur = &entries[i]; - while (cur != &_bs_init_end) { if (cur->when == BS_ON_ENTRY) boot_state_sched_on_entry(&cur->bscb, cur->state); else boot_state_sched_on_exit(&cur->bscb, cur->state); - cur++; + } +} + +static void boot_state_schedule_static_entries(void) +{ + extern void (*_bs_init_begin[])(void); + void (**f)(void); + + f = &_bs_init_begin[0]; + + while (*f != NULL) { + (*f)(); + f++; } } diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f3e7cba..0124c44 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -47,6 +47,8 @@ SECTIONS . = ALIGN(8); _bs_init_begin = .; *(.bs_init) + LONG(0); + LONG(0); _bs_init_end = .; . = ALIGN(8); diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 1290a15..685c92b 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -185,3 +185,4 @@ static void edp_vdden_cb(void *unused) BOOT_STATE_INIT_ENTRIES(edp_vdden_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(edp_vdden_bscb); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 540bbf6..08d7d89 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -226,6 +226,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; +BOOT_STATE_SCHED_ENTRIES(mrc_cache_update); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..dd36ad6 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -227,6 +227,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; +BOOT_STATE_SCHED_ENTRIES(mrc_cache_update); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index 044a807..b05ccbc 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -52,3 +52,4 @@ static void dptf_init(void *unused) BOOT_STATE_INIT_ENTRIES(dptf_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL), }; +BOOT_STATE_SCHED_ENTRIES(dptf_init_bscb); diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 2cde77f..9491617 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -292,3 +292,4 @@ BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL), BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL), }; +BOOT_STATE_SCHED_ENTRIES(disable_rom_cache_bscb); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index d0569b4..ba61ca4 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -575,3 +575,4 @@ BOOT_STATE_INIT_ENTRIES(finalize_bscb) = { BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL), }; +BOOT_STATE_SCHED_ENTRIES(finalize_bscb); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index a83fb8e..6861803 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -326,6 +326,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(spi_init_bscb); #endif int spi_claim_bus(struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index a6a2813..a31a82e 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -136,3 +136,4 @@ static void pch_log_state(void *unused) BOOT_STATE_INIT_ENTRIES(pch_log) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL) }; +BOOT_STATE_SCHED_ENTRIES(pch_log); diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 67cba66..24b7d6c 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -125,3 +125,4 @@ BOOT_STATE_INIT_ENTRIES(finalize) = { BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL), }; +BOOT_STATE_SCHED_ENTRIES(finalize); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 4710271..4636349 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -318,6 +318,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(spi_init_bscb); int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 8f0d18f..99d4a22 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -307,5 +307,6 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; +BOOT_STATE_SCHED_ENTRIES(mrc_cache_update); #endif /* defined(__PRE_RAM__) */ diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 49e2ba6..aa841dd 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -49,6 +49,7 @@ BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL), }; +BOOT_STATE_SCHED_ENTRIES(pci_irq_update); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 2125027..dfcf167 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -330,6 +330,7 @@ BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL), }; +BOOT_STATE_SCHED_ENTRIES(pci_irq_update); /** * @brief SB Cimx entry point sbBeforePciInit wrapper diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index e8836e4..3188155 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -52,6 +52,7 @@ BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL), }; +BOOT_STATE_SCHED_ENTRIES(pci_irq_update); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index d6ab01a..1a75241 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -368,6 +368,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(spi_init_bscb); int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 94abf5f..7424cb3 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -139,5 +139,6 @@ BOOT_STATE_INIT_ENTRIES(finalize) = { BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL), }; +BOOT_STATE_SCHED_ENTRIES(finalize); #endif

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Patch set updated for coreboot: 846804b cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function
by Timothy Pearson 16 Mar '15

16 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8663 -gerrit commit 846804b853edc717aa84cd92924fd34235210fe4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 12:48:31 2015 -0500 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function This is required for early CBMEM support. Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/Makefile.inc | 2 ++ src/cpu/amd/model_10xxx/ram_calc.c | 43 ++++++++++++++++++++++++++++++ src/cpu/amd/model_10xxx/ram_calc.h | 25 +++++++++++++++++ src/northbridge/amd/amdfam10/northbridge.c | 17 ++---------- 4 files changed, 72 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index ba12dcd..c17e66c 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -3,6 +3,8 @@ ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c romstage-y += update_microcode.c +romstage-y += ram_calc.c +ramstage-y += ram_calc.c ramstage-y += monotonic_timer.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c new file mode 100644 index 0000000..98b80e9 --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +#include "ram_calc.h" + +uint64_t get_uma_memory_size(uint64_t topmem) +{ + uint64_t uma_size = 0; + if (IS_ENABLED(CONFIG_GFXUMA)) { + /* refer to UMA Size Consideration in 780 BDG. */ + if (topmem > 0x40000000) /* 1GB and above system memory */ + uma_size = 0x10000000; /* 256M recommended UMA */ + + else if (topmem > 0x20000000) /* 512M - 1023M system memory */ + uma_size = 0x8000000; /* 128M recommended UMA */ + + else if (topmem > 0x10000000) /* 256M - 511M system memory */ + uma_size = 0x4000000; /* 64M recommended UMA */ + } + + return uma_size; +} diff --git a/src/cpu/amd/model_10xxx/ram_calc.h b/src/cpu/amd/model_10xxx/ram_calc.h new file mode 100644 index 0000000..24c120c --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_MODEL_10XXX_RAM_CALC_H_ +#define _AMD_MODEL_10XXX_RAM_CALC_H_ + +uint64_t get_uma_memory_size(uint64_t topmem); + +#endif diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5ce7ae6..e2b1441 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -33,6 +33,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> +#include <cpu/amd/model_10xxx/ram_calc.h> #if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> @@ -740,21 +741,7 @@ static void setup_uma_memory(void) { #if CONFIG_GFXUMA uint32_t topmem = (uint32_t) bsp_topmem(); - /* refer to UMA Size Consideration in 780 BDG. */ - switch (topmem) { - case 0x10000000: /* 256M system memory */ - uma_memory_size = 0x4000000; /* 64M recommended UMA */ - break; - - case 0x20000000: /* 512M system memory */ - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - break; - - default: /* 1GB and above system memory */ - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - break; - } - + uma_memory_size = get_uma_memory_size(topmem); uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base);

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coreboot-gerrit March 2015