coreboot-gerrit March 2015

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Patch set updated for coreboot: 2b675a3 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit
by Timothy Pearson 16 Mar '15

16 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8489 -gerrit commit 2b675a340a7a28d0c38bcc99a9432876ff35381a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:27:58 2015 -0500 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. The CBMEM location code implicitly assumes TOM does not change between romstage and ramstage. TOM is set by romstage raminit, and is never changed by romstage or ramstage afterward. As the CBMEM location is positioned at a specific offset from TOM that is known to both romstage and ramstage early CBMEM is safe on Fam10h systems. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/ram_calc.c | 11 +++++++++++ src/mainboard/advansus/a785e-i/romstage.c | 1 + src/mainboard/amd/bimini_fam10/romstage.c | 1 + src/mainboard/amd/mahogany_fam10/romstage.c | 1 + src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 1 + src/mainboard/amd/tilapia_fam10/romstage.c | 1 + src/mainboard/asus/kfsn4-dre/romstage.c | 1 + src/mainboard/asus/m4a78-em/romstage.c | 1 + src/mainboard/asus/m4a785-m/romstage.c | 1 + src/mainboard/asus/m5a88-v/romstage.c | 1 + src/mainboard/avalue/eax-785e/romstage.c | 1 + src/mainboard/gigabyte/ma785gm/romstage.c | 1 + src/mainboard/gigabyte/ma785gmt/romstage.c | 1 + src/mainboard/gigabyte/ma78gm/romstage.c | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 + src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 + src/mainboard/jetway/pa78vm5/romstage.c | 1 + src/mainboard/msi/ms9652_fam10/romstage.c | 1 + src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 + src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 + src/mainboard/supermicro/h8scm_fam10/romstage.c | 1 + src/mainboard/tyan/s2912_fam10/romstage.c | 1 + src/northbridge/amd/amdfam10/Kconfig | 1 - src/northbridge/amd/amdfam10/northbridge.c | 3 --- src/southbridge/amd/sb700/early_setup.c | 5 +++++ src/southbridge/amd/sb700/lpc.c | 5 +++++ src/southbridge/amd/sb800/early_setup.c | 5 +++++ 27 files changed, 47 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c index 98b80e9..dcf4300 100644 --- a/src/cpu/amd/model_10xxx/ram_calc.c +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -22,6 +22,8 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#include <cbmem.h> + #include "ram_calc.h" uint64_t get_uma_memory_size(uint64_t topmem) @@ -41,3 +43,12 @@ uint64_t get_uma_memory_size(uint64_t topmem) return uma_size; } + +void *cbmem_top(void) +{ + uint32_t topmem = rdmsr(TOP_MEM).lo; + + topmem = topmem - get_uma_memory_size(topmem); + + return (void *) topmem; +} diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 19ce53e..c1c9a1b 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index d8a38d7..6d03685 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -198,6 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e6d7f2e..e53c64d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 76bc73f..ef15e83 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -312,6 +312,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index b7f6869..7d2f272 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 0dab8e8..44864f6 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -343,6 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); printk(BIOS_DEBUG, "disable_spd()\n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 7c93767..47b9c83 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 328955a..7ebec29 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index baa38ac..2339478 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index b586198..c1dbaa7 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -201,6 +201,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4ad3d2c..7b0168d 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 590bb93..d0d6c94 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a7b6b1b..8861ab6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index d7e8447..4aefcd2 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -204,6 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); bcm5785_early_setup(); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index b88baa3..991cd55 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 08b6398..df30a69 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -205,6 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 45f05a5..0bdcd38 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -231,6 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index bc1ca24..4615465 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -228,6 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 2be09bc..c8ed2df 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -292,6 +292,7 @@ post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index eb38a29..4c6292f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -212,6 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 74c0aaa..7dcca17 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -227,6 +227,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index ff7fb9c..37993aa 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES - select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 68c6e35..9206de7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -897,10 +897,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 94f33b7..0c37840 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -728,6 +728,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -742,5 +746,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 658e954..a5f11a6 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -88,6 +88,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; @@ -98,6 +102,7 @@ void backup_top_of_ram(uint64_t ramtop) nvram_pos++; } } +#endif static void sb700_lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 69bc3bd..300b54e 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -673,6 +673,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -687,5 +691,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif

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Patch set updated for coreboot: 65fb7ae northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA
by Timothy Pearson 16 Mar '15

16 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8664 -gerrit commit 65fb7ae5fabf0fbde9a1f824bb290dae840f9a58 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:10:29 2015 -0500 northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA is enabled, however when GFXUMA is disabled an attempt was made to locate the CBMEM memory segment above the I/O hole in certain rare cases. Removing this special case does not impact functionality, and paves the way for early CBMEM support. Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e2b1441..68c6e35 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -756,7 +756,6 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -879,8 +878,6 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -897,15 +894,13 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } #if CONFIG_GFXUMA set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else - set_top_of_ram(ramtop); + set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) {

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Patch set updated for coreboot: aab72c1 southbridge/amd/pi: Enable early I/O decode to LPC
by Dave Frodin 16 Mar '15

16 Mar '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8661 -gerrit commit aab72c1fb62f7f208de7c743642cf1e067721f9a Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Mar 13 08:22:17 2015 -0600 southbridge/amd/pi: Enable early I/O decode to LPC The decode of UART addresses down to the LPC bus needs to occur early to allow romstage console messages to be seen. This enables the decode of most of the I/O ports typically seen in a system. Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/pi/hudson/early_setup.c | 24 ++++++++++++++++++++ src/southbridge/amd/pi/hudson/hudson.h | 35 +++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 9500d0e..08697b9 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -28,6 +28,7 @@ #include <arch/cpu.h> #include <cbmem.h> #include "hudson.h" +#include "pci_devs.h" void hudson_pci_port80(void) { @@ -93,6 +94,29 @@ void hudson_lpc_port80(void) pci_write_config8(dev, 0x4a, byte); } +void hudson_lpc_decode(void) +{ + device_t dev; + u32 tmp = 0; + + /* Enable I/O decode to LPC bus */ + dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); + tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 + | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 + | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 + | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 + | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 + | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 + | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 + | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 + | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT + | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT + | DECODE_ENABLE_ADLIB_PORT; + + pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); +} + int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { int i; diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 90c3205..6cd0f78 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -55,6 +55,40 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 +#define LPC_IO_PORT_DECODE_ENABLE 0x44 +#define DECODE_ENABLE_PARALLEL_PORT0 (1 << 0) +#define DECODE_ENABLE_PARALLEL_PORT1 (1 << 1) +#define DECODE_ENABLE_PARALLEL_PORT2 (1 << 2) +#define DECODE_ENABLE_PARALLEL_PORT3 (1 << 3) +#define DECODE_ENABLE_PARALLEL_PORT4 (1 << 4) +#define DECODE_ENABLE_PARALLEL_PORT5 (1 << 5) +#define DECODE_ENABLE_SERIAL_PORT0 (1 << 6) +#define DECODE_ENABLE_SERIAL_PORT1 (1 << 7) +#define DECODE_ENABLE_SERIAL_PORT2 (1 << 8) +#define DECODE_ENABLE_SERIAL_PORT3 (1 << 9) +#define DECODE_ENABLE_SERIAL_PORT4 (1 << 10) +#define DECODE_ENABLE_SERIAL_PORT5 (1 << 11) +#define DECODE_ENABLE_SERIAL_PORT6 (1 << 12) +#define DECODE_ENABLE_SERIAL_PORT7 (1 << 13) +#define DECODE_ENABLE_AUDIO_PORT0 (1 << 14) +#define DECODE_ENABLE_AUDIO_PORT1 (1 << 15) +#define DECODE_ENABLE_AUDIO_PORT2 (1 << 16) +#define DECODE_ENABLE_AUDIO_PORT3 (1 << 17) +#define DECODE_ENABLE_MIDI_PORT0 (1 << 18) +#define DECODE_ENABLE_MIDI_PORT1 (1 << 19) +#define DECODE_ENABLE_MIDI_PORT2 (1 << 20) +#define DECODE_ENABLE_MIDI_PORT3 (1 << 21) +#define DECODE_ENABLE_MSS_PORT0 (1 << 22) +#define DECODE_ENABLE_MSS_PORT1 (1 << 23) +#define DECODE_ENABLE_MSS_PORT2 (1 << 24) +#define DECODE_ENABLE_MSS_PORT3 (1 << 25) +#define DECODE_ENABLE_FDC_PORT0 (1 << 26) +#define DECODE_ENABLE_FDC_PORT1 (1 << 27) +#define DECODE_ENABLE_GAME_PORT (1 << 28) +#define DECODE_ENABLE_KBC_PORT (1 << 29) +#define DECODE_ENABLE_ACPIUC_PORT (1 << 30) +#define DECODE_ENABLE_ADLIB_PORT (1 << 31) + static inline int hudson_sata_enable(void) { /* True if IDE or AHCI. */ @@ -76,6 +110,7 @@ u16 pm_read16(u16 reg); #ifdef __PRE_RAM__ void hudson_lpc_port80(void); +void hudson_lpc_decode(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void);

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Patch merged into coreboot/master: 84c72de northbridge/amd/pi: Create common agesawrapper.c
by gerrit＠coreboot.org 16 Mar '15

16 Mar '15

the following patch was just integrated into master: commit 84c72dedab605ac79c51d4666e0aa739e05ed973 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Mar 12 13:41:44 2015 -0600 northbridge/amd/pi: Create common agesawrapper.c This removes the mainboard agesawrapper.c file from binarypi based boards and creates a common one. Change-Id: I900dba914f1c401e4ac732eb93d94b98216e629a Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8671 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/8671 for details. -gerrit

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Patch merged into coreboot/master: 4b45dd3 cpu/amd/pi: Add amd_initcpuio() and amd_initmmio()
by gerrit＠coreboot.org 16 Mar '15

16 Mar '15

the following patch was just integrated into master: commit 4b45dd325370b8f3ea11ab103230e131f470e78b Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Mar 13 09:29:20 2015 -0600 cpu/amd/pi: Add amd_initcpuio() and amd_initmmio() This makes the change to the cpu/amd/pi/00730F01 that was made for the cpu/amd/agesa based boards in: commit 48518f0d AGESA: Add amd_initcpuio() and amd_initmmio() These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). The equivalent change has already been made for cpu/amd/pi/00630F01. Change-Id: I591b50ee807436f5a1dee14d2c88a77462024744 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8670 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/8670 for details. -gerrit

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Patch set updated for coreboot: 10c37f7 lib: Add Kconfig option to enable/disable auto fallback control
by Timothy Pearson 16 Mar '15

16 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8698 -gerrit commit 10c37f72d7151158787ec8c147d6a980efe6152c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 16 11:47:45 2015 -0500 lib: Add Kconfig option to enable/disable auto fallback control Under certain conditions, e.g. automated testing, it is useful to have the payload (e.g. Linux) reset the reboot_bits CMOS value. This allows automated recovery in the case of coreboot starting properly but the payload failing to start due to bad configuration data provided by the coreboot image under test. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Change-Id: Ifc8f565f8292941d90b2e520cc9c5993b41e9cdd --- src/Kconfig | 8 ++++++++ src/lib/fallback_boot.c | 5 +++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index a0758bc..6cabc70 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -236,6 +236,14 @@ config BOOTBLOCK_SOURCE default "bootblock_simple.c" if BOOTBLOCK_SIMPLE default "bootblock_normal.c" if BOOTBLOCK_NORMAL +config SKIP_MAX_REBOOT_CNT_CLEAR + bool "Do not clear reboot count after successful boot" + default n + depends on EXPERT + help + Do not clear the reboot count immediately after successful boot. + Set to allow the payload to control normal/fallback image recovery. + config UPDATE_IMAGE bool "Update existing coreboot.rom image" default n diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index b956c94..74572df 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -22,8 +22,9 @@ static void set_boot_successful(void) byte |= (byte & (1 << 1)) >> 1; /* If we are in normal mode set the boot count to 0 */ - if(byte & 1) - byte &= 0x0f; + if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) + if(byte & 1) + byte &= 0x0f; outb(byte, RTC_PORT(1)); } #else

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Patch set updated for coreboot: 1bf6530 lib: Add Kconfig option to enable/disable auto fallback control
by Timothy Pearson 16 Mar '15

16 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8698 -gerrit commit 1bf65305af8e48fa0ca30c3cd9c780024a4226e5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 16 11:47:45 2015 -0500 lib: Add Kconfig option to enable/disable auto fallback control Under certain conditions, e.g. automated testing, it is useful to have the payload (e.g. Linux) reset the reboot_bits CMOS value. This allows automated recovery in the case of coreboot starting properly but the payload failing to start due to bad configuration data provided by the coreboot image under test. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Change-Id: Ifc8f565f8292941d90b2e520cc9c5993b41e9cdd --- src/Kconfig | 8 ++++++++ src/lib/fallback_boot.c | 5 +++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index a0758bc..806e728 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -236,6 +236,14 @@ config BOOTBLOCK_SOURCE default "bootblock_simple.c" if BOOTBLOCK_SIMPLE default "bootblock_normal.c" if BOOTBLOCK_NORMAL +config SKIP_MAX_REBOOT_CNT_CLEAR + bool "Do not clear reboot count after successful boot" + default y + depends on EXPERT + help + Do not clear the reboot count immediately after successful boot. + Set to allow the payload to control normal/fallback image recovery. + config UPDATE_IMAGE bool "Update existing coreboot.rom image" default n diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index b956c94..74572df 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -22,8 +22,9 @@ static void set_boot_successful(void) byte |= (byte & (1 << 1)) >> 1; /* If we are in normal mode set the boot count to 0 */ - if(byte & 1) - byte &= 0x0f; + if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) + if(byte & 1) + byte &= 0x0f; outb(byte, RTC_PORT(1)); } #else

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New patch to review for coreboot: c70726f lib: Add Kconfig option to enable/disable auto fallback control
by Timothy Pearson 16 Mar '15

16 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8698 -gerrit commit c70726f5696f81df23a88587955b90c96e538cfe Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 16 11:47:45 2015 -0500 lib: Add Kconfig option to enable/disable auto fallback control Under certain conditions, e.g. automated testing, it is useful to have the payload (e.g. Linux) reset the reboot_bits CMOS value. This allows automated recovery in the case of coreboot starting properly but the payload failing to start due to bad configuration data provided by the coreboot image under test. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Change-Id: Ifc8f565f8292941d90b2e520cc9c5993b41e9cdd --- src/Kconfig | 10 +++++++++- src/lib/fallback_boot.c | 5 +++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index a0758bc..ecf0573 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -236,6 +236,14 @@ config BOOTBLOCK_SOURCE default "bootblock_simple.c" if BOOTBLOCK_SIMPLE default "bootblock_normal.c" if BOOTBLOCK_NORMAL +config CLEAR_MAX_REBOOT_CNT + bool "Clear reboot count after successful boot" + default y + depends on EXPERT + help + Clear the reboot count immediately after successful boot. + Unset to allow the payload to control normal/fallback image recovery. + config UPDATE_IMAGE bool "Update existing coreboot.rom image" default n @@ -1169,4 +1177,4 @@ config REG_SCRIPT # TODO: Improve description. config MAX_REBOOT_CNT int - default 3 + default 3 \ No newline at end of file diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index b956c94..b191589 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -22,8 +22,9 @@ static void set_boot_successful(void) byte |= (byte & (1 << 1)) >> 1; /* If we are in normal mode set the boot count to 0 */ - if(byte & 1) - byte &= 0x0f; + if (IS_ENABLED(CONFIG_CLEAR_MAX_REBOOT_CNT)) + if(byte & 1) + byte &= 0x0f; outb(byte, RTC_PORT(1)); } #else

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Patch set updated for coreboot: 96912df northbride/i945/gma: undo change that hardcodes tft_brightness
by Francis Rowe 16 Mar '15

16 Mar '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8697 -gerrit commit 96912dff82721788b6d0ab3f789d8b4f214d62df Author: Francis Rowe <info(a)gluglug.org.uk> Date: Mon Mar 16 07:06:30 2015 +0000 northbride/i945/gma: undo change that hardcodes tft_brightness Change-Id: Ib421d33da7e853f509e9e58fad864fb8a36526de Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/i945/gma.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index cee0640..d556a06 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -472,14 +472,17 @@ static void gma_func0_disable(struct device *dev) static void gma_func1_init(struct device *dev) { u32 reg32; + u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */ - pci_write_config8(dev, 0xf4, 0xff); + if (get_option(&val, "tft_brightness") == CB_SUCCESS) + pci_write_config8(dev, 0xf4, val); + else + pci_write_config8(dev, 0xf4, 0xff); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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Patch set updated for coreboot: 928c6d2 northbride/i945/gma: undo change that hardcodes tft_brightness
by Francis Rowe 16 Mar '15

16 Mar '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8697 -gerrit commit 928c6d26fabbf13c5249138389cd8527da6976e8 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Mon Mar 16 07:06:30 2015 +0000 northbride/i945/gma: undo change that hardcodes tft_brightness It was an accident. Change-Id: Ib421d33da7e853f509e9e58fad864fb8a36526de Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/i945/gma.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index cee0640..d556a06 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -472,14 +472,17 @@ static void gma_func0_disable(struct device *dev) static void gma_func1_init(struct device *dev) { u32 reg32; + u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */ - pci_write_config8(dev, 0xf4, 0xff); + if (get_option(&val, "tft_brightness") == CB_SUCCESS) + pci_write_config8(dev, 0xf4, val); + else + pci_write_config8(dev, 0xf4, 0xff); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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coreboot-gerrit March 2015