coreboot-gerrit March 2015

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Patch set updated for coreboot: 3464592 northbridge/i945/gma: fix build error with native graphics init
by Francis Rowe 15 Mar '15

15 Mar '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8696 -gerrit commit 34645923706f7ba050bb8602976036774249186d Author: Francis Rowe <info(a)gluglug.org.uk> Date: Mon Mar 16 05:31:40 2015 +0000 northbridge/i945/gma: fix build error with native graphics init Tested on an X60, Native graphics init still works perfectly. Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/i945/gma.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 204ba01..cee0640 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -51,7 +51,7 @@ #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT -static int gtt_setup(unsigned int mmiobase) +static int gtt_setup(void *mmiobase) { unsigned long PGETBL_save; unsigned long tom; // top of memory @@ -87,7 +87,7 @@ static int gtt_setup(unsigned int mmiobase) static int intel_gma_init(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, - unsigned int pmmio, unsigned int pgfx) + void *pmmio, unsigned int pgfx) { struct edid edid; u8 edid_data[128]; @@ -107,7 +107,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, u16 reg16; printk(BIOS_SPEW, - "i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", + "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", (void *)pgfx, pmmio, piobase, pphysbase); intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); @@ -432,11 +432,12 @@ static void gma_func0_init(struct device *dev) #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); - u32 iobase, mmiobase, graphics_base; + void *mmiobase; + u32 iobase, graphics_base; struct northbridge_intel_i945_config *conf = dev->chip_info; iobase = dev->resource_list[1].base; - mmiobase = dev->resource_list[0].base; + mmiobase = (void *)(uintptr_t)dev->resource_list[0].base; graphics_base = dev->resource_list[2].base; printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", @@ -471,17 +472,14 @@ static void gma_func0_disable(struct device *dev) static void gma_func1_init(struct device *dev) { u32 reg32; - u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - if (get_option(&val, "tft_brightness") == CB_SUCCESS) - pci_write_config8(dev, 0xf4, val); - else - pci_write_config8(dev, 0xf4, 0xff); + /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */ + pci_write_config8(dev, 0xf4, 0xff); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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Patch set updated for coreboot: 5749450 northbridge/i945/gma: fix build error with native graphics init
by Francis Rowe 15 Mar '15

15 Mar '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8696 -gerrit commit 5749450742a43ab33bd67ee87075f15cdd87f392 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Mon Mar 16 05:31:40 2015 +0000 northbridge/i945/gma: fix build error with native graphics init Tested on an X60, and confirmed working. Native graphics init still works perfectly. Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/i945/gma.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 204ba01..cee0640 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -51,7 +51,7 @@ #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT -static int gtt_setup(unsigned int mmiobase) +static int gtt_setup(void *mmiobase) { unsigned long PGETBL_save; unsigned long tom; // top of memory @@ -87,7 +87,7 @@ static int gtt_setup(unsigned int mmiobase) static int intel_gma_init(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, - unsigned int pmmio, unsigned int pgfx) + void *pmmio, unsigned int pgfx) { struct edid edid; u8 edid_data[128]; @@ -107,7 +107,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, u16 reg16; printk(BIOS_SPEW, - "i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", + "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", (void *)pgfx, pmmio, piobase, pphysbase); intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); @@ -432,11 +432,12 @@ static void gma_func0_init(struct device *dev) #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); - u32 iobase, mmiobase, graphics_base; + void *mmiobase; + u32 iobase, graphics_base; struct northbridge_intel_i945_config *conf = dev->chip_info; iobase = dev->resource_list[1].base; - mmiobase = dev->resource_list[0].base; + mmiobase = (void *)(uintptr_t)dev->resource_list[0].base; graphics_base = dev->resource_list[2].base; printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", @@ -471,17 +472,14 @@ static void gma_func0_disable(struct device *dev) static void gma_func1_init(struct device *dev) { u32 reg32; - u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - if (get_option(&val, "tft_brightness") == CB_SUCCESS) - pci_write_config8(dev, 0xf4, val); - else - pci_write_config8(dev, 0xf4, 0xff); + /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */ + pci_write_config8(dev, 0xf4, 0xff); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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Patch set updated for coreboot: 241e1a5 northbridge/i945/gma: fix build error with native graphics init
by Francis Rowe 15 Mar '15

15 Mar '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8696 -gerrit commit 241e1a562b3c54c2447ad9156a727b033f34f534 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Mon Mar 16 05:31:40 2015 +0000 northbridge/i945/gma: fix build error with native graphics init Tested and working. Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/i945/gma.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 204ba01..cee0640 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -51,7 +51,7 @@ #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT -static int gtt_setup(unsigned int mmiobase) +static int gtt_setup(void *mmiobase) { unsigned long PGETBL_save; unsigned long tom; // top of memory @@ -87,7 +87,7 @@ static int gtt_setup(unsigned int mmiobase) static int intel_gma_init(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, - unsigned int pmmio, unsigned int pgfx) + void *pmmio, unsigned int pgfx) { struct edid edid; u8 edid_data[128]; @@ -107,7 +107,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, u16 reg16; printk(BIOS_SPEW, - "i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", + "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", (void *)pgfx, pmmio, piobase, pphysbase); intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); @@ -432,11 +432,12 @@ static void gma_func0_init(struct device *dev) #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); - u32 iobase, mmiobase, graphics_base; + void *mmiobase; + u32 iobase, graphics_base; struct northbridge_intel_i945_config *conf = dev->chip_info; iobase = dev->resource_list[1].base; - mmiobase = dev->resource_list[0].base; + mmiobase = (void *)(uintptr_t)dev->resource_list[0].base; graphics_base = dev->resource_list[2].base; printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", @@ -471,17 +472,14 @@ static void gma_func0_disable(struct device *dev) static void gma_func1_init(struct device *dev) { u32 reg32; - u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - if (get_option(&val, "tft_brightness") == CB_SUCCESS) - pci_write_config8(dev, 0xf4, val); - else - pci_write_config8(dev, 0xf4, 0xff); + /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */ + pci_write_config8(dev, 0xf4, 0xff); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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New patch to review for coreboot: c073c06 northbridge/i945/gma: fix build error with native graphics init
by Francis Rowe 15 Mar '15

15 Mar '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8696 -gerrit commit c073c0680c266c7f67091628b0cd459e0c805e17 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Mon Mar 16 05:31:40 2015 +0000 northbridge/i945/gma: fix build error with native graphics init Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/i945/gma.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 204ba01..cee0640 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -51,7 +51,7 @@ #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT -static int gtt_setup(unsigned int mmiobase) +static int gtt_setup(void *mmiobase) { unsigned long PGETBL_save; unsigned long tom; // top of memory @@ -87,7 +87,7 @@ static int gtt_setup(unsigned int mmiobase) static int intel_gma_init(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, - unsigned int pmmio, unsigned int pgfx) + void *pmmio, unsigned int pgfx) { struct edid edid; u8 edid_data[128]; @@ -107,7 +107,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, u16 reg16; printk(BIOS_SPEW, - "i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", + "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", (void *)pgfx, pmmio, piobase, pphysbase); intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); @@ -432,11 +432,12 @@ static void gma_func0_init(struct device *dev) #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); - u32 iobase, mmiobase, graphics_base; + void *mmiobase; + u32 iobase, graphics_base; struct northbridge_intel_i945_config *conf = dev->chip_info; iobase = dev->resource_list[1].base; - mmiobase = dev->resource_list[0].base; + mmiobase = (void *)(uintptr_t)dev->resource_list[0].base; graphics_base = dev->resource_list[2].base; printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", @@ -471,17 +472,14 @@ static void gma_func0_disable(struct device *dev) static void gma_func1_init(struct device *dev) { u32 reg32; - u8 val; /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - if (get_option(&val, "tft_brightness") == CB_SUCCESS) - pci_write_config8(dev, 0xf4, val); - else - pci_write_config8(dev, 0xf4, 0xff); + /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */ + pci_write_config8(dev, 0xf4, 0xff); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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Patch merged into coreboot/master: ac490b8 coreboot: rk3288: Add a stub implementation of the rk3288 SOC
by gerrit＠coreboot.org 15 Mar '15

15 Mar '15

the following patch was just integrated into master: commit ac490b8a6bb31bf39fe8087ac3ba6a9b814beb87 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Sun Jun 22 20:40:39 2014 -0700 coreboot: rk3288: Add a stub implementation of the rk3288 SOC Most things still needs to be filled in, but this will allow us to build boards which use this SOC. BUG=chrome-os-partner:29778 TEST=emerge-veyron coreboot Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205069 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239 Reviewed-on: http://review.coreboot.org/8653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8653 for details. -gerrit

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Patch merged into coreboot/master: a74d569 genbuild_h.sh: use the last git commit as timesource if available
by gerrit＠coreboot.org 15 Mar '15

15 Mar '15

the following patch was just integrated into master: commit a74d569731ab19a81a1c125b9d65659408649265 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Mar 7 01:50:22 2015 +0100 genbuild_h.sh: use the last git commit as timesource if available Change-Id: I1472265adac9406a86da22839199ec6bbdaa0c69 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: http://review.coreboot.org/8619 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8619 for details. -gerrit

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New patch to review for coreboot: 00a2ae7 x86: Make stdint.h x64 proof
by Stefan Reinauer 15 Mar '15

15 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8695 -gerrit commit 00a2ae76c213a2118d2ce835ce6561c985bf3e5a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 15 19:49:11 2015 +0100 x86: Make stdint.h x64 proof Change-Id: Ibcfdc08c9aac02fe263afd629fc262f71da80e9a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/arch/x86/include/stdint.h | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/stdint.h b/src/arch/x86/include/stdint.h index e8453ab..fdfa4d8 100644 --- a/src/arch/x86/include/stdint.h +++ b/src/arch/x86/include/stdint.h @@ -1,5 +1,5 @@ -#ifndef I386_STDINT_H -#define I386_STDINT_H +#ifndef X86_STDINT_H +#define X86_STDINT_H #if defined(__GNUC__) #define __HAVE_LONG_LONG__ 1 @@ -53,8 +53,8 @@ typedef signed long long int_fast64_t; #endif /* Types for `void *' pointers. */ -typedef int intptr_t; -typedef unsigned int uintptr_t; +typedef long intptr_t; +typedef unsigned long uintptr_t; /* Largest integral types */ #if __HAVE_LONG_LONG__ @@ -85,6 +85,18 @@ typedef uint8_t bool; #ifndef UINT64_MAX # define UINT64_MAX (18446744073709551615ULL) #endif + +#if __x86_64__ + +#ifndef UINT64_C +#define UINT64_C(c) c ## UL +#endif +#ifndef PRIu64 +#define PRIu64 "lu" +#endif + +#else + #ifndef UINT64_C #define UINT64_C(c) c ## ULL #endif @@ -92,7 +104,9 @@ typedef uint8_t bool; #define PRIu64 "llu" #endif +#endif + #undef __HAVE_LONG_LONG__ -#endif /* I386_STDINT_H */ +#endif /* X86_STDINT_H */

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New patch to review for coreboot: 7b8a289 cpu: add x64 class for cpu_microcode
by Stefan Reinauer 15 Mar '15

15 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8694 -gerrit commit 7b8a2893150c4639fe5c5950225cd88c07920fc9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 15 19:43:05 2015 +0100 cpu: add x64 class for cpu_microcode Change-Id: I1535fea97c676ed6465d777f444b0a1a0e023474 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/cpu/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 2411aeb..e51b45f 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -12,6 +12,7 @@ subdirs-y += x86 subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86 $(eval $(call create_class_compiler,cpu_microcode,x86_32)) +$(eval $(call create_class_compiler,cpu_microcode,x86_64)) ################################################################################ ## Rules for building the microcode blob in CBFS ################################################################################

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New patch to review for coreboot: 3ab1167 x86: Make x86 architecture makefiles x64 aware
by Stefan Reinauer 15 Mar '15

15 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8693 -gerrit commit 3ab11673098af7b9175ad7fde76f282ac8e2593c Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 15 19:23:50 2015 +0100 x86: Make x86 architecture makefiles x64 aware Almost all of the code between x86 and x64 can be shared, so select it for either architecture. Change-Id: I681149ed7698c08b702bb19f074f369699cef1bf Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/arch/x86/Makefile.inc | 28 ++++++++++++++++++---------- src/arch/x86/boot/Makefile.inc | 8 ++++---- src/arch/x86/lib/Makefile.inc | 14 ++++++++++---- src/cpu/x86/Makefile.inc | 10 +++++++++- 4 files changed, 41 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a92c55c..4adf7ca 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -51,14 +51,14 @@ cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE)) mbi.bin-type := mbi -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) CBFSTOOL_PRE1_OPTS = -m x86 -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) # Make sure that segment for .car.data is ignored while adding romstage. CBFSTOOL_PRE_OPTS = -b $(shell cat $(objcbfs)/base_xip.txt) -S ".car.data" endif ################################################################################ -# i386 specific tools +# x86 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool $(OPTION_TABLE_H): $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout @@ -74,7 +74,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l # bootblock ############################################################################### -ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) +ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y) bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds @@ -116,7 +116,7 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) $(CFLAGS_x86_32) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm + $(CC_bootblock) $(CFLAGS_bootblock) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" @@ -133,13 +133,13 @@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootbloc $(LD_bootblock) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld -endif # CONFIG_ARCH_BOOTBLOCK_X86_32 +endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ############################################################################### # romstage ############################################################################### -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) crt0s = $(src)/arch/x86/init/prologue.inc ldscripts = @@ -242,19 +242,19 @@ $(objgenerated)/crt0.romstage.S: $$(crt0s) $(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_romstage) $(CFLAGS_x86_32) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm + $(CC_romstage) $(CFLAGS_romstage) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_romstage) $(CPPFLAGS_romstage) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ -endif # CONFIG_ARCH_ROMSTAGE_X86_32 +endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 ############################################################################### # ramstage ############################################################################### -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) ifeq ($(CONFIG_GENERATE_MP_TABLE),y) @@ -300,7 +300,11 @@ ramstage-libs ?= ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32)) +else +$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64)) +endif # The rmodule_link defintion creates an elf file with .rmod extension. $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod @@ -316,9 +320,13 @@ endif $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(LD_ramstage) -m elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --start-group $(ramstage-objs) $(ramstage-libs) $(COMPILER_RT_ramstage) --end-group +else + $(LD_ramstage) -m elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --start-group $(ramstage-objs) $(ramstage-libs) $(COMPILER_RT_ramstage) --end-group +endif -endif # CONFIG_ARCH_RAMSTAGE_X86_32 +endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 ################################################################################ diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 9f06b4f..12d7a3f 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,11 +1,11 @@ -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-y += cbmem.c -endif # CONFIG_ARCH_ROMSTAGE_X86_32 +endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) ramstage-y += boot.c ramstage-y += gdt.c @@ -18,4 +18,4 @@ ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S -endif # CONFIG_ARCH_RAMSTAGE_X86_32 +endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index c7e8b62..a847a74 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -1,5 +1,5 @@ -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-y += cbfs_and_run.c romstage-y += memset.c @@ -7,9 +7,9 @@ romstage-y += memcpy.c romstage-y += memmove.c romstage-y += rom_media.c -endif # CONFIG_ARCH_ROMSTAGE_X86_32 +endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) ramstage-y += c_start.S ramstage-y += cpu.c @@ -33,8 +33,14 @@ smm-y += memcpy.c smm-y += memmove.c smm-y += rom_media.c +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) rmodules_x86_32-y += memset.c rmodules_x86_32-y += memcpy.c rmodules_x86_32-y += memmove.c +else +rmodules_x86_64-y += memset.c +rmodules_x86_64-y += memcpy.c +rmodules_x86_64-y += memmove.c +endif -endif # CONFIG_ARCH_RAMSTAGE_X86_32 +endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 2347f88..4778a62 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-$(CONFIG_CACHE_AS_RAM) += car.c endif @@ -19,11 +19,19 @@ rmodules_$(ARCH-ramstage-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o $(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^ +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32)) +else +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64)) +endif $(SIPI_BIN): $(SIPI_RMOD) $(OBJCOPY_ramstage) -O binary $< $@ $(SIPI_BIN).ramstage.o: $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) +else + cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) +endif

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New patch to review for coreboot: cfd321e Add x64 support to src/arch/x86/Kconfig
by Stefan Reinauer 15 Mar '15

15 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8692 -gerrit commit cfd321e78412078f19bcb6bb27241fdae96f3ace Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 15 04:34:03 2015 +0100 Add x64 support to src/arch/x86/Kconfig Change-Id: I81f6d8a21ea0d8218f5a4aab2feb39be32f88e01 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/arch/x86/Kconfig | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 580814f..c798050 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +# stage selectors for x86 + config ARCH_BOOTBLOCK_X86_32 bool default n @@ -30,6 +32,25 @@ config ARCH_RAMSTAGE_X86_32 bool default n +# stage selectors for x64 + +config ARCH_BOOTBLOCK_X86_64 + bool + default n + select ARCH_X86 + +config ARCH_VERSTAGE_X86_64 + bool + default n + +config ARCH_ROMSTAGE_X86_64 + bool + default n + +config ARCH_RAMSTAGE_X86_64 + bool + default n + # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description.

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coreboot-gerrit March 2015