coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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2443 discussions

New patch to review for coreboot: 213f3ab northbridge/amd/amdht/h3finit.c: Fix boot failure
by Timothy Pearson 14 Mar '15

14 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8685 -gerrit commit 213f3abf49a05eb83454d20cf75cd34b5cb5fb70 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Mar 14 19:59:54 2015 -0500 northbridge/amd/amdht/h3finit.c: Fix boot failure GIT hash 586d6e introduced a regression that causes boot failure with an f0011449 AMD stop code. Change-Id: Ieced9088b79bc89d55117b7240b82a086eff9d21 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/h3finit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 47bf809..1f94b44 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -77,7 +77,7 @@ static const uint16_t ht_speed_limit[16] = static const struct ht_speed_limit_map_t { uint16_t mhz; - uint8_t config; + uint8_t nvram; } ht_speed_limit_map[] = { {0, NVRAM_LIMIT_HT_SPEED_AUTO}, {200, NVRAM_LIMIT_HT_SPEED_200}, @@ -102,7 +102,7 @@ static const uint16_t ht_speed_mhz_to_hw(uint16_t mhz) size_t i; for (i = 0; i < ARRAY_SIZE(ht_speed_limit_map); i++) if (ht_speed_limit_map[i].mhz == mhz) - return ht_speed_limit_map[i].config; + return ht_speed_limit[ht_speed_limit_map[i].nvram]; printk(BIOS_WARNING, "WARNING: Invalid HT link limit frequency %d specified, ignoring...\n",

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New patch to review for coreboot: 430ca1d mainboard/asus/kfsn4-dre: Fix incorrect reboot_bits location
by Timothy Pearson 14 Mar '15

14 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8684 -gerrit commit 430ca1d96b4553daabcd6a33948a7b8c792f2fab Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Mar 14 17:59:51 2015 -0500 mainboard/asus/kfsn4-dre: Fix incorrect reboot_bits location Change-Id: Iead07df714f4f1bbaae6b564431fb4edf7b18ac2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/cmos.layout | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout index da1a586..8c541ec 100644 --- a/src/mainboard/asus/kfsn4-dre/cmos.layout +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -25,7 +25,7 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 385 1 e 4 last_boot -389 4 r 0 reboot_bits +388 4 r 0 reboot_bits 393 3 e 5 baud_rate 396 5 e 10 ecc_scrub_rate 401 1 e 1 interleave_chip_selects

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New patch to review for coreboot: 96d8b19 mainboard/asus/kfsn4-dre: Change default debug level to Spew
by Timothy Pearson 14 Mar '15

14 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8683 -gerrit commit 96d8b19de9a1f13be78c5403f01b60ea4092418e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Mar 14 17:58:24 2015 -0500 mainboard/asus/kfsn4-dre: Change default debug level to Spew This brings the KFSN4-DRE in line with other boards in the tree. Change-Id: I9216130f51ed0576871fd27ca6ae4610c5f5810e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/cmos.default | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/kfsn4-dre/cmos.default b/src/mainboard/asus/kfsn4-dre/cmos.default index 269f407..68f5712 100644 --- a/src/mainboard/asus/kfsn4-dre/cmos.default +++ b/src/mainboard/asus/kfsn4-dre/cmos.default @@ -1,5 +1,5 @@ baud_rate = 115200 -debug_level = Alert +debug_level = Spew multi_core = Enable slow_cpu = off hypertransport_speed_limit = Auto @@ -10,4 +10,4 @@ ecc_scrub_rate = 1.28us interleave_chip_selects = Enable interleave_nodes = Disable interleave_memory_channels = Enable -power_on_after_fail = Enable \ No newline at end of file +power_on_after_fail = Enable

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Patch set updated for coreboot: ff149c8 xcompile: add support for x86-64
by Stefan Reinauer 14 Mar '15

14 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8669 -gerrit commit ff149c8b2f699f37892ea8fed2803bf5678eaa60 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 13 22:52:47 2015 +0100 xcompile: add support for x86-64 Add support for detecting an x86-64 cross compiler in xcompile. Change-Id: Icd2c9af7903956216db1fd54902eab6da0fe3e21 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- util/xcompile/xcompile | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 29cad28..d13358c 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -135,7 +135,7 @@ detect_special_flags() { CFLAGS="$CFLAGS -Wl,--build-id=none" case "$architecture" in - x86) + x86|x64) testcc "$CC" "$CFLAGS -Wa,--divide" && CFLAGS="$CFLAGS -Wa,--divide" # Always build for i686 -- no sse/mmx instructions since SMM @@ -168,7 +168,7 @@ EOF } # Architecture definition -SUPPORTED_ARCHITECTURE="x86 arm arm64 riscv mipsel" +SUPPORTED_ARCHITECTURE="x86 x64 arm arm64 riscv mipsel" arch_config_arm() { TARCH="arm" @@ -196,6 +196,14 @@ arch_config_riscv() { TABI="elf" } +arch_config_x64() { + TARCH="x86_64" + TBFDARCH="x86-64" + TCLIST="x86_64" + TWIDTH="64" + TABI="elf" +} + arch_config_x86() { TARCH="x86_32" TBFDARCH="i386"

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Patch set updated for coreboot: 4a2277f xcompile: add support for x86-64
by Stefan Reinauer 14 Mar '15

14 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8669 -gerrit commit 4a2277f2803783f8ace5a6b8bef868a9a15929fd Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 13 22:52:47 2015 +0100 xcompile: add support for x86-64 Add support for detecting an x86-64 cross compiler in xcompile. Change-Id: Icd2c9af7903956216db1fd54902eab6da0fe3e21 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- util/xcompile/xcompile | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 29cad28..d13358c 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -135,7 +135,7 @@ detect_special_flags() { CFLAGS="$CFLAGS -Wl,--build-id=none" case "$architecture" in - x86) + x86|x64) testcc "$CC" "$CFLAGS -Wa,--divide" && CFLAGS="$CFLAGS -Wa,--divide" # Always build for i686 -- no sse/mmx instructions since SMM @@ -168,7 +168,7 @@ EOF } # Architecture definition -SUPPORTED_ARCHITECTURE="x86 arm arm64 riscv mipsel" +SUPPORTED_ARCHITECTURE="x86 x64 arm arm64 riscv mipsel" arch_config_arm() { TARCH="arm" @@ -196,6 +196,14 @@ arch_config_riscv() { TABI="elf" } +arch_config_x64() { + TARCH="x86_64" + TBFDARCH="x86-64" + TCLIST="x86_64" + TWIDTH="64" + TABI="elf" +} + arch_config_x86() { TARCH="x86_32" TBFDARCH="i386"

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Patch set updated for coreboot: 416bb3e crossgcc: Add x86_64 to list of supported architectures
by Stefan Reinauer 14 Mar '15

14 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8668 -gerrit commit 416bb3efd47c8a0fc953ee6d98839ad36ab942df Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 13 22:50:22 2015 +0100 crossgcc: Add x86_64 to list of supported architectures You can build your new toolchain with: $ cd util/crossgcc/ $ ./buildgcc -d /opt/cross -p x86_64-elf -j 16 or $ make crossgcc-x64 Change-Id: I8eb584166294578d2b33c63e94ed3aca9b5de4f4 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 14 ++++++++++---- util/crossgcc/Makefile | 9 ++++++++- util/crossgcc/buildgcc | 2 ++ 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 656d988..d4748fc 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -424,12 +424,15 @@ gitconfig: git config remote.origin.push HEAD:refs/for/master (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) -crossgcc: crossgcc-i386 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv +crossgcc: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv -.PHONY: crossgcc-i386 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv +.PHONY: crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 crossgcc-mips crossgcc-riscv crossgcc-i386: clean-for-update $(MAKE) -C util/crossgcc build-i386-without-gdb +crossgcc-x64: clean-for-update + $(MAKE) -C util/crossgcc build-x64-without-gdb + crossgcc-arm: clean-for-update $(MAKE) -C util/crossgcc build-armv7a-without-gdb @@ -442,12 +445,15 @@ crossgcc-mips: clean-for-update crossgcc-riscv: clean-for-update $(MAKE) -C util/crossgcc build-riscv-without-gdb -crosstools: crosstools-i386 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv +crosstools: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv -.PHONY: crosstools-i386 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv +.PHONY: crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-i386: clean-for-update $(MAKE) -C util/crossgcc build-i386 +crosstools-x64: clean-for-update + $(MAKE) -C util/crossgcc build-x64 + crosstools-arm: clean-for-update $(MAKE) -C util/crossgcc build-armv7a diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 2d344e3..2f18b17 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -1,8 +1,11 @@ -all: build-i386 build-armv7a build-aarch64 build-mips build-riscv +all: build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv build-i386: bash ./buildgcc -G -p i386-elf +build-x64: + bash ./buildgcc -G -p x86_64-elf + build-armv7a: bash ./buildgcc -G -p armv7a-eabi @@ -19,6 +22,10 @@ build-riscv: build-i386-without-gdb: bash ./buildgcc -p i386-elf +.PHONY: build-x64-without-gdb +build-x64-without-gdb: + bash ./buildgcc -p x86_64-elf + .PHONY: build-armv7a-without-gdb build-armv7a-without-gdb: bash ./buildgcc -p armv7a-eabi diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 7221b83..ceb1d1d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -232,6 +232,8 @@ while true ; do done case "$TARGETARCH" in + x86_64-elf) ;; + x86_64*) TARGETARCH=x86_64-elf;; i386-elf) ;; i386-mingw32) ;; mipsel-elf) ;;

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New patch to review for coreboot: 274f617 Mediawiki editing warning
by David Hedlund 14 Mar '15

14 Mar '15

David Hedlund (davidhedlund999(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8682 -gerrit commit 274f617c6f11b029eac19f6cd426cef011cef26d Author: David Englund <public(a)beloved.name> Date: Sat Mar 14 19:41:09 2015 +0100 Mediawiki editing warning The file have been updated to warn wiki users to edit the page as it is generated by a bot. Change-Id: I5802ff8c7986c0fd93adf58e2353df81de9c2b75 Signed-off-by: David Englund <public(a)beloved.name> --- util/board_status/to-wiki/foreword.wiki | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/board_status/to-wiki/foreword.wiki b/util/board_status/to-wiki/foreword.wiki index be05c8c..ac8fc97 100644 --- a/util/board_status/to-wiki/foreword.wiki +++ b/util/board_status/to-wiki/foreword.wiki @@ -1,3 +1,5 @@ +This page was generated by a bot. + = coreboot status by mainboard = * This list contains reports of successful coreboot execution, ordered by date. It's shows which boards can actually run with current coreboot versions.

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Patch set updated for coreboot: 42ecb7c cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function
by Timothy Pearson 14 Mar '15

14 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8663 -gerrit commit 42ecb7ce7143ff3d392a742933f7f7084673e37e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 12:48:31 2015 -0500 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function This is required for early CBMEM support. Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/Makefile.inc | 2 ++ src/cpu/amd/model_10xxx/ram_calc.c | 43 ++++++++++++++++++++++++++++++ src/cpu/amd/model_10xxx/ram_calc.h | 25 +++++++++++++++++ src/northbridge/amd/amdfam10/northbridge.c | 17 ++---------- 4 files changed, 72 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index ba12dcd..c17e66c 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -3,6 +3,8 @@ ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c romstage-y += update_microcode.c +romstage-y += ram_calc.c +ramstage-y += ram_calc.c ramstage-y += monotonic_timer.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c new file mode 100644 index 0000000..98b80e9 --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +#include "ram_calc.h" + +uint64_t get_uma_memory_size(uint64_t topmem) +{ + uint64_t uma_size = 0; + if (IS_ENABLED(CONFIG_GFXUMA)) { + /* refer to UMA Size Consideration in 780 BDG. */ + if (topmem > 0x40000000) /* 1GB and above system memory */ + uma_size = 0x10000000; /* 256M recommended UMA */ + + else if (topmem > 0x20000000) /* 512M - 1023M system memory */ + uma_size = 0x8000000; /* 128M recommended UMA */ + + else if (topmem > 0x10000000) /* 256M - 511M system memory */ + uma_size = 0x4000000; /* 64M recommended UMA */ + } + + return uma_size; +} diff --git a/src/cpu/amd/model_10xxx/ram_calc.h b/src/cpu/amd/model_10xxx/ram_calc.h new file mode 100644 index 0000000..7ece338 --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_MODEL_10XXX_MEM_CALC_H_ +#define _AMD_MODEL_10XXX_MEM_CALC_H_ + +uint64_t get_uma_memory_size(uint64_t topmem); + +#endif diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5ce7ae6..e2b1441 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -33,6 +33,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> +#include <cpu/amd/model_10xxx/ram_calc.h> #if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> @@ -740,21 +741,7 @@ static void setup_uma_memory(void) { #if CONFIG_GFXUMA uint32_t topmem = (uint32_t) bsp_topmem(); - /* refer to UMA Size Consideration in 780 BDG. */ - switch (topmem) { - case 0x10000000: /* 256M system memory */ - uma_memory_size = 0x4000000; /* 64M recommended UMA */ - break; - - case 0x20000000: /* 512M system memory */ - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - break; - - default: /* 1GB and above system memory */ - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - break; - } - + uma_memory_size = get_uma_memory_size(topmem); uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base);

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Patch set updated for coreboot: 7067b2a cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit
by Timothy Pearson 14 Mar '15

14 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8489 -gerrit commit 7067b2a98361dbae5d7c7e86891bba290eb0a08c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:27:58 2015 -0500 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/ram_calc.c | 11 +++++++++++ src/mainboard/advansus/a785e-i/romstage.c | 1 + src/mainboard/amd/bimini_fam10/romstage.c | 1 + src/mainboard/amd/mahogany_fam10/romstage.c | 1 + src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 1 + src/mainboard/amd/tilapia_fam10/romstage.c | 1 + src/mainboard/asus/kfsn4-dre/romstage.c | 1 + src/mainboard/asus/m4a78-em/romstage.c | 1 + src/mainboard/asus/m4a785-m/romstage.c | 1 + src/mainboard/asus/m5a88-v/romstage.c | 1 + src/mainboard/avalue/eax-785e/romstage.c | 1 + src/mainboard/gigabyte/ma785gm/romstage.c | 1 + src/mainboard/gigabyte/ma785gmt/romstage.c | 1 + src/mainboard/gigabyte/ma78gm/romstage.c | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 + src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 + src/mainboard/jetway/pa78vm5/romstage.c | 1 + src/mainboard/msi/ms9652_fam10/romstage.c | 1 + src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 + src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 + src/mainboard/supermicro/h8scm_fam10/romstage.c | 1 + src/mainboard/tyan/s2912_fam10/romstage.c | 1 + src/northbridge/amd/amdfam10/Kconfig | 1 - src/northbridge/amd/amdfam10/northbridge.c | 3 --- src/southbridge/amd/sb700/early_setup.c | 5 +++++ src/southbridge/amd/sb700/lpc.c | 5 +++++ src/southbridge/amd/sb800/early_setup.c | 5 +++++ 27 files changed, 47 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c index 98b80e9..dcf4300 100644 --- a/src/cpu/amd/model_10xxx/ram_calc.c +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -22,6 +22,8 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#include <cbmem.h> + #include "ram_calc.h" uint64_t get_uma_memory_size(uint64_t topmem) @@ -41,3 +43,12 @@ uint64_t get_uma_memory_size(uint64_t topmem) return uma_size; } + +void *cbmem_top(void) +{ + uint32_t topmem = rdmsr(TOP_MEM).lo; + + topmem = topmem - get_uma_memory_size(topmem); + + return (void *) topmem; +} diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 19ce53e..c1c9a1b 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index d8a38d7..6d03685 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -198,6 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e6d7f2e..e53c64d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 76bc73f..ef15e83 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -312,6 +312,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index b7f6869..7d2f272 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 0dab8e8..44864f6 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -343,6 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); printk(BIOS_DEBUG, "disable_spd()\n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 7c93767..47b9c83 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 328955a..7ebec29 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index baa38ac..2339478 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index b586198..c1dbaa7 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -201,6 +201,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4ad3d2c..7b0168d 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 590bb93..d0d6c94 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a7b6b1b..8861ab6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index d7e8447..4aefcd2 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -204,6 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); bcm5785_early_setup(); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index b88baa3..991cd55 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 08b6398..df30a69 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -205,6 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 45f05a5..0bdcd38 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -231,6 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index bc1ca24..4615465 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -228,6 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 2be09bc..c8ed2df 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -292,6 +292,7 @@ post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index eb38a29..4c6292f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -212,6 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 74c0aaa..7dcca17 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -227,6 +227,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index ff7fb9c..37993aa 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES - select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 68c6e35..9206de7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -897,10 +897,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 94f33b7..0c37840 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -728,6 +728,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -742,5 +746,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 658e954..a5f11a6 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -88,6 +88,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; @@ -98,6 +102,7 @@ void backup_top_of_ram(uint64_t ramtop) nvram_pos++; } } +#endif static void sb700_lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 69bc3bd..300b54e 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -673,6 +673,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -687,5 +691,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif

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Patch set updated for coreboot: effd389 northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA
by Timothy Pearson 14 Mar '15

14 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8664 -gerrit commit effd389e68049d9cf53fa192ef5391e49d8313ca Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:10:29 2015 -0500 northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA is enabled, however when GFXUMA is disabled an attempt was made to locate the CBMEM memory segment above the I/O hole in certain rare cases. Removing this special case does not impact functionality, and paves the way for early CBMEM support. Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e2b1441..68c6e35 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -756,7 +756,6 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -879,8 +878,6 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -897,15 +894,13 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } #if CONFIG_GFXUMA set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else - set_top_of_ram(ramtop); + set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) {

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coreboot-gerrit March 2015