coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

1 participants
2443 discussions

Patch merged into coreboot/master: 8517f94 OxPCIe952: Fix read8/write8 argument
by gerrit＠coreboot.org 13 Mar '15

13 Mar '15

the following patch was just integrated into master: commit 8517f94bfd89175b47f2bbd004fe8fd0f6183528 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 12 11:33:14 2015 +0200 OxPCIe952: Fix read8/write8 argument This was missed in commit bde6d309 as the driver is not enabled in any configuration by default. Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8660 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/8660 for details. -gerrit

1 0

New patch to review for coreboot: e56b8da t132: Add TTB_BUFFER to resource reserved
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8681 -gerrit commit e56b8da01a4ede1a88e616ada73905546d9d9ffc Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 25 14:50:23 2014 -0700 t132: Add TTB_BUFFER to resource reserved TTB_BUFFER holds the MMU tables. Thus, this memory needs to be preserved while performing a wipe in depthcharge. Hence, marking it as reserved BUG=None BRANCH=None TEST=Compiles successfully and boots upto depthcharge. Error wiping memory tables is fixed. Original-Change-Id: Idd5cd0235d50f7b9617df2cead3bf71012e3b630 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210000 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 670e21ed11f985ca6cfef4f051c71b3c06f9c6ff) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ifcbdd4fdaad0bd4bfe384698b13cc5013317345e --- src/soc/nvidia/tegra132/soc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 3a419bc..f4ef928 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -38,6 +38,10 @@ static void soc_read_resources(device_t dev) reserved_ram_resource(dev, index++, begin * KiB, size * KiB); } + reserved_ram_resource(dev, index++, CONFIG_TTB_BUFFER / KiB, + CONFIG_TTB_SIZE / KiB); + + /* * TODO: Frame buffer needs to handled as a carveout from the below_4G * uintptr_t framebuffer_begin = framebuffer_attributes(&framebuffer_size);

1 0

New patch to review for coreboot: 06f5c05 rush: Update rush Kconfig file
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8680 -gerrit commit 06f5c05c0938d50018ed9dfe183240b465fb5b7b Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 25 14:35:46 2014 -0700 rush: Update rush Kconfig file Update rush Kconfig file to include TPM and RAMSTAGE_INDEX options BUG=None BRANCH=None TEST=Compiles successfully. TPM works. Ramstage boots successfully. Original-Change-Id: Ie55260c710ffcb6a2e04c8658ca6dd3cdec6b6db Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209978 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 0088f5aade8533c6ed235de25934d47cd0743a67) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5c4a54b74546de73eee7e7bae072cc712ce1838f --- src/mainboard/google/rush/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index ebcde63..8c162ec 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHROMEOS select SOC_NVIDIA_TEGRA132 select MAINBOARD_HAS_BOOTBLOCK_INIT + select VIRTUAL_DEV_SWITCH select BOARD_ROMSIZE_KB_4096 @@ -73,4 +74,16 @@ config BOOT_MEDIA_SPI_CHIP_SELECT help Which chip select to use for boot media. +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config DRIVER_TPM_I2C_BUS + hex + default 0x2 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + endif # BOARD_GOOGLE_RUSH

1 0

New patch to review for coreboot: 9d00b02 rush: Add ec_dummy file to enable vboot compilation
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8679 -gerrit commit 9d00b025b8f63d0fb92a2b41101c4ca639373999 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 23 13:48:41 2014 -0700 rush: Add ec_dummy file to enable vboot compilation BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ic11bef85e5c7635000582f87727cd9a33b0b36e3 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209975 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 3d3f0494d8758ef5040384f63d023c042686bd2c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ie15781d10a366b68f0db97378ccb348a4f074995 --- src/mainboard/google/rush/Makefile.inc | 2 ++ src/mainboard/google/rush/ec_dummy.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc index b66cd55..e4520c1 100644 --- a/src/mainboard/google/rush/Makefile.inc +++ b/src/mainboard/google/rush/Makefile.inc @@ -36,6 +36,8 @@ romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += ec_dummy.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec_dummy.c \ No newline at end of file diff --git a/src/mainboard/google/rush/ec_dummy.c b/src/mainboard/google/rush/ec_dummy.c new file mode 100644 index 0000000..01a935c --- /dev/null +++ b/src/mainboard/google/rush/ec_dummy.c @@ -0,0 +1,9 @@ +/* Dummy CHROMEEC file to provide stub functions for vboot compilation */ + +#include <stdint.h> + +int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len); +int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len) +{ + return 0; +}

1 0

New patch to review for coreboot: 150175f rush: Pull in chromeos.c from nyan into rush
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8678 -gerrit commit 150175f4081a9893664ac15f26b889db2e4c4ca3 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 23 13:46:13 2014 -0700 rush: Pull in chromeos.c from nyan into rush Hardcoded values are set for developer,recovery mode. Change as per requirements BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles succesfully for rush Original-Change-Id: Ied506a9d1c4e0ba8ee06d57c6ca8c726220998b5 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209974 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 2e6934d47c5b4bb98e60486202b230bae79d927b) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I36e384b0d331fdd9e3f47954decfddaf4f31aed3 --- src/mainboard/google/rush/Kconfig | 1 + src/mainboard/google/rush/Makefile.inc | 2 + src/mainboard/google/rush/chromeos.c | 90 ++++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+) diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index b3dd3de..ebcde63 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -21,6 +21,7 @@ if BOARD_GOOGLE_RUSH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select CHROMEOS select SOC_NVIDIA_TEGRA132 select MAINBOARD_HAS_BOOTBLOCK_INIT select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc index 3c2b5da..b66cd55 100644 --- a/src/mainboard/google/rush/Makefile.inc +++ b/src/mainboard/google/rush/Makefile.inc @@ -35,5 +35,7 @@ bootblock-y += reset.c romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/rush/chromeos.c b/src/mainboard/google/rush/chromeos.c new file mode 100644 index 0000000..91cb9d8 --- /dev/null +++ b/src/mainboard/google/rush/chromeos.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/nvidia/tegra132/gpio.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = GPIO_R1_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_in_value(GPIO(R1)); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = 1; + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Lid: active high */ + gpios->gpios[count].port = GPIO_R4_INDEX; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = 1; + strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); + count++; + + /* Power: active low */ + gpios->gpios[count].port = GPIO_Q0_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = 1; + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: virtual GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return !gpio_get_in_value(GPIO(R1)); +}

1 0

New patch to review for coreboot: 6a8bb20 Tegra132: Configure CPU clock
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8677 -gerrit commit 6a8bb20e0e517af74048b1f82c4122d9cf47ed5c Author: Jimmy Zhang <jimmzhang(a)nvidia.com> Date: Wed Jul 23 17:42:45 2014 -0700 Tegra132: Configure CPU clock Since CCLK_BURST_POLICY and SUPER_CCLK_DIVIDER are not accesible from AVP, the first place that can change CPU clock is after CPU has been brought up, ie, ramstage in this case. CPU initial clock source is set to PLLP by MTS. BUG=None TEST=Norrin64 and A44 Original-Change-Id: I525bb2fa2be0afba52837bc0178950541535fd22 Original-Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209698 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit ba77e26508bb4a50a08d07ad15632ff1ba501bfa) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Icf2458c491b4b3a553d3e01f88c6f25b25639e89 --- src/soc/nvidia/tegra132/Kconfig | 4 ++ src/soc/nvidia/tegra132/clock.c | 41 ++++++++++++++++ src/soc/nvidia/tegra132/clst_clk.h | 61 ++++++++++++++++++++++++ src/soc/nvidia/tegra132/include/soc/addressmap.h | 3 +- src/soc/nvidia/tegra132/include/soc/clock.h | 2 +- src/soc/nvidia/tegra132/ramstage.c | 3 ++ 6 files changed, 112 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 638fb65..b746037 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -113,4 +113,8 @@ config BOOTROM_SDRAM_INIT help Use during Ryu LPDDR3 bringup +# Default to 700MHz. This value is based on nv bootloader setting. +config PLLX_KHZ + int + default 700000 endif diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index a8cabe5..fb8e85f 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -22,12 +22,14 @@ #include <stdlib.h> #include <arch/clock.h> #include "clk_rst.h" +#include "clst_clk.h" #include "flow.h" #include "maincpu.h" #include "pmc.h" #include "sysctr.h" static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; +static struct clst_clk_ctlr *clst_clk = (void *)TEGRA_CLUSTER_CLOCK_BASE; static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE; static struct tegra_pmc_regs *pmc = (void *)TEGRA_PMC_BASE; static struct sysctr_regs *sysctr = (void *)TEGRA_SYSCTR0_BASE; @@ -474,6 +476,45 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, udelay(IO_STABILIZATION_DELAY); } +void clock_cpu0_config(void) +{ + u32 reg; + u32 osc = clock_get_osc_bits(); + u32 timeout = 0; + + /* disable IDDQ */ + reg = readl(&clst_clk->pllx_misc3); + reg &= ~PLLX_IDDQ; + writel(reg, &clst_clk->pllx_misc3); + + /* init pllx */ + init_pll(&clst_clk->pllx_base, &clst_clk->pllx_misc, + osc_table[osc].pllx, PLLPAXS_MISC_LOCK_ENABLE); + + /* + * Change CPU clock source to PLLX_OUT0_LJ + * when above pllx programming has taken effect. + */ + do { + if (readl(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) { + write32((CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28), + &clst_clk->cclk_brst_pol); + break; + } + + /* wait and try again */ + if (timeout >= CLK_SWITCH_TIMEOUT_US) { + printk(BIOS_ERR, "%s: PLLX programming timeout. " + "Switching cpu clock has falied.\n", + __func__); + break; + } + udelay(10); + timeout += 10; + + } while (1); +} + void clock_halt_avp(void) { for (;;) diff --git a/src/soc/nvidia/tegra132/clst_clk.h b/src/soc/nvidia/tegra132/clst_clk.h new file mode 100644 index 0000000..151ead6 --- /dev/null +++ b/src/soc/nvidia/tegra132/clst_clk.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA132_CLST_CLK_H_ +#define _TEGRA132_CLST_CLK_H_ + +/* Cluster Clock (CLUSTER_CLOCKS_PUBLIC_) regs */ +struct __attribute__ ((__packed__)) clst_clk_ctlr { + u32 pllx_base; /* _PLLX_BASE, 0x000 */ + u32 pllx_misc; /* _PLLX_MISC, 0x004 */ + u32 pllx_misc1; /* _PLLX_MISC_1, 0x008 */ + u32 pllx_misc2; /* _PLLX_MISC_2, 0x00c */ + u32 pllx_misc3; /* _PLLX_MISC_3, 0x010 */ + u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x014 */ + u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x018 */ + u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x01c */ + u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ + u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ + u32 _rsv1[10]; /* 0x028-04c */ + u32 shaper; /* _SHAPER, 0x050 */ + u32 shaper1; /* _SHAPER_1, 0x054 */ + u32 _rsv2[80]; /* 0x058-194 */ + u32 misc_ctrl; /* _MISC_CTRL, 0x198 */ +}; +check_member(clst_clk_ctlr, misc_ctrl, 0x198); + +/* CC_CCLK_BRST_POL */ +enum { + CC_CCLK_BRST_POL_PLLX_OUT0_LJ = 0x8, +}; + +/* CC_SUPER_CCLK_DIVIDER */ +enum { + CC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 +}; + +/* PLLX_MISC3 */ +enum { + PLLX_IDDQ = 1 << 3, +}; + +/* MISC_CTRL */ +enum { + CLK_SWITCH_MATCH = 1 << 5, +}; + +#define CLK_SWITCH_TIMEOUT_US 1000 +#endif /* _TEGRA132_CLST_CLK_H_ */ diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h index 52e4d54..f5f72db 100644 --- a/src/soc/nvidia/tegra132/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -70,7 +70,8 @@ enum { TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, TEGRA_MC_BASE = 0x70019000, TEGRA_EMC_BASE = 0x7001B000, - TEGRA_CSITE_BASE = 0x70040000, + TEGRA_CLUSTER_CLOCK_BASE = 0x70040000, + TEGRA_CSITE_BASE = 0x70800000, TEGRA_SYSCTR0_BASE = 0x700F0000, TEGRA_USBD_BASE = 0x7D000000, TEGRA_USB2_BASE = 0x7D004000, diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h index 6f69fef..5259c18 100644 --- a/src/soc/nvidia/tegra132/include/soc/clock.h +++ b/src/soc/nvidia/tegra132/include/soc/clock.h @@ -285,7 +285,7 @@ void clock_external_output(int clk_id); void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, u32 same_freq); -void clock_cpu0_config_and_reset(void * entry); +void clock_cpu0_config(void); void clock_halt_avp(void); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); void clock_reset_l(u32 l); diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index b3b4db2..40d80ff 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -20,10 +20,13 @@ #include <arch/stages.h> #include <soc/addressmap.h> #include "mmu_operations.h" +#include <soc/clock.h> void arm64_soc_init(void) { trustzone_region_init(); tegra132_mmu_init(); + + clock_cpu0_config(); }

1 0

New patch to review for coreboot: 0c98463 ipq806x: Break apart large transfers in spi_xfer()
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8676 -gerrit commit 0c98463e1684e9aae09c2aac5855a5d1138cab4a Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jul 25 12:59:48 2014 -0700 ipq806x: Break apart large transfers in spi_xfer() The current spi_xfer() function sets the count in hardware and then loops while waiting for the requested number of bytes to be sent or received. However, the number of bytes to be transferred may exceed the maximum count that can be programmed into the controller. This patch re-factors spi_xfer() to split the low-level FIFO handling portions for transmit/receive into their own functions to be called by loops in spi_xfer() which will break large transfers into smaller ones. BUG=chrome-os-partner:30904 BRANCH=storm TEST=built and booted with a >64KB payload on Storm Original-Change-Id: I70743487996cf08cfc602449f2181a7fcd99bfa4 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209838 Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> Original-Tested-by: Trevor Bourget <tbourget(a)codeaurora.org> (cherry picked from commit 5ec28de11f12c2438356f45ce978a17fbb603bf7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0033e0dd96006cfd30a7a4f5e5a052f677e05108 --- src/soc/qualcomm/ipq806x/spi.c | 113 +++++++++++++++++++++++++++-------------- 1 file changed, 75 insertions(+), 38 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index f1a180b..2c16cb6 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -34,6 +34,11 @@ #define GSBI_IDX_TO_GSBI(idx) (idx + 5) + +/* MX_INPUT_COUNT and MX_OUTPUT_COUNT are 16-bits. Zero has a special meaning + * (count function disabled) and does not hold significance in the count. */ +#define MAX_PACKET_COUNT ((64 * KiB) - 1) + /* * TLMM Configuration for SPI NOR * gsbi_pin_conf[bus_num][GPIO_NUM, FUNC_SEL, I/O, @@ -644,12 +649,66 @@ void spi_release_bus(struct spi_slave *slave) ds->initialized = 0; } +static int spi_xfer_tx_packet(struct ipq_spi_slave *ds, + const uint8_t *dout, unsigned out_bytes) +{ + int ret; + + writel_i(out_bytes, ds->regs->qup_mx_output_count); + + ret = config_spi_state(ds, SPI_RUN_STATE); + if (ret) + return ret; + + while (out_bytes) { + if (readl_i(ds->regs->qup_operational) & QUP_OUTPUT_FIFO_FULL) + continue; + + writel_i(*dout++, ds->regs->qup_output_fifo); + out_bytes--; + + /* Wait for output FIFO to drain. */ + if (!out_bytes) + while (readl_i(ds->regs->qup_operational) & + QUP_OUTPUT_FIFO_NOT_EMPTY) + ; + } + + return config_spi_state(ds, SPI_RESET_STATE); +} + +static int spi_xfer_rx_packet(struct ipq_spi_slave *ds, + uint8_t *din, unsigned in_bytes) +{ + int ret; + + writel_i(in_bytes, ds->regs->qup_mx_input_count); + writel_i(in_bytes, ds->regs->qup_mx_output_count); + + ret = config_spi_state(ds, SPI_RUN_STATE); + if (ret) + return ret; + + /* Seed clocking */ + writel_i(0xff, ds->regs->qup_output_fifo); + while (in_bytes) { + if (!(readl_i(ds->regs->qup_operational) & + QUP_INPUT_FIFO_NOT_EMPTY)) + continue; + /* Keep it clocking */ + writel_i(0xff, ds->regs->qup_output_fifo); + + *din++ = readl_i(ds->regs->qup_input_fifo) & 0xff; + in_bytes--; + } + + return config_spi_state(ds, SPI_RESET_STATE); +} + int spi_xfer(struct spi_slave *slave, const void *dout, unsigned out_bytes, void *din, unsigned in_bytes) { int ret; - uint8_t* dbuf; - const uint8_t* dobuf; struct ipq_spi_slave *ds = to_ipq_spi(slave); /* Assert the chip select */ @@ -669,29 +728,17 @@ int spi_xfer(struct spi_slave *slave, const void *dout, clrsetbits_le32_i(ds->regs->qup_config, SPI_QUP_CONF_OUTPUT_MSK, SPI_QUP_CONF_OUTPUT_ENA); - writel_i(out_bytes, ds->regs->qup_mx_output_count); - - ret = config_spi_state(ds, SPI_RUN_STATE); - if (ret) - goto out; - - dobuf = dout; /* Alias to make it possible to use pointer autoinc. */ - while (out_bytes) { - if (readl_i(ds->regs->qup_operational) & QUP_OUTPUT_FIFO_FULL) - continue; + unsigned todo = MIN(out_bytes, MAX_PACKET_COUNT); - writel_i(*dobuf++, ds->regs->qup_output_fifo); - out_bytes--; + ret = spi_xfer_tx_packet(ds, dout, todo); + if (ret) + break; - /* Wait for output FIFO to drain. */ - if (!out_bytes) - while (readl_i(ds->regs->qup_operational) & - QUP_OUTPUT_FIFO_NOT_EMPTY) - ; + out_bytes -= todo; + dout += todo; } - ret = config_spi_state(ds, SPI_RESET_STATE); if (ret) goto out; @@ -703,28 +750,18 @@ spi_receive: clrsetbits_le32_i(ds->regs->qup_config, SPI_QUP_CONF_INPUT_MSK, SPI_QUP_CONF_INPUT_ENA); - writel_i(in_bytes, ds->regs->qup_mx_input_count); - writel_i(in_bytes, ds->regs->qup_mx_output_count); - - ret = config_spi_state(ds, SPI_RUN_STATE); - if (ret) - goto out; - - /* Seed clocking */ - writel_i(0xff, ds->regs->qup_output_fifo); - dbuf = din; /* Alias for pointer autoincrement again. */ while (in_bytes) { - if (!(readl_i(ds->regs->qup_operational) & - QUP_INPUT_FIFO_NOT_EMPTY)) - continue; - /* Keep it clocking */ - writel_i(0xff, ds->regs->qup_output_fifo); + unsigned todo = MIN(in_bytes, MAX_PACKET_COUNT); - *dbuf++ = readl_i(ds->regs->qup_input_fifo) & 0xff; - in_bytes--; + ret = spi_xfer_rx_packet(ds, din, todo); + if (ret) + break; + + in_bytes -= todo; + din += todo; } - out: +out: /* Deassert CS */ CS_change(ds->slave.bus, ds->slave.cs, CS_DEASSERT);

1 0

New patch to review for coreboot: 1b2d3dd cbfstool: Add relocation codes for arm mode
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8675 -gerrit commit 1b2d3ddbe25d12def65d6b685191e2694c1a4098 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 23 13:42:22 2014 -0700 cbfstool: Add relocation codes for arm mode Add relocation codes required for arm mode. These are required by armv4. BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ie7c5b3e07689c85091036a619a65f9fea1918b6b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209973 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit dc5f411f95e02a02b4a4ef4652303ce62aa220c2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ie62ed730080299e474c256371ab88f605b54c10f --- util/cbfstool/elf.h | 3 +++ util/cbfstool/rmodule.c | 5 +++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/util/cbfstool/elf.h b/util/cbfstool/elf.h index 8b56a71..f6356c6 100644 --- a/util/cbfstool/elf.h +++ b/util/cbfstool/elf.h @@ -2222,6 +2222,8 @@ typedef Elf32_Addr Elf32_Conflict; #define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ #define R_ARM_GOT32 26 /* 32 bit GOT entry */ #define R_ARM_PLT32 27 /* 32 bit PLT address */ +#define R_ARM_CALL 28 +#define R_ARM_JUMP24 29 #define R_ARM_THM_JUMP24 30 #define R_ARM_ALU_PCREL_7_0 32 #define R_ARM_ALU_PCREL_15_8 33 @@ -2229,6 +2231,7 @@ typedef Elf32_Addr Elf32_Conflict; #define R_ARM_LDR_SBREL_11_0 35 #define R_ARM_ALU_SBREL_19_12 36 #define R_ARM_ALU_SBREL_27_20 37 +#define R_ARM_V4BX 40 #define R_ARM_GNU_VTENTRY 100 #define R_ARM_GNU_VTINHERIT 101 #define R_ARM_THM_PC11 102 /* thumb unconditional branch */ diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index 966c364..1c8aea7 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -88,9 +88,10 @@ static int valid_reloc_arm(struct rmod_context *ctx, Elf64_Rela *rel) type = ELF64_R_TYPE(rel->r_info); - /* Only these 3 relocations are expected to be found. */ + /* Only these 6 relocations are expected to be found. */ return (type == R_ARM_ABS32 || type == R_ARM_THM_PC22 || - type == R_ARM_THM_JUMP24); + type == R_ARM_THM_JUMP24 || type == R_ARM_V4BX || + type == R_ARM_CALL || type == R_ARM_JUMP24); } static int should_emit_arm(struct rmod_context *ctx, Elf64_Rela *rel)

1 0

Patch merged into coreboot/master: f9fb0d9 Use a common boardid.h instead of per board copies
by gerrit＠coreboot.org 13 Mar '15

13 Mar '15

the following patch was just integrated into master: commit f9fb0d9bf3944e643e76ea9336565e28cef30547 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Jul 23 18:32:01 2014 -0700 Use a common boardid.h instead of per board copies There is no point in duplicating boardid.h per board - they are all the same. Let's keep a single instance in the common include directory and let the linker report a problem if one tries using this function on a board where it is not supported. BUG=chrome-os-partner:30489 TEST=verified that coreboot builds fine for nyan_big and nyan_blaze. Original-Change-Id: Ifbe9c2287a1d828d4db74c637d1d02047ac4da25 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209699 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 589e6415faf18ca6aaf44da343dd33eadc8a53d3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8eef89cb822611a0050e5a50fc4b970eebd8d962 Reviewed-on: http://review.coreboot.org/8666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8666 for details. -gerrit

1 0

Patch merged into coreboot/master: 419fa61 libpayload: ipq808x: stale interrupt shall not be cleared unconditionally
by gerrit＠coreboot.org 13 Mar '15

13 Mar '15

the following patch was just integrated into master: commit 419fa61f370072d82c037f84d8f89d0c4c23480b Author: Yogesh Lal <ylal(a)codeaurora.org> Date: Fri Jun 27 12:07:51 2014 +0530 libpayload: ipq808x: stale interrupt shall not be cleared unconditionally The serial driver hangs in cases when FIFO has more than single word to be processed. Easiest way to reproduce is to paste a string of greater than 4 characters in cli. Clearing the RXSTALE interrupt without draining all the characters from FIFO leads to the issue as the driver is dependent on msm_boot_uart_dm_read function to reinitialize for next transfer. Logically the driver is organized in such a manner that next transfer never gets initiated till rx_data_read < total_rx_data. Clearing the RXSTALE without consideration of total number of characters (or words) unprocessed makes the msm_boot_uart_dm_read to return on the first if conditional. Thus the driver is stuck forever. A quick fix is to avoid clearing the stale interrupt. Reset is handled whenever a new transfer is initialized in msm_boot_uart_dm_init_rx_transfer. BUG=chrome-os-partner:29542 TEST=manual -Paste a string greater than 4 characters in cli. Original-Change-Id: I016afb01a77cd14764f0176f6bf144fb29796c2f Original-Signed-off-by: Yogesh Lal <ylal(a)codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209512 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit 61528884ad2c0a8e146054bbfeb01a3bc73b9692) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I936af5daa52a25f62133bdf9fb44f0b68cf34e88 Reviewed-on: http://review.coreboot.org/8667 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8667 for details. -gerrit

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2015