coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 63a2f91 chromeec: Move SERIQ mode to LPC option
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8665 -gerrit commit 63a2f912de489f5219c1e1434a20872fcf9ebb36 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Mar 13 14:26:08 2015 -0600 chromeec: Move SERIQ mode to LPC option SERIRQ_CONTINUOUS_MODE is specific feature of LPC busses. This fixesa KCONFIG unmet dependency warning on ARM mainboards with chromeec. Change-Id: Iae61986219585dcb1124cf3b24fa32a8596d56c8 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/ec/google/chromeec/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 342db3e..cad1b48 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -1,6 +1,5 @@ config EC_GOOGLE_CHROMEEC bool - select SERIRQ_CONTINUOUS_MODE help Google's Chrome EC @@ -23,6 +22,7 @@ config EC_GOOGLE_CHROMEEC_I2C_CHIP config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. def_bool y + select SERIRQ_CONTINUOUS_MODE help Google Chrome EC via LPC bus.

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Patch merged into coreboot/master: 586d6e2 northbridge/amd/amdht: Allow mainboards to set HT frequency limit
by gerrit＠coreboot.org 13 Mar '15

13 Mar '15

the following patch was just integrated into master: commit 586d6e2a8800f29cdfb6111a91d6e8fc8f4fc43c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Feb 16 14:57:06 2015 -0600 northbridge/amd/amdht: Allow mainboards to set HT frequency limit This is useful when the PCB layout of a mainboard does not allow stable operation at the increased HyperTransport speeds of newer processors. Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8464 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/8464 for details. -gerrit

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Patch set updated for coreboot: f22c974 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function
by Timothy Pearson 13 Mar '15

13 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8663 -gerrit commit f22c974a1d5778ab3c99ea01310e53bcd71d3708 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 12:48:31 2015 -0500 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function This is required for early CBMEM support. Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/Makefile.inc | 2 ++ src/cpu/amd/model_10xxx/ram_calc.c | 48 ++++++++++++++++++++++++++++++ src/cpu/amd/model_10xxx/ram_calc.h | 25 ++++++++++++++++ src/northbridge/amd/amdfam10/northbridge.c | 17 ++--------- 4 files changed, 77 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index ba12dcd..c17e66c 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -3,6 +3,8 @@ ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c romstage-y += update_microcode.c +romstage-y += ram_calc.c +ramstage-y += ram_calc.c ramstage-y += monotonic_timer.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c new file mode 100644 index 0000000..27de0ad --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +#include "ram_calc.h" + +uint64_t get_uma_memory_size(uint64_t topmem) +{ + uint64_t uma_size = 0; + if (IS_ENABLED(CONFIG_GFXUMA)) { + /* refer to UMA Size Consideration in 780 BDG. */ + switch (topmem) { + case 0x10000000: /* 256M system memory */ + uma_size = 0x4000000; /* 64M recommended UMA */ + break; + + case 0x20000000: /* 512M system memory */ + uma_size = 0x8000000; /* 128M recommended UMA */ + break; + + default: /* 1GB and above system memory */ + uma_size = 0x10000000; /* 256M recommended UMA */ + break; + } + } + + return uma_size; +} diff --git a/src/cpu/amd/model_10xxx/ram_calc.h b/src/cpu/amd/model_10xxx/ram_calc.h new file mode 100644 index 0000000..7ece338 --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_MODEL_10XXX_MEM_CALC_H_ +#define _AMD_MODEL_10XXX_MEM_CALC_H_ + +uint64_t get_uma_memory_size(uint64_t topmem); + +#endif diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5ce7ae6..e2b1441 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -33,6 +33,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> +#include <cpu/amd/model_10xxx/ram_calc.h> #if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> @@ -740,21 +741,7 @@ static void setup_uma_memory(void) { #if CONFIG_GFXUMA uint32_t topmem = (uint32_t) bsp_topmem(); - /* refer to UMA Size Consideration in 780 BDG. */ - switch (topmem) { - case 0x10000000: /* 256M system memory */ - uma_memory_size = 0x4000000; /* 64M recommended UMA */ - break; - - case 0x20000000: /* 512M system memory */ - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - break; - - default: /* 1GB and above system memory */ - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - break; - } - + uma_memory_size = get_uma_memory_size(topmem); uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base);

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Patch set updated for coreboot: 0490b60 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit
by Timothy Pearson 13 Mar '15

13 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8489 -gerrit commit 0490b60fde8f9c5c33f3500fa6541f2674c1891a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:27:58 2015 -0500 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/ram_calc.c | 11 +++++++++++ src/mainboard/advansus/a785e-i/romstage.c | 1 + src/mainboard/amd/bimini_fam10/romstage.c | 1 + src/mainboard/amd/mahogany_fam10/romstage.c | 1 + src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 1 + src/mainboard/amd/tilapia_fam10/romstage.c | 1 + src/mainboard/asus/kfsn4-dre/romstage.c | 1 + src/mainboard/asus/m4a78-em/romstage.c | 1 + src/mainboard/asus/m4a785-m/romstage.c | 1 + src/mainboard/asus/m5a88-v/romstage.c | 1 + src/mainboard/avalue/eax-785e/romstage.c | 1 + src/mainboard/gigabyte/ma785gm/romstage.c | 1 + src/mainboard/gigabyte/ma785gmt/romstage.c | 1 + src/mainboard/gigabyte/ma78gm/romstage.c | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 + src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 + src/mainboard/jetway/pa78vm5/romstage.c | 1 + src/mainboard/msi/ms9652_fam10/romstage.c | 1 + src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 + src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 + src/mainboard/supermicro/h8scm_fam10/romstage.c | 1 + src/mainboard/tyan/s2912_fam10/romstage.c | 1 + src/northbridge/amd/amdfam10/Kconfig | 1 - src/northbridge/amd/amdfam10/northbridge.c | 3 --- src/southbridge/amd/sb700/early_setup.c | 5 +++++ src/southbridge/amd/sb700/lpc.c | 5 +++++ src/southbridge/amd/sb800/early_setup.c | 5 +++++ 27 files changed, 47 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c index 27de0ad..1b1d2c6 100644 --- a/src/cpu/amd/model_10xxx/ram_calc.c +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -22,6 +22,8 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#include <cbmem.h> + #include "ram_calc.h" uint64_t get_uma_memory_size(uint64_t topmem) @@ -46,3 +48,12 @@ uint64_t get_uma_memory_size(uint64_t topmem) return uma_size; } + +void *cbmem_top(void) +{ + uint32_t topmem = (uint32_t) rdmsr(TOP_MEM).lo; + + topmem = topmem - get_uma_memory_size(topmem); + + return (void *) topmem; +} diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 19ce53e..c1c9a1b 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index d8a38d7..6d03685 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -198,6 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e6d7f2e..e53c64d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 76bc73f..ef15e83 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -312,6 +312,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index b7f6869..7d2f272 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 0dab8e8..44864f6 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -343,6 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); printk(BIOS_DEBUG, "disable_spd()\n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 7c93767..47b9c83 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 328955a..7ebec29 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index baa38ac..2339478 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index b586198..c1dbaa7 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -201,6 +201,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4ad3d2c..7b0168d 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 590bb93..d0d6c94 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a7b6b1b..8861ab6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index d7e8447..4aefcd2 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -204,6 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); bcm5785_early_setup(); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index b88baa3..991cd55 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 08b6398..df30a69 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -205,6 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 45f05a5..0bdcd38 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -231,6 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index bc1ca24..4615465 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -228,6 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 2be09bc..c8ed2df 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -292,6 +292,7 @@ post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index eb38a29..4c6292f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -212,6 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 74c0aaa..7dcca17 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -227,6 +227,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index ff7fb9c..37993aa 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES - select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 68c6e35..9206de7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -897,10 +897,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 94f33b7..0c37840 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -728,6 +728,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -742,5 +746,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 658e954..a5f11a6 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -88,6 +88,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; @@ -98,6 +102,7 @@ void backup_top_of_ram(uint64_t ramtop) nvram_pos++; } } +#endif static void sb700_lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 69bc3bd..300b54e 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -673,6 +673,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -687,5 +691,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif

1 0

Patch set updated for coreboot: 26f1a2a northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA
by Timothy Pearson 13 Mar '15

13 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8664 -gerrit commit 26f1a2abf3000065cf762c726064cb6363531b44 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:10:29 2015 -0500 northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA is enabled, however when GFXUMA is disabled an attempt was made to locate the CBMEM memory segment above the I/O hole in certain rare cases. Removing this special case does not impact functionality, and paves the way for early CBMEM support. Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e2b1441..68c6e35 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -756,7 +756,6 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -879,8 +878,6 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -897,15 +894,13 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } #if CONFIG_GFXUMA set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else - set_top_of_ram(ramtop); + set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) {

1 0

Patch set updated for coreboot: 21c8750 coreboot: rk3288: Add a stub implementation of the rk3288 SOC
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8653 -gerrit commit 21c875003742d439159d9b5c3db3bbf765c11b51 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Sun Jun 22 20:40:39 2014 -0700 coreboot: rk3288: Add a stub implementation of the rk3288 SOC Most things still needs to be filled in, but this will allow us to build boards which use this SOC. BUG=chrome-os-partner:29778 TEST=emerge-veyron coreboot Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205069 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239 --- src/mainboard/google/Kconfig | 3 + src/mainboard/google/veyron/Kconfig | 59 +++++++++++ src/mainboard/google/veyron/Makefile.inc | 23 ++++ src/mainboard/google/veyron/chromeos.c | 46 ++++++++ src/mainboard/google/veyron/devicetree.cb | 49 +++++++++ src/mainboard/google/veyron/mainboard.c | 51 +++++++++ src/mainboard/google/veyron/romstage.c | 59 +++++++++++ src/soc/Kconfig | 1 + src/soc/Makefile.inc | 1 + src/soc/rockchip/Kconfig | 20 ++++ src/soc/rockchip/Makefile.inc | 20 ++++ src/soc/rockchip/rk3288/Kconfig | 118 +++++++++++++++++++++ src/soc/rockchip/rk3288/Makefile.inc | 39 +++++++ src/soc/rockchip/rk3288/addressmap.h | 102 ++++++++++++++++++ src/soc/rockchip/rk3288/bootblock.c | 28 +++++ src/soc/rockchip/rk3288/cbmem.c | 29 ++++++ src/soc/rockchip/rk3288/media.c | 27 +++++ src/soc/rockchip/rk3288/monotonic_timer.c | 40 +++++++ src/soc/rockchip/rk3288/timer.c | 58 +++++++++++ src/soc/rockchip/rk3288/timer.h | 43 ++++++++ src/soc/rockchip/rk3288/uart.c | 167 ++++++++++++++++++++++++++++++ 21 files changed, 983 insertions(+) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 210bf46..fb1ead6 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -59,6 +59,8 @@ config BOARD_GOOGLE_STORM bool "Storm" config BOARD_GOOGLE_STOUT bool "Stout" +config BOARD_GOOGLE_VEYRON + bool "Veyron" endchoice @@ -81,6 +83,7 @@ source "src/mainboard/google/samus/Kconfig" source "src/mainboard/google/slippy/Kconfig" source "src/mainboard/google/storm/Kconfig" source "src/mainboard/google/stout/Kconfig" +source "src/mainboard/google/veyron/Kconfig" config MAINBOARD_VENDOR string "Mainboard Vendor" diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig new file mode 100644 index 0000000..bbbc617 --- /dev/null +++ b/src/mainboard/google/veyron/Kconfig @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_VEYRON + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select SOC_ROCKCHIP_RK3288 + select MAINBOARD_DO_NATIVE_VGA_INIT + select BOARD_ROMSIZE_KB_4096 + +config MAINBOARD_DIR + string + default google/veyron + +config MAINBOARD_PART_NUMBER + string + default "Veyron" + +config MAINBOARD_VENDOR + string + default "Google" + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 1 + +config DRAM_DMA_START + hex + default 0x10000000 + +config DRAM_DMA_SIZE + hex + default 0x00200000 + +config DRAM_SIZE_MB + int + default 2048 + +endif # BOARD_GOOGLE_VEYRON diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc new file mode 100644 index 0000000..50a6ba0 --- /dev/null +++ b/src/mainboard/google/veyron/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += romstage.c +ramstage-y += mainboard.c +ramstage-y += chromeos.c + diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c new file mode 100644 index 0000000..f396b4b --- /dev/null +++ b/src/mainboard/google/veyron/chromeos.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/google/veyron/devicetree.cb b/src/mainboard/google/veyron/devicetree.cb new file mode 100644 index 0000000..0acbae9 --- /dev/null +++ b/src/mainboard/google/veyron/devicetree.cb @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# TODO fill with Versatile Express board data in QEMU. +chip soc/rockchip/rk3288 + device cpu_cluster 0 on end + #SCREEN_RGB + register "screen_type" = "2" + #LVDS_8BIT_2 + register "lvds_format" = "1" + #OUT_D888_P666 + register "out_face" = "33" + register "clock_frequency" = "71000000" + register "hactive" = "1280" + register "vactive" = "800" + register "hback_porch" = "100" + register "hfront_porch" = "18" + register "vback_porch" = "8" + register "vfront_porch" = "6" + register "hsync_len" = "10" + register "vsync_len" = "2" + register "hsync_active" = "0" + register "vsync_active" = "0" + register "de_active" = "0" + register "pixelclk_active" = "0" + register "swap_rb" = "0" + register "swap_rg" = "0" + register "swap_gb" = "0" + #LCD_EN_GPIO:GPIO7_A3 + register "lcd_en_gpio" = "0xff7e0004" + #LCD_CS_GPIO:GPIO7_A4 + register "lcd_cs_gpio" = "0xff7e0005" +end diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c new file mode 100644 index 0000000..607b1d5 --- /dev/null +++ b/src/mainboard/google/veyron/mainboard.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/cache.h> +#include <delay.h> +#include <edid.h> +#include <vbe.h> +#include <boot/coreboot_tables.h> + +static void mainboard_init(device_t dev) +{ + +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = CONFIG_DRAM_DMA_START; + dma->range_size = CONFIG_DRAM_DMA_SIZE; +} diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c new file mode 100644 index 0000000..b9daefe --- /dev/null +++ b/src/mainboard/google/veyron/romstage.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <armv7.h> +#include <cbfs.h> +#include <console/console.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <delay.h> +#include <timestamp.h> +#include <arch/cache.h> +#include <arch/exception.h> + +void main(void) +{ + void *entry; + + console_init(); + + /* used for MMU and CBMEM setup, in MB */ + u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); + u32 dram_size = CONFIG_DRAM_SIZE_MB; + u32 dram_end = dram_start + dram_size; + mmu_init(); + /* Device memory below DRAM is uncached. */ + mmu_config_range(0, dram_start, DCACHE_OFF); + /* DRAM is cached. */ + mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); + /* A window for DMA is uncached. */ + mmu_config_range(CONFIG_DRAM_DMA_START >> 20, + CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + /* The space above DRAM is uncached. */ + if (dram_end < 4096) + mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); + mmu_disable_range(0, 1); + dcache_mmu_enable(); + + cbmem_initialize_empty(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); +} diff --git a/src/soc/Kconfig b/src/soc/Kconfig index 0412919..a36bedd 100644 --- a/src/soc/Kconfig +++ b/src/soc/Kconfig @@ -1,5 +1,6 @@ source src/soc/intel/Kconfig source src/soc/nvidia/Kconfig source src/soc/qualcomm/Kconfig +source src/soc/rockchip/Kconfig source src/soc/samsung/Kconfig source src/soc/ucb/Kconfig diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc index ab3e166..80dd109 100644 --- a/src/soc/Makefile.inc +++ b/src/soc/Makefile.inc @@ -4,5 +4,6 @@ subdirs-y += intel subdirs-y += nvidia subdirs-y += qualcomm +subdirs-y += rockchip subdirs-y += samsung subdirs-y += ucb diff --git a/src/soc/rockchip/Kconfig b/src/soc/rockchip/Kconfig new file mode 100644 index 0000000..b041f89 --- /dev/null +++ b/src/soc/rockchip/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +source src/soc/rockchip/rk3288/Kconfig diff --git a/src/soc/rockchip/Makefile.inc b/src/soc/rockchip/Makefile.inc new file mode 100644 index 0000000..aa67f5c --- /dev/null +++ b/src/soc/rockchip/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-$(CONFIG_SOC_ROCKCHIP_RK3288) += rk3288 diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig new file mode 100644 index 0000000..51cf74c --- /dev/null +++ b/src/soc/rockchip/rk3288/Kconfig @@ -0,0 +1,118 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOC_ROCKCHIP_RK3288 + bool + default n + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_VERSTAGE_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 + select CPU_HAS_BOOTBLOCK_INIT + select HAVE_MONOTONIC_TIMER + select HAVE_UART_MEMORY_MAPPED + select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE + select DYNAMIC_CBMEM + +if SOC_ROCKCHIP_RK3288 + +config BOOTBLOCK_CPU_INIT + string + default "soc/rockchip/rk3288/bootblock.c" + +# ROM image layout. +# +# 0x00000 Combined bootblock and ID Block +# 0x08000 Master CBFS header. +# 0x18000 Free for CBFS data. +# +# iRAM (96k) layout. +# (Note: The BootROM will jump to 0xff704004 after loading bootblock, +# so the bootblock loading address must be at 0xff704004.) +# +# 0xFF70_0000 TTB (16KB). +# 0xFF70_4004 Bootblock (max 16KB-4B). +# 0xFF70_8000 ROM stage (max 40KB). +# 0xFF71_2000 STACK (4KB). +# 0xFF71_3000 CBFS mapping cache (20K) +# 0xFF71_7FFF End of iRAM. + +config SYS_SDRAM_BASE + hex "SDRAM base address" + default 0x00000000 + +config STACK_TOP + hex "STACK TOP" + default 0xff713000 + +config STACK_BOTTOM + hex "STACK BOTTOM" + default 0xff712000 + +config BOOTBLOCK_BASE + hex + default 0xff704004 + +config ROMSTAGE_BASE + hex "ROM STAGE BASE" + default 0xff708000 + +config RAMSTAGE_BASE + hex "RAMSTAGE BASE" + default 0x00200000 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x0008000 + +config CBFS_ROM_OFFSET + hex + default 0x0018000 + +config CBFS_SRAM_CACHE_ADDRESS + hex "sram memory address to put CBFS cache data" + default 0xff713000 + +config CBFS_SRAM_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00005000 + +config CBFS_DRAM_CACHE_ADDRESS + hex "dram memory address to put CBFS cache data" + default 0x01000000 + +config CBFS_DRAM_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00100000 + +config TTB_BUFFER + hex "memory address of the TTB buffer" + default 0xff700000 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0xFF690000 + +endif diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc new file mode 100644 index 0000000..50a1bbf --- /dev/null +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +#bootblock-y += bootblock.c +bootblock-y += cbmem.c +bootblock-y += timer.c +bootblock-y += monotonic_timer.c +bootblock-y += media.c +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_DRIVERS_UART) += uart.c +endif + +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += monotonic_timer.c +romstage-y += media.c +romstage-$(CONFIG_DRIVERS_UART) += uart.c + +ramstage-y += cbmem.c +ramstage-y += timer.c +ramstage-y += monotonic_timer.c +ramstage-y += media.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c diff --git a/src/soc/rockchip/rk3288/addressmap.h b/src/soc/rockchip/rk3288/addressmap.h new file mode 100644 index 0000000..865e3c2 --- /dev/null +++ b/src/soc/rockchip/rk3288/addressmap.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ +#define __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ + +#define SDMMC1_BASE 0xFF0C0000 +#define SDMMC0_BASE 0xFF0D0000 +#define EMMC_BASE 0xFF0F0000 +#define SARADC_BASE 0xFF100000 + +#define SPI0_BASE 0xFF110000 +#define SPI1_BASE 0xFF120000 +#define SPI2_BASE 0xFF130000 + +#define I2C1_BASE 0xFF140000 +#define I2C3_BASE 0xFF150000 +#define I2C4_BASE 0xFF160000 +#define I2C5_BASE 0xFF170000 +#define UART0_BASE 0xFF180000 +#define UART1_BASE 0xFF190000 +#define DMAC_PERI_BASE 0xFF250000 + +#define NANDC0_BASE 0xFF400000 +#define NANDC1_BASE 0xFF410000 + +#define USB_HOST0_EHCI_BASE 0xFF500000 +#define USB_HOST0_OHCI_BASE 0xFF520000 +#define USB_HOST1_BASE 0xFF540000 +#define USB_OTG_BASE 0xFF580000 + +#define DMAC_BUS_BASE 0xFF600000 + +#define DDR_PCTL0_BASE 0xFF610000 +#define DDR_PCTL1_BASE 0xFF630000 +#define DDR_PUBL0_BASE 0xFF620000 +#define DDR_PUBL1_BASE 0xFF640000 + +#define I2C0_BASE 0xFF650000 +#define I2C2_BASE 0xFF660000 +#define DW_PWM0123_BASE 0xFF670000 +#define RK_PWM0123_BASE 0xFF680000 +#define UART2_BASE 0xFF690000 +#define TIMER0_BASE 0xFF6B0000 + +#define SRAM_BASE 0xFF700000 +#define PMU_BASE 0xFF730000 +#define GRF_SECURE_BASE 0xFF740000 +#define GPIO0_BASE 0xFF750000 +#define CRU_BASE 0xFF760000 +#define GRF_BASE 0xFF770000 +#define GPIO1_BASE 0xFF780000 +#define GPIO2_BASE 0xFF790000 +#define GPIO3_BASE 0xFF7A0000 +#define GPIO4_BASE 0xFF7B0000 +#define GPIO5_BASE 0xFF7C0000 +#define GPIO6_BASE 0xFF7D0000 +#define GPIO7_BASE 0xFF7E0000 +#define GPIO8_BASE 0xFF7F0000 + +#define TIMER6_BASE 0xFF810000 +#define TIMER7_BASE 0xFF810020 + +#define VOP_BIG_BASE 0xFF930000 +#define HDMI_TX_BASE 0xFF980000 +#define DMACS_BUS_BASE 0xFFB20000 + +#define SERVICE_CORE_BASE 0xFFA80000 +#define SERVICE_DMA_BASE 0xFFA90000 +#define SERVICE_GPU_BASE 0xFFAA0000 +#define SERVICE_PERI_BASE 0xFFAB0000 +#define SERVICE_BUS_BASE 0xFFAC0000 +#define SERVICE_VIO_BASE 0xFFAD0000 +#define SERVICE_VPU_BASE 0xFFAE0000 +#define SERVICE_HEVC_BASE 0xFFAF0000 + +#define EFUSE_BASE 0xFFB40000 + +#define CORE_GICD_BASE 0xFFC01000 +#define CORE_GICC_BASE 0xFFC02000 +#define CPU_AXI_BUS_BASE 0xFFE00000 + +#define BOOT_ROM_BASE 0xFFFF0000 +#define BOOT_ROM_CHIP_VER (BOOT_ROM+0x27F0) + +#endif /* __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ */ diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c new file mode 100644 index 0000000..9adf6ac --- /dev/null +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/cache.h> +#include <bootblock_common.h> +#include "timer.h" + +static void bootblock_cpu_init(void) +{ + rk3288_init_timer(); +} diff --git a/src/soc/rockchip/rk3288/cbmem.c b/src/soc/rockchip/rk3288/cbmem.c new file mode 100644 index 0000000..b29c87a --- /dev/null +++ b/src/soc/rockchip/rk3288/cbmem.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <cbmem.h> + +#define FB_SIZE_MB 4 +void *cbmem_top(void) +{ + return (void *)(CONFIG_SYS_SDRAM_BASE + + (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)*MiB); +} + diff --git a/src/soc/rockchip/rk3288/media.c b/src/soc/rockchip/rk3288/media.c new file mode 100644 index 0000000..75713eb --- /dev/null +++ b/src/soc/rockchip/rk3288/media.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <string.h> +#include <console/console.h> + +int init_default_cbfs_media(struct cbfs_media *media) +{ + return 0; +} diff --git a/src/soc/rockchip/rk3288/monotonic_timer.c b/src/soc/rockchip/rk3288/monotonic_timer.c new file mode 100644 index 0000000..d33ed68 --- /dev/null +++ b/src/soc/rockchip/rk3288/monotonic_timer.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <timer.h> +#include <arch/io.h> +#include "addressmap.h" +#include "timer.h" + +static uint64_t timer_raw_value(void) +{ + uint64_t value0; + uint64_t value1; + + value0 = (uint64_t)read32(&timer7_ptr->timer_curr_value0); + value1 = (uint64_t)read32(&timer7_ptr->timer_curr_value1); + value0 = value0 | value1<<32; + return value0; +} + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timer_raw_value() / clocks_per_usec); +} diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c new file mode 100644 index 0000000..3a2c34d --- /dev/null +++ b/src/soc/rockchip/rk3288/timer.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <arch/io.h> +#include "timer.h" + +void init_timer(void) +{ +} + +void rk3288_init_timer(void) +{ + write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count0); + write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count1); + write32(1, &timer7_ptr->timer_ctrl_reg); +} + +/* delay x useconds */ +void udelay(unsigned usec) +{ + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_usecs(&end, usec); + + if (mono_time_after(&current, &end)) { + printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", + usec); + /* There's not much we can do if usec is too big. Use a long, + * paranoid delay value and hope for the best... */ + end = current; + mono_time_add_usecs(&end, USECS_PER_SEC); + } + + while (mono_time_before(&current, &end)) + timer_monotonic_get(&current); +} + diff --git a/src/soc/rockchip/rk3288/timer.h b/src/soc/rockchip/rk3288/timer.h new file mode 100644 index 0000000..8c72a4f --- /dev/null +++ b/src/soc/rockchip/rk3288/timer.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ROCKCHIP_RK3288_TIMER_H__ +#define __ROCKCHIP_RK3288_TIMER_H__ + +#include "addressmap.h" + +#define SYS_CLK_FREQ 24000000 +static const uint32_t clocks_per_usec = SYS_CLK_FREQ/1000000; + +struct rk3288_timer { + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_curr_value0; + u32 timer_curr_value1; + u32 timer_ctrl_reg; + u32 timer_int_status; +}; + +static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE; + +#define TIMER_LOAD_VAL 0xffffffff + +void rk3288_init_timer(void); + +#endif /* __ROCKCHIP_RK3288_TIMER_H__ */ diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c new file mode 100644 index 0000000..60b14a3 --- /dev/null +++ b/src/soc/rockchip/rk3288/uart.c @@ -0,0 +1,167 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/uart.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> /* for __console definition */ +#include <stdint.h> +#include <drivers/uart/uart8250reg.h> + +/* + * TODO: Use DRIVERS_UART_8250MEM driver instead. + * There is an issue in the IO call functions where x86 and ARM + * ordering is reversed. This 8250MEM driver uses the x86 convention. + * This driver can be replaced once the IO calls are sorted. + */ + +struct rk3288_uart { + union { + uint32_t thr; /* Transmit holding register. */ + uint32_t rbr; /* Receive buffer register. */ + uint32_t dll; /* Divisor latch lsb. */ + }; + union { + uint32_t ier; /* Interrupt enable register. */ + uint32_t dlm; /* Divisor latch msb. */ + }; + union { + uint32_t iir; /* Interrupt identification register. */ + uint32_t fcr; /* FIFO control register. */ + }; + uint32_t lcr; /* Line control register. */ + uint32_t mcr; /* Modem control register. */ + uint32_t lsr; /* Line status register. */ + uint32_t msr; /* Modem status register. */ + uint32_t scr; + uint32_t reserved1[(0x30 - 0x20) / 4]; + uint32_t srbr[(0x70 - 0x30) / 4]; + uint32_t far; + uint32_t tfr; + uint32_t rfw; + uint32_t usr; + uint32_t tfl; + uint32_t rfl; + uint32_t srr; + uint32_t srts; + uint32_t sbcr; + uint32_t sdmam; + uint32_t sfe; + uint32_t srt; + uint32_t stet; + uint32_t htx; + uint32_t dmasa; + uint32_t reserver2[(0xf4 - 0xac) / 4]; + uint32_t cpr; + uint32_t ucv; + uint32_t ctr; +} __attribute__ ((packed)); + + +static struct rk3288_uart * const uart_ptr = + (void *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + +static void rk3288_uart_tx_flush(void); +static int rk3288_uart_tst_byte(void); + +static void rk3288_uart_init(void) +{ + /* FIXME: Use a hardcoded divisor for now. + * uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(), + * uart_platform_refclk(), 16) + */ + const unsigned divisor = 13; + const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1 + + rk3288_uart_tx_flush(); + + // Disable interrupts. + writel(0, &uart_ptr->ier); + // Force DTR and RTS to high. + writel(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr); + // Set line configuration, access divisor latches. + writel(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr); + // Set the divisor. + writel(divisor & 0xff, &uart_ptr->dll); + writel((divisor >> 8) & 0xff, &uart_ptr->dlm); + // Hide the divisor latches. + writel(line_config, &uart_ptr->lcr); + // Enable FIFOs, and clear receive and transmit. + writel(UART8250_FCR_FIFO_EN | + UART8250_FCR_CLEAR_RCVR | + UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr); +} + +static void rk3288_uart_tx_byte(unsigned char data) +{ + while (!(readl(&uart_ptr->lsr) & UART8250_LSR_THRE)); + writel(data, &uart_ptr->thr); +} + +static void rk3288_uart_tx_flush(void) +{ + while (!(readl(&uart_ptr->lsr) & UART8250_LSR_TEMT)); +} + +static unsigned char rk3288_uart_rx_byte(void) +{ + if (!rk3288_uart_tst_byte()) + return 0; + return readl(&uart_ptr->rbr); +} + +static int rk3288_uart_tst_byte(void) +{ + return (readl(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; +} + + + +void uart_init(int idx) +{ + rk3288_uart_init(); +} + +unsigned char uart_rx_byte(int idx) +{ + return rk3288_uart_rx_byte(); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + rk3288_uart_tx_byte(data); +} + +void uart_tx_flush(int idx) +{ + rk3288_uart_tx_flush(); +} + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

1 0

Patch set updated for coreboot: ab989bf northbridge/amd/amdht: Allow mainboards to set HT frequency limit
by Timothy Pearson 13 Mar '15

13 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8464 -gerrit commit ab989bf9ac1af3efe9ce8e9de9a8e8848fab0a55 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Feb 16 14:57:06 2015 -0600 northbridge/amd/amdht: Allow mainboards to set HT frequency limit This is useful when the PCB layout of a mainboard does not allow stable operation at the increased HyperTransport speeds of newer processors. Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/amdfam10.h | 7 ++++++ src/northbridge/amd/amdht/h3finit.c | 40 ++++++++++++++++++++++++++++++--- src/northbridge/amd/amdht/h3finit.h | 3 +++ src/northbridge/amd/amdht/ht_wrapper.c | 3 ++- 4 files changed, 49 insertions(+), 4 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 96f182d..a77d036 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -1002,6 +1003,10 @@ struct nodes_info_t { u32 up_planes; // down planes will be [up_planes, planes) } __attribute__((packed)); +struct ht_link_config { + uint8_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default) +}; + /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/ struct sys_info { @@ -1015,6 +1020,8 @@ struct sys_info { u8 host_link_freq[NODE_NUMS*8]; // record freq for every link from cpu, 0x0f means don't need to touch it u16 host_link_freq_cap[NODE_NUMS*8]; //cap + struct ht_link_config ht_link_cfg; + u32 segbit; u32 sbdn; u32 sblk; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 4059182..47bf809 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -75,6 +75,41 @@ static const uint16_t ht_speed_limit[16] = 0x00FF, 0x007F, 0x003F, 0x001F, 0x000F, 0x0007, 0x0003, 0x0001}; +static const struct ht_speed_limit_map_t { + uint16_t mhz; + uint8_t config; +} ht_speed_limit_map[] = { + {0, NVRAM_LIMIT_HT_SPEED_AUTO}, + {200, NVRAM_LIMIT_HT_SPEED_200}, + {300, NVRAM_LIMIT_HT_SPEED_300}, + {400, NVRAM_LIMIT_HT_SPEED_400}, + {500, NVRAM_LIMIT_HT_SPEED_500}, + {600, NVRAM_LIMIT_HT_SPEED_600}, + {800, NVRAM_LIMIT_HT_SPEED_800}, + {1000, NVRAM_LIMIT_HT_SPEED_1000}, + {1200, NVRAM_LIMIT_HT_SPEED_1200}, + {1400, NVRAM_LIMIT_HT_SPEED_1400}, + {1600, NVRAM_LIMIT_HT_SPEED_1600}, + {1800, NVRAM_LIMIT_HT_SPEED_1800}, + {2000, NVRAM_LIMIT_HT_SPEED_2000}, + {2200, NVRAM_LIMIT_HT_SPEED_2200}, + {2400, NVRAM_LIMIT_HT_SPEED_2400}, + {2600, NVRAM_LIMIT_HT_SPEED_2600}, +}; + +static const uint16_t ht_speed_mhz_to_hw(uint16_t mhz) +{ + size_t i; + for (i = 0; i < ARRAY_SIZE(ht_speed_limit_map); i++) + if (ht_speed_limit_map[i].mhz == mhz) + return ht_speed_limit_map[i].config; + + printk(BIOS_WARNING, + "WARNING: Invalid HT link limit frequency %d specified, ignoring...\n", + mhz); + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_AUTO]; +} + /*---------------------------------------------------------------------------- * TYPEDEFS AND STRUCTURES * @@ -1359,10 +1394,9 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) for (i = 0; i < pDat->TotalLinks*2; i += 2) { - /* FIXME - * Mainboards need to be able to set cbPCBFreqLimit - */ cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration + if (pDat->HtBlock->ht_link_configuration) + cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); #if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8 diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index 136a5cf..a56c246 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -462,6 +463,8 @@ typedef struct { const u8 *pEventData0 ); + const struct ht_link_config *ht_link_configuration; + } AMD_HTBLOCK; /* diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 3bf81c6..a38caa4 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -139,7 +139,8 @@ static void amd_ht_init(struct sys_info *sysinfo) NULL, // BOOL (*AMD_CB_CustomizeBuffers)(); NULL, // void (*AMD_CB_OverrideDevicePort)(); NULL, // void (*AMD_CB_OverrideCpuPort)(); - AMD_CB_EventNotify // void (*AMD_CB_EventNotify) (); + AMD_CB_EventNotify, // void (*AMD_CB_EventNotify) (); + &sysinfo->ht_link_cfg // struct ht_link_config* }; printk(BIOS_DEBUG, "Enter amd_ht_init()\n");

1 0

Patch set updated for coreboot: 536700c southbridge/amd/pi: Enable early I/O decode to LPC
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8661 -gerrit commit 536700c7ab154c85f09ce3f25cded27a52a86ad8 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Mar 13 08:22:17 2015 -0600 southbridge/amd/pi: Enable early I/O decode to LPC The decode of UART addresses down to the LPC bus needs to occur early to allow romstage console messages to be seen. Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/pi/hudson/early_setup.c | 9 +++++++++ src/southbridge/amd/pi/hudson/hudson.h | 1 + 2 files changed, 10 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 9500d0e..af3240b 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -93,6 +93,15 @@ void hudson_lpc_port80(void) pci_write_config8(dev, 0x4a, byte); } +void hudson_lpc_decode(void) +{ + device_t dev; + + /* Enable I/O decode to LPC bus */ + dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xFF03FFD5); +} + int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { int i; diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 90c3205..6116713 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -76,6 +76,7 @@ u16 pm_read16(u16 reg); #ifdef __PRE_RAM__ void hudson_lpc_port80(void); +void hudson_lpc_decode(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void);

1 0

Patch set updated for coreboot: 1308781 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit
by Timothy Pearson 13 Mar '15

13 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8489 -gerrit commit 13087818d54e7df9e7edac48346b2a7bbf1b94fb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:27:58 2015 -0500 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/ram_calc.c | 9 +++++++++ src/mainboard/advansus/a785e-i/romstage.c | 1 + src/mainboard/amd/bimini_fam10/romstage.c | 1 + src/mainboard/amd/mahogany_fam10/romstage.c | 1 + src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 1 + src/mainboard/amd/tilapia_fam10/romstage.c | 1 + src/mainboard/asus/kfsn4-dre/romstage.c | 1 + src/mainboard/asus/m4a78-em/romstage.c | 1 + src/mainboard/asus/m4a785-m/romstage.c | 1 + src/mainboard/asus/m5a88-v/romstage.c | 1 + src/mainboard/avalue/eax-785e/romstage.c | 1 + src/mainboard/gigabyte/ma785gm/romstage.c | 1 + src/mainboard/gigabyte/ma785gmt/romstage.c | 1 + src/mainboard/gigabyte/ma78gm/romstage.c | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 + src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 + src/mainboard/jetway/pa78vm5/romstage.c | 1 + src/mainboard/msi/ms9652_fam10/romstage.c | 1 + src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 + src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 + src/mainboard/supermicro/h8scm_fam10/romstage.c | 1 + src/mainboard/tyan/s2912_fam10/romstage.c | 1 + src/northbridge/amd/amdfam10/Kconfig | 1 - src/northbridge/amd/amdfam10/northbridge.c | 3 --- src/southbridge/amd/sb700/early_setup.c | 5 +++++ src/southbridge/amd/sb700/lpc.c | 5 +++++ src/southbridge/amd/sb800/early_setup.c | 5 +++++ 27 files changed, 45 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c index 0da8182..1b1d2c6 100644 --- a/src/cpu/amd/model_10xxx/ram_calc.c +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -48,3 +48,12 @@ uint64_t get_uma_memory_size(uint64_t topmem) return uma_size; } + +void *cbmem_top(void) +{ + uint32_t topmem = (uint32_t) rdmsr(TOP_MEM).lo; + + topmem = topmem - get_uma_memory_size(topmem); + + return (void *) topmem; +} diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 19ce53e..c1c9a1b 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index d8a38d7..6d03685 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -198,6 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e6d7f2e..e53c64d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 76bc73f..ef15e83 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -312,6 +312,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index b7f6869..7d2f272 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 0dab8e8..44864f6 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -343,6 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); printk(BIOS_DEBUG, "disable_spd()\n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 7c93767..47b9c83 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 328955a..7ebec29 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index baa38ac..2339478 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index b586198..c1dbaa7 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -201,6 +201,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4ad3d2c..7b0168d 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 590bb93..d0d6c94 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a7b6b1b..8861ab6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index d7e8447..4aefcd2 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -204,6 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); bcm5785_early_setup(); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index b88baa3..991cd55 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 08b6398..df30a69 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -205,6 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 45f05a5..0bdcd38 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -231,6 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index bc1ca24..4615465 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -228,6 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 2be09bc..c8ed2df 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -292,6 +292,7 @@ post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index eb38a29..4c6292f 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -212,6 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); /* diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 74c0aaa..7dcca17 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -227,6 +227,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + cbmem_initialize_empty(); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index ff7fb9c..37993aa 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES - select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 68c6e35..9206de7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -897,10 +897,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 94f33b7..0c37840 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -728,6 +728,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -742,5 +746,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 658e954..a5f11a6 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -88,6 +88,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; @@ -98,6 +102,7 @@ void backup_top_of_ram(uint64_t ramtop) nvram_pos++; } } +#endif static void sb700_lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 69bc3bd..300b54e 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -673,6 +673,10 @@ int acpi_get_sleep_type(void) return ((tmp & (7 << 10)) >> 10); } +/* FIXME + * Remove this block when all processors support early CBMEM init + */ +#if CONFIG_LATE_CBMEM_INIT unsigned long get_top_of_ram(void) { uint32_t xdata = 0; @@ -687,5 +691,6 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } +#endif #endif

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Patch set updated for coreboot: 698d1b9 soc/ipq806x: Replace GPT with fine grained DGT timer.
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8596 -gerrit commit 698d1b92661f1c2e5fbc68e033bbf6cdb39e774d Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Mon Jul 14 16:26:11 2014 -0700 soc/ipq806x: Replace GPT with fine grained DGT timer. Support 1MHz libpayload restriction on timer implementation by using DGT (debug) timer instead of GPT (general purpose) timer. BUG=chrome-os-partner:28880 TEST=manual verified DGT timer functions in coreboot and depthcharge. Original-Change-Id: Iab322d7e863e3959c027e9ce876223a64eb7e257 Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201574 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit ddf11eee5ec2d86a62095e932dbec9313b8fb9e1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id73e805801fd8d135b607df9f4f8caf567ec5b83 --- src/soc/qualcomm/ipq806x/timer.c | 125 ++++++++++++++------------------------- 1 file changed, 43 insertions(+), 82 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c index 3cb9531..55386e9 100644 --- a/src/soc/qualcomm/ipq806x/timer.c +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -1,8 +1,5 @@ /* - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. - * Source : APQ8064 LK boot - * - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2011 - 2014 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,103 +33,67 @@ #include <ipq_timer.h> #include <timer.h> -#define GPT_FREQ_KHZ 32 -#define GPT_FREQ (GPT_FREQ_KHZ * 1000) /* 32 KHz */ +/* + * DGT runs at 25 MHz / 4, or 6.25 ticks per microsecond + */ +#define DGT_MHZ_NUM 25 +#define DGT_MHZ_DEN 4 + +#define TIMER_TICKS(us) ((DGT_MHZ_NUM*(us) + (DGT_MHZ_DEN - 1)) / DGT_MHZ_DEN) +#define TIMER_USECS(ticks) (DGT_MHZ_DEN*(ticks) / DGT_MHZ_NUM) + +/* Clock divider values for the timer. */ +#define DGT_CLK_DIV_1 0 +#define DGT_CLK_DIV_2 1 +#define DGT_CLK_DIV_3 2 +#define DGT_CLK_DIV_4 3 /** * init_timer - initialize timer */ void init_timer(void) { - writel(0, GPT_ENABLE); - writel(GPT_ENABLE_EN, GPT_ENABLE); + /* disable timer */ + writel_i(0, DGT_ENABLE); + + /* DGT uses TCXO source which is 25MHz. + * The timer should run at 1/4th the frequency of TCXO + * according to clock plan. + * Set clock divider to 4. + */ + writel_i(DGT_CLK_DIV_4, DGT_CLK_CTL); + + /* Enable timer */ + writel_i(0, DGT_CLEAR); + writel_i(DGT_ENABLE_EN, DGT_ENABLE); } /** * udelay - generates micro second delay. * @param usec: delay duration in microseconds - * - * With 32KHz clock, minimum possible delay is 31.25 Micro seconds and - * its multiples. In Rumi GPT clock is 32 KHz */ void udelay(unsigned usec) { - unsigned val; - unsigned now, last; - unsigned runcount; + uint32_t now; + uint32_t last; + uint32_t ticks; + uint32_t curr_ticks = 0; - usec = (usec + GPT_FREQ_KHZ - 1) / GPT_FREQ_KHZ; - last = readl(GPT_COUNT_VAL); - runcount = last; - val = usec + last; + /* Calculate number of ticks required. */ + ticks = TIMER_TICKS(usec); - do { - now = readl(GPT_COUNT_VAL); - if (last > now) - runcount += ((GPT_FREQ - last) + now); - else - runcount += (now - last); - last = now; - } while (runcount < val); -} - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, (readl(GPT_COUNT_VAL) * 1000) / GPT_FREQ_KHZ); -} - -#if 0 - -/* - * TODO(vbendeb) clean it up later. - * Compile out the below code but leave it for now in case it will become - * necessary later in order to make the platform fully functional. - */ -static unsigned long timestamp; -static unsigned long lastinc; + /* Obtain the current timer value. */ + last = readl_i(DGT_COUNT_VAL); -inline ulong gpt_to_sys_freq(unsigned int gpt) -{ - /* - * get_timer() expects the timer increments to be in terms - * of CONFIG_SYS_HZ. Convert GPT timer values to CONFIG_SYS_HZ - * units. - */ - return (((ulong)gpt) / (GPT_FREQ / CONFIG_SYS_HZ)); -} - -/** - * get_timer_masked - returns current ticks - * - * Returns the current timer ticks, since boot. - */ -ulong get_timer_masked(void) -{ - ulong now = gpt_to_sys_freq(readl(GPT_COUNT_VAL)); - - if (lastinc <= now) { /* normal mode (non roll) */ - /* normal mode */ - timestamp += now - lastinc; - /* move stamp forward with absolute diff ticks */ - } else { /* we have overflow of the count down timer */ - timestamp += now + (TIMER_LOAD_VAL - lastinc); + /* Loop until the right number of ticks. */ + while (curr_ticks < ticks) { + now = readl_i(DGT_COUNT_VAL); + curr_ticks += now - last; + last = now; } - - lastinc = now; - - return timestamp; } -unsigned long long get_ticks(void) -{ - return readl(GPT_COUNT_VAL); -} - -/* - * Return the number of timer ticks per second. - */ -ulong get_tbclk(void) +void timer_monotonic_get(struct mono_time *mt) { - return GPT_FREQ; + mono_time_set_usecs(mt, TIMER_USECS(readl_i(DGT_COUNT_VAL))); } -#endif

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coreboot-gerrit March 2015