coreboot-gerrit March 2015

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Patch merged into coreboot/master: 668828d siemens/mc_tcu3: Fix build and ACPI IRQ bridge entry
by gerrit＠coreboot.org 13 Mar '15

13 Mar '15

the following patch was just integrated into master: commit 668828d3b3ffbe2891d6176379d990e99ae29be7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 13 16:19:23 2015 +0200 siemens/mc_tcu3: Fix build and ACPI IRQ bridge entry Propagate commit d08057a change to this new FSP platform. Change-Id: Ie83c7f3573c189f4e4576c971dbc12099bb7b123 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8662 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/8662 for details. -gerrit

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New patch to review for coreboot: 3ca8d0a northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA
by Timothy Pearson 13 Mar '15

13 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8664 -gerrit commit 3ca8d0afd4f176f0aa24f5735dfc937a00b29cd9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 13:10:29 2015 -0500 northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA is enabled, however when GFXUMA is disabled an attempt was made to locate the CBMEM memory segment above the I/O hole in certain rare cases. Removing this special case does not impact functionality, and paves the way for early CBMEM support. Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e2b1441..68c6e35 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -756,7 +756,6 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -879,8 +878,6 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -897,15 +894,13 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } #if CONFIG_GFXUMA set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else - set_top_of_ram(ramtop); + set_top_of_ram(bsp_topmem()); #endif for(link = dev->link_list; link; link = link->next) {

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New patch to review for coreboot: e14febc cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function
by Timothy Pearson 13 Mar '15

13 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8663 -gerrit commit e14febc40afaa8199154bb0fb1dddc82741bd7f5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 13 12:48:31 2015 -0500 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function This is required for early CBMEM support. Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/Makefile.inc | 2 ++ src/cpu/amd/model_10xxx/ram_calc.c | 50 ++++++++++++++++++++++++++++++ src/cpu/amd/model_10xxx/ram_calc.h | 25 +++++++++++++++ src/northbridge/amd/amdfam10/northbridge.c | 17 ++-------- 4 files changed, 79 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index ba12dcd..c17e66c 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -3,6 +3,8 @@ ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c romstage-y += update_microcode.c +romstage-y += ram_calc.c +ramstage-y += ram_calc.c ramstage-y += monotonic_timer.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c new file mode 100644 index 0000000..0da8182 --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +#include <cbmem.h> + +#include "ram_calc.h" + +uint64_t get_uma_memory_size(uint64_t topmem) +{ + uint64_t uma_size = 0; + if (IS_ENABLED(CONFIG_GFXUMA)) { + /* refer to UMA Size Consideration in 780 BDG. */ + switch (topmem) { + case 0x10000000: /* 256M system memory */ + uma_size = 0x4000000; /* 64M recommended UMA */ + break; + + case 0x20000000: /* 512M system memory */ + uma_size = 0x8000000; /* 128M recommended UMA */ + break; + + default: /* 1GB and above system memory */ + uma_size = 0x10000000; /* 256M recommended UMA */ + break; + } + } + + return uma_size; +} diff --git a/src/cpu/amd/model_10xxx/ram_calc.h b/src/cpu/amd/model_10xxx/ram_calc.h new file mode 100644 index 0000000..7ece338 --- /dev/null +++ b/src/cpu/amd/model_10xxx/ram_calc.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_MODEL_10XXX_MEM_CALC_H_ +#define _AMD_MODEL_10XXX_MEM_CALC_H_ + +uint64_t get_uma_memory_size(uint64_t topmem); + +#endif diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5ce7ae6..e2b1441 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -33,6 +33,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> +#include <cpu/amd/model_10xxx/ram_calc.h> #if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> @@ -740,21 +741,7 @@ static void setup_uma_memory(void) { #if CONFIG_GFXUMA uint32_t topmem = (uint32_t) bsp_topmem(); - /* refer to UMA Size Consideration in 780 BDG. */ - switch (topmem) { - case 0x10000000: /* 256M system memory */ - uma_memory_size = 0x4000000; /* 64M recommended UMA */ - break; - - case 0x20000000: /* 512M system memory */ - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - break; - - default: /* 1GB and above system memory */ - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - break; - } - + uma_memory_size = get_uma_memory_size(topmem); uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base);

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Patch set updated for coreboot: 60e67f7 soc/ipq806x: Replace GPT with fine grained DGT timer.
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8596 -gerrit commit 60e67f772607d20850f3999e345105acc8c39a10 Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Mon Jul 14 16:26:11 2014 -0700 soc/ipq806x: Replace GPT with fine grained DGT timer. Support 1MHz libpayload restriction on timer implementation by using DGT (debug) timer instead of GPT (general purpose) timer. BUG=chrome-os-partner:28880 TEST=manual verified DGT timer functions in coreboot and depthcharge. Original-Change-Id: Iab322d7e863e3959c027e9ce876223a64eb7e257 Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201574 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit ddf11eee5ec2d86a62095e932dbec9313b8fb9e1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id73e805801fd8d135b607df9f4f8caf567ec5b83 --- src/soc/qualcomm/ipq806x/timer.c | 125 ++++++++++++++------------------------- 1 file changed, 43 insertions(+), 82 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c index 3cb9531..55386e9 100644 --- a/src/soc/qualcomm/ipq806x/timer.c +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -1,8 +1,5 @@ /* - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. - * Source : APQ8064 LK boot - * - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2011 - 2014 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,103 +33,67 @@ #include <ipq_timer.h> #include <timer.h> -#define GPT_FREQ_KHZ 32 -#define GPT_FREQ (GPT_FREQ_KHZ * 1000) /* 32 KHz */ +/* + * DGT runs at 25 MHz / 4, or 6.25 ticks per microsecond + */ +#define DGT_MHZ_NUM 25 +#define DGT_MHZ_DEN 4 + +#define TIMER_TICKS(us) ((DGT_MHZ_NUM*(us) + (DGT_MHZ_DEN - 1)) / DGT_MHZ_DEN) +#define TIMER_USECS(ticks) (DGT_MHZ_DEN*(ticks) / DGT_MHZ_NUM) + +/* Clock divider values for the timer. */ +#define DGT_CLK_DIV_1 0 +#define DGT_CLK_DIV_2 1 +#define DGT_CLK_DIV_3 2 +#define DGT_CLK_DIV_4 3 /** * init_timer - initialize timer */ void init_timer(void) { - writel(0, GPT_ENABLE); - writel(GPT_ENABLE_EN, GPT_ENABLE); + /* disable timer */ + writel_i(0, DGT_ENABLE); + + /* DGT uses TCXO source which is 25MHz. + * The timer should run at 1/4th the frequency of TCXO + * according to clock plan. + * Set clock divider to 4. + */ + writel_i(DGT_CLK_DIV_4, DGT_CLK_CTL); + + /* Enable timer */ + writel_i(0, DGT_CLEAR); + writel_i(DGT_ENABLE_EN, DGT_ENABLE); } /** * udelay - generates micro second delay. * @param usec: delay duration in microseconds - * - * With 32KHz clock, minimum possible delay is 31.25 Micro seconds and - * its multiples. In Rumi GPT clock is 32 KHz */ void udelay(unsigned usec) { - unsigned val; - unsigned now, last; - unsigned runcount; + uint32_t now; + uint32_t last; + uint32_t ticks; + uint32_t curr_ticks = 0; - usec = (usec + GPT_FREQ_KHZ - 1) / GPT_FREQ_KHZ; - last = readl(GPT_COUNT_VAL); - runcount = last; - val = usec + last; + /* Calculate number of ticks required. */ + ticks = TIMER_TICKS(usec); - do { - now = readl(GPT_COUNT_VAL); - if (last > now) - runcount += ((GPT_FREQ - last) + now); - else - runcount += (now - last); - last = now; - } while (runcount < val); -} - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, (readl(GPT_COUNT_VAL) * 1000) / GPT_FREQ_KHZ); -} - -#if 0 - -/* - * TODO(vbendeb) clean it up later. - * Compile out the below code but leave it for now in case it will become - * necessary later in order to make the platform fully functional. - */ -static unsigned long timestamp; -static unsigned long lastinc; + /* Obtain the current timer value. */ + last = readl_i(DGT_COUNT_VAL); -inline ulong gpt_to_sys_freq(unsigned int gpt) -{ - /* - * get_timer() expects the timer increments to be in terms - * of CONFIG_SYS_HZ. Convert GPT timer values to CONFIG_SYS_HZ - * units. - */ - return (((ulong)gpt) / (GPT_FREQ / CONFIG_SYS_HZ)); -} - -/** - * get_timer_masked - returns current ticks - * - * Returns the current timer ticks, since boot. - */ -ulong get_timer_masked(void) -{ - ulong now = gpt_to_sys_freq(readl(GPT_COUNT_VAL)); - - if (lastinc <= now) { /* normal mode (non roll) */ - /* normal mode */ - timestamp += now - lastinc; - /* move stamp forward with absolute diff ticks */ - } else { /* we have overflow of the count down timer */ - timestamp += now + (TIMER_LOAD_VAL - lastinc); + /* Loop until the right number of ticks. */ + while (curr_ticks < ticks) { + now = readl_i(DGT_COUNT_VAL); + curr_ticks += now - last; + last = now; } - - lastinc = now; - - return timestamp; } -unsigned long long get_ticks(void) -{ - return readl(GPT_COUNT_VAL); -} - -/* - * Return the number of timer ticks per second. - */ -ulong get_tbclk(void) +void timer_monotonic_get(struct mono_time *mt) { - return GPT_FREQ; + mono_time_set_usecs(mt, TIMER_USECS(readl_i(DGT_COUNT_VAL))); } -#endif

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Patch merged into coreboot/master: c5cd57c nyan: Remove broken setup_display() from romstage
by gerrit＠coreboot.org 13 Mar '15

13 Mar '15

the following patch was just integrated into master: commit c5cd57c330694a63360be4d93ecf5cb23883aafc Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Jul 11 17:09:41 2014 -0700 nyan: Remove broken setup_display() from romstage This patch removes a chunk of romstage code from Tegra and all Nyan boards that was supposed to enable some LCD power rails early, but never really worked. The dev_find_slot() function can only find PCI devices, which the CPU cluster is not. Since we're done with Nyan-RO and the ramstage display code is fine as it is, there is no point in trying to fix this... but we should remove it from ToT lest someone uses it as a blueprint to add more dead code to future boards. BRANCH=None BUG=None TEST=None Original-Change-Id: I6eee256873299429d4e3934fe7d454120390f34d Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207720 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit a3df62a3bcefcc20ae59648f5d1f0a01db3c02c6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8deedea5e9787848aae3064509c611bc349313cc Reviewed-on: http://review.coreboot.org/8638 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/8638 for details. -gerrit

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Patch set updated for coreboot: b88addc soc/ipq806x: Replace GPT with fine grained DGT timer.
by Marc Jones 13 Mar '15

13 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8596 -gerrit commit b88addcd03c49f1009595dd42d04f576d3fedd37 Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Mon Jul 14 16:26:11 2014 -0700 soc/ipq806x: Replace GPT with fine grained DGT timer. Support 1MHz libpayload restriction on timer implementation by using DGT (debug) timer instead of GPT (general purpose) timer. BUG=chrome-os-partner:28880 TEST=manual verified DGT timer functions in coreboot and depthcharge. Original-Change-Id: Iab322d7e863e3959c027e9ce876223a64eb7e257 Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201574 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit ddf11eee5ec2d86a62095e932dbec9313b8fb9e1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id73e805801fd8d135b607df9f4f8caf567ec5b83 --- src/soc/qualcomm/ipq806x/timer.c | 125 ++++++++++++++------------------------- 1 file changed, 43 insertions(+), 82 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c index 3cb9531..ce11126 100644 --- a/src/soc/qualcomm/ipq806x/timer.c +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -1,8 +1,5 @@ /* - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. - * Source : APQ8064 LK boot - * - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * Copyright (c) 2011 - 2014 The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,103 +33,67 @@ #include <ipq_timer.h> #include <timer.h> -#define GPT_FREQ_KHZ 32 -#define GPT_FREQ (GPT_FREQ_KHZ * 1000) /* 32 KHz */ +/* + * DGT runs at 25 MHz / 4, or 6.25 ticks per microsecond + */ +#define DGT_MHZ_NUM 25 +#define DGT_MHZ_DEN 4 + +#define TIMER_TICKS(us) ((DGT_MHZ_NUM*(us)+(DGT_MHZ_DEN-1))/DGT_MHZ_DEN) +#define TIMER_USECS(ticks) (DGT_MHZ_DEN*(ticks)/DGT_MHZ_NUM) + +/* Clock divider values for the timer. */ +#define DGT_CLK_DIV_1 0 +#define DGT_CLK_DIV_2 1 +#define DGT_CLK_DIV_3 2 +#define DGT_CLK_DIV_4 3 /** * init_timer - initialize timer */ void init_timer(void) { - writel(0, GPT_ENABLE); - writel(GPT_ENABLE_EN, GPT_ENABLE); + /* disable timer */ + writel_i(0, DGT_ENABLE); + + /* DGT uses TCXO source which is 25MHz. + * The timer should run at 1/4th the frequency of TCXO + * according to clock plan. + * Set clock divider to 4. + */ + writel_i(DGT_CLK_DIV_4, DGT_CLK_CTL); + + /* Enable timer */ + writel_i(0, DGT_CLEAR); + writel_i(DGT_ENABLE_EN, DGT_ENABLE); } /** * udelay - generates micro second delay. * @param usec: delay duration in microseconds - * - * With 32KHz clock, minimum possible delay is 31.25 Micro seconds and - * its multiples. In Rumi GPT clock is 32 KHz */ void udelay(unsigned usec) { - unsigned val; - unsigned now, last; - unsigned runcount; + uint32_t now; + uint32_t last; + uint32_t ticks; + uint32_t curr_ticks = 0; - usec = (usec + GPT_FREQ_KHZ - 1) / GPT_FREQ_KHZ; - last = readl(GPT_COUNT_VAL); - runcount = last; - val = usec + last; + /* Calculate number of ticks required. */ + ticks = TIMER_TICKS(usec); - do { - now = readl(GPT_COUNT_VAL); - if (last > now) - runcount += ((GPT_FREQ - last) + now); - else - runcount += (now - last); - last = now; - } while (runcount < val); -} - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, (readl(GPT_COUNT_VAL) * 1000) / GPT_FREQ_KHZ); -} - -#if 0 - -/* - * TODO(vbendeb) clean it up later. - * Compile out the below code but leave it for now in case it will become - * necessary later in order to make the platform fully functional. - */ -static unsigned long timestamp; -static unsigned long lastinc; + /* Obtain the current timer value. */ + last = readl_i(DGT_COUNT_VAL); -inline ulong gpt_to_sys_freq(unsigned int gpt) -{ - /* - * get_timer() expects the timer increments to be in terms - * of CONFIG_SYS_HZ. Convert GPT timer values to CONFIG_SYS_HZ - * units. - */ - return (((ulong)gpt) / (GPT_FREQ / CONFIG_SYS_HZ)); -} - -/** - * get_timer_masked - returns current ticks - * - * Returns the current timer ticks, since boot. - */ -ulong get_timer_masked(void) -{ - ulong now = gpt_to_sys_freq(readl(GPT_COUNT_VAL)); - - if (lastinc <= now) { /* normal mode (non roll) */ - /* normal mode */ - timestamp += now - lastinc; - /* move stamp forward with absolute diff ticks */ - } else { /* we have overflow of the count down timer */ - timestamp += now + (TIMER_LOAD_VAL - lastinc); + /* Loop until the right number of ticks. */ + while (curr_ticks < ticks) { + now = readl_i(DGT_COUNT_VAL); + curr_ticks += now - last; + last = now; } - - lastinc = now; - - return timestamp; } -unsigned long long get_ticks(void) -{ - return readl(GPT_COUNT_VAL); -} - -/* - * Return the number of timer ticks per second. - */ -ulong get_tbclk(void) +void timer_monotonic_get(struct mono_time *mt) { - return GPT_FREQ; + mono_time_set_usecs(mt, TIMER_USECS(readl_i(DGT_COUNT_VAL))); } -#endif

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Patch set updated for coreboot: 8ae18a0 southbridge/amd/pi: Enable early I/O decode to LPC
by Dave Frodin 13 Mar '15

13 Mar '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8661 -gerrit commit 8ae18a036fe2fd787355615ff801b20e24a99446 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Mar 13 08:22:17 2015 -0600 southbridge/amd/pi: Enable early I/O decode to LPC The decode of UART addresses down to the LPC bus needs to occur early to allow romstage console messages to be seen. Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/pi/hudson/early_setup.c | 9 +++++++++ src/southbridge/amd/pi/hudson/hudson.h | 1 + 2 files changed, 10 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 9500d0e..af3240b 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -93,6 +93,15 @@ void hudson_lpc_port80(void) pci_write_config8(dev, 0x4a, byte); } +void hudson_lpc_decode(void) +{ + device_t dev; + + /* Enable I/O decode to LPC bus */ + dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xFF03FFD5); +} + int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { int i; diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 90c3205..6116713 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -76,6 +76,7 @@ u16 pm_read16(u16 reg); #ifdef __PRE_RAM__ void hudson_lpc_port80(void); +void hudson_lpc_decode(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void);

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New patch to review for coreboot: 67582a4 siemens/mc_tcu3: Fix build and ACPI IRQ bridge entry
by Kyösti Mälkki 13 Mar '15

13 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8662 -gerrit commit 67582a49589843c8b8c287d9b271d0be9774d21f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 13 16:19:23 2015 +0200 siemens/mc_tcu3: Fix build and ACPI IRQ bridge entry Propagate commit d08057a change to this new FSP platform. Change-Id: Ie83c7f3573c189f4e4576c971dbc12099bb7b123 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/siemens/mc_tcu3/irqroute.h | 38 +++++++++++++++++++------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/irqroute.h b/src/mainboard/siemens/mc_tcu3/irqroute.h index 08552c5..bce6f63 100644 --- a/src/mainboard/siemens/mc_tcu3/irqroute.h +++ b/src/mainboard/siemens/mc_tcu3/irqroute.h @@ -40,22 +40,30 @@ *IR1Eh SIO INT(ABCD) - PIRQ BDEF *IR1Fh LPC INT(ABCD) - PIRQ HGBC */ + +/* PCIe bridge routing */ +#define BRIDGE1_DEV PCIE_DEV + +/* PCI bridge IRQs need to be updated in both tables and need to match */ +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) + #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) /* * Route each PIRQ[A-H] to a PIC IRQ[0-15]

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Patch set updated for coreboot: 15fed38 OxPCIe952: Fix read8/write8 argument
by Kyösti Mälkki 13 Mar '15

13 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8660 -gerrit commit 15fed38aa6c92e79857865a2246de7fbac9c2cde Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 12 11:33:14 2015 +0200 OxPCIe952: Fix read8/write8 argument This was missed in commit bde6d309 as the driver is not enabled in any configuration by default. Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/uart/oxpcie.c | 5 +++-- src/drivers/uart/uart8250mem.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index 76119d2..d49170d 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -34,11 +34,12 @@ static void oxford_oxpcie_enable(device_t dev) printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); return; } + void *bar0 = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", - (read32(res->base) >> 8), (read32(res->base) & 0xff)); + (read32(bar0) >> 8), (read32(bar0) & 0xff)); printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", - (read32(res->base + 4) & 3)); + (read32(bar0 + 4) & 3)); printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); } diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 5fbbeec..cb70700 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -36,12 +36,12 @@ static uint8_t uart8250_read(void *base, uint8_t reg) { - return read8((uintptr_t) (base + reg)); + return read8(base + reg); } static void uart8250_write(void *base, uint8_t reg, uint8_t data) { - write8((uintptr_t) (base + reg), data); + write8(base + reg, data); } static int uart8250_mem_can_tx_byte(void *base)

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Patch merged into coreboot/master: b7b8371 northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSP
by gerrit＠coreboot.org 13 Mar '15

13 Mar '15

the following patch was just integrated into master: commit b7b83719bf6a304240e221fd5f801debc400461b Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Feb 26 01:30:40 2015 +0100 northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSP This capability means: FERR messages are sent out on system detected an unmasked floating point x87 FPU error. Even though this capability is supported on nehalem it doesn't make sense to set it in early stage. This MSR has a core scope which results in an unsync MSR because it's not set on other cores than the BSP. Found-by: BITS Tested-on: lenovo thinkpad x201t Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: http://review.coreboot.org/8659 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8659 for details. -gerrit

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coreboot-gerrit March 2015