coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 681057e t132: handle optional Trust Zone region correctly
by Marc Jones 12 Mar '15

12 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8639 -gerrit commit 681057e73f1ff84c7ece14baeb7fd27470b170a7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jul 15 10:53:29 2014 -0500 t132: handle optional Trust Zone region correctly Provide a default Trust Zone region size of 1MiB, and correctly account for it in the AVP and the arm64 cores. The different path between the arm64 cores and the AVP is because the AVP cannot access the Trust Zone region registers. Therefore the AVP needs to account for the Trust Zone region. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and ran. Noted Trust Zone region being accounted for. Original-Change-Id: Ie0f117ec7a5ff8519c39778d3cdf88c3eee57ea5 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208062 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 22f2fa05c009c58f53b99b9ebe1b6d01fdac5ba7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I28506b4401145d366b56126b2eddc4c3d3db7b44 --- src/soc/nvidia/tegra132/Kconfig | 6 +++++ src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/addressmap.c | 8 ++++++ src/soc/nvidia/tegra132/ramstage.c | 47 ++++++++++++++++++++++++++++++++++++ 4 files changed, 62 insertions(+) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 3396cc8..8a5d087 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -93,4 +93,10 @@ config MTS_DIRECTORY help Path to directory where MTS microcode files are located. +config TRUSTZONE_CARVEOUT_SIZE_MB + hex "Size of Trust Zone region" + default 0x1 + help + Size of Trust Zone area in MiB to reserve in memory map. + endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 88ba51c..0ab95d4 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += monotonic_timer.c ramstage-y += ../tegra/gpio.c ramstage-y += ../tegra/i2c.c ramstage-y += ../tegra/pinmux.c +ramstage-y += ramstage.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c index bb35a87..7f6d7c3 100644 --- a/src/soc/nvidia/tegra132/addressmap.c +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -147,6 +147,14 @@ uintptr_t framebuffer_attributes(size_t *size_mib) /* Place the framebuffer just below the 32-bit addressable limit. */ memory_range_by_bits(ADDRESS_SPACE_32_BIT, &begin, &end); + /* + * Need to take into account that the Trust Zone region is not able to + * be read by the AVP. The Trust Zone region will live just below the + * rest of the carveout regions. + */ + if (context_avp()) + end -= CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; + *size_mib = FB_SIZE_MB; end -= *size_mib; diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c new file mode 100644 index 0000000..7b2f4e8 --- /dev/null +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/stages.h> +#include <soc/addressmap.h> +#include "mc.h" + +void arm64_soc_init(void) +{ + struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; + const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; + uintptr_t base; + uintptr_t end; + + if (!tz_size_mib) + return; + + /* + * Ramstage is when the arm64 first gets running. It also is the + * only entity that the capabilities to program the Trust Zone region. + * Therefore configure the region early. Also, the TZ region can only + * live in 32-bit space. + */ + memory_range_by_bits(ADDRESS_SPACE_32_BIT, &base, &end); + + /* Place the TZ area just below current carveout regions. */ + end -= tz_size_mib; + write32(end << 20, &mc->security_cfg0); + write32(tz_size_mib, &mc->security_cfg1); +}

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Patch merged into coreboot/master: d08057a intel/fsp_baytrail: Add PCI Root Port IRQ Routing
by gerrit＠coreboot.org 12 Mar '15

12 Mar '15

the following patch was just integrated into master: commit d08057aa20d8dff404ba9121a5d2052ae6575356 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Feb 12 22:51:57 2015 -0700 intel/fsp_baytrail: Add PCI Root Port IRQ Routing This change generates the ASL tables needed for the PCIe bridge routing. It generates this ASL (swizzled for each of the 8 functions) Name(RP1P, Package() { Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, }) Name(RP1A, Package() { Package() {0x0000ffff, 0, 0, 20 }, Package() {0x0000ffff, 1, 0, 21 }, Package() {0x0000ffff, 2, 0, 22 }, Package() {0x0000ffff, 3, 0, 23 }, }) Device(RP01) { Name(_ADR, 0x1c0001) Name(_PRW, Package() { 0, 0 }) Method(_PRT,0) { If(PICM) { Return (RP1A) } Else { Return (RP1P) } } } Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/8429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8429 for details. -gerrit

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Patch set updated for coreboot: 1ba3469 northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSP
by Alexander Couzens 12 Mar '15

12 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8659 -gerrit commit 1ba3469eb4267d6e64d1aaf635a8e9b495a42caa Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Feb 26 01:30:40 2015 +0100 northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSP This capability means: FERR messages are sent out on system detected an unmasked floating point x87 FPU error. Even though this capability is supported on nehalem it doesn't make sense to set it in early stage. This MSR has a core scope which results in an unsync MSR because it's not set on other cores than the BSP. Found-by: BITS Tested-on: lenovo thinkpad x201t Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/nehalem/early_init.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 56c0d68..9c9d1b4 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -131,11 +131,6 @@ static void early_cpu_init (void) m = rdmsr(MSR_IA32_MISC_ENABLES); m.lo |= 0x10000; wrmsr(MSR_IA32_MISC_ENABLES, m); - - m = rdmsr(0x1f1); - m.lo |= 1; - wrmsr(0x1f1, m); - } void nehalem_early_initialization(int chipset_type)

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Patch set updated for coreboot: c61ee6f northbridge/intel/nehelam: don't set FERR_CAPABILITY on BSP
by Alexander Couzens 12 Mar '15

12 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8659 -gerrit commit c61ee6f416281d60b04300ab8930ea91c9ff358f Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Feb 26 01:30:40 2015 +0100 northbridge/intel/nehelam: don't set FERR_CAPABILITY on BSP This capability means: FERR messages are sent out on system detected an unmasked floating point x87 FPU error. Even this capability is supported on nehelem it doesn't makes sense to set it in early stage. This MSR has a core scope which results in an unsync MSR because it's not set on other cores than the BSP. Found-by=BITS Tested-on=lenovo thinkpad x201t Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/nehalem/early_init.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 56c0d68..9c9d1b4 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -131,11 +131,6 @@ static void early_cpu_init (void) m = rdmsr(MSR_IA32_MISC_ENABLES); m.lo |= 0x10000; wrmsr(MSR_IA32_MISC_ENABLES, m); - - m = rdmsr(0x1f1); - m.lo |= 1; - wrmsr(0x1f1, m); - } void nehalem_early_initialization(int chipset_type)

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Patch set updated for coreboot: 4f7eebb cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY
by Alexander Couzens 12 Mar '15

12 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8658 -gerrit commit 4f7eebbc195352255c5f8a5c1117c6be1dd732b7 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Feb 24 03:07:02 2015 +0100 cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY BIOS Writer's Guide, rev 1.6.0, June 2012: This MSR controls whether and FERR message is sent over the system bus when unmasked x87 exceptions are generated. This feature is not supported from Sandy Bridge processor onwards. Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/cpu/intel/model_2065x/model_2065x.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 454f7be..702eceb 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -35,6 +35,8 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 +#define IA32_FERR_CAPABILITY 0x1f1 +#define FERR_ENABLE (1 << 0) #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0

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New patch to review for coreboot: bc6fadd OxPCIe952: Fix read8/write8 argument
by Kyösti Mälkki 12 Mar '15

12 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8660 -gerrit commit bc6fadd825524ccdbcba91daae8aafc34abfe625 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 12 11:33:14 2015 +0200 OxPCIe952: Fix read8/write8 argument This was missed in commit bde6d309 as the driver is not enabled in any configuration by default. Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/uart/oxpcie.c | 5 +++-- src/drivers/uart/uart8250mem.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index 76119d2..af4afa9 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -34,11 +34,12 @@ static void oxford_oxpcie_enable(device_t dev) printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); return; } + void *bar0 = (void*)(uintptr_t) res->base; printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", - (read32(res->base) >> 8), (read32(res->base) & 0xff)); + (read32(bar0) >> 8), (read32(bar0) & 0xff)); printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", - (read32(res->base + 4) & 3)); + (read32(bar0 + 4) & 3)); printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); } diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 5fbbeec..cb70700 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -36,12 +36,12 @@ static uint8_t uart8250_read(void *base, uint8_t reg) { - return read8((uintptr_t) (base + reg)); + return read8(base + reg); } static void uart8250_write(void *base, uint8_t reg, uint8_t data) { - write8((uintptr_t) (base + reg), data); + write8(base + reg, data); } static int uart8250_mem_can_tx_byte(void *base)

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Patch set updated for coreboot: 3214b09 mainboard/lenovo/x201: correct sata_port_map
by Alexander Couzens 12 Mar '15

12 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8657 -gerrit commit 3214b09001bba5eb481e3d3f7926731c63dad5c1 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Feb 28 20:07:10 2015 +0100 mainboard/lenovo/x201: correct sata_port_map x201 has 2 sata ports. 1 port for hard drive and 1 port over the dock. Tested on x201 with hdd in port 1 + cdrom in port 2. Change-Id: I1ee8c547392257d4f2e00a5d48e21447a84f79c0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/x201/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index ffd3add..402b9d4 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -99,7 +99,7 @@ chip northbridge/intel/nehalem register "gpi1_routing" = "2" register "gpi13_routing" = "2" - register "sata_port_map" = "0x33" + register "sata_port_map" = "0x03" register "gpe0_en" = "0x20022046" register "alt_gp_smi_en" = "0x0000"

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Patch set updated for coreboot: 68dd19a cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY
by Alexander Couzens 12 Mar '15

12 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8658 -gerrit commit 68dd19ac15e7cce84f38e7fcc2180b8e015504b5 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Feb 24 03:07:02 2015 +0100 cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY BIOS Writer's Guide, rev 1.6.0, June 2012: This MSR controls whether and FERR message is sent over the system bus when unmasked x87 exceptions are generated. This feature is not supported from Sandy Bridge processor onwards. Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/cpu/intel/model_2065x/model_2065x.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 454f7be..649697f 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -35,6 +35,8 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 +#define IA32_FERR_CAPABILITY 0x1af +#define FERR_ENABLE (1 << 0) #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0

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Patch set updated for coreboot: ad3ba0a northbridge/intel/nehelam: don't set FERR_CAPABILITY on BSP
by Alexander Couzens 12 Mar '15

12 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8659 -gerrit commit ad3ba0a3391ab2428cb740d210d98524783fd5ee Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Feb 26 01:30:40 2015 +0100 northbridge/intel/nehelam: don't set FERR_CAPABILITY on BSP This capability means: FERR messages are sent out on system detected an unmasked floating point x87 FPU error. Even this capability is supported on nehelem it doesn't makes sense to set it in early stage. This MSR has a core scope which results in an unsync MSR because it's not set on other cores than the BSP. Found-by: BITS Tested-on: lenovo thinkpad x201t Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/nehalem/early_init.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 56c0d68..9c9d1b4 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -131,11 +131,6 @@ static void early_cpu_init (void) m = rdmsr(MSR_IA32_MISC_ENABLES); m.lo |= 0x10000; wrmsr(MSR_IA32_MISC_ENABLES, m); - - m = rdmsr(0x1f1); - m.lo |= 1; - wrmsr(0x1f1, m); - } void nehalem_early_initialization(int chipset_type)

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New patch to review for coreboot: 192bd49 northbridge/intel/nehelam: don't set FERR_CAPABILITY on BSP
by Alexander Couzens 11 Mar '15

11 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8659 -gerrit commit 192bd4941df05380ce903f751bbebe5d7da4f5ee Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Feb 26 01:30:40 2015 +0100 northbridge/intel/nehelam: don't set FERR_CAPABILITY on BSP This capability means: FERR messages are sent out on system detected an unmasked floating point x87 FPU error. Even this capability is supported on nehelem it doesn't makes sense to set it in early stage. This MSR has a core scope which results in an unsync MSR because it's not set on other cores than the BSP. Found-by=BITS Tested-on=lenovo thinkpad x201t Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/northbridge/intel/nehalem/early_init.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 56c0d68..9c9d1b4 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -131,11 +131,6 @@ static void early_cpu_init (void) m = rdmsr(MSR_IA32_MISC_ENABLES); m.lo |= 0x10000; wrmsr(MSR_IA32_MISC_ENABLES, m); - - m = rdmsr(0x1f1); - m.lo |= 1; - wrmsr(0x1f1, m); - } void nehalem_early_initialization(int chipset_type)

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coreboot-gerrit March 2015