coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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2443 discussions

New patch to review for coreboot: 8d053d0 coreboot arm64: Add int constants to stdint.h
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8650 -gerrit commit 8d053d0d46c5f25f41fc8279e93593b18854638d Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 22 10:51:43 2014 -0700 coreboot arm64: Add int constants to stdint.h BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I395c9b7bbe34c6834abc1a169779639f940121bd Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209334 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit da15df16464f4203db08fb02ad4c0a0f94d16724) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I818de7cb0d8a44fb20c2bbea108c15ecc2b724ae --- src/arch/arm64/include/stdint.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/arch/arm64/include/stdint.h b/src/arch/arm64/include/stdint.h index 38c2e1e..113c0e7 100644 --- a/src/arch/arm64/include/stdint.h +++ b/src/arch/arm64/include/stdint.h @@ -60,4 +60,14 @@ typedef uint8_t bool; typedef s64 intptr_t; typedef u64 uintptr_t; +#ifndef UINT32_MAX +#define UINT32_MAX (4294967295U) +#endif +#ifndef UINT64_MAX +# define UINT64_MAX (18446744073709551615ULL) +#endif +#ifndef PRIu64 +#define PRIu64 "llu" +#endif + #endif /* ARM64_STDINT_H */

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New patch to review for coreboot: 063b45e tegra132: fix Rx FIFO underruns with slower SPI clock
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8649 -gerrit commit 063b45e6d6063e973112c2b28eb379927fdc6d20 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 21 22:11:29 2014 -0500 tegra132: fix Rx FIFO underruns with slower SPI clock The SPI controller operates on packets which can be variable length up to 32-bit packets. It also has the ability to be put in packed or unpacked mode w.r.t each packet. i.e. does a single fifo register hold >= 1 packet. The current programming uses 8-bit packets in unpacked mode which means 4 fifo slots are used for a 32-bit DMA transfter. As the AHB can only operate on a minimum of 32-bit bursts the triggers need to be programmed correctly so that there is room for a full 32-bit DMA transaction. Previously faster SPI clocks just made things magically work. BUG=chrome-os-partner:30779 BRANCH=None TEST=Built and booted through coreboot with 20MHz SPI clock. Original-Change-Id: I3f1cd4dddcea9514327b2363ed450a527db7e1fe Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208862 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit d9864228a2479e412d7e0d2221fe536f78329acd) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I61c145f35e1f889d4f83f3dfea049bfd347c1196 --- src/soc/nvidia/tegra132/spi.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c index f1be207..973bdc9 100644 --- a/src/soc/nvidia/tegra132/spi.c +++ b/src/soc/nvidia/tegra132/spi.c @@ -530,10 +530,24 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) */ setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); - if (spi->dma_out) + /* + * The DMA triggers have units of packets. As each packet is currently + * 1 byte the triggers need to be set to 4 packets (0b01) to match + * the AHB 32-bit (4 byte) tranfser. Otherwise the FIFO errors can + * occur. + */ + if (spi->dma_out) { + clrsetbits_le32(&spi->regs->dma_ctl, + SPI_DMA_CTL_TX_TRIG_MASK << SPI_DMA_CTL_TX_TRIG_SHIFT, + 1 << SPI_DMA_CTL_TX_TRIG_SHIFT); setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); - if (spi->dma_in) + } + if (spi->dma_in) { + clrsetbits_le32(&spi->regs->dma_ctl, + SPI_DMA_CTL_RX_TRIG_MASK << SPI_DMA_CTL_RX_TRIG_SHIFT, + 1 << SPI_DMA_CTL_RX_TRIG_SHIFT); setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + } /* * To avoid underrun conditions, enable APB DMA before SPI DMA for

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New patch to review for coreboot: 0392b6b tegra132: Trust Zone register access
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8648 -gerrit commit 0392b6b1211e5965acda1a2efefeee21343e76f2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 21 14:24:42 2014 -0500 tegra132: Trust Zone register access The Trust Zone carveout registers are only accessible using a secure access mode. The AVP runs as non-secure all the time. In EL3 the CPU is in secure mode, but when the MMU is enabled the page tables dictate if accesses to certain regions are secure or not. However, ramstage is currently being loaded into non-secure memory and the page tables will live in non-secure memory as well. Therefore, handle all these cases by providing global state which mirrors the TZ register. BUG=chrome-os-partner:30782 BRANCH=None TEST=Built and ran through ramstage with the MMU enabled Resources are read and set accordingly. Original-Change-Id: Ib76b2641497a29ef2adb75934b2df55ecf0b3e78 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209061 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 0bcbdc56978f6ebe3e7d1b74ed2fd861e03bb562) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9c1beed443a48870ba190427e87caf90caf4ff6b --- src/soc/nvidia/tegra132/addressmap.c | 55 ++++++++++++++++-------- src/soc/nvidia/tegra132/include/soc/addressmap.h | 9 ++++ src/soc/nvidia/tegra132/ramstage.c | 23 +--------- src/soc/nvidia/tegra132/romstage.c | 11 +++++ 4 files changed, 58 insertions(+), 40 deletions(-) diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c index 7dbab55..6537187 100644 --- a/src/soc/nvidia/tegra132/addressmap.c +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -27,6 +27,9 @@ #include "mc.h" #include "sdram.h" +static uintptr_t tz_base_mib; +static const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; + /* returns total amount of DRAM (in MB) from memory controller registers */ int sdram_size_mb(void) { @@ -71,13 +74,8 @@ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib) switch (id) { case CARVEOUT_TZ: - /* AVP does not have access to the TZ carveout registers. */ - if (context_avp()) - return; - carveout_from_regs(base_mib, size_mib, - read32(&mc->security_cfg0), - 0, - read32(&mc->security_cfg1)); + *base_mib = tz_base_mib; + *size_mib = tz_size_mib; break; case CARVEOUT_SEC: carveout_from_regs(base_mib, size_mib, @@ -102,7 +100,8 @@ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib) } } -static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib) +static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib, + int ignore_tz) { uintptr_t base; uintptr_t end; @@ -128,6 +127,9 @@ static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib) uintptr_t carveout_end; size_t carveout_size; + if (i == CARVEOUT_TZ && ignore_tz) + continue; + carveout_range(i, &carveout_base, &carveout_size); if (carveout_size == 0) @@ -155,14 +157,14 @@ void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib) { *base_mib = 0; *end_mib = 4096; - memory_in_range(base_mib, end_mib); + memory_in_range(base_mib, end_mib, 0); } void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib) { *base_mib = 4096; *end_mib = ~0UL; - memory_in_range(base_mib, end_mib); + memory_in_range(base_mib, end_mib, 0); } uintptr_t framebuffer_attributes(size_t *size_mib) @@ -173,16 +175,33 @@ uintptr_t framebuffer_attributes(size_t *size_mib) /* Place the framebuffer just below the 32-bit addressable limit. */ memory_in_range_below_4gb(&begin, &end); - /* - * Need to take into account that the Trust Zone region is not able to - * be read by the AVP. The Trust Zone region will live just below the - * rest of the carveout regions. - */ - if (context_avp()) - end -= CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; - *size_mib = FB_SIZE_MB; end -= *size_mib; return end; } + +void trustzone_region_init(void) +{ + struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; + uintptr_t end = 4096; + + /* Already has been initialized. */ + if (tz_size_mib != 0 && tz_base_mib != 0) + return; + + /* + * Get memory layout below 4GiB ignoring the TZ carveout because + * that's the one to initialize. + */ + memory_in_range(&tz_base_mib, &end, 1); + tz_base_mib = end - tz_size_mib; + + /* AVP cannot set the TZ registers proper as it is always non-secure. */ + if (context_avp()) + return; + + /* Set the carveout region. */ + write32(tz_base_mib << 20, &mc->security_cfg0); + write32(tz_size_mib, &mc->security_cfg1); +} diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h index 3d0fc59..52e4d54 100644 --- a/src/soc/nvidia/tegra132/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -99,6 +99,15 @@ enum { /* Provided the careout id, obtain the base and size in 1MiB units. */ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib); +/* + * There are complications accessing the Trust Zone carveout region. The + * AVP cannot access these registers and the CPU can't access this register + * as a non-secure access. When the page tables live in non-secure memory + * these registers cannot be accessed either. Thus, this function handles + * both the AVP case and non-secured access case by keeping global state. + */ +void trustzone_region_init(void); + /* Return pointer and size in 1MiB units. */ uintptr_t framebuffer_attributes(size_t *size_mib); diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index ad553d4..b3b4db2 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -17,34 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/io.h> #include <arch/stages.h> #include <soc/addressmap.h> -#include "mc.h" #include "mmu_operations.h" void arm64_soc_init(void) { - struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; - const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; - uintptr_t base; - uintptr_t end; - - if (!tz_size_mib) - return; - - /* - * Ramstage is when the arm64 first gets running. It also is the - * only entity that the capabilities to program the Trust Zone region. - * Therefore configure the region early. Also, the TZ region can only - * live in 32-bit space. - */ - memory_in_range_below_4gb(&base, &end); - - /* Place the TZ area just below current carveout regions. */ - end -= tz_size_mib; - write32(end << 20, &mc->security_cfg0); - write32(tz_size_mib, &mc->security_cfg1); + trustzone_region_init(); tegra132_mmu_init(); } diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 2a1bd46..4b1c843 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -24,6 +24,7 @@ #include <console/console.h> #include <arch/exception.h> +#include <soc/addressmap.h> #include <soc/sdram_configs.h> #include "sdram.h" #include "ccplex.h" @@ -45,6 +46,16 @@ void romstage(void) sdram_init(get_sdram_config()); printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); #endif + + /* + * Trust Zone needs to be initialized after the DRAM initialization + * because carveout registers are programmed during DRAM init. + * cbmem_initialize() is dependent on the Trust Zone region + * initalization because CBMEM lives right below the Trust Zone which + * needs to be properly identified. + */ + trustzone_region_init(); + cbmem_initialize(); ccplex_cpu_prepare();

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New patch to review for coreboot: cd024ff t132: Add mmu support
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8647 -gerrit commit cd024ff4a345bf98e91c54c51e2737cb18a38b1a Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Jul 17 11:42:35 2014 -0700 t132: Add mmu support Add support for mmu initialization and enabling caches. mmu_operations provides functions to add mmap_regions using memrange library and then calls mmu_init for armv8. BUG=chrome-os-partner:30688 BRANCH=None TEST=Compiles rush successfully and boots until depthcharge load. Goes past all the earlier alignment errors. Original-Change-Id: I57c2be80427fa77239093c79ece73e31fd319239 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208762 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit a6141d13d40cfa5a493bde44e69c588dda97e8fd) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I33bf4b2e28b85a3117b566cb8497f2bd5aabb69b --- src/soc/nvidia/tegra132/Kconfig | 8 ++++ src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/mmu_operations.c | 82 ++++++++++++++++++++++++++++++++ src/soc/nvidia/tegra132/mmu_operations.h | 25 ++++++++++ src/soc/nvidia/tegra132/ramstage.c | 3 ++ 5 files changed, 119 insertions(+) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 0ce29a0..638fb65 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -75,6 +75,14 @@ config RAMSTAGE_STACK_BOTTOM hex default 0x8001c000 +config TTB_BUFFER + hex + default 0x80020000 + +config TTB_SIZE + hex + default 0x110000 + config CBFS_CACHE_ADDRESS hex "memory address to put CBFS cache data" default 0x40006000 diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index f8d4a4c..b246f64 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -50,6 +50,7 @@ ramstage-y += ../tegra/gpio.c ramstage-y += ../tegra/i2c.c ramstage-y += ../tegra/pinmux.c ramstage-y += ramstage.c +ramstage-y += mmu_operations.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ diff --git a/src/soc/nvidia/tegra132/mmu_operations.c b/src/soc/nvidia/tegra132/mmu_operations.c new file mode 100644 index 0000000..1514780 --- /dev/null +++ b/src/soc/nvidia/tegra132/mmu_operations.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <stdint.h> +#include <memrange.h> + +#include <cbmem.h> +#include <console/console.h> + +#include <arch/mmu.h> +#include "mmu_operations.h" +#include <soc/addressmap.h> + +/* This structure keeps track of all the mmap memory ranges for t132 */ +static struct memranges t132_mmap_ranges; + +static void print_memranges(struct memranges *mmap_ranges) +{ + struct range_entry *mmap_entry; + + printk(BIOS_DEBUG,"printing mmap entries\n"); + + memranges_each_entry(mmap_entry, mmap_ranges) { + printk(BIOS_DEBUG,"0x%p 0x%p 0x%lx\n", + (void*)mmap_entry->begin,(void*)mmap_entry->end,mmap_entry->tag); + } + +} + +static void tegra132_memrange_init(void) +{ + uint64_t start,end; + + memranges_init_empty(&t132_mmap_ranges); + + memory_in_range_below_4gb(&start,&end); + + /* Device memory below DRAM */ + memranges_insert(&t132_mmap_ranges, 0, start * MiB, MA_DEV | MA_NS | + MA_RW); + + /* DRAM */ + memranges_insert(&t132_mmap_ranges, start * MiB, (end-start) * MiB, + MA_MEM | MA_NS | MA_RW); + + memory_in_range_above_4gb(&start,&end); + + memranges_insert(&t132_mmap_ranges, start * MiB, (end-start) * MiB, + MA_MEM | MA_NS | MA_RW); + + /* SRAM */ + memranges_insert(&t132_mmap_ranges, TEGRA_SRAM_BASE, TEGRA_SRAM_SIZE, + MA_MEM | MA_NS | MA_RW); + + print_memranges(&t132_mmap_ranges); +} + +void tegra132_mmu_init(void) +{ + uint64_t *ttb_buffer = (uint64_t*)CONFIG_TTB_BUFFER; + uint64_t ttb_size = (uint64_t)CONFIG_TTB_SIZE; + tegra132_memrange_init(); + mmu_init(&t132_mmap_ranges,ttb_buffer,ttb_size); + mmu_enable((uint64_t)ttb_buffer); +} diff --git a/src/soc/nvidia/tegra132/mmu_operations.h b/src/soc/nvidia/tegra132/mmu_operations.h new file mode 100644 index 0000000..bc2773c --- /dev/null +++ b/src/soc/nvidia/tegra132/mmu_operations.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__ +#define __SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__ + +void tegra132_mmu_init(void); + +#endif //__SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__ diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index 8d64c3e..ad553d4 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -21,6 +21,7 @@ #include <arch/stages.h> #include <soc/addressmap.h> #include "mc.h" +#include "mmu_operations.h" void arm64_soc_init(void) { @@ -44,4 +45,6 @@ void arm64_soc_init(void) end -= tz_size_mib; write32(end << 20, &mc->security_cfg0); write32(tz_size_mib, &mc->security_cfg1); + + tegra132_mmu_init(); }

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New patch to review for coreboot: c7ff140 armv8: Add mmu support
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8646 -gerrit commit c7ff140669d2a622a49d1546c4ba33ea60c561ce Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Jul 17 11:36:08 2014 -0700 armv8: Add mmu support Add support for initializing and enabling mmu for armv8. Using 64KiB granule and 33 bits per VA, thus total VA address space is 6GiB. PA Range is 64GiB. Makes use of memrange library to get a list of all the mmap regions from the SoC to initialize XLAT table. Currently, all calculations in mmu.h are based on the assumptions that max 33 bits are used in VA and granule size is 64KiB. Changes in these assumptions will have to reflect in the dependent calculations as well. BUG=chrome-os-partner:30688 BRANCH=None TEST=Compiles rush successfully and boots until "payload not found". Goes past all the earlier alignment errors. Original-Change-Id: Iac1df15f0b81dcf64484a56b94f51357bcd67cc2 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208761 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 6fe96360c03342115f849074f9e45a2c4e210705) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5360a3be95f198bd0b4f79b62f31228cc7a9c285 --- src/arch/arm64/armv8/Makefile.inc | 1 + src/arch/arm64/armv8/mmu.c | 313 ++++++++++++++++++++++++++++++++ src/arch/arm64/include/armv8/arch/mmu.h | 165 +++++++++++++++++ 3 files changed, 479 insertions(+) diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index ca4562b..4cbb6e9 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -69,6 +69,7 @@ ramstage-y += cache.c ramstage-y += cpu.S ramstage-y += exception.c ramstage-y += exception_asm.S +ramstage-y += mmu.c ramstage-c-ccopts += $(armv8_flags) ramstage-S-ccopts += $(armv8_asm_flags) diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c new file mode 100644 index 0000000..e1f088e --- /dev/null +++ b/src/arch/arm64/armv8/mmu.c @@ -0,0 +1,313 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <stdlib.h> +#include <stdint.h> +#include <string.h> + +#include <cbmem.h> +#include <console/console.h> + +#include <memrange.h> +#include <arch/mmu.h> +#include <arch/lib_helpers.h> +#include <arch/cache.h> + +/* Maximum number of XLAT Tables available based on ttb buffer size */ +static unsigned int max_tables; +/* Address of ttb buffer */ +static uint64_t *xlat_addr; + +static const uint64_t level_to_addr_mask[] = { + L1_ADDR_MASK, + L2_ADDR_MASK, + L3_ADDR_MASK, +}; + +static const uint64_t level_to_addr_shift[] = { + L1_ADDR_SHIFT, + L2_ADDR_SHIFT, + L3_ADDR_SHIFT, +}; + +/* Func : get_block_attr + * Desc : Get block descriptor attributes based on the value of tag in memrange + * region + */ +static uint64_t get_block_attr(unsigned long tag) +{ + uint64_t attr; + + attr = (tag & MA_NS)? BLOCK_NS : 0; + attr |= (tag & MA_RO)? BLOCK_AP_RO : BLOCK_AP_RW; + attr |= BLOCK_ACCESS; + attr |= (tag & MA_MEM)? (BLOCK_INDEX_MEM_NORMAL << BLOCK_INDEX_SHIFT) : + (BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT); + + return attr; +} + +/* Func : get_index_from_addr + * Desc : Get index into table at a given level using appropriate bits from the + * base address + */ +static uint64_t get_index_from_addr(uint64_t addr, uint8_t level) +{ + uint64_t mask = level_to_addr_mask[level-1]; + uint8_t shift = level_to_addr_shift[level-1]; + + return ((addr & mask) >> shift); +} + +/* Func : table_desc_valid + * Desc : Check if a table entry contains valid desc + */ +static uint64_t table_desc_valid(uint64_t desc) +{ + return((desc & TABLE_DESC) == TABLE_DESC); +} + +/* Func : get_new_table + * Desc : Return the next free XLAT table from ttb buffer + */ +static uint64_t *get_new_table(void) +{ + static int free_idx = 1; + uint64_t *new; + + if (free_idx >= max_tables) { + printk(BIOS_ERR,"ARM64 MMU: No free table\n"); + return NULL; + } + + new = (uint64_t*)((unsigned char *)xlat_addr + free_idx * GRANULE_SIZE); + free_idx++; + + memset(new, 0, GRANULE_SIZE); + + return new; +} + +/* Func : get_table_from_desc + * Desc : Get next level table address from table descriptor + */ +static uint64_t *get_table_from_desc(uint64_t desc) +{ + uint64_t *ptr = (uint64_t*)(desc & XLAT_TABLE_MASK); + return ptr; +} + +/* Func: get_next_level_table + * Desc: Check if the table entry is a valid descriptor. If not, allocate new + * table, update the entry and return the table addr. If valid, return the addr + */ +static uint64_t *get_next_level_table(uint64_t *ptr) +{ + uint64_t desc = *ptr; + + if (!table_desc_valid(desc)) { + uint64_t *new_table = get_new_table(); + if (new_table == NULL) + return NULL; + desc = ((uint64_t)new_table) | TABLE_DESC; + *ptr = desc; + } + return get_table_from_desc(desc); +} + +/* Func : init_xlat_table + * Desc : Given a base address and size, it identifies the indices within + * different level XLAT tables which map the given base addr. Similar to table + * walk, except that all invalid entries during the walk are updated + * accordingly. On success, it returns the size of the block/page addressed by + * the final table + */ +static uint64_t init_xlat_table(uint64_t base_addr, + uint64_t size, + uint64_t tag) +{ + uint64_t l1_index = get_index_from_addr(base_addr,1); + uint64_t l2_index = get_index_from_addr(base_addr,2); + uint64_t l3_index = get_index_from_addr(base_addr,3); + uint64_t *table = xlat_addr; + uint64_t desc; + uint64_t attr = get_block_attr(tag); + + /* L1 table lookup */ + /* If VA has bits more than 41, lookup starts at L1 */ + if (l1_index) { + table = get_next_level_table(&table[l1_index]); + if (!table) + return 0; + } + + /* L2 table lookup */ + /* If lookup was performed at L1, L2 table addr is obtained from L1 desc + else, lookup starts at ttbr address */ + if (!l3_index && (size >= L2_XLAT_SIZE)) { + /* If block address is aligned and size is greater than or equal + to 512MiB i.e. size addressed by each L2 entry, we can + directly store a block desc */ + desc = base_addr | BLOCK_DESC | attr; + table[l2_index] = desc; + /* L3 lookup is not required */ + return L2_XLAT_SIZE; + } else { + /* L2 entry stores a table descriptor */ + table = get_next_level_table(&table[l2_index]); + if (!table) + return 0; + } + + /* L3 table lookup */ + desc = base_addr | PAGE_DESC | attr; + table[l3_index] = desc; + return L3_XLAT_SIZE; +} + +/* Func : sanity_check + * Desc : Check if the address is aligned and size is atleast the granule size + */ +static uint64_t sanity_check(uint64_t addr, + uint64_t size) +{ + /* Address should be atleast 64 KiB aligned */ + if (addr & GRANULE_SIZE_MASK) + return 1; + + /* Size should be atleast granule size */ + if (size < GRANULE_SIZE) + return 1; + + return 0; +} + +/* Func : init_mmap_entry + * Desc : For each mmap entry, this function calls init_xlat_table with the base + * address. Based on size returned from init_xlat_table, base_addr is updated + * and subsequent calls are made for initializing the xlat table until the whole + * region is initialized. + */ +static void init_mmap_entry(struct range_entry *r) +{ + uint64_t base_addr = range_entry_base(r); + uint64_t size = range_entry_size(r); + uint64_t tag = range_entry_tag(r); + uint64_t temp_size = size; + + while (temp_size) { + uint64_t ret; + + if (sanity_check(base_addr,temp_size)) { + printk(BIOS_ERR, "ARM64 MMU: sanity check failed\n"); + return; + } + + ret = init_xlat_table(base_addr + (size - temp_size), + temp_size,tag); + + if (ret == 0) + return; + + temp_size -= ret; + } +} + +/* Func : mmu_init + * Desc : Initialize mmu based on the mmap_ranges passed. ttb_buffer is used as + * the base address for xlat tables. ttb_size defines the max number of tables + * that can be used + */ +void mmu_init(struct memranges *mmap_ranges, + uint64_t *ttb_buffer, + uint64_t ttb_size) +{ + struct range_entry *mmap_entry; + + if (sanity_check((uint64_t)ttb_buffer, ttb_size)) { + printk(BIOS_ERR, "ARM64: Sanity failed for ttb\n"); + return; + } + + memset((void*)ttb_buffer, 0, GRANULE_SIZE); + max_tables = (ttb_size >> GRANULE_SIZE_SHIFT); + xlat_addr = ttb_buffer; + + printk(BIOS_DEBUG, "ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n", + (void*)xlat_addr, max_tables); + + memranges_each_entry(mmap_entry, mmap_ranges) { + init_mmap_entry(mmap_entry); + } + printk(BIOS_DEBUG, "ARM64: MMU init done\n"); +} + +static uint32_t is_mmu_enabled(void) +{ + uint32_t sctlr; + + sctlr = raw_read_sctlr_el3(); + + return (sctlr & SCTLR_M); +} + +void mmu_enable(uint64_t ttbr) +{ + uint32_t sctlr; + + /* Initialize MAIR indices */ + raw_write_mair_el3(MAIR_ATTRIBUTES); + + /* Invalidate TLBs */ + tlbiall_el3(); + + /* Initialize TCR flags */ + raw_write_tcr_el3(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC | + TCR_SH0_IS | TCR_TG0_64KB | TCR_PS_64GB | + TCR_TBI_USED); + + /* Initialize TTBR */ + raw_write_ttbr0_el3(ttbr); + + /* Ensure all translation table writes are committed before enabling MMU */ + dsb(); + isb(); + + /* Enable MMU */ + sctlr = raw_read_sctlr_el3(); + sctlr |= SCTLR_C | SCTLR_M | SCTLR_I; + raw_write_sctlr_el3(sctlr); + + isb(); + + if (is_mmu_enabled()) + printk(BIOS_DEBUG, "ARM64: MMU enable done\n"); + else + printk(BIOS_DEBUG, "ARM64: MMU enable failed\n"); +} diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h new file mode 100644 index 0000000..f5f60a1 --- /dev/null +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARCH_ARM64_MMU_H__ +#define __ARCH_ARM64_MMU_H__ + +#include <memrange.h> + +/* IMPORTANT!!!!!!! + * Assumptions made: + * Granule size is 64KiB + * BITS per Virtual address is 33 + * All the calculations for tables L1,L2 and L3 are based on these assumptions + * If these values are changed, recalculate the other macros as well + */ + + +/* Memory attributes for mmap regions + * These attributes act as tag values for memrange regions + */ + +/* Normal memory / device */ +#define MA_MEM (1 << 0) +#define MA_DEV (0 << 0) + +/* Secure / non-secure */ +#define MA_NS (1 << 1) +#define MA_S (0 << 1) + +/* Read only / Read-write */ +#define MA_RO (1 << 2) +#define MA_RW (0 << 2) + +/* Descriptor attributes */ + +#define INVALID_DESC 0x0 +#define BLOCK_DESC 0x1 +#define TABLE_DESC 0x3 +#define PAGE_DESC 0x3 + +/* Block descriptor */ +#define BLOCK_NS (1 << 5) + +#define BLOCK_AP_RW (0 << 7) +#define BLOCK_AP_RO (1 << 7) + +#define BLOCK_ACCESS (1 << 10) + +/* XLAT Table Init Attributes */ + +#define VA_START 0x0 +/* If BITS_PER_VA or GRANULE_SIZE are changed, recalculate and change the + macros following them */ +#define BITS_PER_VA 33 +/* Granule size of 64KB is being used */ +#define GRANULE_SIZE_SHIFT 16 +#define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT) +#define XLAT_TABLE_MASK ~(0xffffUL) +#define GRANULE_SIZE_MASK ((1 << 16) - 1) + +#define L1_ADDR_SHIFT 42 +#define L2_ADDR_SHIFT 29 +#define L3_ADDR_SHIFT 16 + +#define L1_ADDR_MASK (0UL << L1_ADDR_SHIFT) +#define L2_ADDR_MASK (0xfUL << L2_ADDR_SHIFT) +#define L3_ADDR_MASK (0x1fffUL << L3_ADDR_SHIFT) + +/* Dependent on BITS_PER_VA and GRANULE_SIZE */ +#define INIT_LEVEL 2 +#define XLAT_MAX_LEVEL 3 + +/* Each entry in XLAT table is 8 bytes */ +#define XLAT_ENTRY_SHIFT 3 +#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SHIFT) + +#define XLAT_TABLE_SHIFT GRANULE_SIZE_SHIFT +#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SHIFT) + +#define XLAT_NUM_ENTRIES_SHIFT (XLAT_TABLE_SHIFT - XLAT_ENTRY_SHIFT) +#define XLAT_NUM_ENTRIES (1 << XLAT_NUM_ENTRIES_SHIFT) + +#define L3_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT) +#define L2_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT + XLAT_NUM_ENTRIES_SHIFT) +#define L1_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT + XLAT_NUM_ENTRIES_SHIFT) + +/* These macros give the size of the region addressed by each entry of a xlat + table at any given level */ +#define L3_XLAT_SIZE (1 << L3_XLAT_SIZE_SHIFT) +#define L2_XLAT_SIZE (1 << L2_XLAT_SIZE_SHIFT) +#define L1_XLAT_SIZE (1 << L1_XLAT_SIZE_SHIFT) + +/* Block indices required for MAIR */ +#define BLOCK_INDEX_MEM_DEV_NGNRNE 0 +#define BLOCK_INDEX_MEM_DEV_NGNRE 1 +#define BLOCK_INDEX_MEM_DEV_GRE 2 +#define BLOCK_INDEX_MEM_NORMAL_NC 3 +#define BLOCK_INDEX_MEM_NORMAL 4 + +#define BLOCK_INDEX_SHIFT 2 + +/* MAIR attributes */ +#define MAIR_ATTRIBUTES ((0x00 << (BLOCK_INDEX_MEM_DEV_NGNRNE*8)) | \ + (0x04 << (BLOCK_INDEX_MEM_DEV_NGNRE*8)) | \ + (0x0c << (BLOCK_INDEX_MEM_DEV_GRE*8)) | \ + (0x44 << (BLOCK_INDEX_MEM_NORMAL_NC*8)) | \ + (0xffUL << (BLOCK_INDEX_MEM_NORMAL*8))) + +/* TCR attributes */ +#define TCR_TOSZ (64 - BITS_PER_VA) + +#define TCR_IRGN0_SHIFT 8 +#define TCR_IRGN0_NM_NC (0x00 << TCR_IRGN0_SHIFT) +#define TCR_IRGN0_NM_WBWAC (0x01 << TCR_IRGN0_SHIFT) +#define TCR_IRGN0_NM_WTC (0x02 << TCR_IRGN0_SHIFT) +#define TCR_IRGN0_NM_WBNWAC (0x03 << TCR_IRGN0_SHIFT) + +#define TCR_ORGN0_SHIFT 10 +#define TCR_ORGN0_NM_NC (0x00 << TCR_ORGN0_SHIFT) +#define TCR_ORGN0_NM_WBWAC (0x01 << TCR_ORGN0_SHIFT) +#define TCR_ORGN0_NM_WTC (0x02 << TCR_ORGN0_SHIFT) +#define TCR_ORGN0_NM_WBNWAC (0x03 << TCR_ORGN0_SHIFT) + +#define TCR_SH0_SHIFT 12 +#define TCR_SH0_NC (0x0 << TCR_SH0_SHIFT) +#define TCR_SH0_OS (0x2 << TCR_SH0_SHIFT) +#define TCR_SH0_IS (0x3 << TCR_SH0_SHIFT) + +#define TCR_TG0_SHIFT 14 +#define TCR_TG0_4KB (0x0 << TCR_TG0_SHIFT) +#define TCR_TG0_64KB (0x1 << TCR_TG0_SHIFT) +#define TCR_TG0_16KB (0x2 << TCR_TG0_SHIFT) + +#define TCR_PS_SHIFT 16 +#define TCR_PS_4GB (0x0 << TCR_PS_SHIFT) +#define TCR_PS_64GB (0x1 << TCR_PS_SHIFT) +#define TCR_PS_1TB (0x2 << TCR_PS_SHIFT) +#define TCR_PS_4TB (0x3 << TCR_PS_SHIFT) +#define TCR_PS_16TB (0x4 << TCR_PS_SHIFT) +#define TCR_PS_256TB (0x5 << TCR_PS_SHIFT) + +#define TCR_TBI_SHIFT 20 +#define TCR_TBI_USED (0x0 << TCR_TBI_SHIFT) +#define TCR_TBI_IGNORED (0x1 << TCR_TBI_SHIFT) + +void mmu_init(struct memranges *,uint64_t *,uint64_t); +void mmu_enable(uint64_t); + +#endif // __ARCH_ARM64_MMU_H__

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New patch to review for coreboot: 79bd0f0 ryu: Add TPS65913 regs/init for VDD_CPU 1.0V
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8645 -gerrit commit 79bd0f0ae6dbf1d04f7fe213b6748cc14057145e Author: Tom Warren <twarren(a)nvidia.com> Date: Wed Jul 16 11:09:39 2014 -0700 ryu: Add TPS65913 regs/init for VDD_CPU 1.0V Other default slams should be added later to the init table once we know what the kernel touches. But for now, only VDD_CPU is needed. Also slipped in a minor name change in mainboard.c BRANCH=none BUG=none TEST=none, no HW here for me to test on yet Change-Id: Ifbe86192449ed0466085808a0a12a15a7b6a1795 Signed-off-by: Tom Warren <twarren(a)nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/208385 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 53b332fb12cd685fbec265695333a70c4064524c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/google/rush_ryu/mainboard.c | 2 +- src/mainboard/google/rush_ryu/pmic.c | 61 ++++++--------------- src/mainboard/google/rush_ryu/pmic.h | 89 +++++++++++++++++++++++-------- 3 files changed, 83 insertions(+), 69 deletions(-) diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 9b8e354..dff5954 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -30,6 +30,6 @@ static void mainboard_enable(device_t dev) } struct chip_operations mainboard_ops = { - .name = "rush", + .name = "rush_ryu", .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/rush_ryu/pmic.c b/src/mainboard/google/rush_ryu/pmic.c index 5fc3b17..8d5ea7a 100644 --- a/src/mainboard/google/rush_ryu/pmic.c +++ b/src/mainboard/google/rush_ryu/pmic.c @@ -23,45 +23,31 @@ #include <device/i2c.h> #include <stdint.h> #include <stdlib.h> - -#include "boardid.h" #include "pmic.h" #include "reset.h" +/* A44/Ryu has a TI 65913 PMIC on bus 4 (PWR_I2C) */ + enum { - AS3722_I2C_ADDR = 0x40 + TI65913_I2C_ADDR = 0x58 }; -struct as3722_init_reg { +struct ti65913_init_reg { u8 reg; u8 val; u8 delay; }; -static struct as3722_init_reg init_list[] = { - {AS3722_SDO0, 0x3C, 1}, - {AS3722_SDO1, 0x32, 0}, - {AS3722_LDO3, 0x59, 0}, - {AS3722_SDO2, 0x3C, 0}, - {AS3722_SDO3, 0x00, 0}, - {AS3722_SDO4, 0x00, 0}, - {AS3722_SDO5, 0x50, 0}, - {AS3722_SDO6, 0x28, 1}, - {AS3722_LDO0, 0x8A, 0}, - {AS3722_LDO1, 0x00, 0}, - {AS3722_LDO2, 0x10, 0}, - {AS3722_LDO4, 0x00, 0}, - {AS3722_LDO5, 0x00, 0}, - {AS3722_LDO6, 0x00, 0}, - {AS3722_LDO7, 0x00, 0}, - {AS3722_LDO9, 0x00, 0}, - {AS3722_LDO10, 0x00, 0}, - {AS3722_LDO11, 0x00, 1}, +static struct ti65913_init_reg init_list[] = { +//TODO(twarren(a)nvidia.com): Add slams back to defaults +// {TI65913_SMPS12_CTRL, 0x01, 0}, +// {TI65913_SMPS12_VOLTAGE, 0x38, 0}, +//etc. }; static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) { - if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) { + if (i2c_writeb(bus, TI65913_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); /* Reset the SoC on any PMIC write error */ @@ -75,38 +61,23 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) static void pmic_slam_defaults(unsigned bus) { int i; + for (i = 0; i < ARRAY_SIZE(init_list); i++) { - struct as3722_init_reg *reg = &init_list[i]; + struct ti65913_init_reg *reg = &init_list[i]; pmic_write_reg(bus, reg->reg, reg->val, reg->delay); } } void pmic_init(unsigned bus) { - /* - * Don't need to set up VDD_CORE - already done - by OTP - * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. - * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. - */ + /* Don't need to set up VDD_CORE - already done - by EC ?? */ /* Restore PMIC POR defaults, in case kernel changed 'em */ pmic_slam_defaults(bus); - /* SDO0: Set VDD_CPU to 1.2V. */ - pmic_write_reg(bus, 0x00, 0x50, 1); - - /* SDO6: Set VDD_GPU to 1.0V. */ - pmic_write_reg(bus, 0x06, 0x28, 1); - - /* LDO2: Set +1.2V_GEN_AVDD to 1.2V */ - pmic_write_reg(bus, 0x12, 0x10, 1); - - /* - * Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set - * the value (register 0x20 bit 4) - */ - pmic_write_reg(bus, 0x0c, 0x07, 0); - pmic_write_reg(bus, 0x20, 0x10, 1); + /* A44: Set VDD_CPU to 1.0V. */ + pmic_write_reg(bus, TI65913_SMPS12_CTRL, 0x01, 1); + pmic_write_reg(bus, TI65913_SMPS12_VOLTAGE, 0x38, 0); printk(BIOS_DEBUG, "PMIC init done\n"); } diff --git a/src/mainboard/google/rush_ryu/pmic.h b/src/mainboard/google/rush_ryu/pmic.h index b56c513..1f102a7 100644 --- a/src/mainboard/google/rush_ryu/pmic.h +++ b/src/mainboard/google/rush_ryu/pmic.h @@ -17,32 +17,75 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __MAINBOARD_GOOGLE_RUSH_PMIC_H__ -#define __MAINBOARD_GOOGLE_RUSH_PMIC_H__ +#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ +#define __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ +/* A44/Ryu has a TI 65913 PMIC */ enum { - AS3722_SDO0 = 0, - AS3722_SDO1, - AS3722_SDO2, - AS3722_SDO3, - AS3722_SDO4, - AS3722_SDO5, - AS3722_SDO6, - - AS3722_LDO0 = 0x10, - AS3722_LDO1, - AS3722_LDO2, - AS3722_LDO3, - AS3722_LDO4, - AS3722_LDO5, - AS3722_LDO6, - AS3722_LDO7, - - AS3722_LDO9 = 0x19, - AS3722_LDO10, - AS3722_LDO11, + TI65913_SMPS12_CTRL = 0x20, + TI65913_SMPS12_TSTEP, + TI65913_SMPS12_FORCE, + TI65913_SMPS12_VOLTAGE, + + TI65913_SMPS3_CTRL, + TI65913_SMPS3_VOLTAGE = 0x27, + + TI65913_SMPS45_CTRL = 0x28, + TI65913_SMPS45_TSTEP, + TI65913_SMPS45_FORCE, + TI65913_SMPS45_VOLTAGE, + + TI65913_SMPS6_CTRL = 0x2C, + TI65913_SMPS6_TSTEP, + TI65913_SMPS6_FORCE, + TI65913_SMPS6_VOLTAGE, + + TI65913_SMPS7_CTRL = 0x30, + TI65913_SMPS7_VOLTAGE = 0x33, + + TI65913_SMPS8_CTRL = 0x34, + TI65913_SMPS8_TSTEP, + TI65913_SMPS8_FORCE, + TI65913_SMPS8_VOLTAGE, + + TI65913_SMPS9_CTRL = 0x38, + TI65913_SMPS9_VOLTAGE = 0x3B, + + TI65913_SMPS10_CTRL = 0x3C, + TI65913_SMPS10_STATUS = 0x3F, + + TI65913_LDO1_CTRL = 0x50, + TI65913_LDO1_VOLTAGE, + TI65913_LDO2_CTRL, + TI65913_LDO2_VOLTAGE, + TI65913_LDO3_CTRL, + TI65913_LDO3_VOLTAGE, + TI65913_LDO4_CTRL, + TI65913_LDO4_VOLTAGE, + TI65913_LDO5_CTRL, + TI65913_LDO5_VOLTAGE, + TI65913_LDO6_CTRL, + TI65913_LDO6_VOLTAGE, + TI65913_LDO7_CTRL, + TI65913_LDO7_VOLTAGE, + TI65913_LDO8_CTRL, + TI65913_LDO8_VOLTAGE, + TI65913_LDO9_CTRL, + TI65913_LDO9_VOLTAGE, + + TI65913_LDOLN_CTRL = 0x62, + TI65913_LDOLN_VOLTAGE = 0x63, + TI65913_LDOUSB_CTRL = 0x64, + TI65913_LDOUSB_VOLTAGE = 0x65, + + TI65913_LDO_CTRL = 0x6A, + TI65913_LDO_PD_CTRL1 = 0x6B, + TI65913_LDO_PD_CTRL2 = 0x6C, + + TI65913_LDO_SHORT_STATUS1 = 0x6D, + TI65913_LDO_SHORT_STATUS2 = 0x6E, }; void pmic_init(unsigned bus); -#endif /* __MAINBOARD_GOOGLE_RUSH_PMIC_H__ */ +#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ */

1 0

New patch to review for coreboot: 653a530 tegra132: Add code to setup chip operations and mem resources.
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8644 -gerrit commit 653a530d6a270519ee0c25fb9a765fadbf7fcbac Author: Tom Warren <twarren(a)nvidia.com> Date: Tue Jul 15 10:34:19 2014 -0700 tegra132: Add code to setup chip operations and mem resources. With this memory resource, the payload loading code should be able to create a bounce buffer and load the payload successfully. Adapted from tegra124 soc.c BUG=None BRANCH=None TEST=Built and booted to ramstage on rush. Original-Change-Id: I2e336ce93c1b0236104e63d3785f0e3d7d76bb01 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208121 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 20765da0b15ee8c35a5bbfe532331fc6b1cef502) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I267ced473ad0773b52f889dfa83c65562444c01f --- src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/soc.c | 81 ++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 0ab95d4..f8d4a4c 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += cbfs.c ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += clock.c +ramstage-y += soc.c ramstage-y += spi.c ramstage-y += i2c.c ramstage-y += dma.c diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c new file mode 100644 index 0000000..3a419bc --- /dev/null +++ b/src/soc/nvidia/tegra132/soc.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/addressmap.h> + +static void soc_read_resources(device_t dev) +{ + unsigned long index = 0; + int i; uintptr_t begin, end; + size_t size; + + printk(BIOS_DEBUG, "%s: entry, device = %p\n", __func__, dev); + for (i = 0; i < CARVEOUT_NUM; i++) { + carveout_range(i, &begin, &size); + if (size == 0) + continue; + reserved_ram_resource(dev, index++, begin * KiB, size * KiB); + } + + /* + * TODO: Frame buffer needs to handled as a carveout from the below_4G + * uintptr_t framebuffer_begin = framebuffer_attributes(&framebuffer_size); + */ + + + memory_in_range_below_4gb(&begin, &end); + size = end - begin; + ram_resource(dev, index++, begin * KiB, size * KiB); + + memory_in_range_above_4gb(&begin, &end); + size = end - begin; + ram_resource(dev, index++, begin * KiB, size * KiB); +} + +static void soc_init(device_t dev) +{ + printk(BIOS_INFO, "CPU: Tegra132\n"); +} + +static void soc_noop(device_t dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .set_resources = soc_noop, + .enable_resources = soc_noop, + .init = soc_init, + .scan_bus = 0, +}; + +static void enable_tegra132_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_nvidia_tegra132_ops = { + CHIP_NAME("SOC Nvidia Tegra132") + .enable_dev = enable_tegra132_dev, +};

1 0

New patch to review for coreboot: 3935bd2 ryu: Add support for full LPDDR3 SDRAM BCT init via BootROM
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8643 -gerrit commit 3935bd2af7f24290e549391163392aaa810c8f43 Author: Tom Warren <twarren(a)nvidia.com> Date: Wed Jul 16 09:03:45 2014 -0700 ryu: Add support for full LPDDR3 SDRAM BCT init via BootROM Once LPDDR3 init is supported in the ryu romstage, this can be reverted. Note that this 528MHz BCT has been pre-qualed by NVIDIA AE's, but will be updated as more tuning is done. BUG=none BRANCH=none TEST=Builds, BCT is in binary, but I have no HW here to test on Original-Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208384 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 660e40cb473d47ce763e79d6061367bf381a1c48) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I29ad31fc83f45ca8f92809a7dc252cf984c8c6fe --- src/mainboard/google/rush_ryu/bct/Makefile.inc | 4 +- .../rush_ryu/bct/sdram-ryu-4GB-528-Micron-full.cfg | 1388 ++++++++++++++++++++ src/soc/nvidia/tegra132/Kconfig | 6 + src/soc/nvidia/tegra132/romstage.c | 6 +- 4 files changed, 1402 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/rush_ryu/bct/Makefile.inc b/src/mainboard/google/rush_ryu/bct/Makefile.inc index e274fa3..09aa562 100644 --- a/src/mainboard/google/rush_ryu/bct/Makefile.inc +++ b/src/mainboard/google/rush_ryu/bct/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2013 Google Inc. +## Copyright 2014 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -21,6 +21,8 @@ bct-cfg-$(CONFIG_RUSH_RYU_BCT_CFG_EMMC) += emmc.cfg bct-cfg-$(CONFIG_RUSH_RYU_BCT_CFG_SPI) += spi.cfg bct-cfg-y += odmdata.cfg bct-cfg-y += jtag.cfg +#NOTE: When full LPDDR3 SDRAM config is done in bootblock, remove this +bct-cfg-$(CONFIG_BOOTROM_SDRAM_INIT) += sdram-ryu-4GB-528-Micron-full.cfg # Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate # the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg". diff --git a/src/mainboard/google/rush_ryu/bct/sdram-ryu-4GB-528-Micron-full.cfg b/src/mainboard/google/rush_ryu/bct/sdram-ryu-4GB-528-Micron-full.cfg new file mode 100644 index 0000000..fb137c1 --- /dev/null +++ b/src/mainboard/google/rush_ryu/bct/sdram-ryu-4GB-528-Micron-full.cfg @@ -0,0 +1,1388 @@ +# CFG Version 01 Samsung K4E6E304EE-EGCF (using Micron part) +# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command: +# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_528MHz_emc_reg.txt 1.89394 +# -o A44_64_528_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6 +# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.89 ns (528.00 MHz) +# bkv file: A44_528MHz_emc_reg.txt +SDRAM[0].MemoryType = NvBootMemoryType_LpDdr2; +SDRAM[0].PllMInputDivider = 0x00000001; +SDRAM[0].PllMFeedbackDivider = 0x0000002c; +SDRAM[0].PllMStableTime = 0x0000012c; +SDRAM[0].PllMSetupControl = 0x00000000; +SDRAM[0].PllMSelectDiv2 = 0x00000000; +SDRAM[0].PllMPDLshiftPh45 = 0x00000001; +SDRAM[0].PllMPDLshiftPh90 = 0x00000001; +SDRAM[0].PllMPDLshiftPh135 = 0x00000001; +SDRAM[0].PllMKCP = 0x00000000; +SDRAM[0].PllMKVCO = 0x00000000; +SDRAM[0].EmcBctSpare0 = 0x00000000; +SDRAM[0].EmcBctSpare1 = 0x00000000; +SDRAM[0].EmcBctSpare2 = 0x00000000; +SDRAM[0].EmcBctSpare3 = 0x00000000; +SDRAM[0].EmcBctSpare4 = 0x00000000; +SDRAM[0].EmcBctSpare5 = 0x00000000; +SDRAM[0].EmcBctSpare6 = 0x00000000; +SDRAM[0].EmcBctSpare7 = 0x00000000; +SDRAM[0].EmcBctSpare8 = 0x00000000; +SDRAM[0].EmcBctSpare9 = 0x00000000; +SDRAM[0].EmcBctSpare10 = 0x00000000; +SDRAM[0].EmcBctSpare11 = 0x00000000; +SDRAM[0].EmcClockSource = 0x80000000; +SDRAM[0].EmcAutoCalInterval = 0x001fffff; +SDRAM[0].EmcAutoCalConfig = 0xa1430000; +SDRAM[0].EmcAutoCalConfig2 = 0x00000000; +SDRAM[0].EmcAutoCalConfig3 = 0x00000000; +SDRAM[0].EmcAutoCalWait = 0x00000190; +SDRAM[0].EmcAdrCfg = 0x00000001; +SDRAM[0].EmcPinProgramWait = 0x00000000; +SDRAM[0].EmcPinExtraWait = 0x00000000; +SDRAM[0].EmcTimingControlWait = 0x00000000; +SDRAM[0].EmcRc = 0x0000001f; +SDRAM[0].EmcRfc = 0x00000044; +SDRAM[0].EmcRfcSlr = 0x00000000; +SDRAM[0].EmcRas = 0x00000016; +SDRAM[0].EmcRp = 0x00000009; +SDRAM[0].EmcR2r = 0x00000000; +SDRAM[0].EmcW2w = 0x00000000; +SDRAM[0].EmcR2w = 0x0000000a; +SDRAM[0].EmcW2r = 0x00000009; +SDRAM[0].EmcR2p = 0x00000003; +SDRAM[0].EmcW2p = 0x0000000d; +SDRAM[0].EmcRdRcd = 0x00000009; +SDRAM[0].EmcWrRcd = 0x00000009; +SDRAM[0].EmcRrd = 0x00000005; +SDRAM[0].EmcRext = 0x00000004; +SDRAM[0].EmcWext = 0x00000000; +SDRAM[0].EmcWdv = 0x00000002; +SDRAM[0].EmcWdvMask = 0x00000002; +SDRAM[0].EmcQUse = 0x00000008; +SDRAM[0].EmcQuseWidth = 0x00000003; +SDRAM[0].EmcIbdly = 0x00000000; +SDRAM[0].EmcEInput = 0x00000003; +SDRAM[0].EmcEInputDuration = 0x0000000a; +SDRAM[0].EmcPutermExtra = 0x00050000; +SDRAM[0].EmcPutermWidth = 0x00000004; +SDRAM[0].EmcPutermAdj = 0x00000000; +SDRAM[0].EmcCdbCntl1 = 0x00000000; +SDRAM[0].EmcCdbCntl2 = 0x00000000; +SDRAM[0].EmcCdbCntl3 = 0x00000000; +SDRAM[0].EmcQRst = 0x00000002; +SDRAM[0].EmcQSafe = 0x00000011; +SDRAM[0].EmcRdv = 0x00000015; +SDRAM[0].EmcRdvMask = 0x00000017; +SDRAM[0].EmcQpop = 0x0000000d; +SDRAM[0].EmcCtt = 0x00000000; +SDRAM[0].EmcCttDuration = 0x00000004; +SDRAM[0].EmcRefresh = 0x000007cd; +SDRAM[0].EmcBurstRefreshNum = 0x00000000; +SDRAM[0].EmcPreRefreshReqCnt = 0x000001f3; +SDRAM[0].EmcPdEx2Wr = 0x00000003; +SDRAM[0].EmcPdEx2Rd = 0x00000003; +SDRAM[0].EmcPChg2Pden = 0x00000009; +SDRAM[0].EmcAct2Pden = 0x00000000; +SDRAM[0].EmcAr2Pden = 0x00000001; +SDRAM[0].EmcRw2Pden = 0x00000011; +SDRAM[0].EmcTxsr = 0x0000004a; +SDRAM[0].EmcTxsrDll = 0x0000004a; +SDRAM[0].EmcTcke = 0x00000004; +SDRAM[0].EmcTckesr = 0x00000008; +SDRAM[0].EmcTpd = 0x00000004; +SDRAM[0].EmcTfaw = 0x00000019; +SDRAM[0].EmcTrpab = 0x0000000c; +SDRAM[0].EmcTClkStable = 0x00000003; +SDRAM[0].EmcTClkStop = 0x00000003; +SDRAM[0].EmcTRefBw = 0x00000895; +SDRAM[0].EmcFbioCfg5 = 0x1363a096; +SDRAM[0].EmcFbioCfg6 = 0x00000000; +SDRAM[0].EmcFbioSpare = 0x00000000; +SDRAM[0].EmcCfgRsv = 0xff00ff00; +SDRAM[0].EmcMrs = 0x00000000; +SDRAM[0].EmcEmrs = 0x00000000; +SDRAM[0].EmcEmrs2 = 0x00000000; +SDRAM[0].EmcEmrs3 = 0x00000000; +SDRAM[0].EmcMrw1 = 0x000100c3; +SDRAM[0].EmcMrw2 = 0x00020006; +SDRAM[0].EmcMrw3 = 0x00030001; +SDRAM[0].EmcMrw4 = 0x800b0000; +SDRAM[0].EmcMrwExtra = 0x000100c3; +SDRAM[0].EmcWarmBootMrwExtra = 0x00020006; +SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; +SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; +SDRAM[0].EmcMrwResetCommand = 0x003f00fc; +SDRAM[0].EmcMrwResetNInitWait = 0x0000000a; +SDRAM[0].EmcMrsWaitCnt = 0x02100013; +SDRAM[0].EmcMrsWaitCnt2 = 0x02100013; +SDRAM[0].EmcCfg = 0xf3300000; +SDRAM[0].EmcCfg2 = 0x0000089f; +SDRAM[0].EmcCfgPipe = 0x000042a0; +SDRAM[0].EmcDbg = 0x01000c00; +SDRAM[0].EmcCmdQ = 0x10004408; +SDRAM[0].EmcMc2EmcQ = 0x06000404; +SDRAM[0].EmcDynSelfRefControl = 0x800010b3; +SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; +SDRAM[0].EmcCfgDigDll = 0xe01200b9; +SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; +SDRAM[0].EmcDevSelect = 0x00000000; +SDRAM[0].EmcSelDpdCtrl = 0x0004001c; +SDRAM[0].EmcDllXformDqs0 = 0x007f400a; +SDRAM[0].EmcDllXformDqs1 = 0x007f400a; +SDRAM[0].EmcDllXformDqs2 = 0x007f400a; +SDRAM[0].EmcDllXformDqs3 = 0x007f400a; +SDRAM[0].EmcDllXformDqs4 = 0x007f400a; +SDRAM[0].EmcDllXformDqs5 = 0x007f400a; +SDRAM[0].EmcDllXformDqs6 = 0x007f400a; +SDRAM[0].EmcDllXformDqs7 = 0x007f400a; +SDRAM[0].EmcDllXformDqs8 = 0x007f400a; +SDRAM[0].EmcDllXformDqs9 = 0x007f400a; +SDRAM[0].EmcDllXformDqs10 = 0x007f400a; +SDRAM[0].EmcDllXformDqs11 = 0x007f400a; +SDRAM[0].EmcDllXformDqs12 = 0x007f400a; +SDRAM[0].EmcDllXformDqs13 = 0x007f400a; +SDRAM[0].EmcDllXformDqs14 = 0x007f400a; +SDRAM[0].EmcDllXformDqs15 = 0x007f400a; +SDRAM[0].EmcDllXformQUse0 = 0x00000000; +SDRAM[0].EmcDllXformQUse1 = 0x00000000; +SDRAM[0].EmcDllXformQUse2 = 0x00000000; +SDRAM[0].EmcDllXformQUse3 = 0x00000000; +SDRAM[0].EmcDllXformQUse4 = 0x00000000; +SDRAM[0].EmcDllXformQUse5 = 0x00000000; +SDRAM[0].EmcDllXformQUse6 = 0x00000000; +SDRAM[0].EmcDllXformQUse7 = 0x00000000; +SDRAM[0].EmcDllXformAddr0 = 0x00024000; +SDRAM[0].EmcDllXformAddr1 = 0x00024000; +SDRAM[0].EmcDllXformAddr2 = 0x00000006; +SDRAM[0].EmcDllXformAddr3 = 0x00024000; +SDRAM[0].EmcDllXformAddr4 = 0x00024000; +SDRAM[0].EmcDllXformAddr5 = 0x00000006; +SDRAM[0].EmcDllXformQUse8 = 0x00000000; +SDRAM[0].EmcDllXformQUse9 = 0x00000000; +SDRAM[0].EmcDllXformQUse10 = 0x00000000; +SDRAM[0].EmcDllXformQUse11 = 0x00000000; +SDRAM[0].EmcDllXformQUse12 = 0x00000000; +SDRAM[0].EmcDllXformQUse13 = 0x00000000; +SDRAM[0].EmcDllXformQUse14 = 0x00000000; +SDRAM[0].EmcDllXformQUse15 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs0 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs1 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs2 = 0x00000008; +SDRAM[0].EmcDliTrimTxDqs3 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs4 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs5 = 0x00000008; +SDRAM[0].EmcDliTrimTxDqs6 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs7 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs8 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs9 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs10 = 0x00000008; +SDRAM[0].EmcDliTrimTxDqs11 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs12 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs13 = 0x00000008; +SDRAM[0].EmcDliTrimTxDqs14 = 0x0000000b; +SDRAM[0].EmcDliTrimTxDqs15 = 0x0000000b; +SDRAM[0].EmcDllXformDq0 = 0x0000000c; +SDRAM[0].EmcDllXformDq1 = 0x0000000c; +SDRAM[0].EmcDllXformDq2 = 0x0000000c; +SDRAM[0].EmcDllXformDq3 = 0x0000000c; +SDRAM[0].EmcDllXformDq4 = 0x0000000c; +SDRAM[0].EmcDllXformDq5 = 0x0000000c; +SDRAM[0].EmcDllXformDq6 = 0x0000000c; +SDRAM[0].EmcDllXformDq7 = 0x0000000c; +SDRAM[0].WarmBootWait = 0x00000001; +SDRAM[0].EmcCttTermCtrl = 0x00000802; +SDRAM[0].EmcOdtWrite = 0x00000000; +SDRAM[0].EmcOdtRead = 0x00000000; +SDRAM[0].EmcZcalInterval = 0x00064000; +SDRAM[0].EmcZcalWaitCnt = 0x00000034; +SDRAM[0].EmcZcalMrwCmd = 0x000a0056; +SDRAM[0].EmcMrsResetDll = 0x00000000; +SDRAM[0].EmcZcalInitDev0 = 0x840a00ff; +SDRAM[0].EmcZcalInitDev1 = 0x440a00ff; +SDRAM[0].EmcZcalInitWait = 0x00000001; +SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; +SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; +SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; +SDRAM[0].EmcZcalWarmBootWait = 0x00000001; +SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; +SDRAM[0].EmcMrsResetDllWait = 0x00000000; +SDRAM[0].EmcMrsExtra = 0x00000000; +SDRAM[0].EmcWarmBootMrsExtra = 0x00000000; +SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; +SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; +SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; +SDRAM[0].EmcDdr2Wait = 0x00000000; +SDRAM[0].EmcClkenOverride = 0x00000000; +SDRAM[0].McDisExtraSnapLevels = 0x00000000; +SDRAM[0].EmcExtraRefreshNum = 0x00000002; +SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; +SDRAM[0].PmcVddpSel = 0x00000001; +SDRAM[0].PmcVddpSelWait = 0x00000002; +SDRAM[0].PmcDdrPwr = 0x00000003; +SDRAM[0].PmcDdrCfg = 0x00001000; +SDRAM[0].PmcIoDpd3Req = 0x4ffefef7; +SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; +SDRAM[0].PmcRegShort = 0x0000330f; +SDRAM[0].PmcNoIoPower = 0x00000000; +SDRAM[0].PmcPorDpdCtrlWait = 0x00000001; +SDRAM[0].EmcXm2CmdPadCtrl = 0x00000220; +SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; +SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; +SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; +SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00100100; +SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; +SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0123123d; +SDRAM[0].EmcXm2DqsPadCtrl3 = 0x51451420; +SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514; +SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514; +SDRAM[0].EmcXm2DqsPadCtrl6 = 0x51451400; +SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; +SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; +SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; +SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc004; +SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000000; +SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f008; +SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070000; +SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x0000003f; +SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x015ddddd; +SDRAM[0].EmcAcpdControl = 0x00000000; +SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00001032; +SDRAM[0].EmcSwizzleRank0Byte0 = 0x53067142; +SDRAM[0].EmcSwizzleRank0Byte1 = 0x73025146; +SDRAM[0].EmcSwizzleRank0Byte2 = 0x20136475; +SDRAM[0].EmcSwizzleRank0Byte3 = 0x46273150; +SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003210; +SDRAM[0].EmcSwizzleRank1Byte0 = 0x73451026; +SDRAM[0].EmcSwizzleRank1Byte1 = 0x73025146; +SDRAM[0].EmcSwizzleRank1Byte2 = 0x20641735; +SDRAM[0].EmcSwizzleRank1Byte3 = 0x42136075; +SDRAM[0].EmcDsrVttgenDrv = 0x0000003f; +SDRAM[0].EmcTxdsrvttgen = 0x00000000; +SDRAM[0].EmcBgbiasCtl0 = 0x00000000; +SDRAM[0].McEmemAdrCfg = 0x00000001; +SDRAM[0].McEmemAdrCfgDev0 = 0x00080304; +SDRAM[0].McEmemAdrCfgDev1 = 0x00080304; +SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; +SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; +SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; +SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; +SDRAM[0].McEmemCfg = 0x00001000; +SDRAM[0].McEmemArbCfg = 0x0f000007; +SDRAM[0].McEmemArbOutstandingReq = 0x80000040; +SDRAM[0].McEmemArbTimingRcd = 0x00000003; +SDRAM[0].McEmemArbTimingRp = 0x00000004; +SDRAM[0].McEmemArbTimingRc = 0x00000010; +SDRAM[0].McEmemArbTimingRas = 0x0000000a; +SDRAM[0].McEmemArbTimingFaw = 0x0000000d; +SDRAM[0].McEmemArbTimingRrd = 0x00000002; +SDRAM[0].McEmemArbTimingRap2Pre = 0x00000002; +SDRAM[0].McEmemArbTimingWap2Pre = 0x00000009; +SDRAM[0].McEmemArbTimingR2R = 0x00000003; +SDRAM[0].McEmemArbTimingW2W = 0x00000001; +SDRAM[0].McEmemArbTimingR2W = 0x00000006; +SDRAM[0].McEmemArbTimingW2R = 0x00000006; +SDRAM[0].McEmemArbDaTurns = 0x06060103; +SDRAM[0].McEmemArbDaCovers = 0x00120b10; +SDRAM[0].McEmemArbMisc0 = 0x71c81811; +SDRAM[0].McEmemArbMisc1 = 0x70000f03; +SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; +SDRAM[0].McEmemArbOverride = 0x10000000; +SDRAM[0].McEmemArbOverride1 = 0x00000000; +SDRAM[0].McEmemArbRsv = 0xff00ff00; +SDRAM[0].McClkenOverride = 0x00000000; +SDRAM[0].McStatControl = 0x00000000; +SDRAM[0].McDisplaySnapRing = 0x00000003; +SDRAM[0].McVideoProtectBom = 0xfff00000; +SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; +SDRAM[0].McVideoProtectSizeMb = 0x00000000; +SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; +SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; +SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; +SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; +SDRAM[0].McSecCarveoutBom = 0xfff00000; +SDRAM[0].McSecCarveoutAdrHi = 0x00000000; +SDRAM[0].McSecCarveoutSizeMb = 0x00000000; +SDRAM[0].McVideoProtectWriteAccess = 0x00000000; +SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; +SDRAM[0].EmcCaTrainingEnable = 0x00000001; +SDRAM[0].EmcCaTrainingTimingCntl1 = 0x09257359; +SDRAM[0].EmcCaTrainingTimingCntl2 = 0x00000017; +SDRAM[0].SwizzleRankByteEncode = 0x00000008; +SDRAM[0].BootRomPatchControl = 0x00000000; +SDRAM[0].BootRomPatchData = 0x00000000; +SDRAM[0].McMtsCarveoutBom = 0x78000000; +SDRAM[0].McMtsCarveoutAdrHi = 0x00000001; +SDRAM[0].McMtsCarveoutSizeMb = 0x00000080; +SDRAM[0].McMtsCarveoutRegCtrl = 0x00000001; +#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000000d; +#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000000fd; +#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00c10038; +#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00c10038; +#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00c1003c; +#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00c10090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00c10041; +#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00c10090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00c10041; +#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; +#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00c10080; +#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080021; +#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000c1; +#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00c10026; +#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00c1001a; +#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00c10024; +#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00c10029; +#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000c1; +#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; +#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; +#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00c10065; +#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00c1002a; + + +# CFG Version 01 Hynix H9CCNNNBLTALAR-NUD (using Micron part) +# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command: +# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_528MHz_emc_reg.txt 1.89394 +# -o A44_64_528_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6 +# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.89 ns (528.00 MHz) +# bkv file: A44_528MHz_emc_reg.txt +SDRAM[1].MemoryType = NvBootMemoryType_LpDdr2; +SDRAM[1].PllMInputDivider = 0x00000001; +SDRAM[1].PllMFeedbackDivider = 0x0000002c; +SDRAM[1].PllMStableTime = 0x0000012c; +SDRAM[1].PllMSetupControl = 0x00000000; +SDRAM[1].PllMSelectDiv2 = 0x00000000; +SDRAM[1].PllMPDLshiftPh45 = 0x00000001; +SDRAM[1].PllMPDLshiftPh90 = 0x00000001; +SDRAM[1].PllMPDLshiftPh135 = 0x00000001; +SDRAM[1].PllMKCP = 0x00000000; +SDRAM[1].PllMKVCO = 0x00000000; +SDRAM[1].EmcBctSpare0 = 0x00000000; +SDRAM[1].EmcBctSpare1 = 0x00000000; +SDRAM[1].EmcBctSpare2 = 0x00000000; +SDRAM[1].EmcBctSpare3 = 0x00000000; +SDRAM[1].EmcBctSpare4 = 0x00000000; +SDRAM[1].EmcBctSpare5 = 0x00000000; +SDRAM[1].EmcBctSpare6 = 0x00000000; +SDRAM[1].EmcBctSpare7 = 0x00000000; +SDRAM[1].EmcBctSpare8 = 0x00000000; +SDRAM[1].EmcBctSpare9 = 0x00000000; +SDRAM[1].EmcBctSpare10 = 0x00000000; +SDRAM[1].EmcBctSpare11 = 0x00000000; +SDRAM[1].EmcClockSource = 0x80000000; +SDRAM[1].EmcAutoCalInterval = 0x001fffff; +SDRAM[1].EmcAutoCalConfig = 0xa1430000; +SDRAM[1].EmcAutoCalConfig2 = 0x00000000; +SDRAM[1].EmcAutoCalConfig3 = 0x00000000; +SDRAM[1].EmcAutoCalWait = 0x00000190; +SDRAM[1].EmcAdrCfg = 0x00000001; +SDRAM[1].EmcPinProgramWait = 0x00000000; +SDRAM[1].EmcPinExtraWait = 0x00000000; +SDRAM[1].EmcTimingControlWait = 0x00000000; +SDRAM[1].EmcRc = 0x0000001f; +SDRAM[1].EmcRfc = 0x00000044; +SDRAM[1].EmcRfcSlr = 0x00000000; +SDRAM[1].EmcRas = 0x00000016; +SDRAM[1].EmcRp = 0x00000009; +SDRAM[1].EmcR2r = 0x00000000; +SDRAM[1].EmcW2w = 0x00000000; +SDRAM[1].EmcR2w = 0x0000000a; +SDRAM[1].EmcW2r = 0x00000009; +SDRAM[1].EmcR2p = 0x00000003; +SDRAM[1].EmcW2p = 0x0000000d; +SDRAM[1].EmcRdRcd = 0x00000009; +SDRAM[1].EmcWrRcd = 0x00000009; +SDRAM[1].EmcRrd = 0x00000005; +SDRAM[1].EmcRext = 0x00000004; +SDRAM[1].EmcWext = 0x00000000; +SDRAM[1].EmcWdv = 0x00000002; +SDRAM[1].EmcWdvMask = 0x00000002; +SDRAM[1].EmcQUse = 0x00000008; +SDRAM[1].EmcQuseWidth = 0x00000003; +SDRAM[1].EmcIbdly = 0x00000000; +SDRAM[1].EmcEInput = 0x00000003; +SDRAM[1].EmcEInputDuration = 0x0000000a; +SDRAM[1].EmcPutermExtra = 0x00050000; +SDRAM[1].EmcPutermWidth = 0x00000004; +SDRAM[1].EmcPutermAdj = 0x00000000; +SDRAM[1].EmcCdbCntl1 = 0x00000000; +SDRAM[1].EmcCdbCntl2 = 0x00000000; +SDRAM[1].EmcCdbCntl3 = 0x00000000; +SDRAM[1].EmcQRst = 0x00000002; +SDRAM[1].EmcQSafe = 0x00000011; +SDRAM[1].EmcRdv = 0x00000015; +SDRAM[1].EmcRdvMask = 0x00000017; +SDRAM[1].EmcQpop = 0x0000000d; +SDRAM[1].EmcCtt = 0x00000000; +SDRAM[1].EmcCttDuration = 0x00000004; +SDRAM[1].EmcRefresh = 0x000007cd; +SDRAM[1].EmcBurstRefreshNum = 0x00000000; +SDRAM[1].EmcPreRefreshReqCnt = 0x000001f3; +SDRAM[1].EmcPdEx2Wr = 0x00000003; +SDRAM[1].EmcPdEx2Rd = 0x00000003; +SDRAM[1].EmcPChg2Pden = 0x00000009; +SDRAM[1].EmcAct2Pden = 0x00000000; +SDRAM[1].EmcAr2Pden = 0x00000001; +SDRAM[1].EmcRw2Pden = 0x00000011; +SDRAM[1].EmcTxsr = 0x0000004a; +SDRAM[1].EmcTxsrDll = 0x0000004a; +SDRAM[1].EmcTcke = 0x00000004; +SDRAM[1].EmcTckesr = 0x00000008; +SDRAM[1].EmcTpd = 0x00000004; +SDRAM[1].EmcTfaw = 0x00000019; +SDRAM[1].EmcTrpab = 0x0000000c; +SDRAM[1].EmcTClkStable = 0x00000003; +SDRAM[1].EmcTClkStop = 0x00000003; +SDRAM[1].EmcTRefBw = 0x00000895; +SDRAM[1].EmcFbioCfg5 = 0x1363a096; +SDRAM[1].EmcFbioCfg6 = 0x00000000; +SDRAM[1].EmcFbioSpare = 0x00000000; +SDRAM[1].EmcCfgRsv = 0xff00ff00; +SDRAM[1].EmcMrs = 0x00000000; +SDRAM[1].EmcEmrs = 0x00000000; +SDRAM[1].EmcEmrs2 = 0x00000000; +SDRAM[1].EmcEmrs3 = 0x00000000; +SDRAM[1].EmcMrw1 = 0x000100c3; +SDRAM[1].EmcMrw2 = 0x00020006; +SDRAM[1].EmcMrw3 = 0x00030001; +SDRAM[1].EmcMrw4 = 0x800b0000; +SDRAM[1].EmcMrwExtra = 0x000100c3; +SDRAM[1].EmcWarmBootMrwExtra = 0x00020006; +SDRAM[1].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; +SDRAM[1].EmcExtraModeRegWriteEnable = 0x00000000; +SDRAM[1].EmcMrwResetCommand = 0x003f00fc; +SDRAM[1].EmcMrwResetNInitWait = 0x0000000a; +SDRAM[1].EmcMrsWaitCnt = 0x02100013; +SDRAM[1].EmcMrsWaitCnt2 = 0x02100013; +SDRAM[1].EmcCfg = 0xf3300000; +SDRAM[1].EmcCfg2 = 0x0000089f; +SDRAM[1].EmcCfgPipe = 0x000042a0; +SDRAM[1].EmcDbg = 0x01000c00; +SDRAM[1].EmcCmdQ = 0x10004408; +SDRAM[1].EmcMc2EmcQ = 0x06000404; +SDRAM[1].EmcDynSelfRefControl = 0x800010b3; +SDRAM[1].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; +SDRAM[1].EmcCfgDigDll = 0xe01200b9; +SDRAM[1].EmcCfgDigDllPeriod = 0x00008000; +SDRAM[1].EmcDevSelect = 0x00000000; +SDRAM[1].EmcSelDpdCtrl = 0x0004001c; +SDRAM[1].EmcDllXformDqs0 = 0x007f400a; +SDRAM[1].EmcDllXformDqs1 = 0x007f400a; +SDRAM[1].EmcDllXformDqs2 = 0x007f400a; +SDRAM[1].EmcDllXformDqs3 = 0x007f400a; +SDRAM[1].EmcDllXformDqs4 = 0x007f400a; +SDRAM[1].EmcDllXformDqs5 = 0x007f400a; +SDRAM[1].EmcDllXformDqs6 = 0x007f400a; +SDRAM[1].EmcDllXformDqs7 = 0x007f400a; +SDRAM[1].EmcDllXformDqs8 = 0x007f400a; +SDRAM[1].EmcDllXformDqs9 = 0x007f400a; +SDRAM[1].EmcDllXformDqs10 = 0x007f400a; +SDRAM[1].EmcDllXformDqs11 = 0x007f400a; +SDRAM[1].EmcDllXformDqs12 = 0x007f400a; +SDRAM[1].EmcDllXformDqs13 = 0x007f400a; +SDRAM[1].EmcDllXformDqs14 = 0x007f400a; +SDRAM[1].EmcDllXformDqs15 = 0x007f400a; +SDRAM[1].EmcDllXformQUse0 = 0x00000000; +SDRAM[1].EmcDllXformQUse1 = 0x00000000; +SDRAM[1].EmcDllXformQUse2 = 0x00000000; +SDRAM[1].EmcDllXformQUse3 = 0x00000000; +SDRAM[1].EmcDllXformQUse4 = 0x00000000; +SDRAM[1].EmcDllXformQUse5 = 0x00000000; +SDRAM[1].EmcDllXformQUse6 = 0x00000000; +SDRAM[1].EmcDllXformQUse7 = 0x00000000; +SDRAM[1].EmcDllXformAddr0 = 0x00024000; +SDRAM[1].EmcDllXformAddr1 = 0x00024000; +SDRAM[1].EmcDllXformAddr2 = 0x00000006; +SDRAM[1].EmcDllXformAddr3 = 0x00024000; +SDRAM[1].EmcDllXformAddr4 = 0x00024000; +SDRAM[1].EmcDllXformAddr5 = 0x00000006; +SDRAM[1].EmcDllXformQUse8 = 0x00000000; +SDRAM[1].EmcDllXformQUse9 = 0x00000000; +SDRAM[1].EmcDllXformQUse10 = 0x00000000; +SDRAM[1].EmcDllXformQUse11 = 0x00000000; +SDRAM[1].EmcDllXformQUse12 = 0x00000000; +SDRAM[1].EmcDllXformQUse13 = 0x00000000; +SDRAM[1].EmcDllXformQUse14 = 0x00000000; +SDRAM[1].EmcDllXformQUse15 = 0x00000000; +SDRAM[1].EmcDliTrimTxDqs0 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs1 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs2 = 0x00000008; +SDRAM[1].EmcDliTrimTxDqs3 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs4 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs5 = 0x00000008; +SDRAM[1].EmcDliTrimTxDqs6 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs7 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs8 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs9 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs10 = 0x00000008; +SDRAM[1].EmcDliTrimTxDqs11 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs12 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs13 = 0x00000008; +SDRAM[1].EmcDliTrimTxDqs14 = 0x0000000b; +SDRAM[1].EmcDliTrimTxDqs15 = 0x0000000b; +SDRAM[1].EmcDllXformDq0 = 0x0000000c; +SDRAM[1].EmcDllXformDq1 = 0x0000000c; +SDRAM[1].EmcDllXformDq2 = 0x0000000c; +SDRAM[1].EmcDllXformDq3 = 0x0000000c; +SDRAM[1].EmcDllXformDq4 = 0x0000000c; +SDRAM[1].EmcDllXformDq5 = 0x0000000c; +SDRAM[1].EmcDllXformDq6 = 0x0000000c; +SDRAM[1].EmcDllXformDq7 = 0x0000000c; +SDRAM[1].WarmBootWait = 0x00000001; +SDRAM[1].EmcCttTermCtrl = 0x00000802; +SDRAM[1].EmcOdtWrite = 0x00000000; +SDRAM[1].EmcOdtRead = 0x00000000; +SDRAM[1].EmcZcalInterval = 0x00064000; +SDRAM[1].EmcZcalWaitCnt = 0x00000034; +SDRAM[1].EmcZcalMrwCmd = 0x000a0056; +SDRAM[1].EmcMrsResetDll = 0x00000000; +SDRAM[1].EmcZcalInitDev0 = 0x840a00ff; +SDRAM[1].EmcZcalInitDev1 = 0x440a00ff; +SDRAM[1].EmcZcalInitWait = 0x00000001; +SDRAM[1].EmcZcalWarmColdBootEnables = 0x00000003; +SDRAM[1].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; +SDRAM[1].EmcZqCalDdr3WarmBoot = 0x00000000; +SDRAM[1].EmcZcalWarmBootWait = 0x00000001; +SDRAM[1].EmcMrsWarmBootEnable = 0x00000001; +SDRAM[1].EmcMrsResetDllWait = 0x00000000; +SDRAM[1].EmcMrsExtra = 0x00000000; +SDRAM[1].EmcWarmBootMrsExtra = 0x00000000; +SDRAM[1].EmcEmrsDdr2DllEnable = 0x00000000; +SDRAM[1].EmcMrsDdr2DllReset = 0x00000000; +SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00000000; +SDRAM[1].EmcDdr2Wait = 0x00000000; +SDRAM[1].EmcClkenOverride = 0x00000000; +SDRAM[1].McDisExtraSnapLevels = 0x00000000; +SDRAM[1].EmcExtraRefreshNum = 0x00000002; +SDRAM[1].EmcClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[1].McClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[1].EmcCfgDigDllPeriodWarmBoot = 0x00000003; +SDRAM[1].PmcVddpSel = 0x00000001; +SDRAM[1].PmcVddpSelWait = 0x00000002; +SDRAM[1].PmcDdrPwr = 0x00000003; +SDRAM[1].PmcDdrCfg = 0x00001000; +SDRAM[1].PmcIoDpd3Req = 0x4ffefef7; +SDRAM[1].PmcIoDpd3ReqWait = 0x00000000; +SDRAM[1].PmcRegShort = 0x0000330f; +SDRAM[1].PmcNoIoPower = 0x00000000; +SDRAM[1].PmcPorDpdCtrlWait = 0x00000001; +SDRAM[1].EmcXm2CmdPadCtrl = 0x00000220; +SDRAM[1].EmcXm2CmdPadCtrl2 = 0x770c0000; +SDRAM[1].EmcXm2CmdPadCtrl3 = 0x050c0000; +SDRAM[1].EmcXm2CmdPadCtrl4 = 0x00000000; +SDRAM[1].EmcXm2CmdPadCtrl5 = 0x00100100; +SDRAM[1].EmcXm2DqsPadCtrl = 0x770c1414; +SDRAM[1].EmcXm2DqsPadCtrl2 = 0x0123123d; +SDRAM[1].EmcXm2DqsPadCtrl3 = 0x51451420; +SDRAM[1].EmcXm2DqsPadCtrl4 = 0x00514514; +SDRAM[1].EmcXm2DqsPadCtrl5 = 0x00514514; +SDRAM[1].EmcXm2DqsPadCtrl6 = 0x51451400; +SDRAM[1].EmcXm2DqPadCtrl = 0x770c2990; +SDRAM[1].EmcXm2DqPadCtrl2 = 0x00000000; +SDRAM[1].EmcXm2DqPadCtrl3 = 0x00000000; +SDRAM[1].EmcXm2ClkPadCtrl = 0x77ffc004; +SDRAM[1].EmcXm2ClkPadCtrl2 = 0x00000000; +SDRAM[1].EmcXm2CompPadCtrl = 0x81f1f008; +SDRAM[1].EmcXm2VttGenPadCtrl = 0x07070000; +SDRAM[1].EmcXm2VttGenPadCtrl2 = 0x0000003f; +SDRAM[1].EmcXm2VttGenPadCtrl3 = 0x015ddddd; +SDRAM[1].EmcAcpdControl = 0x00000000; +SDRAM[1].EmcSwizzleRank0ByteCfg = 0x00001032; +SDRAM[1].EmcSwizzleRank0Byte0 = 0x53067142; +SDRAM[1].EmcSwizzleRank0Byte1 = 0x73025146; +SDRAM[1].EmcSwizzleRank0Byte2 = 0x20136475; +SDRAM[1].EmcSwizzleRank0Byte3 = 0x46273150; +SDRAM[1].EmcSwizzleRank1ByteCfg = 0x00003210; +SDRAM[1].EmcSwizzleRank1Byte0 = 0x73451026; +SDRAM[1].EmcSwizzleRank1Byte1 = 0x73025146; +SDRAM[1].EmcSwizzleRank1Byte2 = 0x20641735; +SDRAM[1].EmcSwizzleRank1Byte3 = 0x42136075; +SDRAM[1].EmcDsrVttgenDrv = 0x0000003f; +SDRAM[1].EmcTxdsrvttgen = 0x00000000; +SDRAM[1].EmcBgbiasCtl0 = 0x00000000; +SDRAM[1].McEmemAdrCfg = 0x00000001; +SDRAM[1].McEmemAdrCfgDev0 = 0x00080304; +SDRAM[1].McEmemAdrCfgDev1 = 0x00080304; +SDRAM[1].McEmemAdrCfgBankMask0 = 0x00001248; +SDRAM[1].McEmemAdrCfgBankMask1 = 0x00002490; +SDRAM[1].McEmemAdrCfgBankMask2 = 0x00000920; +SDRAM[1].McEmemAdrCfgBankSwizzle3 = 0x00000001; +SDRAM[1].McEmemCfg = 0x00001000; +SDRAM[1].McEmemArbCfg = 0x0f000007; +SDRAM[1].McEmemArbOutstandingReq = 0x80000040; +SDRAM[1].McEmemArbTimingRcd = 0x00000003; +SDRAM[1].McEmemArbTimingRp = 0x00000004; +SDRAM[1].McEmemArbTimingRc = 0x00000010; +SDRAM[1].McEmemArbTimingRas = 0x0000000a; +SDRAM[1].McEmemArbTimingFaw = 0x0000000d; +SDRAM[1].McEmemArbTimingRrd = 0x00000002; +SDRAM[1].McEmemArbTimingRap2Pre = 0x00000002; +SDRAM[1].McEmemArbTimingWap2Pre = 0x00000009; +SDRAM[1].McEmemArbTimingR2R = 0x00000003; +SDRAM[1].McEmemArbTimingW2W = 0x00000001; +SDRAM[1].McEmemArbTimingR2W = 0x00000006; +SDRAM[1].McEmemArbTimingW2R = 0x00000006; +SDRAM[1].McEmemArbDaTurns = 0x06060103; +SDRAM[1].McEmemArbDaCovers = 0x00120b10; +SDRAM[1].McEmemArbMisc0 = 0x71c81811; +SDRAM[1].McEmemArbMisc1 = 0x70000f03; +SDRAM[1].McEmemArbRing1Throttle = 0x001f0000; +SDRAM[1].McEmemArbOverride = 0x10000000; +SDRAM[1].McEmemArbOverride1 = 0x00000000; +SDRAM[1].McEmemArbRsv = 0xff00ff00; +SDRAM[1].McClkenOverride = 0x00000000; +SDRAM[1].McStatControl = 0x00000000; +SDRAM[1].McDisplaySnapRing = 0x00000003; +SDRAM[1].McVideoProtectBom = 0xfff00000; +SDRAM[1].McVideoProtectBomAdrHi = 0x00000000; +SDRAM[1].McVideoProtectSizeMb = 0x00000000; +SDRAM[1].McVideoProtectVprOverride = 0xe4bac743; +SDRAM[1].McVideoProtectVprOverride1 = 0x00000013; +SDRAM[1].McVideoProtectGpuOverride0 = 0x00000000; +SDRAM[1].McVideoProtectGpuOverride1 = 0x00000000; +SDRAM[1].McSecCarveoutBom = 0xfff00000; +SDRAM[1].McSecCarveoutAdrHi = 0x00000000; +SDRAM[1].McSecCarveoutSizeMb = 0x00000000; +SDRAM[1].McVideoProtectWriteAccess = 0x00000000; +SDRAM[1].McSecCarveoutProtectWriteAccess = 0x00000000; +SDRAM[1].EmcCaTrainingEnable = 0x00000001; +SDRAM[1].EmcCaTrainingTimingCntl1 = 0x09257359; +SDRAM[1].EmcCaTrainingTimingCntl2 = 0x00000017; +SDRAM[1].SwizzleRankByteEncode = 0x00000008; +SDRAM[1].BootRomPatchControl = 0x00000000; +SDRAM[1].BootRomPatchData = 0x00000000; +SDRAM[1].McMtsCarveoutBom = 0x78000000; +SDRAM[1].McMtsCarveoutAdrHi = 0x00000001; +SDRAM[1].McMtsCarveoutSizeMb = 0x00000080; +SDRAM[1].McMtsCarveoutRegCtrl = 0x00000001; +#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000000d; +#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000000fd; +#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00c10038; +#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00c10038; +#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00c1003c; +#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00c10090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00c10041; +#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00c10090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00c10041; +#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; +#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00c10080; +#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080021; +#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000c1; +#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00c10026; +#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00c1001a; +#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00c10024; +#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00c10029; +#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000c1; +#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; +#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; +#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00c10065; +#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00c1002a; + +# CFG Version 01 Micron EDFA232A2MA-JD-F (using Micron part) +# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command: +# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_528MHz_emc_reg.txt 1.89394 +# -o A44_64_528_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6 +# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.89 ns (528.00 MHz) +# bkv file: A44_528MHz_emc_reg.txt +SDRAM[2].MemoryType = NvBootMemoryType_LpDdr2; +SDRAM[2].PllMInputDivider = 0x00000001; +SDRAM[2].PllMFeedbackDivider = 0x0000002c; +SDRAM[2].PllMStableTime = 0x0000012c; +SDRAM[2].PllMSetupControl = 0x00000000; +SDRAM[2].PllMSelectDiv2 = 0x00000000; +SDRAM[2].PllMPDLshiftPh45 = 0x00000001; +SDRAM[2].PllMPDLshiftPh90 = 0x00000001; +SDRAM[2].PllMPDLshiftPh135 = 0x00000001; +SDRAM[2].PllMKCP = 0x00000000; +SDRAM[2].PllMKVCO = 0x00000000; +SDRAM[2].EmcBctSpare0 = 0x00000000; +SDRAM[2].EmcBctSpare1 = 0x00000000; +SDRAM[2].EmcBctSpare2 = 0x00000000; +SDRAM[2].EmcBctSpare3 = 0x00000000; +SDRAM[2].EmcBctSpare4 = 0x00000000; +SDRAM[2].EmcBctSpare5 = 0x00000000; +SDRAM[2].EmcBctSpare6 = 0x00000000; +SDRAM[2].EmcBctSpare7 = 0x00000000; +SDRAM[2].EmcBctSpare8 = 0x00000000; +SDRAM[2].EmcBctSpare9 = 0x00000000; +SDRAM[2].EmcBctSpare10 = 0x00000000; +SDRAM[2].EmcBctSpare11 = 0x00000000; +SDRAM[2].EmcClockSource = 0x80000000; +SDRAM[2].EmcAutoCalInterval = 0x001fffff; +SDRAM[2].EmcAutoCalConfig = 0xa1430000; +SDRAM[2].EmcAutoCalConfig2 = 0x00000000; +SDRAM[2].EmcAutoCalConfig3 = 0x00000000; +SDRAM[2].EmcAutoCalWait = 0x00000190; +SDRAM[2].EmcAdrCfg = 0x00000001; +SDRAM[2].EmcPinProgramWait = 0x00000000; +SDRAM[2].EmcPinExtraWait = 0x00000000; +SDRAM[2].EmcTimingControlWait = 0x00000000; +SDRAM[2].EmcRc = 0x0000001f; +SDRAM[2].EmcRfc = 0x00000044; +SDRAM[2].EmcRfcSlr = 0x00000000; +SDRAM[2].EmcRas = 0x00000016; +SDRAM[2].EmcRp = 0x00000009; +SDRAM[2].EmcR2r = 0x00000000; +SDRAM[2].EmcW2w = 0x00000000; +SDRAM[2].EmcR2w = 0x0000000a; +SDRAM[2].EmcW2r = 0x00000009; +SDRAM[2].EmcR2p = 0x00000003; +SDRAM[2].EmcW2p = 0x0000000d; +SDRAM[2].EmcRdRcd = 0x00000009; +SDRAM[2].EmcWrRcd = 0x00000009; +SDRAM[2].EmcRrd = 0x00000005; +SDRAM[2].EmcRext = 0x00000004; +SDRAM[2].EmcWext = 0x00000000; +SDRAM[2].EmcWdv = 0x00000002; +SDRAM[2].EmcWdvMask = 0x00000002; +SDRAM[2].EmcQUse = 0x00000008; +SDRAM[2].EmcQuseWidth = 0x00000003; +SDRAM[2].EmcIbdly = 0x00000000; +SDRAM[2].EmcEInput = 0x00000003; +SDRAM[2].EmcEInputDuration = 0x0000000a; +SDRAM[2].EmcPutermExtra = 0x00050000; +SDRAM[2].EmcPutermWidth = 0x00000004; +SDRAM[2].EmcPutermAdj = 0x00000000; +SDRAM[2].EmcCdbCntl1 = 0x00000000; +SDRAM[2].EmcCdbCntl2 = 0x00000000; +SDRAM[2].EmcCdbCntl3 = 0x00000000; +SDRAM[2].EmcQRst = 0x00000002; +SDRAM[2].EmcQSafe = 0x00000011; +SDRAM[2].EmcRdv = 0x00000015; +SDRAM[2].EmcRdvMask = 0x00000017; +SDRAM[2].EmcQpop = 0x0000000d; +SDRAM[2].EmcCtt = 0x00000000; +SDRAM[2].EmcCttDuration = 0x00000004; +SDRAM[2].EmcRefresh = 0x000007cd; +SDRAM[2].EmcBurstRefreshNum = 0x00000000; +SDRAM[2].EmcPreRefreshReqCnt = 0x000001f3; +SDRAM[2].EmcPdEx2Wr = 0x00000003; +SDRAM[2].EmcPdEx2Rd = 0x00000003; +SDRAM[2].EmcPChg2Pden = 0x00000009; +SDRAM[2].EmcAct2Pden = 0x00000000; +SDRAM[2].EmcAr2Pden = 0x00000001; +SDRAM[2].EmcRw2Pden = 0x00000011; +SDRAM[2].EmcTxsr = 0x0000004a; +SDRAM[2].EmcTxsrDll = 0x0000004a; +SDRAM[2].EmcTcke = 0x00000004; +SDRAM[2].EmcTckesr = 0x00000008; +SDRAM[2].EmcTpd = 0x00000004; +SDRAM[2].EmcTfaw = 0x00000019; +SDRAM[2].EmcTrpab = 0x0000000c; +SDRAM[2].EmcTClkStable = 0x00000003; +SDRAM[2].EmcTClkStop = 0x00000003; +SDRAM[2].EmcTRefBw = 0x00000895; +SDRAM[2].EmcFbioCfg5 = 0x1363a096; +SDRAM[2].EmcFbioCfg6 = 0x00000000; +SDRAM[2].EmcFbioSpare = 0x00000000; +SDRAM[2].EmcCfgRsv = 0xff00ff00; +SDRAM[2].EmcMrs = 0x00000000; +SDRAM[2].EmcEmrs = 0x00000000; +SDRAM[2].EmcEmrs2 = 0x00000000; +SDRAM[2].EmcEmrs3 = 0x00000000; +SDRAM[2].EmcMrw1 = 0x000100c3; +SDRAM[2].EmcMrw2 = 0x00020006; +SDRAM[2].EmcMrw3 = 0x00030001; +SDRAM[2].EmcMrw4 = 0x800b0000; +SDRAM[2].EmcMrwExtra = 0x000100c3; +SDRAM[2].EmcWarmBootMrwExtra = 0x00020006; +SDRAM[2].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; +SDRAM[2].EmcExtraModeRegWriteEnable = 0x00000000; +SDRAM[2].EmcMrwResetCommand = 0x003f00fc; +SDRAM[2].EmcMrwResetNInitWait = 0x0000000a; +SDRAM[2].EmcMrsWaitCnt = 0x02100013; +SDRAM[2].EmcMrsWaitCnt2 = 0x02100013; +SDRAM[2].EmcCfg = 0xf3300000; +SDRAM[2].EmcCfg2 = 0x0000089f; +SDRAM[2].EmcCfgPipe = 0x000042a0; +SDRAM[2].EmcDbg = 0x01000c00; +SDRAM[2].EmcCmdQ = 0x10004408; +SDRAM[2].EmcMc2EmcQ = 0x06000404; +SDRAM[2].EmcDynSelfRefControl = 0x800010b3; +SDRAM[2].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; +SDRAM[2].EmcCfgDigDll = 0xe01200b9; +SDRAM[2].EmcCfgDigDllPeriod = 0x00008000; +SDRAM[2].EmcDevSelect = 0x00000000; +SDRAM[2].EmcSelDpdCtrl = 0x0004001c; +SDRAM[2].EmcDllXformDqs0 = 0x007f400a; +SDRAM[2].EmcDllXformDqs1 = 0x007f400a; +SDRAM[2].EmcDllXformDqs2 = 0x007f400a; +SDRAM[2].EmcDllXformDqs3 = 0x007f400a; +SDRAM[2].EmcDllXformDqs4 = 0x007f400a; +SDRAM[2].EmcDllXformDqs5 = 0x007f400a; +SDRAM[2].EmcDllXformDqs6 = 0x007f400a; +SDRAM[2].EmcDllXformDqs7 = 0x007f400a; +SDRAM[2].EmcDllXformDqs8 = 0x007f400a; +SDRAM[2].EmcDllXformDqs9 = 0x007f400a; +SDRAM[2].EmcDllXformDqs10 = 0x007f400a; +SDRAM[2].EmcDllXformDqs11 = 0x007f400a; +SDRAM[2].EmcDllXformDqs12 = 0x007f400a; +SDRAM[2].EmcDllXformDqs13 = 0x007f400a; +SDRAM[2].EmcDllXformDqs14 = 0x007f400a; +SDRAM[2].EmcDllXformDqs15 = 0x007f400a; +SDRAM[2].EmcDllXformQUse0 = 0x00000000; +SDRAM[2].EmcDllXformQUse1 = 0x00000000; +SDRAM[2].EmcDllXformQUse2 = 0x00000000; +SDRAM[2].EmcDllXformQUse3 = 0x00000000; +SDRAM[2].EmcDllXformQUse4 = 0x00000000; +SDRAM[2].EmcDllXformQUse5 = 0x00000000; +SDRAM[2].EmcDllXformQUse6 = 0x00000000; +SDRAM[2].EmcDllXformQUse7 = 0x00000000; +SDRAM[2].EmcDllXformAddr0 = 0x00024000; +SDRAM[2].EmcDllXformAddr1 = 0x00024000; +SDRAM[2].EmcDllXformAddr2 = 0x00000006; +SDRAM[2].EmcDllXformAddr3 = 0x00024000; +SDRAM[2].EmcDllXformAddr4 = 0x00024000; +SDRAM[2].EmcDllXformAddr5 = 0x00000006; +SDRAM[2].EmcDllXformQUse8 = 0x00000000; +SDRAM[2].EmcDllXformQUse9 = 0x00000000; +SDRAM[2].EmcDllXformQUse10 = 0x00000000; +SDRAM[2].EmcDllXformQUse11 = 0x00000000; +SDRAM[2].EmcDllXformQUse12 = 0x00000000; +SDRAM[2].EmcDllXformQUse13 = 0x00000000; +SDRAM[2].EmcDllXformQUse14 = 0x00000000; +SDRAM[2].EmcDllXformQUse15 = 0x00000000; +SDRAM[2].EmcDliTrimTxDqs0 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs1 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs2 = 0x00000008; +SDRAM[2].EmcDliTrimTxDqs3 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs4 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs5 = 0x00000008; +SDRAM[2].EmcDliTrimTxDqs6 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs7 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs8 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs9 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs10 = 0x00000008; +SDRAM[2].EmcDliTrimTxDqs11 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs12 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs13 = 0x00000008; +SDRAM[2].EmcDliTrimTxDqs14 = 0x0000000b; +SDRAM[2].EmcDliTrimTxDqs15 = 0x0000000b; +SDRAM[2].EmcDllXformDq0 = 0x0000000c; +SDRAM[2].EmcDllXformDq1 = 0x0000000c; +SDRAM[2].EmcDllXformDq2 = 0x0000000c; +SDRAM[2].EmcDllXformDq3 = 0x0000000c; +SDRAM[2].EmcDllXformDq4 = 0x0000000c; +SDRAM[2].EmcDllXformDq5 = 0x0000000c; +SDRAM[2].EmcDllXformDq6 = 0x0000000c; +SDRAM[2].EmcDllXformDq7 = 0x0000000c; +SDRAM[2].WarmBootWait = 0x00000001; +SDRAM[2].EmcCttTermCtrl = 0x00000802; +SDRAM[2].EmcOdtWrite = 0x00000000; +SDRAM[2].EmcOdtRead = 0x00000000; +SDRAM[2].EmcZcalInterval = 0x00064000; +SDRAM[2].EmcZcalWaitCnt = 0x00000034; +SDRAM[2].EmcZcalMrwCmd = 0x000a0056; +SDRAM[2].EmcMrsResetDll = 0x00000000; +SDRAM[2].EmcZcalInitDev0 = 0x840a00ff; +SDRAM[2].EmcZcalInitDev1 = 0x440a00ff; +SDRAM[2].EmcZcalInitWait = 0x00000001; +SDRAM[2].EmcZcalWarmColdBootEnables = 0x00000003; +SDRAM[2].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; +SDRAM[2].EmcZqCalDdr3WarmBoot = 0x00000000; +SDRAM[2].EmcZcalWarmBootWait = 0x00000001; +SDRAM[2].EmcMrsWarmBootEnable = 0x00000001; +SDRAM[2].EmcMrsResetDllWait = 0x00000000; +SDRAM[2].EmcMrsExtra = 0x00000000; +SDRAM[2].EmcWarmBootMrsExtra = 0x00000000; +SDRAM[2].EmcEmrsDdr2DllEnable = 0x00000000; +SDRAM[2].EmcMrsDdr2DllReset = 0x00000000; +SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00000000; +SDRAM[2].EmcDdr2Wait = 0x00000000; +SDRAM[2].EmcClkenOverride = 0x00000000; +SDRAM[2].McDisExtraSnapLevels = 0x00000000; +SDRAM[2].EmcExtraRefreshNum = 0x00000002; +SDRAM[2].EmcClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[2].McClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[2].EmcCfgDigDllPeriodWarmBoot = 0x00000003; +SDRAM[2].PmcVddpSel = 0x00000001; +SDRAM[2].PmcVddpSelWait = 0x00000002; +SDRAM[2].PmcDdrPwr = 0x00000003; +SDRAM[2].PmcDdrCfg = 0x00001000; +SDRAM[2].PmcIoDpd3Req = 0x4ffefef7; +SDRAM[2].PmcIoDpd3ReqWait = 0x00000000; +SDRAM[2].PmcRegShort = 0x0000330f; +SDRAM[2].PmcNoIoPower = 0x00000000; +SDRAM[2].PmcPorDpdCtrlWait = 0x00000001; +SDRAM[2].EmcXm2CmdPadCtrl = 0x00000220; +SDRAM[2].EmcXm2CmdPadCtrl2 = 0x770c0000; +SDRAM[2].EmcXm2CmdPadCtrl3 = 0x050c0000; +SDRAM[2].EmcXm2CmdPadCtrl4 = 0x00000000; +SDRAM[2].EmcXm2CmdPadCtrl5 = 0x00100100; +SDRAM[2].EmcXm2DqsPadCtrl = 0x770c1414; +SDRAM[2].EmcXm2DqsPadCtrl2 = 0x0123123d; +SDRAM[2].EmcXm2DqsPadCtrl3 = 0x51451420; +SDRAM[2].EmcXm2DqsPadCtrl4 = 0x00514514; +SDRAM[2].EmcXm2DqsPadCtrl5 = 0x00514514; +SDRAM[2].EmcXm2DqsPadCtrl6 = 0x51451400; +SDRAM[2].EmcXm2DqPadCtrl = 0x770c2990; +SDRAM[2].EmcXm2DqPadCtrl2 = 0x00000000; +SDRAM[2].EmcXm2DqPadCtrl3 = 0x00000000; +SDRAM[2].EmcXm2ClkPadCtrl = 0x77ffc004; +SDRAM[2].EmcXm2ClkPadCtrl2 = 0x00000000; +SDRAM[2].EmcXm2CompPadCtrl = 0x81f1f008; +SDRAM[2].EmcXm2VttGenPadCtrl = 0x07070000; +SDRAM[2].EmcXm2VttGenPadCtrl2 = 0x0000003f; +SDRAM[2].EmcXm2VttGenPadCtrl3 = 0x015ddddd; +SDRAM[2].EmcAcpdControl = 0x00000000; +SDRAM[2].EmcSwizzleRank0ByteCfg = 0x00001032; +SDRAM[2].EmcSwizzleRank0Byte0 = 0x53067142; +SDRAM[2].EmcSwizzleRank0Byte1 = 0x73025146; +SDRAM[2].EmcSwizzleRank0Byte2 = 0x20136475; +SDRAM[2].EmcSwizzleRank0Byte3 = 0x46273150; +SDRAM[2].EmcSwizzleRank1ByteCfg = 0x00003210; +SDRAM[2].EmcSwizzleRank1Byte0 = 0x73451026; +SDRAM[2].EmcSwizzleRank1Byte1 = 0x73025146; +SDRAM[2].EmcSwizzleRank1Byte2 = 0x20641735; +SDRAM[2].EmcSwizzleRank1Byte3 = 0x42136075; +SDRAM[2].EmcDsrVttgenDrv = 0x0000003f; +SDRAM[2].EmcTxdsrvttgen = 0x00000000; +SDRAM[2].EmcBgbiasCtl0 = 0x00000000; +SDRAM[2].McEmemAdrCfg = 0x00000001; +SDRAM[2].McEmemAdrCfgDev0 = 0x00080304; +SDRAM[2].McEmemAdrCfgDev1 = 0x00080304; +SDRAM[2].McEmemAdrCfgBankMask0 = 0x00001248; +SDRAM[2].McEmemAdrCfgBankMask1 = 0x00002490; +SDRAM[2].McEmemAdrCfgBankMask2 = 0x00000920; +SDRAM[2].McEmemAdrCfgBankSwizzle3 = 0x00000001; +SDRAM[2].McEmemCfg = 0x00001000; +SDRAM[2].McEmemArbCfg = 0x0f000007; +SDRAM[2].McEmemArbOutstandingReq = 0x80000040; +SDRAM[2].McEmemArbTimingRcd = 0x00000003; +SDRAM[2].McEmemArbTimingRp = 0x00000004; +SDRAM[2].McEmemArbTimingRc = 0x00000010; +SDRAM[2].McEmemArbTimingRas = 0x0000000a; +SDRAM[2].McEmemArbTimingFaw = 0x0000000d; +SDRAM[2].McEmemArbTimingRrd = 0x00000002; +SDRAM[2].McEmemArbTimingRap2Pre = 0x00000002; +SDRAM[2].McEmemArbTimingWap2Pre = 0x00000009; +SDRAM[2].McEmemArbTimingR2R = 0x00000003; +SDRAM[2].McEmemArbTimingW2W = 0x00000001; +SDRAM[2].McEmemArbTimingR2W = 0x00000006; +SDRAM[2].McEmemArbTimingW2R = 0x00000006; +SDRAM[2].McEmemArbDaTurns = 0x06060103; +SDRAM[2].McEmemArbDaCovers = 0x00120b10; +SDRAM[2].McEmemArbMisc0 = 0x71c81811; +SDRAM[2].McEmemArbMisc1 = 0x70000f03; +SDRAM[2].McEmemArbRing1Throttle = 0x001f0000; +SDRAM[2].McEmemArbOverride = 0x10000000; +SDRAM[2].McEmemArbOverride1 = 0x00000000; +SDRAM[2].McEmemArbRsv = 0xff00ff00; +SDRAM[2].McClkenOverride = 0x00000000; +SDRAM[2].McStatControl = 0x00000000; +SDRAM[2].McDisplaySnapRing = 0x00000003; +SDRAM[2].McVideoProtectBom = 0xfff00000; +SDRAM[2].McVideoProtectBomAdrHi = 0x00000000; +SDRAM[2].McVideoProtectSizeMb = 0x00000000; +SDRAM[2].McVideoProtectVprOverride = 0xe4bac743; +SDRAM[2].McVideoProtectVprOverride1 = 0x00000013; +SDRAM[2].McVideoProtectGpuOverride0 = 0x00000000; +SDRAM[2].McVideoProtectGpuOverride1 = 0x00000000; +SDRAM[2].McSecCarveoutBom = 0xfff00000; +SDRAM[2].McSecCarveoutAdrHi = 0x00000000; +SDRAM[2].McSecCarveoutSizeMb = 0x00000000; +SDRAM[2].McVideoProtectWriteAccess = 0x00000000; +SDRAM[2].McSecCarveoutProtectWriteAccess = 0x00000000; +SDRAM[2].EmcCaTrainingEnable = 0x00000001; +SDRAM[2].EmcCaTrainingTimingCntl1 = 0x09257359; +SDRAM[2].EmcCaTrainingTimingCntl2 = 0x00000017; +SDRAM[2].SwizzleRankByteEncode = 0x00000008; +SDRAM[2].BootRomPatchControl = 0x00000000; +SDRAM[2].BootRomPatchData = 0x00000000; +SDRAM[2].McMtsCarveoutBom = 0x78000000; +SDRAM[2].McMtsCarveoutAdrHi = 0x00000001; +SDRAM[2].McMtsCarveoutSizeMb = 0x00000080; +SDRAM[2].McMtsCarveoutRegCtrl = 0x00000001; +#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000000d; +#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000000fd; +#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00c10038; +#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00c10038; +#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00c1003c; +#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00c10090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00c10041; +#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00c10090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00c10041; +#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; +#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00c10080; +#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080021; +#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000c1; +#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00c10026; +#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00c1001a; +#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00c10024; +#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00c10029; +#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000c1; +#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; +#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; +#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00c10065; +#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00c1002a; + +# CFG Version 01 Spare (using Micron part) +# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command: +# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_528MHz_emc_reg.txt 1.89394 +# -o A44_64_528_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6 +# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.89 ns (528.00 MHz) +# bkv file: A44_528MHz_emc_reg.txt +SDRAM[3].MemoryType = NvBootMemoryType_LpDdr2; +SDRAM[3].PllMInputDivider = 0x00000001; +SDRAM[3].PllMFeedbackDivider = 0x0000002c; +SDRAM[3].PllMStableTime = 0x0000012c; +SDRAM[3].PllMSetupControl = 0x00000000; +SDRAM[3].PllMSelectDiv2 = 0x00000000; +SDRAM[3].PllMPDLshiftPh45 = 0x00000001; +SDRAM[3].PllMPDLshiftPh90 = 0x00000001; +SDRAM[3].PllMPDLshiftPh135 = 0x00000001; +SDRAM[3].PllMKCP = 0x00000000; +SDRAM[3].PllMKVCO = 0x00000000; +SDRAM[3].EmcBctSpare0 = 0x00000000; +SDRAM[3].EmcBctSpare1 = 0x00000000; +SDRAM[3].EmcBctSpare2 = 0x00000000; +SDRAM[3].EmcBctSpare3 = 0x00000000; +SDRAM[3].EmcBctSpare4 = 0x00000000; +SDRAM[3].EmcBctSpare5 = 0x00000000; +SDRAM[3].EmcBctSpare6 = 0x00000000; +SDRAM[3].EmcBctSpare7 = 0x00000000; +SDRAM[3].EmcBctSpare8 = 0x00000000; +SDRAM[3].EmcBctSpare9 = 0x00000000; +SDRAM[3].EmcBctSpare10 = 0x00000000; +SDRAM[3].EmcBctSpare11 = 0x00000000; +SDRAM[3].EmcClockSource = 0x80000000; +SDRAM[3].EmcAutoCalInterval = 0x001fffff; +SDRAM[3].EmcAutoCalConfig = 0xa1430000; +SDRAM[3].EmcAutoCalConfig2 = 0x00000000; +SDRAM[3].EmcAutoCalConfig3 = 0x00000000; +SDRAM[3].EmcAutoCalWait = 0x00000190; +SDRAM[3].EmcAdrCfg = 0x00000001; +SDRAM[3].EmcPinProgramWait = 0x00000000; +SDRAM[3].EmcPinExtraWait = 0x00000000; +SDRAM[3].EmcTimingControlWait = 0x00000000; +SDRAM[3].EmcRc = 0x0000001f; +SDRAM[3].EmcRfc = 0x00000044; +SDRAM[3].EmcRfcSlr = 0x00000000; +SDRAM[3].EmcRas = 0x00000016; +SDRAM[3].EmcRp = 0x00000009; +SDRAM[3].EmcR2r = 0x00000000; +SDRAM[3].EmcW2w = 0x00000000; +SDRAM[3].EmcR2w = 0x0000000a; +SDRAM[3].EmcW2r = 0x00000009; +SDRAM[3].EmcR2p = 0x00000003; +SDRAM[3].EmcW2p = 0x0000000d; +SDRAM[3].EmcRdRcd = 0x00000009; +SDRAM[3].EmcWrRcd = 0x00000009; +SDRAM[3].EmcRrd = 0x00000005; +SDRAM[3].EmcRext = 0x00000004; +SDRAM[3].EmcWext = 0x00000000; +SDRAM[3].EmcWdv = 0x00000002; +SDRAM[3].EmcWdvMask = 0x00000002; +SDRAM[3].EmcQUse = 0x00000008; +SDRAM[3].EmcQuseWidth = 0x00000003; +SDRAM[3].EmcIbdly = 0x00000000; +SDRAM[3].EmcEInput = 0x00000003; +SDRAM[3].EmcEInputDuration = 0x0000000a; +SDRAM[3].EmcPutermExtra = 0x00050000; +SDRAM[3].EmcPutermWidth = 0x00000004; +SDRAM[3].EmcPutermAdj = 0x00000000; +SDRAM[3].EmcCdbCntl1 = 0x00000000; +SDRAM[3].EmcCdbCntl2 = 0x00000000; +SDRAM[3].EmcCdbCntl3 = 0x00000000; +SDRAM[3].EmcQRst = 0x00000002; +SDRAM[3].EmcQSafe = 0x00000011; +SDRAM[3].EmcRdv = 0x00000015; +SDRAM[3].EmcRdvMask = 0x00000017; +SDRAM[3].EmcQpop = 0x0000000d; +SDRAM[3].EmcCtt = 0x00000000; +SDRAM[3].EmcCttDuration = 0x00000004; +SDRAM[3].EmcRefresh = 0x000007cd; +SDRAM[3].EmcBurstRefreshNum = 0x00000000; +SDRAM[3].EmcPreRefreshReqCnt = 0x000001f3; +SDRAM[3].EmcPdEx2Wr = 0x00000003; +SDRAM[3].EmcPdEx2Rd = 0x00000003; +SDRAM[3].EmcPChg2Pden = 0x00000009; +SDRAM[3].EmcAct2Pden = 0x00000000; +SDRAM[3].EmcAr2Pden = 0x00000001; +SDRAM[3].EmcRw2Pden = 0x00000011; +SDRAM[3].EmcTxsr = 0x0000004a; +SDRAM[3].EmcTxsrDll = 0x0000004a; +SDRAM[3].EmcTcke = 0x00000004; +SDRAM[3].EmcTckesr = 0x00000008; +SDRAM[3].EmcTpd = 0x00000004; +SDRAM[3].EmcTfaw = 0x00000019; +SDRAM[3].EmcTrpab = 0x0000000c; +SDRAM[3].EmcTClkStable = 0x00000003; +SDRAM[3].EmcTClkStop = 0x00000003; +SDRAM[3].EmcTRefBw = 0x00000895; +SDRAM[3].EmcFbioCfg5 = 0x1363a096; +SDRAM[3].EmcFbioCfg6 = 0x00000000; +SDRAM[3].EmcFbioSpare = 0x00000000; +SDRAM[3].EmcCfgRsv = 0xff00ff00; +SDRAM[3].EmcMrs = 0x00000000; +SDRAM[3].EmcEmrs = 0x00000000; +SDRAM[3].EmcEmrs2 = 0x00000000; +SDRAM[3].EmcEmrs3 = 0x00000000; +SDRAM[3].EmcMrw1 = 0x000100c3; +SDRAM[3].EmcMrw2 = 0x00020006; +SDRAM[3].EmcMrw3 = 0x00030001; +SDRAM[3].EmcMrw4 = 0x800b0000; +SDRAM[3].EmcMrwExtra = 0x000100c3; +SDRAM[3].EmcWarmBootMrwExtra = 0x00020006; +SDRAM[3].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; +SDRAM[3].EmcExtraModeRegWriteEnable = 0x00000000; +SDRAM[3].EmcMrwResetCommand = 0x003f00fc; +SDRAM[3].EmcMrwResetNInitWait = 0x0000000a; +SDRAM[3].EmcMrsWaitCnt = 0x02100013; +SDRAM[3].EmcMrsWaitCnt2 = 0x02100013; +SDRAM[3].EmcCfg = 0xf3300000; +SDRAM[3].EmcCfg2 = 0x0000089f; +SDRAM[3].EmcCfgPipe = 0x000042a0; +SDRAM[3].EmcDbg = 0x01000c00; +SDRAM[3].EmcCmdQ = 0x10004408; +SDRAM[3].EmcMc2EmcQ = 0x06000404; +SDRAM[3].EmcDynSelfRefControl = 0x800010b3; +SDRAM[3].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; +SDRAM[3].EmcCfgDigDll = 0xe01200b9; +SDRAM[3].EmcCfgDigDllPeriod = 0x00008000; +SDRAM[3].EmcDevSelect = 0x00000000; +SDRAM[3].EmcSelDpdCtrl = 0x0004001c; +SDRAM[3].EmcDllXformDqs0 = 0x007f400a; +SDRAM[3].EmcDllXformDqs1 = 0x007f400a; +SDRAM[3].EmcDllXformDqs2 = 0x007f400a; +SDRAM[3].EmcDllXformDqs3 = 0x007f400a; +SDRAM[3].EmcDllXformDqs4 = 0x007f400a; +SDRAM[3].EmcDllXformDqs5 = 0x007f400a; +SDRAM[3].EmcDllXformDqs6 = 0x007f400a; +SDRAM[3].EmcDllXformDqs7 = 0x007f400a; +SDRAM[3].EmcDllXformDqs8 = 0x007f400a; +SDRAM[3].EmcDllXformDqs9 = 0x007f400a; +SDRAM[3].EmcDllXformDqs10 = 0x007f400a; +SDRAM[3].EmcDllXformDqs11 = 0x007f400a; +SDRAM[3].EmcDllXformDqs12 = 0x007f400a; +SDRAM[3].EmcDllXformDqs13 = 0x007f400a; +SDRAM[3].EmcDllXformDqs14 = 0x007f400a; +SDRAM[3].EmcDllXformDqs15 = 0x007f400a; +SDRAM[3].EmcDllXformQUse0 = 0x00000000; +SDRAM[3].EmcDllXformQUse1 = 0x00000000; +SDRAM[3].EmcDllXformQUse2 = 0x00000000; +SDRAM[3].EmcDllXformQUse3 = 0x00000000; +SDRAM[3].EmcDllXformQUse4 = 0x00000000; +SDRAM[3].EmcDllXformQUse5 = 0x00000000; +SDRAM[3].EmcDllXformQUse6 = 0x00000000; +SDRAM[3].EmcDllXformQUse7 = 0x00000000; +SDRAM[3].EmcDllXformAddr0 = 0x00024000; +SDRAM[3].EmcDllXformAddr1 = 0x00024000; +SDRAM[3].EmcDllXformAddr2 = 0x00000006; +SDRAM[3].EmcDllXformAddr3 = 0x00024000; +SDRAM[3].EmcDllXformAddr4 = 0x00024000; +SDRAM[3].EmcDllXformAddr5 = 0x00000006; +SDRAM[3].EmcDllXformQUse8 = 0x00000000; +SDRAM[3].EmcDllXformQUse9 = 0x00000000; +SDRAM[3].EmcDllXformQUse10 = 0x00000000; +SDRAM[3].EmcDllXformQUse11 = 0x00000000; +SDRAM[3].EmcDllXformQUse12 = 0x00000000; +SDRAM[3].EmcDllXformQUse13 = 0x00000000; +SDRAM[3].EmcDllXformQUse14 = 0x00000000; +SDRAM[3].EmcDllXformQUse15 = 0x00000000; +SDRAM[3].EmcDliTrimTxDqs0 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs1 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs2 = 0x00000008; +SDRAM[3].EmcDliTrimTxDqs3 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs4 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs5 = 0x00000008; +SDRAM[3].EmcDliTrimTxDqs6 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs7 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs8 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs9 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs10 = 0x00000008; +SDRAM[3].EmcDliTrimTxDqs11 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs12 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs13 = 0x00000008; +SDRAM[3].EmcDliTrimTxDqs14 = 0x0000000b; +SDRAM[3].EmcDliTrimTxDqs15 = 0x0000000b; +SDRAM[3].EmcDllXformDq0 = 0x0000000c; +SDRAM[3].EmcDllXformDq1 = 0x0000000c; +SDRAM[3].EmcDllXformDq2 = 0x0000000c; +SDRAM[3].EmcDllXformDq3 = 0x0000000c; +SDRAM[3].EmcDllXformDq4 = 0x0000000c; +SDRAM[3].EmcDllXformDq5 = 0x0000000c; +SDRAM[3].EmcDllXformDq6 = 0x0000000c; +SDRAM[3].EmcDllXformDq7 = 0x0000000c; +SDRAM[3].WarmBootWait = 0x00000001; +SDRAM[3].EmcCttTermCtrl = 0x00000802; +SDRAM[3].EmcOdtWrite = 0x00000000; +SDRAM[3].EmcOdtRead = 0x00000000; +SDRAM[3].EmcZcalInterval = 0x00064000; +SDRAM[3].EmcZcalWaitCnt = 0x00000034; +SDRAM[3].EmcZcalMrwCmd = 0x000a0056; +SDRAM[3].EmcMrsResetDll = 0x00000000; +SDRAM[3].EmcZcalInitDev0 = 0x840a00ff; +SDRAM[3].EmcZcalInitDev1 = 0x440a00ff; +SDRAM[3].EmcZcalInitWait = 0x00000001; +SDRAM[3].EmcZcalWarmColdBootEnables = 0x00000003; +SDRAM[3].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; +SDRAM[3].EmcZqCalDdr3WarmBoot = 0x00000000; +SDRAM[3].EmcZcalWarmBootWait = 0x00000001; +SDRAM[3].EmcMrsWarmBootEnable = 0x00000001; +SDRAM[3].EmcMrsResetDllWait = 0x00000000; +SDRAM[3].EmcMrsExtra = 0x00000000; +SDRAM[3].EmcWarmBootMrsExtra = 0x00000000; +SDRAM[3].EmcEmrsDdr2DllEnable = 0x00000000; +SDRAM[3].EmcMrsDdr2DllReset = 0x00000000; +SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00000000; +SDRAM[3].EmcDdr2Wait = 0x00000000; +SDRAM[3].EmcClkenOverride = 0x00000000; +SDRAM[3].McDisExtraSnapLevels = 0x00000000; +SDRAM[3].EmcExtraRefreshNum = 0x00000002; +SDRAM[3].EmcClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[3].McClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[3].EmcCfgDigDllPeriodWarmBoot = 0x00000003; +SDRAM[3].PmcVddpSel = 0x00000001; +SDRAM[3].PmcVddpSelWait = 0x00000002; +SDRAM[3].PmcDdrPwr = 0x00000003; +SDRAM[3].PmcDdrCfg = 0x00001000; +SDRAM[3].PmcIoDpd3Req = 0x4ffefef7; +SDRAM[3].PmcIoDpd3ReqWait = 0x00000000; +SDRAM[3].PmcRegShort = 0x0000330f; +SDRAM[3].PmcNoIoPower = 0x00000000; +SDRAM[3].PmcPorDpdCtrlWait = 0x00000001; +SDRAM[3].EmcXm2CmdPadCtrl = 0x00000220; +SDRAM[3].EmcXm2CmdPadCtrl2 = 0x770c0000; +SDRAM[3].EmcXm2CmdPadCtrl3 = 0x050c0000; +SDRAM[3].EmcXm2CmdPadCtrl4 = 0x00000000; +SDRAM[3].EmcXm2CmdPadCtrl5 = 0x00100100; +SDRAM[3].EmcXm2DqsPadCtrl = 0x770c1414; +SDRAM[3].EmcXm2DqsPadCtrl2 = 0x0123123d; +SDRAM[3].EmcXm2DqsPadCtrl3 = 0x51451420; +SDRAM[3].EmcXm2DqsPadCtrl4 = 0x00514514; +SDRAM[3].EmcXm2DqsPadCtrl5 = 0x00514514; +SDRAM[3].EmcXm2DqsPadCtrl6 = 0x51451400; +SDRAM[3].EmcXm2DqPadCtrl = 0x770c2990; +SDRAM[3].EmcXm2DqPadCtrl2 = 0x00000000; +SDRAM[3].EmcXm2DqPadCtrl3 = 0x00000000; +SDRAM[3].EmcXm2ClkPadCtrl = 0x77ffc004; +SDRAM[3].EmcXm2ClkPadCtrl2 = 0x00000000; +SDRAM[3].EmcXm2CompPadCtrl = 0x81f1f008; +SDRAM[3].EmcXm2VttGenPadCtrl = 0x07070000; +SDRAM[3].EmcXm2VttGenPadCtrl2 = 0x0000003f; +SDRAM[3].EmcXm2VttGenPadCtrl3 = 0x015ddddd; +SDRAM[3].EmcAcpdControl = 0x00000000; +SDRAM[3].EmcSwizzleRank0ByteCfg = 0x00001032; +SDRAM[3].EmcSwizzleRank0Byte0 = 0x53067142; +SDRAM[3].EmcSwizzleRank0Byte1 = 0x73025146; +SDRAM[3].EmcSwizzleRank0Byte2 = 0x20136475; +SDRAM[3].EmcSwizzleRank0Byte3 = 0x46273150; +SDRAM[3].EmcSwizzleRank1ByteCfg = 0x00003210; +SDRAM[3].EmcSwizzleRank1Byte0 = 0x73451026; +SDRAM[3].EmcSwizzleRank1Byte1 = 0x73025146; +SDRAM[3].EmcSwizzleRank1Byte2 = 0x20641735; +SDRAM[3].EmcSwizzleRank1Byte3 = 0x42136075; +SDRAM[3].EmcDsrVttgenDrv = 0x0000003f; +SDRAM[3].EmcTxdsrvttgen = 0x00000000; +SDRAM[3].EmcBgbiasCtl0 = 0x00000000; +SDRAM[3].McEmemAdrCfg = 0x00000001; +SDRAM[3].McEmemAdrCfgDev0 = 0x00080304; +SDRAM[3].McEmemAdrCfgDev1 = 0x00080304; +SDRAM[3].McEmemAdrCfgBankMask0 = 0x00001248; +SDRAM[3].McEmemAdrCfgBankMask1 = 0x00002490; +SDRAM[3].McEmemAdrCfgBankMask2 = 0x00000920; +SDRAM[3].McEmemAdrCfgBankSwizzle3 = 0x00000001; +SDRAM[3].McEmemCfg = 0x00001000; +SDRAM[3].McEmemArbCfg = 0x0f000007; +SDRAM[3].McEmemArbOutstandingReq = 0x80000040; +SDRAM[3].McEmemArbTimingRcd = 0x00000003; +SDRAM[3].McEmemArbTimingRp = 0x00000004; +SDRAM[3].McEmemArbTimingRc = 0x00000010; +SDRAM[3].McEmemArbTimingRas = 0x0000000a; +SDRAM[3].McEmemArbTimingFaw = 0x0000000d; +SDRAM[3].McEmemArbTimingRrd = 0x00000002; +SDRAM[3].McEmemArbTimingRap2Pre = 0x00000002; +SDRAM[3].McEmemArbTimingWap2Pre = 0x00000009; +SDRAM[3].McEmemArbTimingR2R = 0x00000003; +SDRAM[3].McEmemArbTimingW2W = 0x00000001; +SDRAM[3].McEmemArbTimingR2W = 0x00000006; +SDRAM[3].McEmemArbTimingW2R = 0x00000006; +SDRAM[3].McEmemArbDaTurns = 0x06060103; +SDRAM[3].McEmemArbDaCovers = 0x00120b10; +SDRAM[3].McEmemArbMisc0 = 0x71c81811; +SDRAM[3].McEmemArbMisc1 = 0x70000f03; +SDRAM[3].McEmemArbRing1Throttle = 0x001f0000; +SDRAM[3].McEmemArbOverride = 0x10000000; +SDRAM[3].McEmemArbOverride1 = 0x00000000; +SDRAM[3].McEmemArbRsv = 0xff00ff00; +SDRAM[3].McClkenOverride = 0x00000000; +SDRAM[3].McStatControl = 0x00000000; +SDRAM[3].McDisplaySnapRing = 0x00000003; +SDRAM[3].McVideoProtectBom = 0xfff00000; +SDRAM[3].McVideoProtectBomAdrHi = 0x00000000; +SDRAM[3].McVideoProtectSizeMb = 0x00000000; +SDRAM[3].McVideoProtectVprOverride = 0xe4bac743; +SDRAM[3].McVideoProtectVprOverride1 = 0x00000013; +SDRAM[3].McVideoProtectGpuOverride0 = 0x00000000; +SDRAM[3].McVideoProtectGpuOverride1 = 0x00000000; +SDRAM[3].McSecCarveoutBom = 0xfff00000; +SDRAM[3].McSecCarveoutAdrHi = 0x00000000; +SDRAM[3].McSecCarveoutSizeMb = 0x00000000; +SDRAM[3].McVideoProtectWriteAccess = 0x00000000; +SDRAM[3].McSecCarveoutProtectWriteAccess = 0x00000000; +SDRAM[3].EmcCaTrainingEnable = 0x00000001; +SDRAM[3].EmcCaTrainingTimingCntl1 = 0x09257359; +SDRAM[3].EmcCaTrainingTimingCntl2 = 0x00000017; +SDRAM[3].SwizzleRankByteEncode = 0x00000008; +SDRAM[3].BootRomPatchControl = 0x00000000; +SDRAM[3].BootRomPatchData = 0x00000000; +SDRAM[3].McMtsCarveoutBom = 0x78000000; +SDRAM[3].McMtsCarveoutAdrHi = 0x00000001; +SDRAM[3].McMtsCarveoutSizeMb = 0x00000080; +SDRAM[3].McMtsCarveoutRegCtrl = 0x00000001; +#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000000d; +#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000000fd; +#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00c10038; +#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00c10038; +#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00c1003c; +#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00c10090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00c10041; +#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00c10090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00c10041; +#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; +#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00c10080; +#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080021; +#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000c1; +#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00c10004; +#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00c10026; +#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00c1001a; +#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00c10024; +#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00c10029; +#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000c1; +#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; +#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; +#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00c100c1; +#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00c10065; +#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00c1002a; diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 8a5d087..0ce29a0 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -99,4 +99,10 @@ config TRUSTZONE_CARVEOUT_SIZE_MB help Size of Trust Zone area in MiB to reserve in memory map. +config BOOTROM_SDRAM_INIT + bool "SoC BootROM does SDRAM init with full BCT" + default n + help + Use during Ryu LPDDR3 bringup + endif diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index e7e545d..2a1bd46 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -38,9 +38,13 @@ void romstage(void) printk(BIOS_INFO, "T132: romstage here\n"); +#if CONFIG_BOOTROM_SDRAM_INIT + printk(BIOS_INFO, "T132 romstage: SDRAM init done by BootROM, RAMCODE = %d\n", + sdram_get_ram_code()); +#else sdram_init(get_sdram_config()); printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); - +#endif cbmem_initialize(); ccplex_cpu_prepare();

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New patch to review for coreboot: 4ff5173 armv8: correct dcache line size calculation
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8642 -gerrit commit 4ff5173ba97e0dd40851a2ee1f836595285e90f1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 17 13:08:06 2014 -0500 armv8: correct dcache line size calculation The CCSIDR_EL1 register has cache attribute information for a given cache selection in CSSELR_EL1. However, the cache isn't being selected before reading CCSIDR_EL1. Instead use CTR_EL0 which better fits with the semantics of dcache_line_bytes(). CTR_EL0 has the minimum data cache line size of all caches in the system encoded in 19:16 encoded as lg(line size in words). BUG=None TEST=Built. Original-Change-Id: I2cbf888a93031736e668918de928c3a99c26bedd Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208720 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 8d5dfba35d74fc4c6ee14365a2e9d9ed9f43115d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1db47ff5850c276d0246ac67e8b96f7ed19016c0 --- src/arch/arm64/armv8/cache.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index 97822ff..c1dba92 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -46,16 +46,17 @@ void tlb_invalidate_all(void) unsigned int dcache_line_bytes(void) { - uint32_t ccsidr; + uint32_t ctr_el0; static unsigned int line_bytes = 0; if (line_bytes) return line_bytes; - ccsidr = raw_read_ccsidr_el1(); - /* [2:0] - Indicates (Log2(number of words in cache line)) - 4 */ - line_bytes = 1 << ((ccsidr & 0x7) + 4); /* words per line */ - line_bytes *= sizeof(uint32_t); /* bytes per word */ + ctr_el0 = raw_read_ctr_el0(); + /* [19:16] - Indicates (Log2(number of words in cache line) */ + line_bytes = 1 << ((ctr_el0 >> 16) & 0xf); + /* Bytes in a word (32-bit) */ + line_bytes *= sizeof(uint32_t); return line_bytes; }

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New patch to review for coreboot: 7312841 tegra132: split memory range querying to above/below 4GiB
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8641 -gerrit commit 73128413b0b070d5cca34c72b659a20d80d7ddc5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jul 15 13:13:51 2014 -0500 tegra132: split memory range querying to above/below 4GiB The address map code was originally assuming all carveouts would be packed together in the upper end of the physical memory address space. However, the trust zone carveout is always in the 32-bit address space. Therefore, one needs to query memory ranges by above and below 4GiB with the assumption of carveouts being packed at the top of *each* resulting range. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and ran through coreboot on rush. Original-Change-Id: Iab134a049f3726f1ec41fc6626b1a6683d9f5362 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208101 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 8d5795fbff36e91906384e10774a32541d358324) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If15ff48d5a4c81731eb364980b30c8086deb1cca --- src/soc/nvidia/tegra132/addressmap.c | 36 ++++++++++++++++++++---- src/soc/nvidia/tegra132/include/soc/addressmap.h | 13 ++------- src/soc/nvidia/tegra132/ramstage.c | 2 +- 3 files changed, 35 insertions(+), 16 deletions(-) diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c index 7f6d7c3..7dbab55 100644 --- a/src/soc/nvidia/tegra132/addressmap.c +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -102,7 +102,7 @@ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib) } } -void memory_range_by_bits(int bits, uintptr_t *base_mib, uintptr_t *end_mib) +static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib) { uintptr_t base; uintptr_t end; @@ -111,11 +111,21 @@ void memory_range_by_bits(int bits, uintptr_t *base_mib, uintptr_t *end_mib) base = CONFIG_SYS_SDRAM_BASE / MiB; end = base + sdram_size_mb(); - if (bits == ADDRESS_SPACE_32_BIT) - end = MIN(end, 4096); + /* Requested limits out of range. */ + if (*end_mib <= base || *base_mib >= end) { + *end_mib = *base_mib = 0; + return; + } + + /* Clip region to passed in limits. */ + if (*end_mib < end) + end = *end_mib; + if (*base_mib > base) + base = *base_mib; for (i = 0; i < CARVEOUT_NUM; i++) { uintptr_t carveout_base; + uintptr_t carveout_end; size_t carveout_size; carveout_range(i, &carveout_base, &carveout_size); @@ -123,8 +133,10 @@ void memory_range_by_bits(int bits, uintptr_t *base_mib, uintptr_t *end_mib) if (carveout_size == 0) continue; + carveout_end = carveout_base + carveout_size; + /* Bypass carveouts out of requested range. */ - if (carveout_base >= end) + if (carveout_base >= end || carveout_end <= base) continue; /* @@ -139,13 +151,27 @@ void memory_range_by_bits(int bits, uintptr_t *base_mib, uintptr_t *end_mib) *end_mib = end; } +void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib) +{ + *base_mib = 0; + *end_mib = 4096; + memory_in_range(base_mib, end_mib); +} + +void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib) +{ + *base_mib = 4096; + *end_mib = ~0UL; + memory_in_range(base_mib, end_mib); +} + uintptr_t framebuffer_attributes(size_t *size_mib) { uintptr_t begin; uintptr_t end; /* Place the framebuffer just below the 32-bit addressable limit. */ - memory_range_by_bits(ADDRESS_SPACE_32_BIT, &begin, &end); + memory_in_range_below_4gb(&begin, &end); /* * Need to take into account that the Trust Zone region is not able to diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h index 2c6dc5e..3d0fc59 100644 --- a/src/soc/nvidia/tegra132/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -84,16 +84,9 @@ enum { /* Return total size of DRAM memory configured on the platform. */ int sdram_size_mb(void); -enum { - ADDRESS_SPACE_32_BIT = 32, - ADDRESS_SPACE_64_BIT = 64, -}; - -/* - * Return the address range of memory for provided address width. The base - * and end parameters in 1MiB units with end being exclusive to the range. - */ -void memory_range_by_bits(int bits, uintptr_t *base_mib, uintptr_t *end_mib); +/* Find memory below and above 4GiB boundary repsectively. All units 1MiB. */ +void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib); +void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib); enum { CARVEOUT_TZ, diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index 7b2f4e8..8d64c3e 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -38,7 +38,7 @@ void arm64_soc_init(void) * Therefore configure the region early. Also, the TZ region can only * live in 32-bit space. */ - memory_range_by_bits(ADDRESS_SPACE_32_BIT, &base, &end); + memory_in_range_below_4gb(&base, &end); /* Place the TZ area just below current carveout regions. */ end -= tz_size_mib;

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coreboot-gerrit March 2015