coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

1 participants
2443 discussions

New patch to review for coreboot: 0f0ba7e storm: allow to override CBFS_SIZE configuration setting
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8640 -gerrit commit 0f0ba7eb9f8abc3f0d782ccc2c05753a5032f649 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jul 15 13:19:19 2014 -0700 storm: allow to override CBFS_SIZE configuration setting The default CBFS size configuration setting is incorrect in case of Qualcomm SOC targets, as the coreboot blob is much smaller than the actual bootprom. Note that this size also must match the board fmap defined in the appropriate depthcharge board directory. BUG=chromium:394068 TEST=manual . previously failing to boot coreboot image does not fail to load depthcharge anymore. Original-Change-Id: I1b178970b1deee05705490542e4a0c57500379dd Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208146 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 01f3561fdee7b5547534e20d423fbbb1b490532c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If573bbc6254cf6786e75970eae3ad2b327a7ecfe --- src/soc/qualcomm/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/qualcomm/Kconfig b/src/soc/qualcomm/Kconfig index b7a12d4..918093b 100644 --- a/src/soc/qualcomm/Kconfig +++ b/src/soc/qualcomm/Kconfig @@ -1 +1,9 @@ source src/soc/qualcomm/ipq806x/Kconfig + +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default ROM_SIZE + help + CBFS size needs to match the size of memory allocated to the + coreboot blob elsewhere in the system. Make sure this config option + is fine tuned in the board config file.

1 0

New patch to review for coreboot: 4843814 t132: handle optional Trust Zone region correctly
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8639 -gerrit commit 4843814a9cb745e102c1123559e697236871417d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jul 15 10:53:29 2014 -0500 t132: handle optional Trust Zone region correctly Provide a default Trust Zone region size of 1MiB, and correctly account for it in the AVP and the arm64 cores. The different paths between the arm64 cores and the AVP is because the AVP cannot access the Trust Zone region registers. Therefore the AVP needs to account for the Trust Zone region. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and ran. Noted Trust Zone region being accounted for. Original-Change-Id: Ie0f117ec7a5ff8519c39778d3cdf88c3eee57ea5 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208062 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 22f2fa05c009c58f53b99b9ebe1b6d01fdac5ba7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I28506b4401145d366b56126b2eddc4c3d3db7b44 --- src/soc/nvidia/tegra132/Kconfig | 6 +++++ src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/addressmap.c | 8 ++++++ src/soc/nvidia/tegra132/ramstage.c | 47 ++++++++++++++++++++++++++++++++++++ 4 files changed, 62 insertions(+) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 3396cc8..8a5d087 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -93,4 +93,10 @@ config MTS_DIRECTORY help Path to directory where MTS microcode files are located. +config TRUSTZONE_CARVEOUT_SIZE_MB + hex "Size of Trust Zone region" + default 0x1 + help + Size of Trust Zone area in MiB to reserve in memory map. + endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 88ba51c..0ab95d4 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += monotonic_timer.c ramstage-y += ../tegra/gpio.c ramstage-y += ../tegra/i2c.c ramstage-y += ../tegra/pinmux.c +ramstage-y += ramstage.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c index bb35a87..7f6d7c3 100644 --- a/src/soc/nvidia/tegra132/addressmap.c +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -147,6 +147,14 @@ uintptr_t framebuffer_attributes(size_t *size_mib) /* Place the framebuffer just below the 32-bit addressable limit. */ memory_range_by_bits(ADDRESS_SPACE_32_BIT, &begin, &end); + /* + * Need to take into account that the Trust Zone region is not able to + * be read by the AVP. The Trust Zone region will live just below the + * rest of the carveout regions. + */ + if (context_avp()) + end -= CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; + *size_mib = FB_SIZE_MB; end -= *size_mib; diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c new file mode 100644 index 0000000..7b2f4e8 --- /dev/null +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/stages.h> +#include <soc/addressmap.h> +#include "mc.h" + +void arm64_soc_init(void) +{ + struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; + const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; + uintptr_t base; + uintptr_t end; + + if (!tz_size_mib) + return; + + /* + * Ramstage is when the arm64 first gets running. It also is the + * only entity that the capabilities to program the Trust Zone region. + * Therefore configure the region early. Also, the TZ region can only + * live in 32-bit space. + */ + memory_range_by_bits(ADDRESS_SPACE_32_BIT, &base, &end); + + /* Place the TZ area just below current carveout regions. */ + end -= tz_size_mib; + write32(end << 20, &mc->security_cfg0); + write32(tz_size_mib, &mc->security_cfg1); +}

1 0

Patch merged into coreboot/master: a49c0cc crossgcc: fix copy-paste mistake on riscv make target
by gerrit＠coreboot.org 10 Mar '15

10 Mar '15

the following patch was just integrated into master: commit a49c0cca9fb29541b30c7cec7f1b49c376a7c12d Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Mar 10 20:24:34 2015 +0100 crossgcc: fix copy-paste mistake on riscv make target Change-Id: Id618595a321529770964b125f7490dcb08376643 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: http://review.coreboot.org/8637 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8637 for details. -gerrit

1 0

New patch to review for coreboot: 2932963 nyan: Remove broken setup_display() from romstage
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8638 -gerrit commit 2932963390a03194a52c8d5991422abfb24b7b58 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Jul 11 17:09:41 2014 -0700 nyan: Remove broken setup_display() from romstage This patch removes a chunk of romstage code from Tegra and all Nyan boards that was supposed to enable some LCD power rails early, but never really worked. The dev_find_slot() function can only find PCI devices, which the CPU cluster is not. Since we're done with Nyan-RO and the ramstage display code is fine as it is, there is no point in trying to fix this... but we should remove it from ToT lest someone uses it as a blueprint to add more dead code to future boards. BRANCH=None BUG=None TEST=None Original-Change-Id: I6eee256873299429d4e3934fe7d454120390f34d Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207720 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit a3df62a3bcefcc20ae59648f5d1f0a01db3c02c6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8deedea5e9787848aae3064509c611bc349313cc --- src/mainboard/google/nyan/romstage.c | 20 ---------- src/mainboard/google/nyan_big/romstage.c | 20 ---------- src/mainboard/google/nyan_blaze/romstage.c | 20 ---------- src/soc/nvidia/tegra124/Makefile.inc | 1 - src/soc/nvidia/tegra124/early_display.c | 61 ------------------------------ 5 files changed, 122 deletions(-) diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 749b87d..5ab77b3 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -22,7 +22,6 @@ #include <arch/exception.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/device.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -191,25 +190,6 @@ static void __attribute__((noinline)) romstage(void) cpu_reset(); } - /* For quality of the user experience, it's important to get - * the video going ASAP. Because there are long delays in some - * of the powerup steps, we do some very early setup here in - * romstage. The only thing setup_display does is manage - * 4 GPIOs, under control of the config struct members. - * In general, it is safe to enable panel power, and disable - * anything related to the backlight. If we get something wrong, - * we can easily fix it in ramstage by further GPIO manipulation, - * so we feel it is ok to do some setting at this point. - */ - - const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); - printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc); - if (soc && soc->chip_info) { - const struct soc_nvidia_tegra124_config *config = - soc->chip_info; - setup_display((struct soc_nvidia_tegra124_config *)config); - } - cbmem_initialize_empty(); timestamp_init(0); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 749b87d..5ab77b3 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -22,7 +22,6 @@ #include <arch/exception.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/device.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -191,25 +190,6 @@ static void __attribute__((noinline)) romstage(void) cpu_reset(); } - /* For quality of the user experience, it's important to get - * the video going ASAP. Because there are long delays in some - * of the powerup steps, we do some very early setup here in - * romstage. The only thing setup_display does is manage - * 4 GPIOs, under control of the config struct members. - * In general, it is safe to enable panel power, and disable - * anything related to the backlight. If we get something wrong, - * we can easily fix it in ramstage by further GPIO manipulation, - * so we feel it is ok to do some setting at this point. - */ - - const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); - printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc); - if (soc && soc->chip_info) { - const struct soc_nvidia_tegra124_config *config = - soc->chip_info; - setup_display((struct soc_nvidia_tegra124_config *)config); - } - cbmem_initialize_empty(); timestamp_init(0); diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index a23937e..a5f6194 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -22,7 +22,6 @@ #include <arch/exception.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/device.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -191,25 +190,6 @@ static void __attribute__((noinline)) romstage(void) cpu_reset(); } - /* For quality of the user experience, it's important to get - * the video going ASAP. Because there are long delays in some - * of the powerup steps, we do some very early setup here in - * romstage. The only thing setup_display does is manage - * 4 GPIOs, under control of the config struct members. - * In general, it is safe to enable panel power, and disable - * anything related to the backlight. If we get something wrong, - * we can easily fix it in ramstage by further GPIO manipulation, - * so we feel it is ok to do some setting at this point. - */ - - const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); - printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc); - if (soc && soc->chip_info) { - const struct soc_nvidia_tegra124_config *config = - soc->chip_info; - setup_display((struct soc_nvidia_tegra124_config *)config); - } - cbmem_initialize_empty(); timestamp_init(0); diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 8054ca2..6631364 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -33,7 +33,6 @@ verstage-y += ../tegra/pinmux.c romstage-y += cbfs.c romstage-y += cbmem.c romstage-y += clock.c -romstage-y += early_display.c romstage-y += dma.c romstage-y += i2c.c romstage-y += monotonic_timer.c diff --git a/src/soc/nvidia/tegra124/early_display.c b/src/soc/nvidia/tegra124/early_display.c deleted file mode 100644 index 4356a62..0000000 --- a/src/soc/nvidia/tegra124/early_display.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <stdlib.h> -#include <stddef.h> -#include <arch/cache.h> -#include "chip.h" -#include <soc/display.h> -#include "gpio.h" - -/* the primary purpose of this function is to kick off things in - * romstage that are time consuming. No more should be done at this - * point than the bare minimum that will allow us to pick up the work - * in the ramstage and not require lots of udelays. ramstage will do - * the rest. As it happens, that merely means 'turn off everything you can, - * save the minimum long-delay bit that you need to get graphics going'. It's - * important not to have the backlight on as people don't like display trash - * on startup, even if I do. - */ -void setup_display(struct soc_nvidia_tegra124_config *config) -{ - if (config->panel_vdd_gpio){ - gpio_output(config->panel_vdd_gpio, 1); - printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", - __func__, config->panel_vdd_gpio, 1); - } - if (config->lvds_shutdown_gpio){ - gpio_output(config->lvds_shutdown_gpio, 0); - printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", - __func__, config->lvds_shutdown_gpio, 0); - } - if (config->backlight_en_gpio){ - gpio_output(config->backlight_en_gpio, 0); - printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", - __func__, config->backlight_en_gpio, 0); - } - if (config->backlight_vdd_gpio){ - gpio_output(config->backlight_vdd_gpio, 0); - printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", - __func__, config->backlight_vdd_gpio, 0); - } - -} -

1 0

Patch set updated for coreboot: 2db850b coreboot: x86 enable gc-sections
by Aaron Durbin 10 Mar '15

10 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8635 -gerrit commit 2db850b878ab4d7e71bd1edf28363be15357aaf8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 10 11:45:25 2015 -0500 coreboot: x86 enable gc-sections Garbage collected sections allow for trimming the size of the binaries as well as allowing for not needing to config off unused functions. To that end, on a rambi build the following differences are observed: $ diff -up \ <(readelf -l coreboot-builds/google_rambi/cbfs/fallback/ramstage.elf) \ <(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/ramstage.elf) --- /dev/fd/63 2015-03-10 12:07:27.927985430 -0500 +++ /dev/fd/62 2015-03-10 12:07:27.927985430 -0500 @@ -6,9 +6,9 @@ There are 4 program headers, starting at Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x00000000 0x00000000 0x00040 0x00040 RWE 0 - LOAD 0x001040 0x00000040 0x00000040 0x34560 0x34560 RWE 0 - LOAD 0x0355a0 0x000345a0 0x000345a0 0x02578 0x02578 RWE 0 - LOAD 0x037b18 0x00036b18 0x00036b18 0x00000 0x0b560 0 + LOAD 0x001040 0x00000040 0x00000040 0x2cbf8 0x2cbf8 RWE 0 + LOAD 0x02dc38 0x0002cc38 0x0002cc38 0x02208 0x02208 RWE 0 + LOAD 0x02fe40 0x0002ee40 0x0002ee40 0x00000 0x0a888 0 Section to Segment mapping: Segment Sections... $ diff -up \ <(readelf -l coreboot-builds/google_rambi/cbfs/fallback/romstage.elf) \ <(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/romstage.elf) --- /dev/fd/63 2015-03-10 12:08:16.855985880 -0500 +++ /dev/fd/62 2015-03-10 12:08:16.851985880 -0500 @@ -5,8 +5,8 @@ There are 1 program headers, starting at Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align - LOAD 0x000060 0xfff20000 0xfff20000 0x08b81 0x08b81 R E 0x10 + LOAD 0x000060 0xfff20000 0xfff20000 0x06300 0x06300 R E 0x10 Section to Segment mapping: Segment Sections... - 00 .rom .text + 00 .rom The following warnings needed to be applied to CFLAGS_common because for some reason gcc was miraculously emitting the warnings with the unrelated *-sections options: -Wno-unused-but-set-variable Change-Id: I210784fdfc273ce4cb9927352cbd5a51be3c6929 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 8 ++------ src/arch/x86/init/romstage.ld | 7 +++++-- src/arch/x86/ramstage.ld | 11 +++++++---- src/lib/Makefile.inc | 2 +- src/lib/rmodule.ld | 10 ++++++---- toolchain.inc | 2 ++ 7 files changed, 24 insertions(+), 18 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 656d988..4e435bc 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -253,7 +253,7 @@ CPPFLAGS_common += -include $(src)/include/kconfig.h CFLAGS_common += -pipe -g -nostdinc CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS_common += -Wstrict-aliasing -Wshadow +CFLAGS_common += -Wstrict-aliasing -Wshadow -Wno-unused-but-set-variable ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS_common += -Werror endif diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a92c55c..7acdb57 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -27,11 +27,7 @@ subdirs-y += boot subdirs-y += lib subdirs-y += smp -ifeq ($(CONFIG_COMPILER_GCC),y) -DISASSEMBLY=-Wa,-acdlns -else DISASSEMBLY=-Wa,--divide -endif OPTION_TABLE_H:= ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) @@ -214,7 +210,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null. $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --start-group $(romstage-objs) $(romstage-libs) $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld + $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --start-group $(romstage-objs) $(romstage-libs) $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" @@ -310,7 +306,7 @@ else $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld + $(LD_ramstage) --gc-sections -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld endif diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 50eb4ab..95b9571 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -30,13 +30,16 @@ SECTIONS .rom . : { _rom = .; *(.rom.text); + *(.rom.text.*); + *(.text); + *(.text.*); *(.rom.data); *(.rodata); *(.rodata.*); *(.rom.data.*); . = ALIGN(16); _car_migrate_start = .; - *(.car.migrate); + KEEP(*(.car.migrate)); LONG(0); _car_migrate_end = .; . = ALIGN(16); @@ -73,7 +76,7 @@ SECTIONS . = 0xffffff00; .illegal_globals . : { *(EXCLUDE_FILE (*/libagesa.*.a: */buildOpts.romstage.o */agesawrapper.romstage.o */vendorcode/amd/agesa/* */vendorcode/amd/cimx/*) .data) - *(.data.*) + *(EXCLUDE_FILE (*/libagesa.*.a: */buildOpts.romstage.o */agesawrapper.romstage.o */vendorcode/amd/agesa/* */vendorcode/amd/cimx/*) .data.*) *(.bss) *(.bss.*) *(.sbss) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 1c8e8dc..0843be7 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -42,7 +42,7 @@ SECTIONS .ctors : { . = ALIGN(0x100); __CTOR_LIST__ = .; - *(.ctors); + KEEP(*(.ctors)); LONG(0); __CTOR_END__ = .; } @@ -55,13 +55,13 @@ SECTIONS * section names the equivalent changes need to made to * rmodule.ld. */ pci_drivers = . ; - *(.rodata.pci_driver) + KEEP(*(.rodata.pci_driver)); epci_drivers = . ; cpu_drivers = . ; - *(.rodata.cpu_driver) + KEEP(*(.rodata.cpu_driver)); ecpu_drivers = . ; _bs_init_begin = .; - *(.bs_init) + KEEP(*(.bs_init)); _bs_init_end = .; *(.rodata) @@ -82,6 +82,7 @@ SECTIONS .data : { _data = .; *(.data) + *(.data.*) _edata = .; } @@ -92,7 +93,9 @@ SECTIONS _bss = .; .bss . : { *(.bss) + *(.bss.*) *(.sbss) + *(.sbss.*) *(COMMON) } _ebss = .; diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d5ba8e4..72b4c68 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -125,7 +125,7 @@ ramstage-y += rmodule.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c RMODULE_LDSCRIPT := $(src)/lib/rmodule.ld -RMODULE_LDFLAGS := -nostartfiles --emit-relocs -z defs -Bsymbolic -T$(RMODULE_LDSCRIPT) +RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic -T$(RMODULE_LDSCRIPT) # rmodule_link_rules is a function that should be called with: # (1) the object name to link diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f3e7cba..c1669be 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -14,6 +14,8 @@ BASE_ADDRESS = 0x00000; +ENTRY(__rmodule_entry); + SECTIONS { . = BASE_ADDRESS; @@ -38,15 +40,15 @@ SECTIONS * ramstage.ld should be made here as well. */ . = ALIGN(8); pci_drivers = . ; - *(.rodata.pci_driver) + KEEP(*(.rodata.pci_driver)); epci_drivers = . ; . = ALIGN(8); cpu_drivers = . ; - *(.rodata.cpu_driver) + KEEP(*(.rodata.cpu_driver)); ecpu_drivers = . ; . = ALIGN(8); _bs_init_begin = .; - *(.bs_init) + KEEP(*(.bs_init)); _bs_init_end = .; . = ALIGN(8); @@ -59,7 +61,7 @@ SECTIONS * to a module, however there has to be an prior agreement * on how to interpret the parameters. */ _module_params_begin = .; - *(.module_parameters); + KEEP(*(.module_parameters)); _module_params_end = .; . = ALIGN(8); diff --git a/toolchain.inc b/toolchain.inc index f888d68..8241e25 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -66,6 +66,8 @@ CFLAGS_arm64 := -ffunction-sections -fdata-sections CFLAGS_mipsel := -mips32r2 -G 0 +CFLAGS_x86_32 := -ffunction-sections -fdata-sections + toolchain_to_dir = \ $(foreach arch,$(ARCH_SUPPORTED),\ $(eval CPPFLAGS_$(arch) += \

1 0

Patch set updated for coreboot: d4fa2b4 coreboot: x86 enable gc-sections
by Aaron Durbin 10 Mar '15

10 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8635 -gerrit commit d4fa2b46f37644d34ee6ebc7b654f6cf31e62a7d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 10 11:45:25 2015 -0500 coreboot: x86 enable gc-sections Garbage collected sections allow for trimming the size of the binaries as well as allowing for not needing to config off unused functions. To that end, on a rambi build the following differences are observed: $ diff -up \ <(readelf -l coreboot-builds/google_rambi/cbfs/fallback/ramstage.elf) \ <(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/ramstage.elf) --- /dev/fd/63 2015-03-10 12:07:27.927985430 -0500 +++ /dev/fd/62 2015-03-10 12:07:27.927985430 -0500 @@ -6,9 +6,9 @@ There are 4 program headers, starting at Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x00000000 0x00000000 0x00040 0x00040 RWE 0 - LOAD 0x001040 0x00000040 0x00000040 0x34560 0x34560 RWE 0 - LOAD 0x0355a0 0x000345a0 0x000345a0 0x02578 0x02578 RWE 0 - LOAD 0x037b18 0x00036b18 0x00036b18 0x00000 0x0b560 0 + LOAD 0x001040 0x00000040 0x00000040 0x2cbf8 0x2cbf8 RWE 0 + LOAD 0x02dc38 0x0002cc38 0x0002cc38 0x02208 0x02208 RWE 0 + LOAD 0x02fe40 0x0002ee40 0x0002ee40 0x00000 0x0a888 0 Section to Segment mapping: Segment Sections... $ diff -up \ <(readelf -l coreboot-builds/google_rambi/cbfs/fallback/romstage.elf) \ <(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/romstage.elf) --- /dev/fd/63 2015-03-10 12:08:16.855985880 -0500 +++ /dev/fd/62 2015-03-10 12:08:16.851985880 -0500 @@ -5,8 +5,8 @@ There are 1 program headers, starting at Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align - LOAD 0x000060 0xfff20000 0xfff20000 0x08b81 0x08b81 R E 0x10 + LOAD 0x000060 0xfff20000 0xfff20000 0x06300 0x06300 R E 0x10 Section to Segment mapping: Segment Sections... - 00 .rom .text + 00 .rom The following warnings needed to be applied to CFLAGS_common because for some reason gcc was miraculously emitting the warnings with the unrelated *-sections options: -Wno-unused-but-set-variable Change-Id: I210784fdfc273ce4cb9927352cbd5a51be3c6929 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 8 ++------ src/arch/x86/init/romstage.ld | 5 ++++- src/arch/x86/ramstage.ld | 11 +++++++---- src/lib/Makefile.inc | 2 +- src/lib/rmodule.ld | 10 ++++++---- toolchain.inc | 2 ++ 7 files changed, 23 insertions(+), 17 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 656d988..4e435bc 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -253,7 +253,7 @@ CPPFLAGS_common += -include $(src)/include/kconfig.h CFLAGS_common += -pipe -g -nostdinc CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS_common += -Wstrict-aliasing -Wshadow +CFLAGS_common += -Wstrict-aliasing -Wshadow -Wno-unused-but-set-variable ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS_common += -Werror endif diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a92c55c..7acdb57 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -27,11 +27,7 @@ subdirs-y += boot subdirs-y += lib subdirs-y += smp -ifeq ($(CONFIG_COMPILER_GCC),y) -DISASSEMBLY=-Wa,-acdlns -else DISASSEMBLY=-Wa,--divide -endif OPTION_TABLE_H:= ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) @@ -214,7 +210,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null. $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --start-group $(romstage-objs) $(romstage-libs) $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld + $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --start-group $(romstage-objs) $(romstage-libs) $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" @@ -310,7 +306,7 @@ else $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld + $(LD_ramstage) --gc-sections -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld endif diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 50eb4ab..bb83c5e 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -30,13 +30,16 @@ SECTIONS .rom . : { _rom = .; *(.rom.text); + *(.rom.text.*); + *(.text); + *(.text.*); *(.rom.data); *(.rodata); *(.rodata.*); *(.rom.data.*); . = ALIGN(16); _car_migrate_start = .; - *(.car.migrate); + KEEP(*(.car.migrate)); LONG(0); _car_migrate_end = .; . = ALIGN(16); diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 1c8e8dc..0843be7 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -42,7 +42,7 @@ SECTIONS .ctors : { . = ALIGN(0x100); __CTOR_LIST__ = .; - *(.ctors); + KEEP(*(.ctors)); LONG(0); __CTOR_END__ = .; } @@ -55,13 +55,13 @@ SECTIONS * section names the equivalent changes need to made to * rmodule.ld. */ pci_drivers = . ; - *(.rodata.pci_driver) + KEEP(*(.rodata.pci_driver)); epci_drivers = . ; cpu_drivers = . ; - *(.rodata.cpu_driver) + KEEP(*(.rodata.cpu_driver)); ecpu_drivers = . ; _bs_init_begin = .; - *(.bs_init) + KEEP(*(.bs_init)); _bs_init_end = .; *(.rodata) @@ -82,6 +82,7 @@ SECTIONS .data : { _data = .; *(.data) + *(.data.*) _edata = .; } @@ -92,7 +93,9 @@ SECTIONS _bss = .; .bss . : { *(.bss) + *(.bss.*) *(.sbss) + *(.sbss.*) *(COMMON) } _ebss = .; diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d5ba8e4..72b4c68 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -125,7 +125,7 @@ ramstage-y += rmodule.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c RMODULE_LDSCRIPT := $(src)/lib/rmodule.ld -RMODULE_LDFLAGS := -nostartfiles --emit-relocs -z defs -Bsymbolic -T$(RMODULE_LDSCRIPT) +RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic -T$(RMODULE_LDSCRIPT) # rmodule_link_rules is a function that should be called with: # (1) the object name to link diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f3e7cba..c1669be 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -14,6 +14,8 @@ BASE_ADDRESS = 0x00000; +ENTRY(__rmodule_entry); + SECTIONS { . = BASE_ADDRESS; @@ -38,15 +40,15 @@ SECTIONS * ramstage.ld should be made here as well. */ . = ALIGN(8); pci_drivers = . ; - *(.rodata.pci_driver) + KEEP(*(.rodata.pci_driver)); epci_drivers = . ; . = ALIGN(8); cpu_drivers = . ; - *(.rodata.cpu_driver) + KEEP(*(.rodata.cpu_driver)); ecpu_drivers = . ; . = ALIGN(8); _bs_init_begin = .; - *(.bs_init) + KEEP(*(.bs_init)); _bs_init_end = .; . = ALIGN(8); @@ -59,7 +61,7 @@ SECTIONS * to a module, however there has to be an prior agreement * on how to interpret the parameters. */ _module_params_begin = .; - *(.module_parameters); + KEEP(*(.module_parameters)); _module_params_end = .; . = ALIGN(8); diff --git a/toolchain.inc b/toolchain.inc index f888d68..8241e25 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -66,6 +66,8 @@ CFLAGS_arm64 := -ffunction-sections -fdata-sections CFLAGS_mipsel := -mips32r2 -G 0 +CFLAGS_x86_32 := -ffunction-sections -fdata-sections + toolchain_to_dir = \ $(foreach arch,$(ARCH_SUPPORTED),\ $(eval CPPFLAGS_$(arch) += \

1 0

New patch to review for coreboot: d3e8ff7 crossgcc: fix copy-paste mistake on riscv make target
by Alexander Couzens 10 Mar '15

10 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8637 -gerrit commit d3e8ff7b449ff89a598caf7f40de3835ec930c7d Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Mar 10 20:24:34 2015 +0100 crossgcc: fix copy-paste mistake on riscv make target Change-Id: Id618595a321529770964b125f7490dcb08376643 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/crossgcc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 4c3e19e..2d344e3 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -12,7 +12,7 @@ build-aarch64: build-mips: bash ./buildgcc -G -p mips-elf -build-mips: +build-riscv: bash ./buildgcc -G -p riscv-elf .PHONY: build-i386-without-gdb

1 0

New patch to review for coreboot: 65cd54c x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE option
by Kyösti Mälkki 10 Mar '15

10 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8636 -gerrit commit 65cd54cffee881c4fb31f039590daa5d398bc9dc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Mar 10 07:25:35 2015 +0200 x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE option This was added to handle cases of Intel FSP platforms that had EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM. These boards were recently fixed. To support combination of EARLY_CBMEM_INIT without CAR migration was added maintenance effort with little benefits. You had no CBMEM console for romstage and the few timestamps you could store were circulated via PCI scratchpads or CMOS nvram. Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Kconfig | 8 -------- src/console/Kconfig | 2 +- src/cpu/amd/agesa/Kconfig | 1 - src/cpu/amd/pi/Kconfig | 1 - src/cpu/intel/ep80579/Kconfig | 1 - src/cpu/x86/car.c | 5 ++--- src/mainboard/asus/dsbf/Kconfig | 1 - src/mainboard/iwave/iWRainbowG6/Kconfig | 1 - src/mainboard/supermicro/x7db8/Kconfig | 1 - 9 files changed, 3 insertions(+), 18 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index dfb91fa..2087619 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -51,16 +51,8 @@ config ROMCC bool default n -config BROKEN_CAR_MIGRATE - def_bool n - help - Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and - manage CAR migration on S3 resume path only. Couple boards use - CAR_GLOBAL and never do CAR migration. - config LATE_CBMEM_INIT def_bool n - select BROKEN_CAR_MIGRATE help Enable this in chipset's Kconfig if northbridge does not implement early get_top_of_ram() call for romstage. CBMEM tables will be diff --git a/src/console/Kconfig b/src/console/Kconfig index 2969c0f..26e0866 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -186,7 +186,7 @@ config CONSOLE_CBMEM_BUFFER_SIZE config CONSOLE_PRERAM_BUFFER_BASE hex - default 0xabadbeef if !CACHE_AS_RAM || BROKEN_CAR_MIGRATE + default 0xabadbeef if !CACHE_AS_RAM || LATE_CBMEM_INIT default 0x0 config CONSOLE_PRERAM_BUFFER_SIZE diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 2aeb8d7..84d50c8 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -34,7 +34,6 @@ config CPU_AMD_AGESA select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE select SPI_FLASH if HAVE_ACPI_RESUME if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 3fa6263..6702a19 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -29,7 +29,6 @@ config CPU_AMD_PI select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE select SPI_FLASH if HAVE_ACPI_RESUME if CPU_AMD_PI diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig index 5d90611..062f101 100644 --- a/src/cpu/intel/ep80579/Kconfig +++ b/src/cpu/intel/ep80579/Kconfig @@ -6,7 +6,6 @@ config CPU_INTEL_EP80579 select ARCH_RAMSTAGE_X86_32 select SSE select SUPPORT_CPU_UCODE_IN_CBFS - select BROKEN_CAR_MIGRATE if CPU_INTEL_EP80579 diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 9f1a26e..18d74b2 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -149,9 +149,8 @@ static void do_car_migrate_hooks(void) void car_migrate_variables(void) { - if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE) && !IS_ENABLED(PLATFORM_USES_FSP)) + if (!IS_ENABLED(PLATFORM_USES_FSP)) do_car_migrate_variables(); - if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) - do_car_migrate_hooks(); + do_car_migrate_hooks(); } diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig index c130a9f..481d4fa 100644 --- a/src/mainboard/asus/dsbf/Kconfig +++ b/src/mainboard/asus/dsbf/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 select DRIVERS_GENERIC_IOAPIC - select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index e9ecede..7bca220 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_LAPIC select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 - select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig index f5b0e11..82a4ebb 100644 --- a/src/mainboard/supermicro/x7db8/Kconfig +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 select DRIVERS_GENERIC_IOAPIC - select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string

1 0

Patch set updated for coreboot: a354dbe ARM romstages: Support and fix COLLECT_TIMESTAMPS
by Kyösti Mälkki 10 Mar '15

10 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8021 -gerrit commit a354dbee94487589b5cd74011a3cc394ef668a34 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 08:50:36 2014 +0200 ARM romstages: Support and fix COLLECT_TIMESTAMPS Change-Id: I53959eb937c1db3c4211e23a6476340383a33c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/daisy/romstage.c | 12 ++++++++++++ src/mainboard/google/nyan/romstage.c | 12 ++++-------- src/mainboard/google/nyan_big/romstage.c | 12 ++++-------- src/mainboard/google/nyan_blaze/romstage.c | 12 ++++-------- src/mainboard/google/peach_pit/romstage.c | 11 +++++++++++ 5 files changed, 35 insertions(+), 24 deletions(-) diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index 9b35c4a..46c6593 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -22,6 +22,7 @@ #include <armv7.h> #include <cbfs.h> #include <cbmem.h> +#include <timestamp.h> #include <arch/cache.h> #include <arch/exception.h> @@ -147,6 +148,9 @@ void main(void) void *entry; int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = setup_clock(); @@ -155,8 +159,13 @@ void main(void) exception_init(); setup_power(is_resume); + + timestamp_add_now(TS_BEFORE_INITRAM); + setup_memory(mem, is_resume); + timestamp_add_now(TS_AFTER_INITRAM); + /* This needs to happen on normal boots and on resume. */ trustzone_init(); @@ -174,5 +183,8 @@ void main(void) cbmem_initialize_empty(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + + timestamp_add_now(TS_END_ROMSTAGE); + stage_exit(entry); } diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 749b87d..1af3c31 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -149,9 +149,8 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); -#endif + timestamp_init(0); + timestamp_add_now(TS_START_ROMSTAGE); configure_l2ctlr(); configure_l2actlr(); @@ -212,9 +211,6 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - // Enable additional peripherals we need for ROM stage. clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); @@ -225,10 +221,10 @@ static void __attribute__((noinline)) romstage(void) vboot_verify_firmware(romstage_handoff_find_or_add()); - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); stage_exit(entry); } diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 749b87d..1af3c31 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -149,9 +149,8 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); -#endif + timestamp_init(0); + timestamp_add_now(TS_START_ROMSTAGE); configure_l2ctlr(); configure_l2actlr(); @@ -212,9 +211,6 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - // Enable additional peripherals we need for ROM stage. clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); @@ -225,10 +221,10 @@ static void __attribute__((noinline)) romstage(void) vboot_verify_firmware(romstage_handoff_find_or_add()); - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); stage_exit(entry); } diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index a23937e..2e52648 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -149,9 +149,8 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); -#endif + timestamp_init(0); + timestamp_add_now(TS_START_ROMSTAGE); configure_l2ctlr(); configure_l2actlr(); @@ -212,9 +211,6 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - // Enable additional peripherals we need for ROM stage. clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); @@ -229,10 +225,10 @@ static void __attribute__((noinline)) romstage(void) vboot_verify_firmware(romstage_handoff_find_or_add()); #endif - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); stage_exit(entry); } diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 248809d..ce4e399 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -23,6 +23,7 @@ #include <armv7.h> #include <cbfs.h> #include <cbmem.h> +#include <timestamp.h> #include <arch/cache.h> #include <arch/exception.h> @@ -234,6 +235,9 @@ void main(void) exynos5420_config_smp(); power_init_failed = setup_power(is_resume); + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ system_clock_init(); @@ -248,8 +252,12 @@ void main(void) /* re-initialize PMIC I2C channel after (re-)setting system clocks */ i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ + timestamp_add_now(TS_BEFORE_INITRAM); + setup_memory(&mem_timings, is_resume); + timestamp_add_now(TS_AFTER_INITRAM); + primitive_mem_test(); trustzone_init(); @@ -272,5 +280,8 @@ void main(void) entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); simple_spi_test(); + + timestamp_add_now(TS_END_ROMSTAGE); + stage_exit(entry); }

1 0

Patch set updated for coreboot: 69ae99a cbmem console: Allow the cbmem console on non-x86 systems again.
by Kyösti Mälkki 10 Mar '15

10 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7748 -gerrit commit 69ae99aea7d1258222bb20e71e4de9a3950dea9d Author: Gabe Black <gabeblack(a)google.com> Date: Thu Apr 3 14:04:42 2014 -0700 cbmem console: Allow the cbmem console on non-x86 systems again. If it's not supported on a particular board, either the build will fail or checks within the cbmem console itself should detect the problem. There shouldn't be random memory corruption any more. BUG=None TEST=Built with CONSOLE_CBMEM enabled on nyan and saw that it was actually enabled. BRANCH=None Original-Change-Id: Id6c8c7675daafe07aa4878cfcf13faefe576e520 Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193167 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 20b486443bfc2d93d72bbc9e496023a00ab9ab30) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I39fbcdff61f6d8f520f2e9d7612dee78e97898b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 5974695..2969c0f 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -168,7 +168,6 @@ config CONSOLE_NE2K_IO_PORT boundary, qemu needs broader align) config CONSOLE_CBMEM - depends on ARCH_X86 bool "Send console output to a CBMEM buffer" default n help

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2015