coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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2443 discussions

New patch to review for coreboot: ae50a6f cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY
by Alexander Couzens 11 Mar '15

11 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8658 -gerrit commit ae50a6fa2d0b59fcb0c82e7001a92a5e4d1bcf9e Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Feb 24 03:07:02 2015 +0100 cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY BIOS Writer's Guide, rev 1.6.0, June 2012: This MSR controls whether and FERR message is sent over the system bus when unmasked x87 exceptions are generated. This feature is not supported from Sandy Bridge processor onwards. Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/cpu/intel/model_2065x/model_2065x.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 454f7be..649697f 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -35,6 +35,8 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 +#define IA32_FERR_CAPABILITY 0x1af +#define FERR_ENABLE (1 << 0) #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0

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New patch to review for coreboot: 9177028 mainboard/x201: correct sata_port_map
by Alexander Couzens 11 Mar '15

11 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8657 -gerrit commit 9177028537257696d3293b618e17ed2b81a3f7d0 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Feb 28 20:07:10 2015 +0100 mainboard/x201: correct sata_port_map x201 has 2 sata ports. 1 port for hard drive and 1 port over the dock. Tested on x201 with hdd in port 1 + cdrom in port 2. Change-Id: I1ee8c547392257d4f2e00a5d48e21447a84f79c0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/x201/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index ffd3add..402b9d4 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -99,7 +99,7 @@ chip northbridge/intel/nehalem register "gpi1_routing" = "2" register "gpi13_routing" = "2" - register "sata_port_map" = "0x33" + register "sata_port_map" = "0x03" register "gpe0_en" = "0x20022046" register "alt_gp_smi_en" = "0x0000"

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Patch set updated for coreboot: 06ae912 northbridge/amd/amdht: Allow mainboards to set HT frequency limit
by Timothy Pearson 11 Mar '15

11 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8464 -gerrit commit 06ae9127c7f958f29c7c2d80d8c98a5364a88348 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Feb 16 14:57:06 2015 -0600 northbridge/amd/amdht: Allow mainboards to set HT frequency limit This is useful when the PCB layout of a mainboard does not allow stable operation at the increased HyperTransport speeds of newer processors. Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/amdfam10.h | 7 ++++++ src/northbridge/amd/amdht/h3finit.c | 41 ++++++++++++++++++++++++++++++--- src/northbridge/amd/amdht/h3finit.h | 3 +++ src/northbridge/amd/amdht/ht_wrapper.c | 3 ++- 4 files changed, 50 insertions(+), 4 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 96f182d..a77d036 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -1002,6 +1003,10 @@ struct nodes_info_t { u32 up_planes; // down planes will be [up_planes, planes) } __attribute__((packed)); +struct ht_link_config { + uint8_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default) +}; + /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/ struct sys_info { @@ -1015,6 +1020,8 @@ struct sys_info { u8 host_link_freq[NODE_NUMS*8]; // record freq for every link from cpu, 0x0f means don't need to touch it u16 host_link_freq_cap[NODE_NUMS*8]; //cap + struct ht_link_config ht_link_cfg; + u32 segbit; u32 sbdn; u32 sblk; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 4059182..1e32956 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -75,6 +75,42 @@ static const uint16_t ht_speed_limit[16] = 0x00FF, 0x007F, 0x003F, 0x001F, 0x000F, 0x0007, 0x0003, 0x0001}; +typedef struct +{ + uint16_t mhz; + uint8_t config; +} ht_speed_limit_map_t; + +static const ht_speed_limit_map_t ht_speed_limit_map[16] = { + {0, NVRAM_LIMIT_HT_SPEED_AUTO}, + {200, NVRAM_LIMIT_HT_SPEED_200}, + {300, NVRAM_LIMIT_HT_SPEED_300}, + {400, NVRAM_LIMIT_HT_SPEED_400}, + {500, NVRAM_LIMIT_HT_SPEED_500}, + {600, NVRAM_LIMIT_HT_SPEED_600}, + {800, NVRAM_LIMIT_HT_SPEED_800}, + {1000, NVRAM_LIMIT_HT_SPEED_1000}, + {1200, NVRAM_LIMIT_HT_SPEED_1200}, + {1400, NVRAM_LIMIT_HT_SPEED_1400}, + {1600, NVRAM_LIMIT_HT_SPEED_1600}, + {1800, NVRAM_LIMIT_HT_SPEED_1800}, + {2000, NVRAM_LIMIT_HT_SPEED_2000}, + {2200, NVRAM_LIMIT_HT_SPEED_2200}, + {2400, NVRAM_LIMIT_HT_SPEED_2400}, + {2600, NVRAM_LIMIT_HT_SPEED_2600}, + }; + +static const uint16_t ht_speed_mhz_to_hw(uint16_t mhz) +{ + uint8_t i; + for (i = 0; i < 16; i++) + if (ht_speed_limit_map[i].mhz == mhz) + return ht_speed_limit_map[i].config; + + printk(BIOS_WARNING, "WARNING: Invalid HT link limit frequency %d specified, ignoring...\n", mhz); + return ht_speed_limit[NVRAM_LIMIT_HT_SPEED_AUTO]; +} + /*---------------------------------------------------------------------------- * TYPEDEFS AND STRUCTURES * @@ -1359,10 +1395,9 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) for (i = 0; i < pDat->TotalLinks*2; i += 2) { - /* FIXME - * Mainboards need to be able to set cbPCBFreqLimit - */ cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration + if (pDat->HtBlock->ht_link_configuration) + cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); #if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8 diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index 136a5cf..a56c246 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -462,6 +463,8 @@ typedef struct { const u8 *pEventData0 ); + const struct ht_link_config *ht_link_configuration; + } AMD_HTBLOCK; /* diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 3bf81c6..a38caa4 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -139,7 +139,8 @@ static void amd_ht_init(struct sys_info *sysinfo) NULL, // BOOL (*AMD_CB_CustomizeBuffers)(); NULL, // void (*AMD_CB_OverrideDevicePort)(); NULL, // void (*AMD_CB_OverrideCpuPort)(); - AMD_CB_EventNotify // void (*AMD_CB_EventNotify) (); + AMD_CB_EventNotify, // void (*AMD_CB_EventNotify) (); + &sysinfo->ht_link_cfg // struct ht_link_config* }; printk(BIOS_DEBUG, "Enter amd_ht_init()\n");

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Patch merged into coreboot/master: 48b3dbc x86 SMM: Replace weak prototypes with weak function stub
by gerrit＠coreboot.org 11 Mar '15

11 Mar '15

the following patch was just integrated into master: commit 48b3dbc7483f5404a2dfb3b8bb5f4bcf7d3c4b09 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 29 19:36:50 2014 +0200 x86 SMM: Replace weak prototypes with weak function stub Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/7961 for details. -gerrit

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Patch set updated for coreboot: 9fa9989 x86 SMM: Replace weak prototypes with weak function stub
by Kyösti Mälkki 11 Mar '15

11 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7961 -gerrit commit 9fa99899ae4cea30ecbbbb9b5e7a34098d64cf21 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 29 19:36:50 2014 +0200 x86 SMM: Replace weak prototypes with weak function stub Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/smm/smihandler.c | 21 +++++++++++++++------ src/include/cpu/x86/smm.h | 16 ++++++---------- src/southbridge/amd/agesa/hudson/smihandler.c | 6 ++---- src/southbridge/amd/pi/hudson/smihandler.c | 6 ++---- src/southbridge/intel/bd82x6x/smihandler.c | 16 ++++++---------- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 16 ++++++---------- src/southbridge/intel/i82801dx/smihandler.c | 10 ++++------ src/southbridge/intel/i82801gx/smihandler.c | 12 +++++------- src/southbridge/intel/i82801ix/smihandler.c | 12 +++++------- src/southbridge/intel/ibexpeak/smihandler.c | 16 ++++++---------- 10 files changed, 57 insertions(+), 74 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index bd03030..cbd6d44 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -199,12 +199,9 @@ void smi_handler(u32 smm_revision) } /* Call chipset specific SMI handlers. */ - if (cpu_smi_handler) - cpu_smi_handler(node, &state_save); - if (northbridge_smi_handler) - northbridge_smi_handler(node, &state_save); - if (southbridge_smi_handler) - southbridge_smi_handler(node, &state_save); + cpu_smi_handler(node, &state_save); + northbridge_smi_handler(node, &state_save); + southbridge_smi_handler(node, &state_save); smi_restore_pci_address(); @@ -215,3 +212,15 @@ void smi_handler(u32 smm_revision) /* De-assert SMI# signal to allow another SMI */ smi_set_eos(); } + +/* Provide a default implementation for all weak handlers so that relocation + * entries in the modules make sense. Without default implementations the + * weak relocations w/o a symbol have a 0 address which is where the modules + * are linked at. */ +int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; } +void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {} +int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; } +void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 7b529e0..c16a6c5 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -467,7 +467,7 @@ void smi_handler(u32 smm_revision); void io_trap_handler(int smif); int southbridge_io_trap_handler(int smif); -int __attribute__((weak)) mainboard_io_trap_handler(int smif); +int mainboard_io_trap_handler(int smif); void southbridge_smi_set_eos(void); @@ -475,18 +475,14 @@ void southbridge_smi_set_eos(void); void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); +#else +void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +#endif /* CONFIG_SMM_MODULES */ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); -#else -void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); - -void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts); -int __attribute__((weak)) mainboard_smi_apmc(u8 data); -void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ); -#endif /* CONFIG_SMM_MODULES */ #if !CONFIG_SMM_TSEG void smi_release_lock(void); diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index d1b661b..af8c215 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -41,8 +41,7 @@ static void hudson_apmc_smi_handler(void) break; } - if (mainboard_smi_apmc) - mainboard_smi_apmc(cmd); + mainboard_smi_apmc(cmd); } int southbridge_io_trap_handler(int smif) @@ -66,8 +65,7 @@ static void process_gpe_smi(void) /* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { /* A GEVENT SMI occurred */ - if (mainboard_smi_gpi) - mainboard_smi_gpi(status & gevent_mask); + mainboard_smi_gpi(status & gevent_mask); } /* Clear events to prevent re-entering SMI if event isn't handled */ diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index e762d0b..6f2504b 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -41,8 +41,7 @@ static void hudson_apmc_smi_handler(void) break; } - if (mainboard_smi_apmc) - mainboard_smi_apmc(cmd); + mainboard_smi_apmc(cmd); } int southbridge_io_trap_handler(int smif) @@ -66,8 +65,7 @@ static void process_gpe_smi(void) /* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { /* A GEVENT SMI occured */ - if (mainboard_smi_gpi) - mainboard_smi_gpi(status & gevent_mask); + mainboard_smi_gpi(status & gevent_mask); } /* Clear events to prevent re-entering SMI if event isn't handled */ diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 45612d0..f69c1f4 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -419,8 +419,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -607,8 +606,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -650,12 +648,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); } diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index c98e267..8164e7e 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -353,8 +353,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -541,8 +540,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -584,12 +582,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); } diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index e5a3282..6375876 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -441,12 +441,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index e2505ce..e83c722 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -369,7 +369,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); - if (mainboard_smi_apmc && mainboard_smi_apmc(reg8)) + if (mainboard_smi_apmc(reg8)) return; switch (reg8) { @@ -454,12 +454,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 45a09df..611429f 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -235,7 +235,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); - if (mainboard_smi_apmc && mainboard_smi_apmc(reg8)) + if (mainboard_smi_apmc(reg8)) return; switch (reg8) { @@ -322,12 +322,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e2032ad..019e6db 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -419,8 +419,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -607,8 +606,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -650,12 +648,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); }

1 0

New patch to review for coreboot: 0607afc x60, t60, x201, macbook21 : Declare GPIs for EC
by Kyösti Mälkki 10 Mar '15

10 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8656 -gerrit commit 0607afc985f375671188369807701f072e04d876 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 29 11:32:27 2014 +0200 x60,t60,x201,macbook21 : Declare GPIs for EC For lenovo/x201, this also changes GPI_ROUT (0xb8-0xbb) programming to use GPI1 between SCI/SMI modes, while previous programming was for GPI12. Change-Id: I3ac0feaa1d10c8f0e53a5fa5af72366503bb5d2d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/apple/macbook21/smihandler.c | 6 ++++-- src/mainboard/lenovo/t60/smihandler.c | 8 +++++--- src/mainboard/lenovo/x201/smihandler.c | 15 +++++++++------ src/mainboard/lenovo/x60/smihandler.c | 8 +++++--- 4 files changed, 23 insertions(+), 14 deletions(-) diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index 449e367..f90bb38 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -27,6 +27,8 @@ #include <pc80/mc146818rtc.h> #include <delay.h> +#define GPE_EC_SCI 12 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -69,7 +71,7 @@ int mainboard_smi_apmc(u8 data) switch(data) { case APM_CNT_ACPI_ENABLE: /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; @@ -77,7 +79,7 @@ int mainboard_smi_apmc(u8 data) break; case APM_CNT_ACPI_DISABLE: /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x01; diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 36495dc..3833ae2 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -28,6 +28,8 @@ #include "dock.h" #include "smi.h" +#define GPE_EC_SCI 12 + #define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */ /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler @@ -154,7 +156,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi) { - if (gpi & (1 << 12)) + if (gpi & (1 << GPE_EC_SCI)) mainboard_smi_handle_ec_sci(); } @@ -173,7 +175,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; @@ -184,7 +186,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x01; diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 7af613b..0cabf1a 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -34,6 +34,9 @@ #include "dock.h" #include "smi.h" +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -137,7 +140,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 1)) + if (gpi_sts & (1 << GPE_EC_SCI)) mainboard_smi_handle_ec_sci(); } @@ -173,7 +176,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; @@ -186,7 +189,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; @@ -211,11 +214,11 @@ void mainboard_smi_sleep(u8 slp_typ) u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + outl(inl(pmbase + GPE0_EN) | (1 << (16 + GPE_EC_WAKE)), pmbase + GPE0_EN); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); + gpe_rout &= ~(3 << (2 * GPE_EC_WAKE)); + gpe_rout |= (2 << (2 * GPE_EC_WAKE)); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); } } diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index ccc328e..fee54f2 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -31,6 +31,8 @@ #include "dock.h" #include "smi.h" +#define GPE_EC_SCI 12 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -160,7 +162,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi) { - if (gpi & (1 << 12)) + if (gpi & (1 << GPE_EC_SCI)) mainboard_smi_handle_ec_sci(); } @@ -179,7 +181,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; @@ -192,7 +194,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x01;

1 0

Patch set updated for coreboot: 6500813 intel SMI handlers: Refactor GPI SMI/SCI routing
by Kyösti Mälkki 10 Mar '15

10 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7967 -gerrit commit 650081314d082af04d963a6ca4cea77445e2f445 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 29 11:32:27 2014 +0200 intel SMI handlers: Refactor GPI SMI/SCI routing Move the GPI interrupt routing selection between SMI/SCI from mainboards to southbridge. There is speculation if this is all just legacy APM stuff that could be removed with a followup. Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/apple/macbook21/smihandler.c | 20 ++----------- src/mainboard/google/parrot/smihandler.c | 43 ++------------------------- src/mainboard/lenovo/t420s/smihandler.c | 34 +++------------------ src/mainboard/lenovo/t520/smihandler.c | 34 +++------------------ src/mainboard/lenovo/t530/smihandler.c | 34 +++------------------ src/mainboard/lenovo/t60/smihandler.c | 20 ++----------- src/mainboard/lenovo/x201/smihandler.c | 32 ++------------------ src/mainboard/lenovo/x220/smihandler.c | 34 +++------------------ src/mainboard/lenovo/x230/smihandler.c | 34 +++------------------ src/mainboard/lenovo/x60/smihandler.c | 20 ++----------- src/mainboard/packardbell/ms2290/smihandler.c | 24 +++++---------- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/bd82x6x/pch.h | 6 ++++ src/southbridge/intel/bd82x6x/smihandler.c | 36 ++++++++++++++++++++++ src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +- src/southbridge/intel/i82801gx/i82801gx.h | 7 +++++ src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 36 ++++++++++++++++++++++ src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/ibexpeak/pch.h | 6 ++++ src/southbridge/intel/ibexpeak/smihandler.c | 36 ++++++++++++++++++++++ src/southbridge/intel/lynxpoint/lpc.c | 2 +- 22 files changed, 170 insertions(+), 296 deletions(-) diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index f90bb38..5c6cd44 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -60,30 +60,14 @@ int mainboard_io_trap_handler(int smif) int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); - - if (!pmbase) - return 0; - switch(data) { case APM_CNT_ACPI_ENABLE: /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); break; default: break; diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 4a189f8..1d1b23c 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -29,44 +29,6 @@ #include <ec/compal/ene932/ec.h> #include "ec.h" -/* Power Management PCI Configuration Registers - * Bus 0, Device 31, Function 0, Offset 0xB8 - * 00 = No Effect - * 01 = SMI# - * 10 = SCI - * 11 = NMI - */ -#define GPI_ROUT 0x8000F8B8 -#define GPI_IS_SMI 0x01 -#define GPI_IS_SCI 0x02 - -static void set_lid_gpi_mode(u32 mode) -{ - u32 reg32 = 0; - u16 reg16 = 0; - - /* read the GPI register, clear the lid GPI's mode, write the new mode - * and write out the register. - */ - outl(GPI_ROUT, 0xcf8); - reg32 = inl(0xcfc); - reg32 &= ~(0x03 << (EC_LID_GPI * 2)); - reg32 |= (mode << (EC_LID_GPI * 2)); - outl(GPI_ROUT, 0xcf8); - outl(reg32, 0xcfc); - - /* Set or Disable Lid GPE as SMI source in the ALT_GPI_SMI_EN register. */ - reg16 = inw(smm_get_pmbase() + ALT_GP_SMI_EN); - if (mode == GPI_IS_SCI) { - reg16 &= ~(1 << EC_LID_GPI); - } else { - reg16 |= (1 << EC_LID_GPI); - } - outw(reg16, smm_get_pmbase() + ALT_GP_SMI_EN); - - return; -} - int mainboard_io_trap_handler(int smif) { printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif); @@ -200,8 +162,7 @@ int mainboard_smi_apmc(u8 apmc) ec_kbc_write_ib(0xE8); /* Set LID GPI to generate SCIs */ - set_lid_gpi_mode(GPI_IS_SCI); - + gpi_route_interrupt(EC_LID_GPI, GPI_IS_SCI); break; case APMC_ACPI_DIS: printk(BIOS_DEBUG, "APMC: ACPI_DIS\n"); @@ -211,7 +172,7 @@ int mainboard_smi_apmc(u8 apmc) ec_kbc_write_ib(0xE9); /* Set LID GPI to generate SMIs */ - set_lid_gpi_mode(GPI_IS_SMI); + gpi_route_interrupt(EC_LID_GPI, GPI_IS_SMI); break; } return 0; diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index 27a33cf..430ad1b 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -119,25 +119,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route EC_SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -145,13 +132,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route EC_SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -182,16 +164,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); - gpe_rout |= (2 << (GPE_EC_WAKE * 2)); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index 479ce0a..4d874fd 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -114,25 +114,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route EC_SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -140,13 +127,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route EC_SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -177,16 +159,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); - gpe_rout |= (2 << (GPE_EC_WAKE * 2)); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index 372f280..8208fe7 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -119,25 +119,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route EC_SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -145,13 +132,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route EC_SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -182,16 +164,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); - gpe_rout |= (2 << (GPE_EC_WAKE * 2)); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 3833ae2..6e46bfd 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -162,35 +162,19 @@ void mainboard_smi_gpi(u32 gpi) int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); - - if (!pmbase) - return 0; - switch(data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); break; default: break; diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 0cabf1a..541cd4f 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -148,15 +148,6 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "APMC: FINALIZE\n"); @@ -176,11 +167,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -189,12 +176,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -210,16 +192,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << (16 + GPE_EC_WAKE)), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << (2 * GPE_EC_WAKE)); - gpe_rout |= (2 << (2 * GPE_EC_WAKE)); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 372f280..8208fe7 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -119,25 +119,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route EC_SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -145,13 +132,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route EC_SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -182,16 +164,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); - gpe_rout |= (2 << (GPE_EC_WAKE * 2)); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index 372f280..8208fe7 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -119,25 +119,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route EC_SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -145,13 +132,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route EC_SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -182,16 +164,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); - gpe_rout |= (2 << (GPE_EC_WAKE * 2)); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index fee54f2..be6efce 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -168,24 +168,12 @@ void mainboard_smi_gpi(u32 gpi) int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); - - if (!pmbase) - return 0; - switch(data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -194,11 +182,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index f04ff90..eda17f3 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -31,6 +31,9 @@ #include <pc80/mc146818rtc.h> #include <delay.h> +/* This GPI is not confirmed. */ +#define MS2290_ENABLE_GPI12 1 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -69,15 +72,6 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "APMC: FINALIZE\n"); @@ -94,16 +88,12 @@ int mainboard_smi_apmc(u8 data) mainboard_finalized = 1; break; case APM_CNT_ACPI_ENABLE: - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + if (MS2290_ENABLE_GPI12) + gpi_route_interrupt(12, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + if (MS2290_ENABLE_GPI12) + gpi_route_interrupt(12, GPI_IS_SMI); break; default: break; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c323f73..6062131 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -167,7 +167,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 029da9f..6faceeb 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -70,6 +70,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void gpi_route_interrupt(u8 gpi, u8 mode); #if CONFIG_ELOG void pch_log_state(void); #endif @@ -146,7 +147,12 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ + #define GPIO_ROUT 0xb8 +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 45612d0..8f69af9 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -75,6 +75,42 @@ void tseg_relocate(void **ptr) } #endif +static void alt_gpi_mask(u16 clr, u16 set) +{ + u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); + alt_gp &= ~clr; + alt_gp |= set; + outw(alt_gp, pmbase + ALT_GP_SMI_EN); +} + +static void gpe0_mask(u32 clr, u32 set) +{ + u32 gpe0 = inl(pmbase + GPE0_EN); + gpe0 &= ~clr; + gpe0 |= set; + outl(gpe0, pmbase + GPE0_EN); +} + +void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + if (gpi >= 16) + return; + + alt_gpi_mask(1 << gpi, 0); + gpe0_mask(1 << (gpi+16), 0); + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); + + if (mode == GPI_IS_SCI) + gpe0_mask(0, 1 << (gpi+16)); + else if (mode == GPI_IS_SMI) + alt_gpi_mask(0, 1 << gpi); +} + /** * @brief read and clear PM1_STS * @return PM1_STS register diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index f9961f9..6b95d08 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -185,7 +185,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 4624841..815768b 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -45,6 +45,7 @@ #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); +void gpi_route_interrupt(u8 gpi, u8 mode); #else void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); @@ -78,6 +79,12 @@ int southbridge_detect_s3_resume(void); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 +#define GPIO_ROUT 0xb8 +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index cbc0106..39e1658 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -158,7 +158,7 @@ static void i82801gx_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void i82801gx_power_options(device_t dev) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index e2505ce..fb439c6 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -50,6 +50,42 @@ u8 smm_initialized = 0; */ global_nvs_t *gnvs = (global_nvs_t *)0x0; +static void alt_gpi_mask(u16 clr, u16 set) +{ + u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); + alt_gp &= ~clr; + alt_gp |= set; + outw(alt_gp, pmbase + ALT_GP_SMI_EN); +} + +static void gpe0_mask(u32 clr, u32 set) +{ + u32 gpe0 = inl(pmbase + GPE0_EN); + gpe0 &= ~clr; + gpe0 |= set; + outl(gpe0, pmbase + GPE0_EN); +} + +void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + if (gpi >= 16) + return; + + alt_gpi_mask(1 << gpi, 0); + gpe0_mask(1 << (gpi+16), 0); + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); + + if (mode == GPI_IS_SCI) + gpe0_mask(0, 1 << (gpi+16)); + else if (mode == GPI_IS_SMI) + alt_gpi_mask(0, 1 << gpi); +} + /** * @brief read and clear PM1_STS * @return PM1_STS register diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index db73b0a..9550a9e 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -166,7 +166,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 12e9345..23eb6cd 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -71,6 +71,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void gpi_route_interrupt(u8 gpi, u8 mode); #if CONFIG_ELOG void pch_log_state(void); #endif @@ -133,7 +134,12 @@ void southbridge_configure_default_intmap(void); #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ + #define GPIO_ROUT 0xb8 +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e2032ad..95530c4 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -75,6 +75,42 @@ void tseg_relocate(void **ptr) } #endif +static void alt_gpi_mask(u16 clr, u16 set) +{ + u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); + alt_gp &= ~clr; + alt_gp |= set; + outw(alt_gp, pmbase + ALT_GP_SMI_EN); +} + +static void gpe0_mask(u32 clr, u32 set) +{ + u32 gpe0 = inl(pmbase + GPE0_EN); + gpe0 &= ~clr; + gpe0 |= set; + outl(gpe0, pmbase + GPE0_EN); +} + +void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + if (gpi >= 16) + return; + + alt_gpi_mask(1 << gpi, 0); + gpe0_mask(1 << (gpi+16), 0); + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); + + if (mode == GPI_IS_SCI) + gpe0_mask(0, 1 << (gpi+16)); + else if (mode == GPI_IS_SMI) + alt_gpi_mask(0, 1 << gpi); +} + /** * @brief read and clear PM1_STS * @return PM1_STS register diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d753bea..d83ec0a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -175,7 +175,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev)

1 0

Patch set updated for coreboot: 075ae80 global: Refactor get_option usage
by Varad Gautam 10 Mar '15

10 Mar '15

Varad Gautam (varadgautam(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8631 -gerrit commit 075ae80f70f813fa1db461611c41af2824f557a5 Author: Varad Gautam <varadgautam(a)gmail.com> Date: Wed Mar 11 09:54:41 2015 +0530 global: Refactor get_option usage Restructure get_option() calls to avoid unnecessary return value checks by pre-assigning defaults to the options being retrieved. Change-Id: I9159afe149a8eeed0785d1efd6eee8420b88b8f4 Signed-off-by: Varad Gautam <varadgautam(a)gmail.com> --- src/console/init.c | 4 ++-- src/cpu/amd/model_fxx/model_fxx_init.c | 5 ++--- src/mainboard/ibase/mb899/superio_hwm.c | 26 +++++++++++++------------- src/mainboard/kontron/986lcd-m/mainboard.c | 26 +++++++++++++------------- src/northbridge/amd/amdk8/misc_control.c | 5 ++--- src/southbridge/amd/sb600/sata.c | 6 ++---- src/southbridge/intel/i82801dx/lpc.c | 4 ++-- src/southbridge/intel/i82801gx/lpc.c | 4 ++-- src/southbridge/intel/i82801ix/lpc.c | 4 ++-- 9 files changed, 40 insertions(+), 44 deletions(-) diff --git a/src/console/init.c b/src/console/init.c index e638216..1fbe22a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -37,8 +37,8 @@ int console_log_level(int msg_level) void console_init(void) { #if !defined(__PRE_RAM__) - if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS) - console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; + console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; + get_option(&console_loglevel, "debug_level"); #endif #if CONFIG_EARLY_PCI_BRIDGE && !defined(__SMM__) diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 341bb62..a6561ee 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -250,9 +250,8 @@ static void init_ecc_memory(unsigned node_id) } /* See if we scrubbing should be enabled */ - enable_scrubbing = 1; - if (get_option(&enable_scrubbing, "hw_scrubber") != CB_SUCCESS) - enable_scrubbing = CONFIG_HW_SCRUBBER; + enable_scrubbing = CONFIG_HW_SCRUBBER; + get_option(&enable_scrubbing, "hw_scrubber"); /* Enable cache scrubbing at the lowest possible rate */ if (enable_scrubbing) { diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 7864264..4c7d123 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -80,19 +80,19 @@ void hwm_setup(void) int cpufan_speed = 0, sysfan_speed = 0; int cpufan_temperature = 0, sysfan_temperature = 0; - if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) - cpufan_speed = FAN_SPEED_5625; - //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) - // cpufan_temperature = FAN_TEMPERATURE_30DEGC; - - if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) - sysfan_speed = FAN_SPEED_5625; - //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) - // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&cpufan_control, "cpufan_cruise_control"); + cpufan_speed = FAN_SPEED_5625; + get_option(&cpufan_speed, "cpufan_speed"); + //cpufan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&cpufan_temperature, "cpufan_temperature"); + + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&sysfan_control, "sysfan_cruise_control"); + sysfan_speed = FAN_SPEED_5625; + get_option(&sysfan_speed, "sysfan_speed"); + //sysfan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&sysfan_temperature, "sysfan_temperature"); // hwm_write(0x31, 0x20); // AVCC high limit // hwm_write(0x34, 0x06); // VIN2 low limit diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index afca796..d943127 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -79,19 +79,19 @@ static void hwm_setup(void) int cpufan_speed = 0, sysfan_speed = 0; int cpufan_temperature = 0, sysfan_temperature = 0; - if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) - cpufan_speed = FAN_SPEED_5625; - //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) - // cpufan_temperature = FAN_TEMPERATURE_30DEGC; - - if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) - sysfan_speed = FAN_SPEED_5625; - //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) - // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&cpufan_control, "cpufan_cruise_control"); + cpufan_speed = FAN_SPEED_5625; + get_option(&cpufan_speed, "cpufan_speed"); + //cpufan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&cpufan_temperature, "cpufan_temperature"); + + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&sysfan_control, "sysfan_cruise_control"); + sysfan_speed = FAN_SPEED_5625; + get_option(&sysfan_speed, "sysfan_speed"); + //sysfan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&sysfan_temperature, "sysfan_temperature"); // hwm_write(0x31, 0x20); // AVCC high limit // hwm_write(0x34, 0x06); // VIN2 low limit diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 956692d..9b521ee 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -47,9 +47,8 @@ static void mcf3_read_resources(device_t dev) return; } - iommu = 1; - if (get_option(&iommu, "iommu") != CB_SUCCESS) - iommu = CONFIG_IOMMU; + iommu = CONFIG_IOMMU; + get_option(&iommu, "iommu"); if (iommu) { /* Add a GART aperture resource */ diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index 2ff7182..34ac0ac 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -119,10 +119,8 @@ static void sata_init(struct device *dev) pci_write_config8(dev, 0x40, byte); // 1 means IDE, 0 means AHCI - if (get_option(&i, "sata_mode") != CB_SUCCESS) { - // no cmos option - i = CONFIG_SATA_MODE; - } + i = CONFIG_SATA_MODE; + get_option(&i, "sata_mode"); printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" ); dword = pci_read_config32(dev, 0x8); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 83d6178..2f3db86 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -116,8 +116,8 @@ static void i82801dx_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) - pwr_on = MAINBOARD_POWER_ON; + pwr_on = MAINBOARD_POWER_ON; + get_option(&pwr_on, "power_on_after_fail"); reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index cbc0106..b8edfe3 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -179,8 +179,8 @@ static void i82801gx_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) - pwr_on = MAINBOARD_POWER_ON; + pwr_on = MAINBOARD_POWER_ON; + get_option(&pwr_on, "power_on_after_fail"); reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 0ba33d6..4f576c4 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -186,8 +186,8 @@ static void i82801ix_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) - pwr_on = MAINBOARD_POWER_ON; + pwr_on = MAINBOARD_POWER_ON; + get_option(&pwr_on, "power_on_after_fail"); reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); reg8 &= 0xfe;

1 0

New patch to review for coreboot: 245850b vboot2: translate shared data to hand off to depthcharge
by Aaron Durbin 10 Mar '15

10 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8655 -gerrit commit 245850b010f1d079cd21611aabf25621856c3261 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Jun 30 08:51:39 2014 -0700 vboot2: translate shared data to hand off to depthcharge TEST=Built Blaze with USE=+/-vboot2. Ran faft: CorruptBothFwAB, CorruptBothFWSigAB, CorruptFwBodyA/B, CoccurptFwSigA/B, DevBootUSB, DevMode, TryFwB, UserRequestRecovery, SelfSignedBoot, RollbackFirmware. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I45a1efd4d55fde37cc67fc02642fed0bc9366469 Original-Reviewed-on: https://chromium-review.googlesource.com/205236 Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> (cherry picked from commit 0a9e7f099251c33ce286fa8d704a3e021eac4d3e) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I5f61c03c66ca83a5837c14378905ba178aba5300 --- src/lib/coreboot_table.c | 2 +- src/mainboard/google/nyan_blaze/romstage.c | 2 +- src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/chromeos.h | 1 + src/vendorcode/google/chromeos/vboot_handoff.c | 142 +++++++++++++++++++++++++ src/vendorcode/google/chromeos/vboot_handoff.h | 1 + 6 files changed, 147 insertions(+), 2 deletions(-) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index abcb0ed..9112cd1 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -191,7 +191,7 @@ static void lb_vbnv(struct lb_header *header) #endif } -#if CONFIG_VBOOT_VERIFY_FIRMWARE +#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE static void lb_vboot_handoff(struct lb_header *header) { void *addr; diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index a23937e..c22a564 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -224,7 +224,7 @@ static void __attribute__((noinline)) romstage(void) configure_tpm_i2c_bus(); #if CONFIG_VBOOT2_VERIFY_FIRMWARE - // vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS); + vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS); #else vboot_verify_firmware(romstage_handoff_find_or_add()); #endif diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index c8781dd..1fcb42e 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -102,6 +102,7 @@ INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include INCLUDES += -I$(VB_SOURCE)/firmware/include verstage-y += vboot_main.c fmap.c chromeos.c verstage-y += antirollback.c vbnv_ec.c +romstage-y += vboot_handoff.c VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y)) VB2_LIB = $(obj)/external/vboot_reference/vboot_fw2.a diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index a799528..724ff57 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -88,6 +88,7 @@ static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} #if CONFIG_VBOOT2_VERIFY_FIRMWARE void select_firmware(void); +void vboot_create_handoff(void * vboot_workbuf); #endif #endif diff --git a/src/vendorcode/google/chromeos/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot_handoff.c new file mode 100644 index 0000000..3b276aa --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_handoff.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <2recovery_reasons.h> +#include <2struct.h> +#include <stdint.h> +#include <stddef.h> +#include <string.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <console/vtxprintf.h> +#include <stdlib.h> +#include <timestamp.h> +#include "chromeos.h" +#include "fmap.h" +#include "vboot_handoff.h" +#include <vboot_struct.h> + +/** + * Sets vboot_handoff based on the information in vb2_shared_data + * + * TODO: Read wp switch to set VBSD_BOOT_FIRMWARE_WP_ENABLED + */ +static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, + struct vb2_shared_data *vb2_sd) +{ + VbSharedDataHeader *vb_sd = + (VbSharedDataHeader *)vboot_handoff->shared_data; + uint32_t *oflags = &vboot_handoff->init_params.out_flags; + + vb_sd->flags |= VBSD_BOOT_FIRMWARE_VBOOT2; + + vboot_handoff->selected_firmware = vb2_sd->fw_slot; + + /* TODO: fw_slot is never 0xff while firmware_index can. */ + vb_sd->firmware_index = vb2_sd->fw_slot; + + vb_sd->magic = VB_SHARED_DATA_MAGIC; + vb_sd->struct_version = VB_SHARED_DATA_VERSION; + vb_sd->struct_size = sizeof(VbSharedDataHeader); + vb_sd->data_size = VB_SHARED_DATA_MIN_SIZE; + vb_sd->data_used = sizeof(VbSharedDataHeader); + + if (vb2_sd->recovery_reason) { + vb_sd->firmware_index = 0xFF; + if (vb2_sd->recovery_reason == VB2_RECOVERY_RO_MANUAL) + vb_sd->flags |= VBSD_BOOT_REC_SWITCH_ON; + *oflags |= VB_INIT_OUT_ENABLE_RECOVERY; + *oflags |= VB_INIT_OUT_CLEAR_RAM; + *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; + *oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE; + } + if (vb2_sd->flags & VB2_SD_DEV_MODE_ENABLED) { + *oflags |= VB_INIT_OUT_ENABLE_DEVELOPER; + *oflags |= VB_INIT_OUT_CLEAR_RAM; + *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; + *oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE; + vb_sd->flags |= VBSD_BOOT_DEV_SWITCH_ON; + vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; + } + if (CONFIG_VIRTUAL_DEV_SWITCH) + vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH; + if (CONFIG_EC_SOFTWARE_SYNC) { + vb_sd->flags |= VBSD_EC_SOFTWARE_SYNC; + vb_sd->flags |= VBSD_BOOT_REC_SWITCH_VIRTUAL; + } + /* In vboot1, VBSD_FWB_TRIED is + * set only if B is booted as explicitly requested. Therefore, if B is + * booted because A was found bad, the flag should not be set. It's + * better not to touch it if we can only ambiguously control it. */ + /* if (vb2_sd->fw_slot) + vb_sd->flags |= VBSD_FWB_TRIED; */ + + /* copy kernel subkey if it's found */ + if (vb2_sd->workbuf_preamble_size) { + struct vb2_fw_preamble *fp; + uintptr_t dst, src; + printk(BIOS_ERR, "Copying FW preamble\n"); + fp = (struct vb2_fw_preamble *)( (uintptr_t)vb2_sd + + vb2_sd->workbuf_preamble_offset); + src = (uintptr_t)&fp->kernel_subkey + fp->kernel_subkey.key_offset; + dst = (uintptr_t)vb_sd + sizeof(VbSharedDataHeader); + memcpy((void *)dst, (void *)src, fp->kernel_subkey.key_size); + vb_sd->data_used += fp->kernel_subkey.key_size; + vb_sd->kernel_subkey.key_offset = + dst - (uintptr_t)&vb_sd->kernel_subkey; + vb_sd->kernel_subkey.key_size = fp->kernel_subkey.key_size; + vb_sd->kernel_subkey.algorithm = fp->kernel_subkey.algorithm; + vb_sd->kernel_subkey.key_version = fp->kernel_subkey.key_version; + } + + vb_sd->recovery_reason = vb2_sd->recovery_reason; +} + +/** + * Create vboot handoff struct + * + * struct vboot_handoff { + * VbInitParams init_params; + * uint32_t selected_firmware; + * struct firmware_component components[MAX_PARSED_FW_COMPONENTS]; + * char shared_data[VB_SHARED_DATA_MIN_SIZE]; + * } __attribute__((packed)); + */ +void vboot_create_handoff(void *vboot_workbuf) +{ + struct vboot_handoff *vh; + struct vb2_shared_data *sd; + + sd = (struct vb2_shared_data *)vboot_workbuf; + sd->workbuf_hash_offset = 0; + sd->workbuf_hash_size = 0; + + printk(BIOS_INFO, "Creating vboot_handoff structure\n"); + vh = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, sizeof(*vh)); + + if (vh == NULL) { + printk(BIOS_ERR, "Could not add vboot_handoff structure\n"); + return; + } + + memset(vh, 0, sizeof(*vh)); + + fill_vboot_handoff(vh, sd); +} diff --git a/src/vendorcode/google/chromeos/vboot_handoff.h b/src/vendorcode/google/chromeos/vboot_handoff.h index 09c7897..e1e519f 100644 --- a/src/vendorcode/google/chromeos/vboot_handoff.h +++ b/src/vendorcode/google/chromeos/vboot_handoff.h @@ -20,6 +20,7 @@ #define VBOOT_HANDOFF_H #include <vboot_api.h> +#include <vboot_struct.h> /* * The vboot handoff structure keeps track of a maximum number of firmware

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New patch to review for coreboot: 23e2df9 chromeos: rename for easier patch merging
by Aaron Durbin 10 Mar '15

10 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8654 -gerrit commit 23e2df9812c9f464e5c7f86817cdca5fb9986910 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 10 18:20:58 2015 -0500 chromeos: rename for easier patch merging In order to more cleanly apply upcoming changes some files will need to do a dance. Change-Id: Ib50670743c10221785447490190ecdbff8c764fe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/Makefile.inc | 4 +- src/vendorcode/google/chromeos/vboot_handoff.c | 175 ------------------------- src/vendorcode/google/chromeos/vboot_helper.c | 175 +++++++++++++++++++++++++ 3 files changed, 177 insertions(+), 177 deletions(-) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 4438a92..c8781dd 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -38,8 +38,8 @@ CFLAGS_common += -DMOCK_TPM=0 endif ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) -romstage-y += vboot_handoff.c -ramstage-y += vboot_handoff.c +romstage-y += vboot_helper.c +ramstage-y += vboot_helper.c romstage-y += vboot_loader.c rmodules_$(ARCH-romstage-y)-y += vboot_wrapper.c diff --git a/src/vendorcode/google/chromeos/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot_handoff.c deleted file mode 100644 index 7ea21ea..0000000 --- a/src/vendorcode/google/chromeos/vboot_handoff.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stddef.h> -#include <string.h> -#include "chromeos.h" -#include <boot/coreboot_tables.h> -#include <cbfs.h> -#include <cbmem.h> -#include <console/console.h> -#include <payload_loader.h> -#include "vboot_handoff.h" - -int vboot_enable_developer(void) -{ - struct vboot_handoff *vbho; - - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vbho == NULL) { - printk(BIOS_ERR, "%s: Couldn't find vboot_handoff structure!\n", - __func__); - return 0; - } - - return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER); -} - -int vboot_enable_recovery(void) -{ - struct vboot_handoff *vbho; - - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vbho == NULL) - return 0; - - return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_RECOVERY); -} - -int __attribute__((weak)) clear_recovery_mode_switch(void) -{ - // Can be implemented by a mainboard - return 0; -} - -int vboot_skip_display_init(void) -{ - struct vboot_handoff *vbho; - - vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vbho == NULL) - return 0; - - return !(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DISPLAY); -} - -void *vboot_get_region(uintptr_t offset_addr, size_t size, void *dest) -{ - if (IS_ENABLED(CONFIG_SPI_FLASH_MEMORY_MAPPED)) { - if (dest != NULL) - return memcpy(dest, (void *)offset_addr, size); - else - return (void *)offset_addr; - } else { - struct cbfs_media default_media, *media = &default_media; - void *cache; - - init_default_cbfs_media(media); - media->open(media); - if (dest != NULL) { - cache = dest; - if (media->read(media, dest, offset_addr, size) != size) - cache = NULL; - } else { - cache = media->map(media, offset_addr, size); - if (cache == CBFS_MEDIA_INVALID_MAP_ADDRESS) - cache = NULL; - } - media->close(media); - return cache; - } -} - -int __attribute((weak)) vboot_get_sw_write_protect(void) -{ - // Can be implemented by a platform / mainboard - return 0; -} - -#if CONFIG_VBOOT2_VERIFY_FIRMWARE - -void *vboot_get_payload(int *len) { return NULL; } - -#else /* CONFIG_VBOOT2_VERIFY_FIRMWARE */ - -static void *vboot_get_payload(size_t *len) -{ - struct vboot_handoff *vboot_handoff; - struct firmware_component *fwc; - - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vboot_handoff == NULL) - return NULL; - - if (CONFIG_VBOOT_BOOT_LOADER_INDEX >= MAX_PARSED_FW_COMPONENTS) { - printk(BIOS_ERR, "Invalid boot loader index: %d\n", - CONFIG_VBOOT_BOOT_LOADER_INDEX); - return NULL; - } - - fwc = &vboot_handoff->components[CONFIG_VBOOT_BOOT_LOADER_INDEX]; - - if (len != NULL) - *len = fwc->size; - - printk(BIOS_DEBUG, "Booting 0x%x byte payload at 0x%08x.\n", - fwc->size, fwc->address); - - return (void *)fwc->address; -} -#endif - -static int vboot_locate_payload(struct payload *payload) -{ - void *buffer; - size_t size; - - buffer = vboot_get_payload(&size); - - if (buffer == NULL) - return -1; - - payload->backing_store.data = buffer; - payload->backing_store.size = size; - - return 0; -} - -const struct payload_loader_ops vboot_payload_loader = { - .name = "VBOOT", - .locate = vboot_locate_payload, -}; - -int vboot_get_handoff_info(void **addr, uint32_t *size) -{ - struct vboot_handoff *vboot_handoff; - - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vboot_handoff == NULL) - return -1; - - *addr = vboot_handoff; - *size = sizeof(*vboot_handoff); - return 0; -} diff --git a/src/vendorcode/google/chromeos/vboot_helper.c b/src/vendorcode/google/chromeos/vboot_helper.c new file mode 100644 index 0000000..7ea21ea --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_helper.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <string.h> +#include "chromeos.h" +#include <boot/coreboot_tables.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <payload_loader.h> +#include "vboot_handoff.h" + +int vboot_enable_developer(void) +{ + struct vboot_handoff *vbho; + + vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vbho == NULL) { + printk(BIOS_ERR, "%s: Couldn't find vboot_handoff structure!\n", + __func__); + return 0; + } + + return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER); +} + +int vboot_enable_recovery(void) +{ + struct vboot_handoff *vbho; + + vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vbho == NULL) + return 0; + + return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_RECOVERY); +} + +int __attribute__((weak)) clear_recovery_mode_switch(void) +{ + // Can be implemented by a mainboard + return 0; +} + +int vboot_skip_display_init(void) +{ + struct vboot_handoff *vbho; + + vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vbho == NULL) + return 0; + + return !(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DISPLAY); +} + +void *vboot_get_region(uintptr_t offset_addr, size_t size, void *dest) +{ + if (IS_ENABLED(CONFIG_SPI_FLASH_MEMORY_MAPPED)) { + if (dest != NULL) + return memcpy(dest, (void *)offset_addr, size); + else + return (void *)offset_addr; + } else { + struct cbfs_media default_media, *media = &default_media; + void *cache; + + init_default_cbfs_media(media); + media->open(media); + if (dest != NULL) { + cache = dest; + if (media->read(media, dest, offset_addr, size) != size) + cache = NULL; + } else { + cache = media->map(media, offset_addr, size); + if (cache == CBFS_MEDIA_INVALID_MAP_ADDRESS) + cache = NULL; + } + media->close(media); + return cache; + } +} + +int __attribute((weak)) vboot_get_sw_write_protect(void) +{ + // Can be implemented by a platform / mainboard + return 0; +} + +#if CONFIG_VBOOT2_VERIFY_FIRMWARE + +void *vboot_get_payload(int *len) { return NULL; } + +#else /* CONFIG_VBOOT2_VERIFY_FIRMWARE */ + +static void *vboot_get_payload(size_t *len) +{ + struct vboot_handoff *vboot_handoff; + struct firmware_component *fwc; + + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vboot_handoff == NULL) + return NULL; + + if (CONFIG_VBOOT_BOOT_LOADER_INDEX >= MAX_PARSED_FW_COMPONENTS) { + printk(BIOS_ERR, "Invalid boot loader index: %d\n", + CONFIG_VBOOT_BOOT_LOADER_INDEX); + return NULL; + } + + fwc = &vboot_handoff->components[CONFIG_VBOOT_BOOT_LOADER_INDEX]; + + if (len != NULL) + *len = fwc->size; + + printk(BIOS_DEBUG, "Booting 0x%x byte payload at 0x%08x.\n", + fwc->size, fwc->address); + + return (void *)fwc->address; +} +#endif + +static int vboot_locate_payload(struct payload *payload) +{ + void *buffer; + size_t size; + + buffer = vboot_get_payload(&size); + + if (buffer == NULL) + return -1; + + payload->backing_store.data = buffer; + payload->backing_store.size = size; + + return 0; +} + +const struct payload_loader_ops vboot_payload_loader = { + .name = "VBOOT", + .locate = vboot_locate_payload, +}; + +int vboot_get_handoff_info(void **addr, uint32_t *size) +{ + struct vboot_handoff *vboot_handoff; + + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vboot_handoff == NULL) + return -1; + + *addr = vboot_handoff; + *size = sizeof(*vboot_handoff); + return 0; +}

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coreboot-gerrit March 2015