coreboot-gerrit March 2015

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Patch set updated for coreboot: 181ca73 vboot2: read secdata and nvdata
by Aaron Durbin 10 Mar '15

10 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8615 -gerrit commit 181ca73b75789199788c299042d6a35936c53ea7 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Tue Jul 15 19:47:32 2014 -0700 vboot2: read secdata and nvdata This code ports antirollback module and tpm library from platform/vboot_reference. names are modified to conform to coreboot's style. The rollback_index module is split in a bottom half and top half. The top half contains generic code which hides the underlying storage implementation. The bottom half implements the storage abstraction. With this change, the bottom half is moved to coreboot, while the top half stays in vboot_reference. TEST=Built with USE=+/-vboot2 for Blaze. Built Samus, Link. BUG=none Branch=none Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I77e3ae1a029e09d3cdefe8fd297a3b432bbb9e9e Original-Reviewed-on: https://chromium-review.googlesource.com/206065 Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> Original-Reviewed-by: Luigi Semenzato <semenzato(a)chromium.org> (cherry picked from commit 6b66140ac979a991237bf1fe25e0a55244a406d0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia3b8f27d6b1c2055e898ce716c4a93782792599c --- src/drivers/i2c/tpm/Makefile.inc | 1 + src/include/antirollback.h | 138 +----- src/include/tpm_lite/tlcl.h | 116 +---- src/lib/Makefile.inc | 1 + src/lib/tlcl.c | 600 ++++++++++--------------- src/lib/tlcl_internal.h | 34 +- src/soc/nvidia/tegra124/Makefile.inc | 3 + src/soc/nvidia/tegra124/bootblock.c | 81 +++- src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/antirollback.c | 602 +++++--------------------- src/vendorcode/google/chromeos/vboot_main.c | 81 +++- 11 files changed, 559 insertions(+), 1099 deletions(-) diff --git a/src/drivers/i2c/tpm/Makefile.inc b/src/drivers/i2c/tpm/Makefile.inc index e06097f..55c01de 100644 --- a/src/drivers/i2c/tpm/Makefile.inc +++ b/src/drivers/i2c/tpm/Makefile.inc @@ -1,2 +1,3 @@ ramstage-$(CONFIG_I2C_TPM) += tis.c tpm.c romstage-$(CONFIG_I2C_TPM) += tis.c tpm.c +verstage-$(CONFIG_I2C_TPM) += tis.c tpm.c \ No newline at end of file diff --git a/src/include/antirollback.h b/src/include/antirollback.h index dd0de32..0473e24 100644 --- a/src/include/antirollback.h +++ b/src/include/antirollback.h @@ -6,133 +6,39 @@ * stored in the TPM NVRAM. */ -#ifndef VBOOT_REFERENCE_ROLLBACK_INDEX_H_ -#define VBOOT_REFERENCE_ROLLBACK_INDEX_H_ +#ifndef ANTIROLLBACK_H_ +#define ANTIROLLBACK_H_ -#include "sysincludes.h" -#include "tss_constants.h" +#include "2sysincludes.h" +#include <2api.h> +#include "tpm_lite/tss_constants.h" /* TPM NVRAM location indices. */ #define FIRMWARE_NV_INDEX 0x1007 -#define KERNEL_NV_INDEX 0x1008 -/* This is just an opaque space for backup purposes */ -#define BACKUP_NV_INDEX 0x1009 -#define BACKUP_NV_SIZE 16 - /* Structure definitions for TPM spaces */ -/* Kernel space - KERNEL_NV_INDEX, locked with physical presence. */ -#define ROLLBACK_SPACE_KERNEL_VERSION 2 -#define ROLLBACK_SPACE_KERNEL_UID 0x4752574C /* 'GRWL' */ - -typedef struct RollbackSpaceKernel { - /* Struct version, for backwards compatibility */ - uint8_t struct_version; - /* Unique ID to detect space redefinition */ - uint32_t uid; - /* Kernel versions */ - uint32_t kernel_versions; - /* Reserved for future expansion */ - uint8_t reserved[3]; - /* Checksum (v2 and later only) */ - uint8_t crc8; -} __attribute__((packed)) RollbackSpaceKernel; - /* Flags for firmware space */ + /* * Last boot was developer mode. TPM ownership is cleared when transitioning * to/from developer mode. */ #define FLAG_LAST_BOOT_DEVELOPER 0x01 -/* - * Some systems may not have a dedicated dev-mode switch, but enter and leave - * dev-mode through some recovery-mode magic keypresses. For those systems, the - * dev-mode "switch" state is in this bit (0=normal, 1=dev). To make it work, a - * new flag is passed to VbInit(), indicating that the system lacks a physical - * dev-mode switch. If a physical switch is present, this bit is ignored. - */ -#define FLAG_VIRTUAL_DEV_MODE_ON 0x02 - -/* Firmware space - FIRMWARE_NV_INDEX, locked with global lock. */ -#define ROLLBACK_SPACE_FIRMWARE_VERSION 2 - -typedef struct RollbackSpaceFirmware { - /* Struct version, for backwards compatibility */ - uint8_t struct_version; - /* Flags (see FLAG_* above) */ - uint8_t flags; - /* Firmware versions */ - uint32_t fw_versions; - /* Reserved for future expansion */ - uint8_t reserved[3]; - /* Checksum (v2 and later only) */ - uint8_t crc8; -} __attribute__((packed)) RollbackSpaceFirmware; - /* All functions return TPM_SUCCESS (zero) if successful, non-zero if error */ -/* - * These functions are called from VbInit(). They cannot use global - * variables. - */ - -uint32_t RollbackS3Resume(void); - -/* - * These functions are callable from VbSelectFirmware(). They cannot use - * global variables. - */ - -/** - * This must be called. - */ -uint32_t RollbackFirmwareSetup(int is_hw_dev, - int disable_dev_request, - int clear_tpm_owner_request, - /* two outputs on success */ - int *is_virt_dev, uint32_t *tpm_version); +uint32_t antirollback_read_space_firmware(struct vb2_context *ctx); /** * Write may be called if the versions change. */ -uint32_t RollbackFirmwareWrite(uint32_t version); +uint32_t antirollback_write_space_firmware(struct vb2_context *ctx); /** * Lock must be called. */ -uint32_t RollbackFirmwareLock(void); - -/* - * These functions are callable from VbSelectAndLoadKernel(). They may use - * global variables. - */ - -/** - * Read stored kernel version. - */ -uint32_t RollbackKernelRead(uint32_t *version); - -/** - * Write stored kernel version. - */ -uint32_t RollbackKernelWrite(uint32_t version); - -/** - * Read backup data. - */ -uint32_t RollbackBackupRead(uint8_t *raw); - -/** - * Write backup data. - */ -uint32_t RollbackBackupWrite(uint8_t *raw); - -/** - * Lock must be called. Internally, it's ignored in recovery mode. - */ -uint32_t RollbackKernelLock(int recovery_mode); +uint32_t antirollback_lock_space_firmware(void); /****************************************************************************/ @@ -144,23 +50,23 @@ uint32_t RollbackKernelLock(int recovery_mode); /** * Issue a TPM_Clear and reenable/reactivate the TPM. */ -uint32_t TPMClearAndReenable(void); +uint32_t tpm_clear_and_reenable(void); /** - * Like TlclWrite(), but checks for write errors due to hitting the 64-write + * Like tlcl_write(), but checks for write errors due to hitting the 64-write * limit and clears the TPM when that happens. This can only happen when the * TPM is unowned, so it is OK to clear it (and we really have no choice). * This is not expected to happen frequently, but it could happen. */ -uint32_t SafeWrite(uint32_t index, const void *data, uint32_t length); +uint32_t safe_write(uint32_t index, const void *data, uint32_t length); /** - * Similarly to SafeWrite(), this ensures we don't fail a DefineSpace because + * Similarly to safe_write(), this ensures we don't fail a DefineSpace because * we hit the TPM write limit. This is even less likely to happen than with * writes because we only define spaces once at initialization, but we'd rather * be paranoid about this. */ -uint32_t SafeDefineSpace(uint32_t index, uint32_t perm, uint32_t size); +uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size); /** * Perform one-time initializations. @@ -169,19 +75,11 @@ uint32_t SafeDefineSpace(uint32_t index, uint32_t perm, uint32_t size); * nvLocked bit and ensures the physical presence command is enabled and * locked. */ -uint32_t OneTimeInitializeTPM(RollbackSpaceFirmware *rsf, - RollbackSpaceKernel *rsk); - -/** - * Start the TPM and establish the root of trust for the anti-rollback - * mechanism. - */ -uint32_t SetupTPM(int developer_mode, int disable_dev_request, - int clear_tpm_owner_request, RollbackSpaceFirmware *rsf); +uint32_t factory_initialize_tpm(struct vb2_context *ctx); /** - * Utility function to turn the virtual dev-mode flag on or off. 0=off, 1=on. + * Start the TPM and establish the root of trust for the antirollback mechanism. */ -uint32_t SetVirtualDevMode(int val); +uint32_t setup_tpm(struct vb2_context *ctx); -#endif /* VBOOT_REFERENCE_ROLLBACK_INDEX_H_ */ +#endif /* ANTIROLLBACK_H_ */ diff --git a/src/include/tpm_lite/tlcl.h b/src/include/tpm_lite/tlcl.h index 5373120..7724592 100644 --- a/src/include/tpm_lite/tlcl.h +++ b/src/include/tpm_lite/tlcl.h @@ -21,45 +21,27 @@ /** * Call this first. Returns 0 if success, nonzero if error. */ -uint32_t TlclLibInit(void); - -/** - * Call this on shutdown. Returns 0 if success, nonzero if error. - */ -uint32_t TlclLibClose(void); - -/* Low-level operations */ +uint32_t tlcl_lib_init(void); /** * Perform a raw TPM request/response transaction. */ -uint32_t TlclSendReceive(const uint8_t *request, uint8_t *response, +uint32_t tlcl_send_receive(const uint8_t *request, uint8_t *response, int max_length); -/** - * Return the size of a TPM request or response packet. - */ -int TlclPacketSize(const uint8_t *packet); - /* Commands */ /** * Send a TPM_Startup(ST_CLEAR). The TPM error code is returned (0 for * success). */ -uint32_t TlclStartup(void); - -/** - * Save the TPM state. Normally done by the kernel before a suspend, included - * here for tests. The TPM error code is returned (0 for success). - */ -uint32_t TlclSaveState(void); +uint32_t tlcl_startup(void); /** * Resume by sending a TPM_Startup(ST_STATE). The TPM error code is returned * (0 for success). */ -uint32_t TlclResume(void); +uint32_t tlcl_resume(void); /** * Run the self test. @@ -67,143 +49,89 @@ uint32_t TlclResume(void); * Note---this is synchronous. To run this in parallel with other firmware, * use ContinueSelfTest(). The TPM error code is returned. */ -uint32_t TlclSelfTestFull(void); +uint32_t tlcl_self_test_full(void); /** * Run the self test in the background. */ -uint32_t TlclContinueSelfTest(void); +uint32_t tlcl_continue_self_test(void); /** * Define a space with permission [perm]. [index] is the index for the space, * [size] the usable data size. The TPM error code is returned. */ -uint32_t TlclDefineSpace(uint32_t index, uint32_t perm, uint32_t size); +uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size); /** * Write [length] bytes of [data] to space at [index]. The TPM error code is * returned. */ -uint32_t TlclWrite(uint32_t index, const void *data, uint32_t length); +uint32_t tlcl_write(uint32_t index, const void *data, uint32_t length); /** * Read [length] bytes from space at [index] into [data]. The TPM error code * is returned. */ -uint32_t TlclRead(uint32_t index, void *data, uint32_t length); - -/** - * Read PCR at [index] into [data]. [length] must be TPM_PCR_DIGEST or - * larger. The TPM error code is returned. - */ -uint32_t TlclPCRRead(uint32_t index, void *data, uint32_t length); - -/** - * Write-lock space at [index]. The TPM error code is returned. - */ -uint32_t TlclWriteLock(uint32_t index); - -/** - * Read-lock space at [index]. The TPM error code is returned. - */ -uint32_t TlclReadLock(uint32_t index); +uint32_t tlcl_read(uint32_t index, void *data, uint32_t length); /** * Assert physical presence in software. The TPM error code is returned. */ -uint32_t TlclAssertPhysicalPresence(void); +uint32_t tlcl_assert_physical_presence(void); /** * Enable the physical presence command. The TPM error code is returned. */ -uint32_t TlclPhysicalPresenceCMDEnable(void); +uint32_t tlcl_physical_presence_cmd_enable(void); /** * Finalize the physical presence settings: sofware PP is enabled, hardware PP * is disabled, and the lifetime lock is set. The TPM error code is returned. */ -uint32_t TlclFinalizePhysicalPresence(void); - -uint32_t TlclAssertPhysicalPresenceResult(void); - -/** - * Turn off physical presence and locks it off until next reboot. The TPM - * error code is returned. - */ -uint32_t TlclLockPhysicalPresence(void); +uint32_t tlcl_finalize_physical_presence(void); /** * Set the nvLocked bit. The TPM error code is returned. */ -uint32_t TlclSetNvLocked(void); - -/** - * Return 1 if the TPM is owned, 0 otherwise. - */ -int TlclIsOwned(void); +uint32_t tlcl_set_nv_locked(void); /** * Issue a ForceClear. The TPM error code is returned. */ -uint32_t TlclForceClear(void); +uint32_t tlcl_force_clear(void); /** * Issue a PhysicalEnable. The TPM error code is returned. */ -uint32_t TlclSetEnable(void); - -/** - * Issue a PhysicalDisable. The TPM error code is returned. - */ -uint32_t TlclClearEnable(void); +uint32_t tlcl_set_enable(void); /** * Issue a SetDeactivated. Pass 0 to activate. Returns result code. */ -uint32_t TlclSetDeactivated(uint8_t flag); +uint32_t tlcl_set_deactivated(uint8_t flag); /** * Get flags of interest. Pointers for flags you aren't interested in may * be NULL. The TPM error code is returned. */ -uint32_t TlclGetFlags(uint8_t *disable, uint8_t *deactivated, - uint8_t *nvlocked); +uint32_t tlcl_get_flags(uint8_t *disable, uint8_t *deactivated, + uint8_t *nvlocked); /** * Set the bGlobalLock flag, which only a reboot can clear. The TPM error * code is returned. */ -uint32_t TlclSetGlobalLock(void); +uint32_t tlcl_set_global_lock(void); /** * Perform a TPM_Extend. */ -uint32_t TlclExtend(int pcr_num, const uint8_t *in_digest, uint8_t *out_digest); - -/** - * Get the permission bits for the NVRAM space with |index|. - */ -uint32_t TlclGetPermissions(uint32_t index, uint32_t *permissions); +uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, + uint8_t *out_digest); /** * Get the entire set of permanent flags. */ -uint32_t TlclGetPermanentFlags(TPM_PERMANENT_FLAGS *pflags); - -/** - * Get the entire set of volatile (ST_CLEAR) flags. - */ -uint32_t TlclGetSTClearFlags(TPM_STCLEAR_FLAGS *pflags); - -/** - * Get the ownership flag. The TPM error code is returned. - */ -uint32_t TlclGetOwnership(uint8_t *owned); - -/** - * Request [length] bytes from TPM RNG to be stored in [data]. Actual number of - * bytes read is stored in [size]. The TPM error code is returned. - */ -uint32_t TlclGetRandom(uint8_t *data, uint32_t length, uint32_t *size); +uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS *pflags); #endif /* TPM_LITE_TLCL_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9650fd5..1d5e8d9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -29,6 +29,7 @@ verstage-y += delay.c verstage-y += cbfs.c verstage-y += memcmp.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c +verstage-y += tlcl.c romstage-y += memchr.c diff --git a/src/lib/tlcl.c b/src/lib/tlcl.c index bf2d27f..2b337a9 100644 --- a/src/lib/tlcl.c +++ b/src/lib/tlcl.c @@ -14,453 +14,313 @@ * time. */ -#include "sysincludes.h" - -#include "tlcl.h" +#include <2api.h> +#include <2sysincludes.h> +#include <assert.h> +#include <tpm_lite/tlcl.h> +#include <tpm.h> #include "tlcl_internal.h" #include "tlcl_structures.h" -#include "utility.h" -#include "vboot_api.h" #ifdef FOR_TEST -/* Allow unit testing implementation of TlclSendReceive() */ -#undef CHROMEOS_ENVIRONMENT +#include <stdio.h> +#define VBDEBUG(format, args...) printf(format, ## args) +#else +#include <console/console.h> +#define VBDEBUG(format, args...) printk(BIOS_DEBUG, format, ## args) #endif +static int tpm_send_receive(const uint8_t *request, + uint32_t request_length, + uint8_t *response, + uint32_t *response_length) +{ + size_t len = *response_length; + if (tis_sendrecv(request, request_length, response, &len)) + return VB2_ERROR_UNKNOWN; + /* check 64->32bit overflow and (re)check response buffer overflow */ + if (len > *response_length) + return VB2_ERROR_UNKNOWN; + *response_length = len; + return VB2_SUCCESS; +} + /* Sets the size field of a TPM command. */ -static inline void SetTpmCommandSize(uint8_t* buffer, uint32_t size) { - ToTpmUint32(buffer + sizeof(uint16_t), size); +static inline void set_tpm_command_size(uint8_t* buffer, uint32_t size) { + to_tpm_uint32(buffer + sizeof(uint16_t), size); } /* Gets the size field of a TPM command. */ __attribute__((unused)) -static inline int TpmCommandSize(const uint8_t* buffer) { - uint32_t size; - FromTpmUint32(buffer + sizeof(uint16_t), &size); - return (int) size; -} - -/* Gets the size field of a TPM request or response. */ -int TlclPacketSize(const uint8_t* packet) { - return TpmCommandSize(packet); +static inline int tpm_command_size(const uint8_t* buffer) { + uint32_t size; + from_tpm_uint32(buffer + sizeof(uint16_t), &size); + return (int) size; } /* Gets the code field of a TPM command. */ -static inline int TpmCommandCode(const uint8_t* buffer) { - uint32_t code; - FromTpmUint32(buffer + sizeof(uint16_t) + sizeof(uint32_t), &code); - return code; +static inline int tpm_command_code(const uint8_t* buffer) { + uint32_t code; + from_tpm_uint32(buffer + sizeof(uint16_t) + sizeof(uint32_t), &code); + return code; } /* Gets the return code field of a TPM result. */ -static inline int TpmReturnCode(const uint8_t* buffer) { - return TpmCommandCode(buffer); +static inline int tpm_return_code(const uint8_t* buffer) { + return tpm_command_code(buffer); } /* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or * DOING_SELFTEST errors are returned. */ -static uint32_t TlclSendReceiveNoRetry(const uint8_t* request, - uint8_t* response, int max_length) { - - uint32_t response_length = max_length; - uint32_t result; - -#ifdef EXTRA_LOGGING - VBDEBUG(("TPM: command: %x%x %x%x%x%x %x%x%x%x\n", - request[0], request[1], - request[2], request[3], request[4], request[5], - request[6], request[7], request[8], request[9])); -#endif - - result = VbExTpmSendReceive(request, TpmCommandSize(request), - response, &response_length); - if (0 != result) { - /* Communication with TPM failed, so response is garbage */ - VBDEBUG(("TPM: command 0x%x send/receive failed: 0x%x\n", - TpmCommandCode(request), result)); - return result; - } - /* Otherwise, use the result code from the response */ - result = TpmReturnCode(response); - - /* TODO: add paranoia about returned response_length vs. max_length - * (and possibly expected length from the response header). See - * crosbug.com/17017 */ - -#ifdef EXTRA_LOGGING - VBDEBUG(("TPM: response: %x%x %x%x%x%x %x%x%x%x\n", - response[0], response[1], - response[2], response[3], response[4], response[5], - response[6], response[7], response[8], response[9])); -#endif - - VBDEBUG(("TPM: command 0x%x returned 0x%x\n", - TpmCommandCode(request), result)); - - return result; +static uint32_t tlcl_send_receive_no_retry(const uint8_t* request, + uint8_t* response, int max_length) { + uint32_t response_length = max_length; + uint32_t result; + + result = tpm_send_receive(request, tpm_command_size(request), + response, &response_length); + if (0 != result) { + /* Communication with TPM failed, so response is garbage */ + VBDEBUG("TPM: command 0x%x send/receive failed: 0x%x\n", + tpm_command_code(request), result); + return result; + } + /* Otherwise, use the result code from the response */ + result = tpm_return_code(response); + + /* TODO: add paranoia about returned response_length vs. max_length + * (and possibly expected length from the response header). See + * crosbug.com/17017 */ + + VBDEBUG("TPM: command 0x%x returned 0x%x\n", + tpm_command_code(request), result); + +return result; } /* Sends a TPM command and gets a response. Returns 0 if success or the TPM - * error code if error. In the firmware, waits for the self test to complete - * if needed. In the host, reports the first error without retries. */ -uint32_t TlclSendReceive(const uint8_t* request, uint8_t* response, - int max_length) { - uint32_t result = TlclSendReceiveNoRetry(request, response, max_length); - /* When compiling for the firmware, hide command failures due to the self - * test not having run or completed. */ -#ifndef CHROMEOS_ENVIRONMENT - /* If the command fails because the self test has not completed, try it - * again after attempting to ensure that the self test has completed. */ - if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { - result = TlclContinueSelfTest(); - if (result != TPM_SUCCESS) { - return result; - } + * error code if error. Waits for the self test to complete if needed. */ +uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, + int max_length) { + uint32_t result = tlcl_send_receive_no_retry(request, response, + max_length); + /* If the command fails because the self test has not completed, try it + * again after attempting to ensure that the self test has completed. */ + if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { + result = tlcl_continue_self_test(); + if (result != TPM_SUCCESS) + return result; #if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) - /* Retry only once */ - result = TlclSendReceiveNoRetry(request, response, max_length); + /* Retry only once */ + result = tlcl_send_receive_no_retry(request, response, + max_length); #else - /* This needs serious testing. The TPM specification says: "iii. The - * caller MUST wait for the actions of TPM_ContinueSelfTest to complete - * before reissuing the command C1." But, if ContinueSelfTest is - * non-blocking, how do we know that the actions have completed other than - * trying again? */ - do { - result = TlclSendReceiveNoRetry(request, response, max_length); - } while (result == TPM_E_DOING_SELFTEST); + /* This needs serious testing. The TPM specification says: "iii. + * The caller MUST wait for the actions of TPM_ContinueSelfTest + * to complete before reissuing the command C1." But, if + * ContinueSelfTest is non-blocking, how do we know that the + * actions have completed other than trying again? */ + do { + result = tlcl_send_receive_no_retry(request, response, + max_length); + } while (result == TPM_E_DOING_SELFTEST); #endif - } -#endif /* ! defined(CHROMEOS_ENVIRONMENT) */ - return result; + } + return result; } /* Sends a command and returns the error code. */ -static uint32_t Send(const uint8_t* command) { - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - return TlclSendReceive(command, response, sizeof(response)); +static uint32_t send(const uint8_t* command) { + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + return tlcl_send_receive(command, response, sizeof(response)); } /* Exported functions. */ -uint32_t TlclLibInit(void) { - return VbExTpmInit(); -} - -uint32_t TlclLibClose(void) { - return VbExTpmClose(); -} - -uint32_t TlclStartup(void) { - VBDEBUG(("TPM: Startup\n")); - return Send(tpm_startup_cmd.buffer); -} - -uint32_t TlclSaveState(void) { - VBDEBUG(("TPM: SaveState\n")); - return Send(tpm_savestate_cmd.buffer); +uint32_t tlcl_lib_init(void) { + if (tis_init()) + return VB2_ERROR_UNKNOWN; + if (tis_open()) + return VB2_ERROR_UNKNOWN; + return VB2_SUCCESS; } -uint32_t TlclResume(void) { - VBDEBUG(("TPM: Resume\n")); - return Send(tpm_resume_cmd.buffer); +uint32_t tlcl_startup(void) { + VBDEBUG("TPM: Startup\n"); + return send(tpm_startup_cmd.buffer); } -uint32_t TlclSelfTestFull(void) { - VBDEBUG(("TPM: Self test full\n")); - return Send(tpm_selftestfull_cmd.buffer); +uint32_t tlcl_resume(void) { + VBDEBUG("TPM: Resume\n"); + return send(tpm_resume_cmd.buffer); } -uint32_t TlclContinueSelfTest(void) { - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - VBDEBUG(("TPM: Continue self test\n")); - /* Call the No Retry version of SendReceive to avoid recursion. */ - return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, - response, sizeof(response)); +uint32_t tlcl_self_test_full(void) +{ + VBDEBUG("TPM: Self test full\n"); + return send(tpm_selftestfull_cmd.buffer); } -uint32_t TlclDefineSpace(uint32_t index, uint32_t perm, uint32_t size) { - struct s_tpm_nv_definespace_cmd cmd; - VBDEBUG(("TPM: TlclDefineSpace(0x%x, 0x%x, %d)\n", index, perm, size)); - Memcpy(&cmd, &tpm_nv_definespace_cmd, sizeof(cmd)); - ToTpmUint32(cmd.buffer + tpm_nv_definespace_cmd.index, index); - ToTpmUint32(cmd.buffer + tpm_nv_definespace_cmd.perm, perm); - ToTpmUint32(cmd.buffer + tpm_nv_definespace_cmd.size, size); - return Send(cmd.buffer); +uint32_t tlcl_continue_self_test(void) +{ + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + VBDEBUG("TPM: Continue self test\n"); + /* Call the No Retry version of SendReceive to avoid recursion. */ + return tlcl_send_receive_no_retry(tpm_continueselftest_cmd.buffer, + response, sizeof(response)); } -uint32_t TlclWrite(uint32_t index, const void* data, uint32_t length) { - struct s_tpm_nv_write_cmd cmd; - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - const int total_length = - kTpmRequestHeaderLength + kWriteInfoLength + length; - - VBDEBUG(("TPM: TlclWrite(0x%x, %d)\n", index, length)); - Memcpy(&cmd, &tpm_nv_write_cmd, sizeof(cmd)); - VbAssert(total_length <= TPM_LARGE_ENOUGH_COMMAND_SIZE); - SetTpmCommandSize(cmd.buffer, total_length); - - ToTpmUint32(cmd.buffer + tpm_nv_write_cmd.index, index); - ToTpmUint32(cmd.buffer + tpm_nv_write_cmd.length, length); - Memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length); - - return TlclSendReceive(cmd.buffer, response, sizeof(response)); +uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) +{ + struct s_tpm_nv_definespace_cmd cmd; + VBDEBUG("TPM: TlclDefineSpace(0x%x, 0x%x, %d)\n", index, perm, size); + memcpy(&cmd, &tpm_nv_definespace_cmd, sizeof(cmd)); + to_tpm_uint32(cmd.buffer + tpm_nv_definespace_cmd.index, index); + to_tpm_uint32(cmd.buffer + tpm_nv_definespace_cmd.perm, perm); + to_tpm_uint32(cmd.buffer + tpm_nv_definespace_cmd.size, size); + return send(cmd.buffer); } -uint32_t TlclRead(uint32_t index, void* data, uint32_t length) { - struct s_tpm_nv_read_cmd cmd; - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - uint32_t result_length; - uint32_t result; - - VBDEBUG(("TPM: TlclRead(0x%x, %d)\n", index, length)); - Memcpy(&cmd, &tpm_nv_read_cmd, sizeof(cmd)); - ToTpmUint32(cmd.buffer + tpm_nv_read_cmd.index, index); - ToTpmUint32(cmd.buffer + tpm_nv_read_cmd.length, length); - - result = TlclSendReceive(cmd.buffer, response, sizeof(response)); - if (result == TPM_SUCCESS && length > 0) { - uint8_t* nv_read_cursor = response + kTpmResponseHeaderLength; - FromTpmUint32(nv_read_cursor, &result_length); - nv_read_cursor += sizeof(uint32_t); - Memcpy(data, nv_read_cursor, result_length); - } - - return result; -} +uint32_t tlcl_write(uint32_t index, const void* data, uint32_t length) +{ + struct s_tpm_nv_write_cmd cmd; + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + const int total_length = + kTpmRequestHeaderLength + kWriteInfoLength + length; -uint32_t TlclPCRRead(uint32_t index, void* data, uint32_t length) { - struct s_tpm_pcr_read_cmd cmd; - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - uint32_t result; - - VBDEBUG(("TPM: TlclPCRRead(0x%x, %d)\n", index, length)); - if (length < kPcrDigestLength) { - return TPM_E_IOERROR; - } - Memcpy(&cmd, &tpm_pcr_read_cmd, sizeof(cmd)); - ToTpmUint32(cmd.buffer + tpm_pcr_read_cmd.pcrNum, index); - - result = TlclSendReceive(cmd.buffer, response, sizeof(response)); - if (result == TPM_SUCCESS) { - uint8_t* pcr_read_cursor = response + kTpmResponseHeaderLength; - Memcpy(data, pcr_read_cursor, kPcrDigestLength); - } - - return result; -} + VBDEBUG("TPM: tlcl_write(0x%x, %d)\n", index, length); + memcpy(&cmd, &tpm_nv_write_cmd, sizeof(cmd)); + assert(total_length <= TPM_LARGE_ENOUGH_COMMAND_SIZE); + set_tpm_command_size(cmd.buffer, total_length); -uint32_t TlclWriteLock(uint32_t index) { - VBDEBUG(("TPM: Write lock 0x%x\n", index)); - return TlclWrite(index, NULL, 0); -} + to_tpm_uint32(cmd.buffer + tpm_nv_write_cmd.index, index); + to_tpm_uint32(cmd.buffer + tpm_nv_write_cmd.length, length); + memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length); -uint32_t TlclReadLock(uint32_t index) { - VBDEBUG(("TPM: Read lock 0x%x\n", index)); - return TlclRead(index, NULL, 0); + return tlcl_send_receive(cmd.buffer, response, sizeof(response)); } -uint32_t TlclAssertPhysicalPresence(void) { - VBDEBUG(("TPM: Asserting physical presence\n")); - return Send(tpm_ppassert_cmd.buffer); -} +uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) +{ + struct s_tpm_nv_read_cmd cmd; + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + uint32_t result_length; + uint32_t result; -uint32_t TlclPhysicalPresenceCMDEnable(void) { - VBDEBUG(("TPM: Enable the physical presence command\n")); - return Send(tpm_ppenable_cmd.buffer); -} + VBDEBUG("TPM: tlcl_read(0x%x, %d)\n", index, length); + memcpy(&cmd, &tpm_nv_read_cmd, sizeof(cmd)); + to_tpm_uint32(cmd.buffer + tpm_nv_read_cmd.index, index); + to_tpm_uint32(cmd.buffer + tpm_nv_read_cmd.length, length); -uint32_t TlclFinalizePhysicalPresence(void) { - VBDEBUG(("TPM: Enable PP cmd, disable HW pp, and set lifetime lock\n")); - return Send(tpm_finalizepp_cmd.buffer); -} + result = tlcl_send_receive(cmd.buffer, response, sizeof(response)); + if (result == TPM_SUCCESS && length > 0) { + uint8_t* nv_read_cursor = response + kTpmResponseHeaderLength; + from_tpm_uint32(nv_read_cursor, &result_length); + nv_read_cursor += sizeof(uint32_t); + memcpy(data, nv_read_cursor, result_length); + } -uint32_t TlclAssertPhysicalPresenceResult(void) { - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - return TlclSendReceive(tpm_ppassert_cmd.buffer, response, sizeof(response)); + return result; } -uint32_t TlclLockPhysicalPresence(void) { - VBDEBUG(("TPM: Lock physical presence\n")); - return Send(tpm_pplock_cmd.buffer); -} -uint32_t TlclSetNvLocked(void) { - VBDEBUG(("TPM: Set NV locked\n")); - return TlclDefineSpace(TPM_NV_INDEX_LOCK, 0, 0); +uint32_t tlcl_assert_physical_presence(void) { + VBDEBUG("TPM: Asserting physical presence\n"); + return send(tpm_ppassert_cmd.buffer); } -int TlclIsOwned(void) { - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE + TPM_PUBEK_SIZE]; - uint32_t result; - result = TlclSendReceive(tpm_readpubek_cmd.buffer, - response, sizeof(response)); - return (result != TPM_SUCCESS); +uint32_t tlcl_physical_presence_cmd_enable(void) { + VBDEBUG("TPM: Enable the physical presence command\n"); + return send(tpm_ppenable_cmd.buffer); } -uint32_t TlclForceClear(void) { - VBDEBUG(("TPM: Force clear\n")); - return Send(tpm_forceclear_cmd.buffer); +uint32_t tlcl_finalize_physical_presence(void) { + VBDEBUG("TPM: Enable PP cmd, disable HW pp, and set lifetime lock\n"); + return send(tpm_finalizepp_cmd.buffer); } -uint32_t TlclSetEnable(void) { - VBDEBUG(("TPM: Enabling TPM\n")); - return Send(tpm_physicalenable_cmd.buffer); +uint32_t tlcl_set_nv_locked(void) { + VBDEBUG("TPM: Set NV locked\n"); + return tlcl_define_space(TPM_NV_INDEX_LOCK, 0, 0); } -uint32_t TlclClearEnable(void) { - VBDEBUG(("TPM: Disabling TPM\n")); - return Send(tpm_physicaldisable_cmd.buffer); +uint32_t tlcl_force_clear(void) { + VBDEBUG("TPM: Force clear\n"); + return send(tpm_forceclear_cmd.buffer); } -uint32_t TlclSetDeactivated(uint8_t flag) { - struct s_tpm_physicalsetdeactivated_cmd cmd; - VBDEBUG(("TPM: SetDeactivated(%d)\n", flag)); - Memcpy(&cmd, &tpm_physicalsetdeactivated_cmd, sizeof(cmd)); - *(cmd.buffer + cmd.deactivated) = flag; - return Send(cmd.buffer); +uint32_t tlcl_set_enable(void) { + VBDEBUG("TPM: Enabling TPM\n"); + return send(tpm_physicalenable_cmd.buffer); } -uint32_t TlclGetPermanentFlags(TPM_PERMANENT_FLAGS* pflags) { - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - uint32_t size; - uint32_t result = - TlclSendReceive(tpm_getflags_cmd.buffer, response, sizeof(response)); - if (result != TPM_SUCCESS) - return result; - FromTpmUint32(response + kTpmResponseHeaderLength, &size); - /* TODO(crbug.com/379255): This fails. Find out why. - * VbAssert(size == sizeof(TPM_PERMANENT_FLAGS)); - */ - Memcpy(pflags, - response + kTpmResponseHeaderLength + sizeof(size), - sizeof(TPM_PERMANENT_FLAGS)); - return result; +uint32_t tlcl_set_deactivated(uint8_t flag) +{ + struct s_tpm_physicalsetdeactivated_cmd cmd; + VBDEBUG("TPM: SetDeactivated(%d)\n", flag); + memcpy(&cmd, &tpm_physicalsetdeactivated_cmd, sizeof(cmd)); + *(cmd.buffer + cmd.deactivated) = flag; + return send(cmd.buffer); +} + +uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS* pflags) +{ + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + uint32_t size; + uint32_t result = tlcl_send_receive(tpm_getflags_cmd.buffer, response, + sizeof(response)); + if (result != TPM_SUCCESS) + return result; + from_tpm_uint32(response + kTpmResponseHeaderLength, &size); + assert(size == sizeof(TPM_PERMANENT_FLAGS)); + memcpy(pflags, response + kTpmResponseHeaderLength + sizeof(size), + sizeof(TPM_PERMANENT_FLAGS)); + return result; } -uint32_t TlclGetSTClearFlags(TPM_STCLEAR_FLAGS* vflags) { - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - uint32_t size; - uint32_t result = - TlclSendReceive(tpm_getstclearflags_cmd.buffer, response, sizeof(response)); - if (result != TPM_SUCCESS) - return result; - FromTpmUint32(response + kTpmResponseHeaderLength, &size); - /* Ugly assertion, but the struct is padded up by one byte. */ - /* TODO(crbug.com/379255): This fails. Find out why. - * VbAssert(size == 7 && sizeof(TPM_STCLEAR_FLAGS) - 1 == 7); - */ - Memcpy(vflags, - response + kTpmResponseHeaderLength + sizeof(size), - sizeof(TPM_STCLEAR_FLAGS)); - return result; +uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, + uint8_t *nvlocked) +{ + TPM_PERMANENT_FLAGS pflags; + uint32_t result = tlcl_get_permanent_flags(&pflags); + if (result == TPM_SUCCESS) { + if (disable) + *disable = pflags.disable; + if (deactivated) + *deactivated = pflags.deactivated; + if (nvlocked) + *nvlocked = pflags.nvLocked; + VBDEBUG("TPM: flags disable=%d, deactivated=%d, nvlocked=%d\n", + pflags.disable, pflags.deactivated, pflags.nvLocked); + } + return result; } -uint32_t TlclGetFlags(uint8_t* disable, - uint8_t* deactivated, - uint8_t *nvlocked) { - TPM_PERMANENT_FLAGS pflags; - uint32_t result = TlclGetPermanentFlags(&pflags); - if (result == TPM_SUCCESS) { - if (disable) - *disable = pflags.disable; - if (deactivated) - *deactivated = pflags.deactivated; - if (nvlocked) - *nvlocked = pflags.nvLocked; - VBDEBUG(("TPM: Got flags disable=%d, deactivated=%d, nvlocked=%d\n", - pflags.disable, pflags.deactivated, pflags.nvLocked)); - } - return result; -} - -uint32_t TlclSetGlobalLock(void) { - uint32_t x; - VBDEBUG(("TPM: Set global lock\n")); - return TlclWrite(TPM_NV_INDEX0, (uint8_t*) &x, 0); -} +uint32_t tlcl_set_global_lock(void) +{ + uint32_t x; + VBDEBUG("TPM: Set global lock\n"); + return tlcl_write(TPM_NV_INDEX0, (uint8_t*) &x, 0); +} -uint32_t TlclExtend(int pcr_num, const uint8_t* in_digest, - uint8_t* out_digest) { - struct s_tpm_extend_cmd cmd; - uint8_t response[kTpmResponseHeaderLength + kPcrDigestLength]; - uint32_t result; +uint32_t tlcl_extend(int pcr_num, const uint8_t* in_digest, + uint8_t* out_digest) +{ + struct s_tpm_extend_cmd cmd; + uint8_t response[kTpmResponseHeaderLength + kPcrDigestLength]; + uint32_t result; - Memcpy(&cmd, &tpm_extend_cmd, sizeof(cmd)); - ToTpmUint32(cmd.buffer + tpm_extend_cmd.pcrNum, pcr_num); - Memcpy(cmd.buffer + cmd.inDigest, in_digest, kPcrDigestLength); + memcpy(&cmd, &tpm_extend_cmd, sizeof(cmd)); + to_tpm_uint32(cmd.buffer + tpm_extend_cmd.pcrNum, pcr_num); + memcpy(cmd.buffer + cmd.inDigest, in_digest, kPcrDigestLength); - result = TlclSendReceive(cmd.buffer, response, sizeof(response)); - if (result != TPM_SUCCESS) - return result; - - Memcpy(out_digest, response + kTpmResponseHeaderLength, kPcrDigestLength); - return result; -} - -uint32_t TlclGetPermissions(uint32_t index, uint32_t* permissions) { - struct s_tpm_getpermissions_cmd cmd; - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - uint8_t* nvdata; - uint32_t result; - uint32_t size; - - Memcpy(&cmd, &tpm_getpermissions_cmd, sizeof(cmd)); - ToTpmUint32(cmd.buffer + tpm_getpermissions_cmd.index, index); - result = TlclSendReceive(cmd.buffer, response, sizeof(response)); - if (result != TPM_SUCCESS) - return result; - - nvdata = response + kTpmResponseHeaderLength + sizeof(size); - FromTpmUint32(nvdata + kNvDataPublicPermissionsOffset, permissions); - return result; -} - -uint32_t TlclGetOwnership(uint8_t* owned) { - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - uint32_t size; - uint32_t result = - TlclSendReceive(tpm_getownership_cmd.buffer, response, sizeof(response)); - if (result != TPM_SUCCESS) - return result; - FromTpmUint32(response + kTpmResponseHeaderLength, &size); - /* TODO(crbug.com/379255): This fails. Find out why. - * VbAssert(size == sizeof(*owned)); - */ - Memcpy(owned, - response + kTpmResponseHeaderLength + sizeof(size), - sizeof(*owned)); - return result; -} + result = tlcl_send_receive(cmd.buffer, response, sizeof(response)); + if (result != TPM_SUCCESS) + return result; -uint32_t TlclGetRandom(uint8_t* data, uint32_t length, uint32_t *size) { - struct s_tpm_get_random_cmd cmd; - uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - uint32_t result; - - VBDEBUG(("TPM: TlclGetRandom(%d)\n", length)); - Memcpy(&cmd, &tpm_get_random_cmd, sizeof(cmd)); - ToTpmUint32(cmd.buffer + tpm_get_random_cmd.bytesRequested, length); - /* There must be room in the response buffer for the bytes. */ - if (length > TPM_LARGE_ENOUGH_COMMAND_SIZE - kTpmResponseHeaderLength - - sizeof(uint32_t)) { - return TPM_E_IOERROR; - } - - result = TlclSendReceive(cmd.buffer, response, sizeof(response)); - if (result == TPM_SUCCESS) { - uint8_t* get_random_cursor; - FromTpmUint32(response + kTpmResponseHeaderLength, size); - - /* There must be room in the target buffer for the bytes. */ - if (*size > length) { - return TPM_E_RESPONSE_TOO_LARGE; - } - get_random_cursor = response + kTpmResponseHeaderLength - + sizeof(uint32_t); - Memcpy(data, get_random_cursor, *size); - } - - return result; + memcpy(out_digest, response + kTpmResponseHeaderLength, + kPcrDigestLength); + return result; } diff --git a/src/lib/tlcl_internal.h b/src/lib/tlcl_internal.h index 51fe6ef..8261b0d 100644 --- a/src/lib/tlcl_internal.h +++ b/src/lib/tlcl_internal.h @@ -18,44 +18,44 @@ /* - * Conversion functions. ToTpmTYPE puts a value of type TYPE into a TPM - * command buffer. FromTpmTYPE gets a value of type TYPE from a TPM command + * Conversion functions. to_tpm_TYPE puts a value of type TYPE into a TPM + * command buffer. from_tpm_TYPE gets a value of type TYPE from a TPM command * buffer into a variable. */ __attribute__((unused)) -static inline void ToTpmUint32(uint8_t *buffer, uint32_t x) { - buffer[0] = (uint8_t)(x >> 24); - buffer[1] = (uint8_t)((x >> 16) & 0xff); - buffer[2] = (uint8_t)((x >> 8) & 0xff); - buffer[3] = (uint8_t)(x & 0xff); +static inline void to_tpm_uint32(uint8_t *buffer, uint32_t x) { + buffer[0] = (uint8_t)(x >> 24); + buffer[1] = (uint8_t)((x >> 16) & 0xff); + buffer[2] = (uint8_t)((x >> 8) & 0xff); + buffer[3] = (uint8_t)(x & 0xff); } /* * See comment for above function. */ __attribute__((unused)) -static inline void FromTpmUint32(const uint8_t *buffer, uint32_t *x) { - *x = ((buffer[0] << 24) | - (buffer[1] << 16) | - (buffer[2] << 8) | - buffer[3]); +static inline void from_tpm_uint32(const uint8_t *buffer, uint32_t *x) { + *x = ((buffer[0] << 24) | + (buffer[1] << 16) | + (buffer[2] << 8) | + buffer[3]); } /* * See comment for above function. */ __attribute__((unused)) -static inline void ToTpmUint16(uint8_t *buffer, uint16_t x) { - buffer[0] = (uint8_t)(x >> 8); - buffer[1] = (uint8_t)(x & 0xff); +static inline void to_tpm_uint16(uint8_t *buffer, uint16_t x) { + buffer[0] = (uint8_t)(x >> 8); + buffer[1] = (uint8_t)(x & 0xff); } /* * See comment for above function. */ __attribute__((unused)) -static inline void FromTpmUint16(const uint8_t *buffer, uint16_t *x) { - *x = (buffer[0] << 8) | buffer[1]; +static inline void from_tpm_uint16(const uint8_t *buffer, uint16_t *x) { + *x = (buffer[0] << 8) | buffer[1]; } #endif /* TPM_LITE_TLCL_INTERNAL_H_ */ diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 8054ca2..aeb7c3a 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -28,7 +28,10 @@ verstage-y += spi.c verstage-y += timer.c verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += ../tegra/gpio.c +verstage-y += ../tegra/i2c.c verstage-y += ../tegra/pinmux.c +verstage-y += clock.c +verstage-y += i2c.c romstage-y += cbfs.c romstage-y += cbmem.c diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index aec9145..22e7ba8 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -18,6 +18,7 @@ */ #include <assert.h> +#include <arch/cache.h> #include <arch/exception.h> #include <bootblock_common.h> #include <cbfs.h> @@ -27,6 +28,78 @@ #include "pinmux.h" #include "power.h" #include "verstage.h" +#include <soc/addressmap.h> +#include <soc/nvidia/tegra/i2c.h> +#include <soc/nvidia/tegra124/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void setup_pinmux(void) +{ + // Write protect. + gpio_input_pullup(GPIO(R1)); + // Recovery mode. + gpio_input_pullup(GPIO(Q7)); + // Lid switch. + gpio_input_pullup(GPIO(R4)); + // Power switch. + gpio_input_pullup(GPIO(Q0)); + // Developer mode. + gpio_input_pullup(GPIO(Q6)); + // EC in RW. + gpio_input_pullup(GPIO(U4)); + + // route PU4/5 to GMI to remove conflict w/PWM1/2. + pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); + pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); + + // SOC and TPM reset GPIO, active low. + gpio_output(GPIO(I5), 1); + + // SPI1 MOSI + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 MISO + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 SCLK + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 CS0 + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + + // I2C3 (cam) clock. + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) data. + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + + // switch unused pin to GPIO + gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO); +} + +static void configure_ec_spi_bus(void) +{ + clock_configure_source(sbc1, CLK_M, 3000); +} + +static void configure_tpm_i2c_bus(void) +{ + clock_configure_i2c_scl_freq(i2c3, PLLP, 400); + + i2c_init(2); +} void main(void) { @@ -70,9 +143,13 @@ void main(void) PINMUX_PWR_INT_N_FUNC_PMICINTR | PINMUX_INPUT_ENABLE); - if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) + if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) { + clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); + setup_pinmux(); + configure_ec_spi_bus(); + configure_tpm_i2c_bus(); entry = (void *)verstage_vboot_main; - else + } else entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); ASSERT(entry); diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index cb3d9a6..4438a92 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -101,6 +101,7 @@ VERSTAGE_LIB = $(obj)/vendorcode/google/chromeos/verstage.a INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include INCLUDES += -I$(VB_SOURCE)/firmware/include verstage-y += vboot_main.c fmap.c chromeos.c +verstage-y += antirollback.c vbnv_ec.c VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y)) VB2_LIB = $(obj)/external/vboot_reference/vboot_fw2.a diff --git a/src/vendorcode/google/chromeos/antirollback.c b/src/vendorcode/google/chromeos/antirollback.c index 306e903..020a06a 100644 --- a/src/vendorcode/google/chromeos/antirollback.c +++ b/src/vendorcode/google/chromeos/antirollback.c @@ -6,261 +6,118 @@ * stored in the TPM NVRAM. */ -#include "sysincludes.h" - -#include "crc8.h" -#include "rollback_index.h" -#include "tlcl.h" -#include "tss_constants.h" -#include "utility.h" -#include "vboot_api.h" +#include <2api.h> +#include <2sysincludes.h> +#include <antirollback.h> +#include <tpm_lite/tlcl.h> +#include <tpm_lite/tss_constants.h> #ifndef offsetof #define offsetof(A,B) __builtin_offsetof(A,B) #endif -/* - * Provide protoypes for functions not in the header file. These prototypes - * fix -Wmissing-prototypes warnings. - */ -uint32_t ReadSpaceFirmware(RollbackSpaceFirmware *rsf); -uint32_t WriteSpaceFirmware(RollbackSpaceFirmware *rsf); -uint32_t ReadSpaceKernel(RollbackSpaceKernel *rsk); -uint32_t WriteSpaceKernel(RollbackSpaceKernel *rsk); - #ifdef FOR_TEST -/* - * Compiling for unit test, so we need the real implementations of - * rollback functions. The unit test mocks the underlying tlcl - * functions, so this is ok to run on the host. - */ -#undef CHROMEOS_ENVIRONMENT -#undef DISABLE_ROLLBACK_TPM +#include <stdio.h> +#define VBDEBUG(format, args...) printf(format, ## args) +#else +#include <console/console.h> +#define VBDEBUG(format, args...) \ + printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) #endif -#define RETURN_ON_FAILURE(tpm_command) do { \ +#define RETURN_ON_FAILURE(tpm_cmd) do { \ uint32_t result_; \ - if ((result_ = (tpm_command)) != TPM_SUCCESS) { \ - VBDEBUG(("Rollback: %08x returned by " #tpm_command \ - "\n", (int)result_)); \ + if ((result_ = (tpm_cmd)) != TPM_SUCCESS) { \ + VBDEBUG("Antirollback: %08x returned by " #tpm_cmd \ + "\n", (int)result_); \ return result_; \ } \ } while (0) -uint32_t TPMClearAndReenable(void) +uint32_t tpm_clear_and_reenable(void) { - VBDEBUG(("TPM: Clear and re-enable\n")); - RETURN_ON_FAILURE(TlclForceClear()); - RETURN_ON_FAILURE(TlclSetEnable()); - RETURN_ON_FAILURE(TlclSetDeactivated(0)); + VBDEBUG("TPM: Clear and re-enable\n"); + RETURN_ON_FAILURE(tlcl_force_clear()); + RETURN_ON_FAILURE(tlcl_set_enable()); + RETURN_ON_FAILURE(tlcl_set_deactivated(0)); return TPM_SUCCESS; } -uint32_t SafeWrite(uint32_t index, const void *data, uint32_t length) +uint32_t safe_write(uint32_t index, const void *data, uint32_t length) { - uint32_t result = TlclWrite(index, data, length); + uint32_t result = tlcl_write(index, data, length); if (result == TPM_E_MAXNVWRITES) { - RETURN_ON_FAILURE(TPMClearAndReenable()); - return TlclWrite(index, data, length); + RETURN_ON_FAILURE(tpm_clear_and_reenable()); + return tlcl_write(index, data, length); } else { return result; } } -uint32_t SafeDefineSpace(uint32_t index, uint32_t perm, uint32_t size) +uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size) { - uint32_t result = TlclDefineSpace(index, perm, size); + uint32_t result = tlcl_define_space(index, perm, size); if (result == TPM_E_MAXNVWRITES) { - RETURN_ON_FAILURE(TPMClearAndReenable()); - return TlclDefineSpace(index, perm, size); + RETURN_ON_FAILURE(tpm_clear_and_reenable()); + return tlcl_define_space(index, perm, size); } else { return result; } } -/* Functions to read and write firmware and kernel spaces. */ -uint32_t ReadSpaceFirmware(RollbackSpaceFirmware *rsf) +static uint32_t read_space_firmware(struct vb2_context *ctx) { - uint32_t r; int attempts = 3; while (attempts--) { - r = TlclRead(FIRMWARE_NV_INDEX, rsf, - sizeof(RollbackSpaceFirmware)); - if (r != TPM_SUCCESS) - return r; - - /* - * No CRC in this version, so we'll create one when we write - * it. Note that we're marking this as version 2, not - * ROLLBACK_SPACE_FIRMWARE_VERSION, because version 2 just - * added the CRC. Later versions will need to set default - * values for any extra fields explicitly (probably here). - */ - if (rsf->struct_version < 2) { - /* Danger Will Robinson! Danger! */ - rsf->struct_version = 2; - return TPM_SUCCESS; - } + RETURN_ON_FAILURE(tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, + VB2_SECDATA_SIZE)); - /* - * If the CRC is good, we're done. If it's bad, try a couple - * more times to see if it gets better before we give up. It - * could just be noise. - */ - if (rsf->crc8 == Crc8(rsf, - offsetof(RollbackSpaceFirmware, crc8))) + if (vb2api_secdata_check(ctx) == VB2_SUCCESS) return TPM_SUCCESS; - VBDEBUG(("TPM: %s() - bad CRC\n", __func__)); + VBDEBUG("TPM: %s() - bad CRC\n", __func__); } - VBDEBUG(("TPM: %s() - too many bad CRCs, giving up\n", __func__)); + VBDEBUG("TPM: %s() - too many bad CRCs, giving up\n", __func__); return TPM_E_CORRUPTED_STATE; } -uint32_t WriteSpaceFirmware(RollbackSpaceFirmware *rsf) +static uint32_t write_space_firmware(struct vb2_context *ctx) { - RollbackSpaceFirmware rsf2; + uint8_t secdata[VB2_SECDATA_SIZE]; uint32_t r; int attempts = 3; - /* All writes should use struct_version 2 or greater. */ - if (rsf->struct_version < 2) - rsf->struct_version = 2; - rsf->crc8 = Crc8(rsf, offsetof(RollbackSpaceFirmware, crc8)); - + memcpy(secdata, ctx->secdata, VB2_SECDATA_SIZE); while (attempts--) { - r = SafeWrite(FIRMWARE_NV_INDEX, rsf, - sizeof(RollbackSpaceFirmware)); + r = safe_write(FIRMWARE_NV_INDEX, secdata, VB2_SECDATA_SIZE); /* Can't write, not gonna try again */ if (r != TPM_SUCCESS) return r; /* Read it back to be sure it got the right values. */ - r = ReadSpaceFirmware(&rsf2); /* This checks the CRC */ - if (r == TPM_SUCCESS) + r = read_space_firmware(ctx); + if (r == TPM_SUCCESS && memcmp(secdata, ctx->secdata, + VB2_SECDATA_SIZE) == 0) return r; - VBDEBUG(("TPM: %s() - bad CRC\n", __func__)); + VBDEBUG("TPM: %s() failed\n", __func__); /* Try writing it again. Maybe it was garbled on the way out. */ } - VBDEBUG(("TPM: %s() - too many bad CRCs, giving up\n", __func__)); + VBDEBUG("TPM: %s() - too many failures, giving up\n", __func__); return TPM_E_CORRUPTED_STATE; } -uint32_t SetVirtualDevMode(int val) +uint32_t factory_initialize_tpm(struct vb2_context *ctx) { - RollbackSpaceFirmware rsf; - - VBDEBUG(("TPM: Entering %s()\n", __func__)); - if (TPM_SUCCESS != ReadSpaceFirmware(&rsf)) - return VBERROR_TPM_FIRMWARE_SETUP; - - VBDEBUG(("TPM: flags were 0x%02x\n", rsf.flags)); - if (val) - rsf.flags |= FLAG_VIRTUAL_DEV_MODE_ON; - else - rsf.flags &= ~FLAG_VIRTUAL_DEV_MODE_ON; - /* - * NOTE: This doesn't update the FLAG_LAST_BOOT_DEVELOPER bit. That - * will be done by SetupTPM() on the next boot. - */ - VBDEBUG(("TPM: flags are now 0x%02x\n", rsf.flags)); - - if (TPM_SUCCESS != WriteSpaceFirmware(&rsf)) - return VBERROR_TPM_SET_BOOT_MODE_STATE; - - VBDEBUG(("TPM: Leaving %s()\n", __func__)); - return VBERROR_SUCCESS; -} - -uint32_t ReadSpaceKernel(RollbackSpaceKernel *rsk) -{ - uint32_t r; - int attempts = 3; - - while (attempts--) { - r = TlclRead(KERNEL_NV_INDEX, rsk, sizeof(RollbackSpaceKernel)); - if (r != TPM_SUCCESS) - return r; - - /* - * No CRC in this version, so we'll create one when we write - * it. Note that we're marking this as version 2, not - * ROLLBACK_SPACE_KERNEL_VERSION, because version 2 just added - * the CRC. Later versions will need to set default values for - * any extra fields explicitly (probably here). - */ - if (rsk->struct_version < 2) { - /* Danger Will Robinson! Danger! */ - rsk->struct_version = 2; - return TPM_SUCCESS; - } - - /* - * If the CRC is good, we're done. If it's bad, try a couple - * more times to see if it gets better before we give up. It - * could just be noise. - */ - if (rsk->crc8 == Crc8(rsk, offsetof(RollbackSpaceKernel, crc8))) - return TPM_SUCCESS; - - VBDEBUG(("TPM: %s() - bad CRC\n", __func__)); - } - - VBDEBUG(("TPM: %s() - too many bad CRCs, giving up\n", __func__)); - return TPM_E_CORRUPTED_STATE; -} - -uint32_t WriteSpaceKernel(RollbackSpaceKernel *rsk) -{ - RollbackSpaceKernel rsk2; - uint32_t r; - int attempts = 3; - - /* All writes should use struct_version 2 or greater. */ - if (rsk->struct_version < 2) - rsk->struct_version = 2; - rsk->crc8 = Crc8(rsk, offsetof(RollbackSpaceKernel, crc8)); - - while (attempts--) { - r = SafeWrite(KERNEL_NV_INDEX, rsk, - sizeof(RollbackSpaceKernel)); - /* Can't write, not gonna try again */ - if (r != TPM_SUCCESS) - return r; - - /* Read it back to be sure it got the right values. */ - r = ReadSpaceKernel(&rsk2); /* This checks the CRC */ - if (r == TPM_SUCCESS) - return r; - - VBDEBUG(("TPM: %s() - bad CRC\n", __func__)); - /* Try writing it again. Maybe it was garbled on the way out. */ - } - - VBDEBUG(("TPM: %s() - too many bad CRCs, giving up\n", __func__)); - return TPM_E_CORRUPTED_STATE; -} - -uint32_t OneTimeInitializeTPM(RollbackSpaceFirmware *rsf, - RollbackSpaceKernel *rsk) -{ - static const RollbackSpaceFirmware rsf_init = { - .struct_version = ROLLBACK_SPACE_FIRMWARE_VERSION, - }; - static const RollbackSpaceKernel rsk_init = { - .struct_version = ROLLBACK_SPACE_KERNEL_VERSION, - .uid = ROLLBACK_SPACE_KERNEL_UID, - }; TPM_PERMANENT_FLAGS pflags; uint32_t result; - VBDEBUG(("TPM: One-time initialization\n")); + VBDEBUG("TPM: factory initialization\n"); /* * Do a full test. This only happens the first time the device is @@ -270,11 +127,11 @@ uint32_t OneTimeInitializeTPM(RollbackSpaceFirmware *rsf, * test---specifically the ones that set lifetime flags, and are only * executed once per physical TPM. */ - result = TlclSelfTestFull(); + result = tlcl_self_test_full(); if (result != TPM_SUCCESS) return result; - result = TlclGetPermanentFlags(&pflags); + result = tlcl_get_permanent_flags(&pflags); if (result != TPM_SUCCESS) return result; @@ -282,11 +139,11 @@ uint32_t OneTimeInitializeTPM(RollbackSpaceFirmware *rsf, * TPM may come from the factory without physical presence finalized. * Fix if necessary. */ - VBDEBUG(("TPM: physicalPresenceLifetimeLock=%d\n", - pflags.physicalPresenceLifetimeLock)); + VBDEBUG("TPM: physicalPresenceLifetimeLock=%d\n", + pflags.physicalPresenceLifetimeLock); if (!pflags.physicalPresenceLifetimeLock) { - VBDEBUG(("TPM: Finalizing physical presence\n")); - RETURN_ON_FAILURE(TlclFinalizePhysicalPresence()); + VBDEBUG("TPM: Finalizing physical presence\n"); + RETURN_ON_FAILURE(tlcl_finalize_physical_presence()); } /* @@ -294,40 +151,27 @@ uint32_t OneTimeInitializeTPM(RollbackSpaceFirmware *rsf, * execution of a TPM_NV_DefineSpace with the handle of * TPM_NV_INDEX_LOCK. Here we create that space if it doesn't already * exist. */ - VBDEBUG(("TPM: nvLocked=%d\n", pflags.nvLocked)); + VBDEBUG("TPM: nvLocked=%d\n", pflags.nvLocked); if (!pflags.nvLocked) { - VBDEBUG(("TPM: Enabling NV locking\n")); - RETURN_ON_FAILURE(TlclSetNvLocked()); + VBDEBUG("TPM: Enabling NV locking\n"); + RETURN_ON_FAILURE(tlcl_set_nv_locked()); } /* Clear TPM owner, in case the TPM is already owned for some reason. */ - VBDEBUG(("TPM: Clearing owner\n")); - RETURN_ON_FAILURE(TPMClearAndReenable()); - - /* Initializes the firmware and kernel spaces */ - Memcpy(rsf, &rsf_init, sizeof(RollbackSpaceFirmware)); - Memcpy(rsk, &rsk_init, sizeof(RollbackSpaceKernel)); + VBDEBUG("TPM: Clearing owner\n"); + RETURN_ON_FAILURE(tpm_clear_and_reenable()); - /* Define the backup space. No need to initialize it, though. */ - RETURN_ON_FAILURE(SafeDefineSpace( - BACKUP_NV_INDEX, TPM_NV_PER_PPWRITE, BACKUP_NV_SIZE)); - - /* Define and initialize the kernel space */ - RETURN_ON_FAILURE(SafeDefineSpace(KERNEL_NV_INDEX, TPM_NV_PER_PPWRITE, - sizeof(RollbackSpaceKernel))); - RETURN_ON_FAILURE(WriteSpaceKernel(rsk)); - - /* Do the firmware space last, so we retry if we don't get this far. */ - RETURN_ON_FAILURE(SafeDefineSpace( - FIRMWARE_NV_INDEX, - TPM_NV_PER_GLOBALLOCK | TPM_NV_PER_PPWRITE, - sizeof(RollbackSpaceFirmware))); - RETURN_ON_FAILURE(WriteSpaceFirmware(rsf)); + /* Defines and sets vb2 secdata space */ + vb2api_secdata_create(ctx); + RETURN_ON_FAILURE(safe_define_space(FIRMWARE_NV_INDEX, + TPM_NV_PER_GLOBALLOCK | + TPM_NV_PER_PPWRITE, + VB2_SECDATA_SIZE)); + RETURN_ON_FAILURE(write_space_firmware(ctx)); return TPM_SUCCESS; } - /* * SetupTPM starts the TPM and establishes the root of trust for the * anti-rollback mechanism. SetupTPM can fail for three reasons. 1 A bug. 2 a @@ -348,329 +192,107 @@ uint32_t OneTimeInitializeTPM(RollbackSpaceFirmware *rsf, * to the TPM flashram at every reboot or wake-up, because of concerns about * the durability of the NVRAM. */ -uint32_t SetupTPM(int developer_mode, int disable_dev_request, - int clear_tpm_owner_request, RollbackSpaceFirmware* rsf) +uint32_t setup_tpm(struct vb2_context *ctx) { - uint8_t in_flags; uint8_t disable; uint8_t deactivated; uint32_t result; - uint32_t versions; - RETURN_ON_FAILURE(TlclLibInit()); + RETURN_ON_FAILURE(tlcl_lib_init()); #ifdef TEGRA_SOFT_REBOOT_WORKAROUND - result = TlclStartup(); + result = tlcl_startup(); if (result == TPM_E_INVALID_POSTINIT) { /* * Some prototype hardware doesn't reset the TPM on a CPU * reset. We do a hard reset to get around this. */ - VBDEBUG(("TPM: soft reset detected\n", result)); + VBDEBUG("TPM: soft reset detected\n", result); return TPM_E_MUST_REBOOT; } else if (result != TPM_SUCCESS) { - VBDEBUG(("TPM: TlclStartup returned %08x\n", result)); + VBDEBUG("TPM: tlcl_startup returned %08x\n", result); return result; } #else - RETURN_ON_FAILURE(TlclStartup()); + RETURN_ON_FAILURE(tlcl_startup()); #endif - /* - * Some TPMs start the self test automatically at power on. In that case we - * don't need to call ContinueSelfTest. On some (other) TPMs, - * ContinueSelfTest may block. In that case, we definitely don't want to - * call it here. For TPMs in the intersection of these two sets, we're - * screwed. (In other words: TPMs that require manually starting the - * self-test AND block will have poor performance until we split - * TlclSendReceive() into Send() and Receive(), and have a state machine to - * control setup.) - * - * This comment is likely to become obsolete in the near future, so don't - * trust it. It may have not been updated. - */ + /* + * Some TPMs start the self test automatically at power on. In that case + * we don't need to call ContinueSelfTest. On some (other) TPMs, + * continue_self_test may block. In that case, we definitely don't want + * to call it here. For TPMs in the intersection of these two sets, we + * are screwed. (In other words: TPMs that require manually starting the + * self-test AND block will have poor performance until we split + * tlcl_send_receive() into send() and receive(), and have a state + * machine to control setup.) + * + * This comment is likely to become obsolete in the near future, so + * don't trust it. It may have not been updated. + */ #ifdef TPM_MANUAL_SELFTEST #ifdef TPM_BLOCKING_CONTINUESELFTEST #warning "lousy TPM!" #endif - RETURN_ON_FAILURE(TlclContinueSelfTest()); + RETURN_ON_FAILURE(tlcl_continue_self_test()); #endif - result = TlclAssertPhysicalPresence(); + result = tlcl_assert_physical_presence(); if (result != TPM_SUCCESS) { /* * It is possible that the TPM was delivered with the physical * presence command disabled. This tries enabling it, then * tries asserting PP again. */ - RETURN_ON_FAILURE(TlclPhysicalPresenceCMDEnable()); - RETURN_ON_FAILURE(TlclAssertPhysicalPresence()); + RETURN_ON_FAILURE(tlcl_physical_presence_cmd_enable()); + RETURN_ON_FAILURE(tlcl_assert_physical_presence()); } /* Check that the TPM is enabled and activated. */ - RETURN_ON_FAILURE(TlclGetFlags(&disable, &deactivated, NULL)); + RETURN_ON_FAILURE(tlcl_get_flags(&disable, &deactivated, NULL)); if (disable || deactivated) { - VBDEBUG(("TPM: disabled (%d) or deactivated (%d). Fixing...\n", - disable, deactivated)); - RETURN_ON_FAILURE(TlclSetEnable()); - RETURN_ON_FAILURE(TlclSetDeactivated(0)); - VBDEBUG(("TPM: Must reboot to re-enable\n")); + VBDEBUG("TPM: disabled (%d) or deactivated (%d). Fixing...\n", + disable, deactivated); + RETURN_ON_FAILURE(tlcl_set_enable()); + RETURN_ON_FAILURE(tlcl_set_deactivated(0)); + VBDEBUG("TPM: Must reboot to re-enable\n"); return TPM_E_MUST_REBOOT; } - /* Read the firmware space. */ - result = ReadSpaceFirmware(rsf); - if (TPM_E_BADINDEX == result) { - RollbackSpaceKernel rsk; - - /* - * This is the first time we've run, and the TPM has not been - * initialized. Initialize it. - */ - VBDEBUG(("TPM: Not initialized yet.\n")); - RETURN_ON_FAILURE(OneTimeInitializeTPM(rsf, &rsk)); - } else if (TPM_SUCCESS != result) { - VBDEBUG(("TPM: Firmware space in a bad state; giving up.\n")); - return TPM_E_CORRUPTED_STATE; - } - Memcpy(&versions, &rsf->fw_versions, sizeof(versions)); - VBDEBUG(("TPM: Firmware space sv%d f%x v%x\n", - rsf->struct_version, rsf->flags, versions)); - in_flags = rsf->flags; - - /* If we've been asked to clear the virtual dev-mode flag, do so now */ - if (disable_dev_request) { - rsf->flags &= ~FLAG_VIRTUAL_DEV_MODE_ON; - VBDEBUG(("TPM: Clearing virt dev-switch: f%x\n", rsf->flags)); - } - - /* - * The developer_mode value that's passed in is only set by a hardware - * dev-switch. We should OR it with the virtual switch, whether or not - * the virtual switch is used. If it's not used, it shouldn't change, - * so it doesn't matter. - */ - if (rsf->flags & FLAG_VIRTUAL_DEV_MODE_ON) - developer_mode = 1; - - /* - * Clear ownership if developer flag has toggled, or if an owner-clear - * has been requested. - */ - if ((developer_mode ? FLAG_LAST_BOOT_DEVELOPER : 0) != - (in_flags & FLAG_LAST_BOOT_DEVELOPER)) { - VBDEBUG(("TPM: Developer flag changed; clearing owner.\n")); - RETURN_ON_FAILURE(TPMClearAndReenable()); - } else if (clear_tpm_owner_request) { - VBDEBUG(("TPM: Clearing owner as specifically requested.\n")); - RETURN_ON_FAILURE(TPMClearAndReenable()); - } - - if (developer_mode) - rsf->flags |= FLAG_LAST_BOOT_DEVELOPER; - else - rsf->flags &= ~FLAG_LAST_BOOT_DEVELOPER; - - - /* If firmware space is dirty, flush it back to the TPM */ - if (rsf->flags != in_flags) { - VBDEBUG(("TPM: Updating firmware space.\n")); - RETURN_ON_FAILURE(WriteSpaceFirmware(rsf)); - } - - VBDEBUG(("TPM: SetupTPM() succeeded\n")); - return TPM_SUCCESS; -} - - -#ifdef DISABLE_ROLLBACK_TPM -/* Dummy implementations which don't support TPM rollback protection */ - -uint32_t RollbackS3Resume(void) -{ -#ifndef CHROMEOS_ENVIRONMENT - /* - * Initialize the TPM, but ignore return codes. In ChromeOS - * environment, don't even talk to the TPM. - */ - TlclLibInit(); - TlclResume(); -#endif - return TPM_SUCCESS; -} - -uint32_t RollbackFirmwareSetup(int is_hw_dev, - int disable_dev_request, - int clear_tpm_owner_request, - int *is_virt_dev, uint32_t *version) -{ -#ifndef CHROMEOS_ENVIRONMENT - /* - * Initialize the TPM, but ignores return codes. In ChromeOS - * environment, don't even talk to the TPM. - */ - TlclLibInit(); - TlclStartup(); - TlclContinueSelfTest(); -#endif - *is_virt_dev = 0; - *version = 0; - return TPM_SUCCESS; -} - -uint32_t RollbackFirmwareWrite(uint32_t version) -{ - return TPM_SUCCESS; -} - -uint32_t RollbackFirmwareLock(void) -{ - return TPM_SUCCESS; -} - -uint32_t RollbackKernelRead(uint32_t* version) -{ - *version = 0; - return TPM_SUCCESS; -} - -uint32_t RollbackKernelWrite(uint32_t version) -{ - return TPM_SUCCESS; -} - -uint32_t RollbackBackupRead(uint8_t *raw) -{ + VBDEBUG("TPM: SetupTPM() succeeded\n"); return TPM_SUCCESS; } -uint32_t RollbackBackupWrite(uint8_t *raw) +uint32_t antirollback_read_space_firmware(struct vb2_context *ctx) { - return TPM_SUCCESS; -} + uint32_t rv; -uint32_t RollbackKernelLock(int recovery_mode) -{ - return TPM_SUCCESS; -} + rv = setup_tpm(ctx); + if (rv) + return rv; -#else - -uint32_t RollbackS3Resume(void) -{ - uint32_t result; - RETURN_ON_FAILURE(TlclLibInit()); - result = TlclResume(); - if (result == TPM_E_INVALID_POSTINIT) { + /* Read the firmware space. */ + rv = read_space_firmware(ctx); + if (rv == TPM_E_BADINDEX) { /* - * We're on a platform where the TPM maintains power in S3, so - * it's already initialized. + * This seems the first time we've run. Initialize the TPM. */ - return TPM_SUCCESS; - } - return result; -} - -uint32_t RollbackFirmwareSetup(int is_hw_dev, - int disable_dev_request, - int clear_tpm_owner_request, - int *is_virt_dev, uint32_t *version) -{ - RollbackSpaceFirmware rsf; - - /* Set version to 0 in case we fail */ - *version = 0; - - RETURN_ON_FAILURE(SetupTPM(is_hw_dev, disable_dev_request, - clear_tpm_owner_request, &rsf)); - Memcpy(version, &rsf.fw_versions, sizeof(*version)); - *is_virt_dev = (rsf.flags & FLAG_VIRTUAL_DEV_MODE_ON) ? 1 : 0; - VBDEBUG(("TPM: RollbackFirmwareSetup %x\n", (int)*version)); - return TPM_SUCCESS; -} - -uint32_t RollbackFirmwareWrite(uint32_t version) -{ - RollbackSpaceFirmware rsf; - uint32_t old_version; - - RETURN_ON_FAILURE(ReadSpaceFirmware(&rsf)); - Memcpy(&old_version, &rsf.fw_versions, sizeof(old_version)); - VBDEBUG(("TPM: RollbackFirmwareWrite %x --> %x\n", (int)old_version, - (int)version)); - Memcpy(&rsf.fw_versions, &version, sizeof(version)); - return WriteSpaceFirmware(&rsf); -} - -uint32_t RollbackFirmwareLock(void) -{ - return TlclSetGlobalLock(); -} - -uint32_t RollbackKernelRead(uint32_t* version) -{ - RollbackSpaceKernel rsk; - uint32_t perms, uid; - - /* - * Read the kernel space and verify its permissions. If the kernel - * space has the wrong permission, or it doesn't contain the right - * identifier, we give up. This will need to be fixed by the - * recovery kernel. We have to worry about this because at any time - * (even with PP turned off) the TPM owner can remove and redefine a - * PP-protected space (but not write to it). - */ - RETURN_ON_FAILURE(ReadSpaceKernel(&rsk)); - RETURN_ON_FAILURE(TlclGetPermissions(KERNEL_NV_INDEX, &perms)); - Memcpy(&uid, &rsk.uid, sizeof(uid)); - if (TPM_NV_PER_PPWRITE != perms || ROLLBACK_SPACE_KERNEL_UID != uid) + VBDEBUG("TPM: Not initialized yet.\n"); + RETURN_ON_FAILURE(factory_initialize_tpm(ctx)); + } else if (rv != TPM_SUCCESS) { + VBDEBUG("TPM: Firmware space in a bad state; giving up.\n"); + //RETURN_ON_FAILURE(factory_initialize_tpm(ctx)); return TPM_E_CORRUPTED_STATE; + } - Memcpy(version, &rsk.kernel_versions, sizeof(*version)); - VBDEBUG(("TPM: RollbackKernelRead %x\n", (int)*version)); return TPM_SUCCESS; } -uint32_t RollbackKernelWrite(uint32_t version) +uint32_t antirollback_write_space_firmware(struct vb2_context *ctx) { - RollbackSpaceKernel rsk; - uint32_t old_version; - RETURN_ON_FAILURE(ReadSpaceKernel(&rsk)); - Memcpy(&old_version, &rsk.kernel_versions, sizeof(old_version)); - VBDEBUG(("TPM: RollbackKernelWrite %x --> %x\n", - (int)old_version, (int)version)); - Memcpy(&rsk.kernel_versions, &version, sizeof(version)); - return WriteSpaceKernel(&rsk); + return write_space_firmware(ctx); } -/* - * We don't really care whether the TPM owner has been messing with this or - * not. We lock it along with the Kernel space just to avoid problems, but it's - * only useful in dev-mode and only when the battery has been drained - * completely. There aren't any security issues. It's just in the TPM because - * we don't have any other place to keep it. - */ -uint32_t RollbackBackupRead(uint8_t *raw) -{ - uint32_t r; - r = TlclRead(BACKUP_NV_INDEX, raw, BACKUP_NV_SIZE); - VBDEBUG(("TPM: %s returning 0x%x\n", __func__, r)); - return r; -} - -uint32_t RollbackBackupWrite(uint8_t *raw) +uint32_t antirollback_lock_space_firmware() { - uint32_t r; - r = TlclWrite(BACKUP_NV_INDEX, raw, BACKUP_NV_SIZE); - VBDEBUG(("TPM: %s returning 0x%x\n", __func__, r)); - return r; + return tlcl_set_global_lock(); } - -uint32_t RollbackKernelLock(int recovery_mode) -{ - if (recovery_mode) - return TPM_SUCCESS; - else - return TlclLockPhysicalPresence(); -} - -#endif /* DISABLE_ROLLBACK_TPM */ diff --git a/src/vendorcode/google/chromeos/vboot_main.c b/src/vendorcode/google/chromeos/vboot_main.c index 8251cfd..252dfb1 100644 --- a/src/vendorcode/google/chromeos/vboot_main.c +++ b/src/vendorcode/google/chromeos/vboot_main.c @@ -1,10 +1,14 @@ #include <2api.h> #include <2struct.h> +#include <antirollback.h> +#include <arch/exception.h> #include <arch/stages.h> #include <cbfs.h> #include <console/console.h> #include <console/vtxprintf.h> #include <reset.h> +#include <soc/addressmap.h> +#include <soc/clock.h> #include <string.h> #include "chromeos.h" @@ -64,8 +68,12 @@ void vb2ex_printf(const char *func, const char *fmt, ...) int vb2ex_tpm_clear_owner(struct vb2_context *ctx) { - VBDEBUG("Clearing owner\n"); - return VB2_ERROR_UNKNOWN; + uint32_t rv; + VBDEBUG("Clearing TPM owner\n"); + rv = tpm_clear_and_reenable(); + if (rv) + return VB2_ERROR_EX_TPM_CLEAR_OWNER; + return VB2_SUCCESS; } int vb2ex_read_resource(struct vb2_context *ctx, @@ -222,6 +230,54 @@ static void enter_stage(struct cbfs_stage *stage) stage_exit((void *)(uintptr_t)stage->entry); } +enum { + L2CTLR_ECC_PARITY = 0x1 << 21, + L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, + L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, + L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, + L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 +}; + +enum { + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, + L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 +}; + +/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ +static void configure_l2ctlr(void) +{ + uint32_t val; + + val = read_l2ctlr(); + val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); + val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | + L2CTLR_ECC_PARITY); + write_l2ctlr(val); +} + +/* Configures L2 Auxiliary Control Register for Cortex A15. */ +static void configure_l2actlr(void) +{ + uint32_t val; + + val = read_l2actlr(); + val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); + write_l2actlr(val); +} + +static void enable_cache(void) +{ + mmu_init(); + mmu_config_range(0, CONFIG_SYS_SDRAM_BASE >> 20, DCACHE_OFF); + mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); + mmu_disable_range(0, 1); + VBDEBUG("Enabling cache\n"); + dcache_mmu_enable(); +} + /** * Save non-volatile and/or secure data if needed. */ @@ -229,16 +285,24 @@ static void save_if_needed(struct vb2_context *ctx) { if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { VBDEBUG("Saving nvdata\n"); - //save_vbnv(ctx->nvdata); + save_vbnv(ctx->nvdata); ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; } if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { VBDEBUG("Saving secdata\n"); - //antirollback_write_space_firmware(ctx); + antirollback_write_space_firmware(ctx); ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED; } } +/** + * Load and verify the next stage from RW image and jump to it + * + * If validation fails, it exits to romstage for recovery or reboots. + * + * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage). + * when per-stage verification is ready. + */ void __attribute__((noinline)) select_firmware(void) { struct vb2_context ctx; @@ -248,7 +312,12 @@ void __attribute__((noinline)) select_firmware(void) struct cbfs_stage *stage; int rv; + /* Do minimum to enable cache and run vboot at full speed */ + configure_l2ctlr(); + configure_l2actlr(); console_init(); + exception_init(); + enable_cache(); /* Set up context */ memset(&ctx, 0, sizeof(ctx)); @@ -257,12 +326,12 @@ void __attribute__((noinline)) select_firmware(void) memset(ctx.workbuf, 0, ctx.workbuf_size); /* Read nvdata from a non-volatile storage */ - //read_vbnv(ctx.nvdata); + read_vbnv(ctx.nvdata); /* Read secdata from TPM. Initialize TPM if secdata not found. We don't * check the return value here because vb2api_fw_phase1 will catch * invalid secdata and tell us what to do (=reboot). */ - //antirollback_read_space_firmware(&ctx); + antirollback_read_space_firmware(&ctx); if (get_developer_mode_switch()) ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;

1 0

New patch to review for coreboot: 59e17eb coreboot: rk3288: Add a stub implementation of the rk3288 SOC
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8653 -gerrit commit 59e17eb720e3342aaff9d2c229b218cdb308c9c4 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Sun Jun 22 20:40:39 2014 -0700 coreboot: rk3288: Add a stub implementation of the rk3288 SOC Most things still needs to be filled in, but this will allow us to build boards which use this SOC. BUG=chrome-os-partner:29778 TEST=emerge-veyron coreboot Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205069 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239 --- src/mainboard/google/Kconfig | 3 + src/mainboard/google/veyron/Kconfig | 58 +++++++++++ src/mainboard/google/veyron/Makefile.inc | 23 +++++ src/mainboard/google/veyron/chromeos.c | 46 +++++++++ src/mainboard/google/veyron/devicetree.cb | 49 +++++++++ src/mainboard/google/veyron/mainboard.c | 51 ++++++++++ src/mainboard/google/veyron/romstage.c | 59 +++++++++++ src/soc/Kconfig | 1 + src/soc/Makefile.inc | 1 + src/soc/rockchip/Kconfig | 20 ++++ src/soc/rockchip/Makefile.inc | 20 ++++ src/soc/rockchip/rk3288/Kconfig | 118 ++++++++++++++++++++++ src/soc/rockchip/rk3288/Makefile.inc | 41 ++++++++ src/soc/rockchip/rk3288/addressmap.h | 102 +++++++++++++++++++ src/soc/rockchip/rk3288/bootblock.c | 28 ++++++ src/soc/rockchip/rk3288/cbmem.c | 29 ++++++ src/soc/rockchip/rk3288/media.c | 27 +++++ src/soc/rockchip/rk3288/monotonic_timer.c | 40 ++++++++ src/soc/rockchip/rk3288/timer.c | 58 +++++++++++ src/soc/rockchip/rk3288/timer.h | 43 ++++++++ src/soc/rockchip/rk3288/uart.c | 159 ++++++++++++++++++++++++++++++ 21 files changed, 976 insertions(+) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 210bf46..fb1ead6 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -59,6 +59,8 @@ config BOARD_GOOGLE_STORM bool "Storm" config BOARD_GOOGLE_STOUT bool "Stout" +config BOARD_GOOGLE_VEYRON + bool "Veyron" endchoice @@ -81,6 +83,7 @@ source "src/mainboard/google/samus/Kconfig" source "src/mainboard/google/slippy/Kconfig" source "src/mainboard/google/storm/Kconfig" source "src/mainboard/google/stout/Kconfig" +source "src/mainboard/google/veyron/Kconfig" config MAINBOARD_VENDOR string "Mainboard Vendor" diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig new file mode 100644 index 0000000..e65001f --- /dev/null +++ b/src/mainboard/google/veyron/Kconfig @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_VEYRON + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select SOC_ROCKCHIP_RK3288 + select MAINBOARD_DO_NATIVE_VGA_INIT + +config MAINBOARD_DIR + string + default google/veyron + +config MAINBOARD_PART_NUMBER + string + default "Veyron" + +config MAINBOARD_VENDOR + string + default "Google" + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 1 + +config DRAM_DMA_START + hex + default 0x10000000 + +config DRAM_DMA_SIZE + hex + default 0x00200000 + +config DRAM_SIZE_MB + int + default 2048 + +endif # BOARD_GOOGLE_VEYRON diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc new file mode 100644 index 0000000..50a6ba0 --- /dev/null +++ b/src/mainboard/google/veyron/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += romstage.c +ramstage-y += mainboard.c +ramstage-y += chromeos.c + diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c new file mode 100644 index 0000000..f396b4b --- /dev/null +++ b/src/mainboard/google/veyron/chromeos.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/google/veyron/devicetree.cb b/src/mainboard/google/veyron/devicetree.cb new file mode 100644 index 0000000..0acbae9 --- /dev/null +++ b/src/mainboard/google/veyron/devicetree.cb @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# TODO fill with Versatile Express board data in QEMU. +chip soc/rockchip/rk3288 + device cpu_cluster 0 on end + #SCREEN_RGB + register "screen_type" = "2" + #LVDS_8BIT_2 + register "lvds_format" = "1" + #OUT_D888_P666 + register "out_face" = "33" + register "clock_frequency" = "71000000" + register "hactive" = "1280" + register "vactive" = "800" + register "hback_porch" = "100" + register "hfront_porch" = "18" + register "vback_porch" = "8" + register "vfront_porch" = "6" + register "hsync_len" = "10" + register "vsync_len" = "2" + register "hsync_active" = "0" + register "vsync_active" = "0" + register "de_active" = "0" + register "pixelclk_active" = "0" + register "swap_rb" = "0" + register "swap_rg" = "0" + register "swap_gb" = "0" + #LCD_EN_GPIO:GPIO7_A3 + register "lcd_en_gpio" = "0xff7e0004" + #LCD_CS_GPIO:GPIO7_A4 + register "lcd_cs_gpio" = "0xff7e0005" +end diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c new file mode 100644 index 0000000..607b1d5 --- /dev/null +++ b/src/mainboard/google/veyron/mainboard.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/cache.h> +#include <delay.h> +#include <edid.h> +#include <vbe.h> +#include <boot/coreboot_tables.h> + +static void mainboard_init(device_t dev) +{ + +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = CONFIG_DRAM_DMA_START; + dma->range_size = CONFIG_DRAM_DMA_SIZE; +} diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c new file mode 100644 index 0000000..b9daefe --- /dev/null +++ b/src/mainboard/google/veyron/romstage.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <armv7.h> +#include <cbfs.h> +#include <console/console.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <delay.h> +#include <timestamp.h> +#include <arch/cache.h> +#include <arch/exception.h> + +void main(void) +{ + void *entry; + + console_init(); + + /* used for MMU and CBMEM setup, in MB */ + u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); + u32 dram_size = CONFIG_DRAM_SIZE_MB; + u32 dram_end = dram_start + dram_size; + mmu_init(); + /* Device memory below DRAM is uncached. */ + mmu_config_range(0, dram_start, DCACHE_OFF); + /* DRAM is cached. */ + mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); + /* A window for DMA is uncached. */ + mmu_config_range(CONFIG_DRAM_DMA_START >> 20, + CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + /* The space above DRAM is uncached. */ + if (dram_end < 4096) + mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); + mmu_disable_range(0, 1); + dcache_mmu_enable(); + + cbmem_initialize_empty(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); +} diff --git a/src/soc/Kconfig b/src/soc/Kconfig index 0412919..a36bedd 100644 --- a/src/soc/Kconfig +++ b/src/soc/Kconfig @@ -1,5 +1,6 @@ source src/soc/intel/Kconfig source src/soc/nvidia/Kconfig source src/soc/qualcomm/Kconfig +source src/soc/rockchip/Kconfig source src/soc/samsung/Kconfig source src/soc/ucb/Kconfig diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc index ab3e166..80dd109 100644 --- a/src/soc/Makefile.inc +++ b/src/soc/Makefile.inc @@ -4,5 +4,6 @@ subdirs-y += intel subdirs-y += nvidia subdirs-y += qualcomm +subdirs-y += rockchip subdirs-y += samsung subdirs-y += ucb diff --git a/src/soc/rockchip/Kconfig b/src/soc/rockchip/Kconfig new file mode 100644 index 0000000..b041f89 --- /dev/null +++ b/src/soc/rockchip/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +source src/soc/rockchip/rk3288/Kconfig diff --git a/src/soc/rockchip/Makefile.inc b/src/soc/rockchip/Makefile.inc new file mode 100644 index 0000000..aa67f5c --- /dev/null +++ b/src/soc/rockchip/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-$(CONFIG_SOC_ROCKCHIP_RK3288) += rk3288 diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig new file mode 100644 index 0000000..e15a9ae --- /dev/null +++ b/src/soc/rockchip/rk3288/Kconfig @@ -0,0 +1,118 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOC_ROCKCHIP_RK3288 + bool + default n + select CPU_HAS_BOOTBLOCK_INIT + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select EARLY_CONSOLE + select DYNAMIC_CBMEM + select ARCH_BOOTBLOCK_ARM_V7 + select ARCH_ROMSTAGE_ARM_V7 + select ARCH_RAMSTAGE_ARM_V7 + select HAVE_UART_MEMORY_MAPPED + select BOOTBLOCK_CONSOLE + +if SOC_ROCKCHIP_RK3288 + +config BOOTBLOCK_CPU_INIT + string + default "soc/rockchip/rk3288/bootblock.c" + +# ROM image layout. +# +# 0x00000 Combined bootblock and ID Block +# 0x08000 Master CBFS header. +# 0x18000 Free for CBFS data. +# +# iRAM (96k) layout. +# (Note: The BootROM will jump to 0xff704004 after loading bootblock, +# so the bootblock loading address must be at 0xff704004.) +# +# 0xFF70_0000 TTB (16KB). +# 0xFF70_4004 Bootblock (max 16KB-4B). +# 0xFF70_8000 ROM stage (max 40KB). +# 0xFF71_2000 STACK (4KB). +# 0xFF71_3000 CBFS mapping cache (20K) +# 0xFF71_7FFF End of iRAM. + +config SYS_SDRAM_BASE + hex "SDRAM base address" + default 0x00000000 + +config STACK_TOP + hex "STACK TOP" + default 0xff713000 + +config STACK_BOTTOM + hex "STACK BOTTOM" + default 0xff712000 + +config BOOTBLOCK_BASE + hex + default 0xff704004 + +config ROMSTAGE_BASE + hex "ROM STAGE BASE" + default 0xff708000 + +config RAMSTAGE_BASE + hex "RAMSTAGE BASE" + default 0x00200000 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x0008000 + +config CBFS_ROM_OFFSET + hex + default 0x0018000 + +config CBFS_SRAM_CACHE_ADDRESS + hex "sram memory address to put CBFS cache data" + default 0xff713000 + +config CBFS_SRAM_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00005000 + +config CBFS_DRAM_CACHE_ADDRESS + hex "dram memory address to put CBFS cache data" + default 0x01000000 + +config CBFS_DRAM_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00100000 + +config TTB_BUFFER + hex "memory address of the TTB buffer" + default 0xff700000 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0xFF690000 + +endif diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc new file mode 100644 index 0000000..ae908a7 --- /dev/null +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bootblock-y += bootblock.c +bootblock-y += cbmem.c +bootblock-y += timer.c +bootblock-y += monotonic_timer.c +bootblock-y += media.c +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +endif + +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += monotonic_timer.c +romstage-y += media.c +ifeq ($(CONFIG_EARLY_CONSOLE),y) +romstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +endif + +ramstage-y += cbmem.c +ramstage-y += timer.c +ramstage-y += monotonic_timer.c +ramstage-y += media.c +ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c diff --git a/src/soc/rockchip/rk3288/addressmap.h b/src/soc/rockchip/rk3288/addressmap.h new file mode 100644 index 0000000..865e3c2 --- /dev/null +++ b/src/soc/rockchip/rk3288/addressmap.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ +#define __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ + +#define SDMMC1_BASE 0xFF0C0000 +#define SDMMC0_BASE 0xFF0D0000 +#define EMMC_BASE 0xFF0F0000 +#define SARADC_BASE 0xFF100000 + +#define SPI0_BASE 0xFF110000 +#define SPI1_BASE 0xFF120000 +#define SPI2_BASE 0xFF130000 + +#define I2C1_BASE 0xFF140000 +#define I2C3_BASE 0xFF150000 +#define I2C4_BASE 0xFF160000 +#define I2C5_BASE 0xFF170000 +#define UART0_BASE 0xFF180000 +#define UART1_BASE 0xFF190000 +#define DMAC_PERI_BASE 0xFF250000 + +#define NANDC0_BASE 0xFF400000 +#define NANDC1_BASE 0xFF410000 + +#define USB_HOST0_EHCI_BASE 0xFF500000 +#define USB_HOST0_OHCI_BASE 0xFF520000 +#define USB_HOST1_BASE 0xFF540000 +#define USB_OTG_BASE 0xFF580000 + +#define DMAC_BUS_BASE 0xFF600000 + +#define DDR_PCTL0_BASE 0xFF610000 +#define DDR_PCTL1_BASE 0xFF630000 +#define DDR_PUBL0_BASE 0xFF620000 +#define DDR_PUBL1_BASE 0xFF640000 + +#define I2C0_BASE 0xFF650000 +#define I2C2_BASE 0xFF660000 +#define DW_PWM0123_BASE 0xFF670000 +#define RK_PWM0123_BASE 0xFF680000 +#define UART2_BASE 0xFF690000 +#define TIMER0_BASE 0xFF6B0000 + +#define SRAM_BASE 0xFF700000 +#define PMU_BASE 0xFF730000 +#define GRF_SECURE_BASE 0xFF740000 +#define GPIO0_BASE 0xFF750000 +#define CRU_BASE 0xFF760000 +#define GRF_BASE 0xFF770000 +#define GPIO1_BASE 0xFF780000 +#define GPIO2_BASE 0xFF790000 +#define GPIO3_BASE 0xFF7A0000 +#define GPIO4_BASE 0xFF7B0000 +#define GPIO5_BASE 0xFF7C0000 +#define GPIO6_BASE 0xFF7D0000 +#define GPIO7_BASE 0xFF7E0000 +#define GPIO8_BASE 0xFF7F0000 + +#define TIMER6_BASE 0xFF810000 +#define TIMER7_BASE 0xFF810020 + +#define VOP_BIG_BASE 0xFF930000 +#define HDMI_TX_BASE 0xFF980000 +#define DMACS_BUS_BASE 0xFFB20000 + +#define SERVICE_CORE_BASE 0xFFA80000 +#define SERVICE_DMA_BASE 0xFFA90000 +#define SERVICE_GPU_BASE 0xFFAA0000 +#define SERVICE_PERI_BASE 0xFFAB0000 +#define SERVICE_BUS_BASE 0xFFAC0000 +#define SERVICE_VIO_BASE 0xFFAD0000 +#define SERVICE_VPU_BASE 0xFFAE0000 +#define SERVICE_HEVC_BASE 0xFFAF0000 + +#define EFUSE_BASE 0xFFB40000 + +#define CORE_GICD_BASE 0xFFC01000 +#define CORE_GICC_BASE 0xFFC02000 +#define CPU_AXI_BUS_BASE 0xFFE00000 + +#define BOOT_ROM_BASE 0xFFFF0000 +#define BOOT_ROM_CHIP_VER (BOOT_ROM+0x27F0) + +#endif /* __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ */ diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c new file mode 100644 index 0000000..2bdd508 --- /dev/null +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/cache.h> +#include <bootblock_common.h> +#include "timer.h" + +void bootblock_cpu_init(void) +{ + rk3288_init_timer(); +} diff --git a/src/soc/rockchip/rk3288/cbmem.c b/src/soc/rockchip/rk3288/cbmem.c new file mode 100644 index 0000000..b29c87a --- /dev/null +++ b/src/soc/rockchip/rk3288/cbmem.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <cbmem.h> + +#define FB_SIZE_MB 4 +void *cbmem_top(void) +{ + return (void *)(CONFIG_SYS_SDRAM_BASE + + (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)*MiB); +} + diff --git a/src/soc/rockchip/rk3288/media.c b/src/soc/rockchip/rk3288/media.c new file mode 100644 index 0000000..75713eb --- /dev/null +++ b/src/soc/rockchip/rk3288/media.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <string.h> +#include <console/console.h> + +int init_default_cbfs_media(struct cbfs_media *media) +{ + return 0; +} diff --git a/src/soc/rockchip/rk3288/monotonic_timer.c b/src/soc/rockchip/rk3288/monotonic_timer.c new file mode 100644 index 0000000..d33ed68 --- /dev/null +++ b/src/soc/rockchip/rk3288/monotonic_timer.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <timer.h> +#include <arch/io.h> +#include "addressmap.h" +#include "timer.h" + +static uint64_t timer_raw_value(void) +{ + uint64_t value0; + uint64_t value1; + + value0 = (uint64_t)read32(&timer7_ptr->timer_curr_value0); + value1 = (uint64_t)read32(&timer7_ptr->timer_curr_value1); + value0 = value0 | value1<<32; + return value0; +} + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timer_raw_value() / clocks_per_usec); +} diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c new file mode 100644 index 0000000..3a2c34d --- /dev/null +++ b/src/soc/rockchip/rk3288/timer.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <arch/io.h> +#include "timer.h" + +void init_timer(void) +{ +} + +void rk3288_init_timer(void) +{ + write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count0); + write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count1); + write32(1, &timer7_ptr->timer_ctrl_reg); +} + +/* delay x useconds */ +void udelay(unsigned usec) +{ + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_usecs(&end, usec); + + if (mono_time_after(&current, &end)) { + printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", + usec); + /* There's not much we can do if usec is too big. Use a long, + * paranoid delay value and hope for the best... */ + end = current; + mono_time_add_usecs(&end, USECS_PER_SEC); + } + + while (mono_time_before(&current, &end)) + timer_monotonic_get(&current); +} + diff --git a/src/soc/rockchip/rk3288/timer.h b/src/soc/rockchip/rk3288/timer.h new file mode 100644 index 0000000..8c72a4f --- /dev/null +++ b/src/soc/rockchip/rk3288/timer.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ROCKCHIP_RK3288_TIMER_H__ +#define __ROCKCHIP_RK3288_TIMER_H__ + +#include "addressmap.h" + +#define SYS_CLK_FREQ 24000000 +static const uint32_t clocks_per_usec = SYS_CLK_FREQ/1000000; + +struct rk3288_timer { + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_curr_value0; + u32 timer_curr_value1; + u32 timer_ctrl_reg; + u32 timer_int_status; +}; + +static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE; + +#define TIMER_LOAD_VAL 0xffffffff + +void rk3288_init_timer(void); + +#endif /* __ROCKCHIP_RK3288_TIMER_H__ */ diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c new file mode 100644 index 0000000..ef02241 --- /dev/null +++ b/src/soc/rockchip/rk3288/uart.c @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <uart.h> +#include <arch/io.h> +#include <console/console.h> /* for __console definition */ +#include <stdint.h> +#include <uart8250.h> + +struct rk3288_uart { + union { + uint32_t thr; /* Transmit holding register. */ + uint32_t rbr; /* Receive buffer register. */ + uint32_t dll; /* Divisor latch lsb. */ + }; + union { + uint32_t ier; /* Interrupt enable register. */ + uint32_t dlm; /* Divisor latch msb. */ + }; + union { + uint32_t iir; /* Interrupt identification register. */ + uint32_t fcr; /* FIFO control register. */ + }; + uint32_t lcr; /* Line control register. */ + uint32_t mcr; /* Modem control register. */ + uint32_t lsr; /* Line status register. */ + uint32_t msr; /* Modem status register. */ + uint32_t scr; + uint32_t reserved1[(0x30 - 0x20) / 4]; + uint32_t srbr[(0x70 - 0x30) / 4]; + uint32_t far; + uint32_t tfr; + uint32_t rfw; + uint32_t usr; + uint32_t tfl; + uint32_t rfl; + uint32_t srr; + uint32_t srts; + uint32_t sbcr; + uint32_t sdmam; + uint32_t sfe; + uint32_t srt; + uint32_t stet; + uint32_t htx; + uint32_t dmasa; + uint32_t reserver2[(0xf4 - 0xac) / 4]; + uint32_t cpr; + uint32_t ucv; + uint32_t ctr; +} __attribute__ ((packed)); + +static struct rk3288_uart * const uart_ptr = + (void *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + +static void rk3288_uart_tx_flush(void); +static int rk3288_uart_tst_byte(void); + +static void rk3288_uart_init(void) +{ + // Use a hardcoded divisor for now. + const unsigned divisor = 13; + const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1 + + rk3288_uart_tx_flush(); + + // Disable interrupts. + writel(0, &uart_ptr->ier); + // Force DTR and RTS to high. + writel(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr); + // Set line configuration, access divisor latches. + writel(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr); + // Set the divisor. + writel(divisor & 0xff, &uart_ptr->dll); + writel((divisor >> 8) & 0xff, &uart_ptr->dlm); + // Hide the divisor latches. + writel(line_config, &uart_ptr->lcr); + // Enable FIFOs, and clear receive and transmit. + writel(UART8250_FCR_FIFO_EN | + UART8250_FCR_CLEAR_RCVR | + UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr); +} + +static void rk3288_uart_tx_byte(unsigned char data) +{ + while (!(readl(&uart_ptr->lsr) & UART8250_LSR_THRE)); + writel(data, &uart_ptr->thr); +} + +static void rk3288_uart_tx_flush(void) +{ + while (!(readl(&uart_ptr->lsr) & UART8250_LSR_TEMT)); +} + +static unsigned char rk3288_uart_rx_byte(void) +{ + if (!rk3288_uart_tst_byte()) + return 0; + return readl(&uart_ptr->rbr); +} + +static int rk3288_uart_tst_byte(void) +{ + return (readl(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; +} + +#if !defined(__PRE_RAM__) + +static const struct console_driver rk3288_uart_console __console = { + .init = rk3288_uart_init, + .tx_byte = rk3288_uart_tx_byte, + .tx_flush = rk3288_uart_tx_flush, + .rx_byte = rk3288_uart_rx_byte, + .tst_byte = rk3288_uart_tst_byte, +}; + +uint32_t uartmem_getbaseaddr(void) +{ + return (uintptr_t)uart_ptr; +} + +#else + +void uart_init(void) +{ + rk3288_uart_init(); +} + +void uart_tx_byte(unsigned char data) +{ + rk3288_uart_tx_byte(data); +} + +void uart_tx_flush(void) +{ + rk3288_uart_tx_flush(); +} + +unsigned char uart_rx_byte(void) +{ + return rk3288_uart_rx_byte(); +} + +#endif

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Patch merged into coreboot/master: b0922f0 lenovo: fix smi gpe + wakeup pin for t420s t520 t530 x220 x230
by gerrit＠coreboot.org 10 Mar '15

10 Mar '15

the following patch was just integrated into master: commit b0922f0183cb50b9714285c539c387956d86814c Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Feb 1 02:53:35 2015 +0100 lenovo: fix smi gpe + wakeup pin for t420s t520 t530 x220 x230 Set correct gpio routing and enable bits for EC SMI gpio and EC WAKE gpio. Verified with schematics. Change-Id: Ie3b98c4456a870c881e7663b19eb8ca8e5564c5c Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/8358 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8358 for details. -gerrit

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Patch merged into coreboot/master: 60ef456 console/Kconfig: Enable CBMEM console by default
by gerrit＠coreboot.org 10 Mar '15

10 Mar '15

the following patch was just integrated into master: commit 60ef456f46d81faa4f15b8a49b39037037b8b643 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 8 10:46:52 2014 +0100 console/Kconfig: Enable CBMEM console by default Currently on AMD boards no romstage messages can be saved in CBMEM, so only messages from ramstage on will be stored in CBMEM. Other than that nothing changes. Enabling CBMEM console by default does not noticeably decrease boot time as the messages are directly written to CAR or RAM. The board status script under `util/board_status/` reads the coreboot messages from CBMEM, which are then uploaded to the board status repository. With CBMEM console disabled by default, currently no coreboot console messages are uploaded to the board status repository, although it is important to have those. Enabling CBMEM console by default improves this situation, so that for all boards at least ramstage messages are stored in the board status repository. Change-Id: I8d5a58c078325c43a0317bcfaafc722d039aab0b Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5350 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/5350 for details. -gerrit

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Patch merged into coreboot/master: 9e94dbf ACPI: Get S3 resume state from romstage_handoff
by gerrit＠coreboot.org 10 Mar '15

10 Mar '15

the following patch was just integrated into master: commit 9e94dbfcd089db31b2201381f9d83a89cdea86b9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 ACPI: Get S3 resume state from romstage_handoff There is nothing platform specific in retrieving S3 resume state from romstage_handoff structure. Boards without EARLY_CBMEM_INIT update acpi_slp_type from ACPI power-management block or scratchpad registers. Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8188 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8188 for details. -gerrit

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Patch merged into coreboot/master: a637194 x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE option
by gerrit＠coreboot.org 10 Mar '15

10 Mar '15

the following patch was just integrated into master: commit a63719407fc5fad17eebe0e5086511a511466353 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Mar 10 07:25:35 2015 +0200 x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE option This was added to handle cases of Intel FSP platforms that had EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM. These boards were recently fixed. To support combination of EARLY_CBMEM_INIT without CAR migration was added maintenance effort with little benefits. You had no CBMEM console for romstage and the few timestamps you could store were circulated via PCI scratchpads or CMOS nvram. Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8636 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/8636 for details. -gerrit

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Patch merged into coreboot/master: f48b38b ARM romstages: Support and fix COLLECT_TIMESTAMPS
by gerrit＠coreboot.org 10 Mar '15

10 Mar '15

the following patch was just integrated into master: commit f48b38b8d794fda4f1be523e1f823c6b78ab83e3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 08:50:36 2014 +0200 ARM romstages: Support and fix COLLECT_TIMESTAMPS Change-Id: I53959eb937c1db3c4211e23a6476340383a33c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8021 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8021 for details. -gerrit

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Patch merged into coreboot/master: 01fe638 cbmem console: Allow the cbmem console on non-x86 systems again.
by gerrit＠coreboot.org 10 Mar '15

10 Mar '15

the following patch was just integrated into master: commit 01fe6380108a03990150673e034944eafa8b9f8d Author: Gabe Black <gabeblack(a)google.com> Date: Thu Apr 3 14:04:42 2014 -0700 cbmem console: Allow the cbmem console on non-x86 systems again. If it's not supported on a particular board, either the build will fail or checks within the cbmem console itself should detect the problem. There shouldn't be random memory corruption any more. BUG=None TEST=Built with CONSOLE_CBMEM enabled on nyan and saw that it was actually enabled. BRANCH=None Original-Change-Id: Id6c8c7675daafe07aa4878cfcf13faefe576e520 Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193167 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 20b486443bfc2d93d72bbc9e496023a00ab9ab30) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I39fbcdff61f6d8f520f2e9d7612dee78e97898b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7748 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7748 for details. -gerrit

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New patch to review for coreboot: 589ed2d coreboot t132: Remove empty function cpu0_config_and_reset
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8652 -gerrit commit 589ed2d50d6c3e1beb6e152f7aa69fd3ce11e086 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 22 17:25:42 2014 -0700 coreboot t132: Remove empty function cpu0_config_and_reset This function is not used/required in t132. BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: Iba5ea3c14cc9facbf2a86aa08021edb9907f92da Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209425 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit c615136aa82d457540eb1f1308c9e986dbc9bce7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id92d464db24298dd888cbc022204379eb8aa8aba --- src/soc/nvidia/tegra132/clock.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 66eaf1e..a8cabe5 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -474,10 +474,6 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, udelay(IO_STABILIZATION_DELAY); } -void clock_cpu0_config_and_reset(void *entry) -{ -} - void clock_halt_avp(void) { for (;;)

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New patch to review for coreboot: 92d6a99 coreboot t132: Stop running AVP at the end of romstage
by Marc Jones 10 Mar '15

10 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8651 -gerrit commit 92d6a9991e558ad92e19253a576e7acce9900852 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 22 17:21:14 2014 -0700 coreboot t132: Stop running AVP at the end of romstage Stop running AVP at the end of romstage until event conditions are met (JTAG, GIC_IRQ or LIC_IRQ). BUG=chrome-os-partner:30831 BRANCH=None TEST=Compiles successfully and boots till last known good checkpoint. Original-Change-Id: Ia221f08b27ac0c60a66d588e351677144cc6a322 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209424 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit df4e8b4c8a1002443a936bd0563fbc9e0710f489) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I59f7702bd50a1039b8723e9cb12b8d714e353d37 --- src/soc/nvidia/tegra132/romstage.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 4b1c843..812d147 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -29,6 +29,8 @@ #include "sdram.h" #include "ccplex.h" +#include <soc/clock.h> + void romstage(void); void romstage(void) { @@ -71,5 +73,5 @@ void romstage(void) ccplex_cpu_start(entry); - while (1); + clock_halt_avp(); }

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coreboot-gerrit March 2015