coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

1 participants
2443 discussions

Patch merged into coreboot/master: ed48dfd cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY
by gerrit＠coreboot.org 13 Mar '15

13 Mar '15

the following patch was just integrated into master: commit ed48dfdc4edd08d4e9641a87839a9904fdd98c13 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Feb 24 03:07:02 2015 +0100 cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY BIOS Writer's Guide, rev 1.6.0, June 2012: This MSR controls whether and FERR message is sent over the system bus when unmasked x87 exceptions are generated. This feature is not supported from Sandy Bridge processor onwards. Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: http://review.coreboot.org/8658 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8658 for details. -gerrit

1 0

Patch set updated for coreboot: 546fa51 OxPCIe952: Fix read8/write8 argument
by Kyösti Mälkki 13 Mar '15

13 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8660 -gerrit commit 546fa513bccd5020c2366871acf703d54116f69a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 12 11:33:14 2015 +0200 OxPCIe952: Fix read8/write8 argument This was missed in commit bde6d309 as the driver is not enabled in any configuration by default. Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/uart/oxpcie.c | 5 +++-- src/drivers/uart/uart8250mem.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index 76119d2..d49170d 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -34,11 +34,12 @@ static void oxford_oxpcie_enable(device_t dev) printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); return; } + void *bar0 = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", - (read32(res->base) >> 8), (read32(res->base) & 0xff)); + (read32(bar0) >> 8), (read32(bar0) & 0xff)); printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", - (read32(res->base + 4) & 3)); + (read32(bar0 + 4) & 3)); printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); } diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 5fbbeec..cb70700 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -36,12 +36,12 @@ static uint8_t uart8250_read(void *base, uint8_t reg) { - return read8((uintptr_t) (base + reg)); + return read8(base + reg); } static void uart8250_write(void *base, uint8_t reg, uint8_t data) { - write8((uintptr_t) (base + reg), data); + write8(base + reg, data); } static int uart8250_mem_can_tx_byte(void *base)

1 0

Patch merged into coreboot/master: 144a68a coreboot t132: Remove empty function cpu0_config_and_reset
by gerrit＠coreboot.org 12 Mar '15

12 Mar '15

the following patch was just integrated into master: commit 144a68a4ad5123ee03bd9bf0a8596c339e888fd7 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 22 17:25:42 2014 -0700 coreboot t132: Remove empty function cpu0_config_and_reset This function is not used/required in t132. BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: Iba5ea3c14cc9facbf2a86aa08021edb9907f92da Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209425 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit c615136aa82d457540eb1f1308c9e986dbc9bce7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id92d464db24298dd888cbc022204379eb8aa8aba Reviewed-on: http://review.coreboot.org/8652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8652 for details. -gerrit

1 0

Patch merged into coreboot/master: d123f86 coreboot t132: Stop running AVP at the end of romstage
by gerrit＠coreboot.org 12 Mar '15

12 Mar '15

the following patch was just integrated into master: commit d123f865ad06d788a05fe1391ef8861671d0b2da Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 22 17:21:14 2014 -0700 coreboot t132: Stop running AVP at the end of romstage Stop running AVP at the end of romstage until event conditions are met (JTAG, GIC_IRQ or LIC_IRQ). BUG=chrome-os-partner:30831 BRANCH=None TEST=Compiles successfully and boots till last known good checkpoint. Original-Change-Id: Ia221f08b27ac0c60a66d588e351677144cc6a322 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209424 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit df4e8b4c8a1002443a936bd0563fbc9e0710f489) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I59f7702bd50a1039b8723e9cb12b8d714e353d37 Reviewed-on: http://review.coreboot.org/8651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8651 for details. -gerrit

1 0

Patch merged into coreboot/master: 9ad04c6 coreboot arm64: Add int constants to stdint.h
by gerrit＠coreboot.org 12 Mar '15

12 Mar '15

the following patch was just integrated into master: commit 9ad04c61e908e9587ebbc4a5b45b0f4d531ba02e Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 22 10:51:43 2014 -0700 coreboot arm64: Add int constants to stdint.h BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I395c9b7bbe34c6834abc1a169779639f940121bd Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209334 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit da15df16464f4203db08fb02ad4c0a0f94d16724) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I818de7cb0d8a44fb20c2bbea108c15ecc2b724ae Reviewed-on: http://review.coreboot.org/8650 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8650 for details. -gerrit

1 0

Patch merged into coreboot/master: 44f465d tegra132: fix Rx FIFO underruns with slower SPI clock
by gerrit＠coreboot.org 12 Mar '15

12 Mar '15

the following patch was just integrated into master: commit 44f465d21cad78c87c32b916f72e1bff2ef532a0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 21 22:11:29 2014 -0500 tegra132: fix Rx FIFO underruns with slower SPI clock The SPI controller operates on packets which can be variable length up to 32-bit packets. It also has the ability to be put in packed or unpacked mode w.r.t each packet. i.e. does a single fifo register hold >= 1 packet. The current programming uses 8-bit packets in unpacked mode which means 4 fifo slots are used for a 32-bit DMA transfter. As the AHB can only operate on a minimum of 32-bit bursts the triggers need to be programmed correctly so that there is room for a full 32-bit DMA transaction. Previously faster SPI clocks just made things magically work. BUG=chrome-os-partner:30779 BRANCH=None TEST=Built and booted through coreboot with 20MHz SPI clock. Original-Change-Id: I3f1cd4dddcea9514327b2363ed450a527db7e1fe Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208862 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit d9864228a2479e412d7e0d2221fe536f78329acd) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I61c145f35e1f889d4f83f3dfea049bfd347c1196 Reviewed-on: http://review.coreboot.org/8649 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See http://review.coreboot.org/8649 for details. -gerrit

1 0

Patch merged into coreboot/master: 7ddb5f7 tegra132: Add Trust Zone register access
by gerrit＠coreboot.org 12 Mar '15

12 Mar '15

the following patch was just integrated into master: commit 7ddb5f76feea37ed055f2eede944c2971214e2f2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 21 14:24:42 2014 -0500 tegra132: Add Trust Zone register access The Trust Zone carveout registers are only accessible using a secure access mode. The AVP runs as non-secure all the time. In EL3 the CPU is in secure mode, but when the MMU is enabled the page tables dictate if accesses to certain regions are secure or not. However, ramstage is currently being loaded into non-secure memory and the page tables will live in non-secure memory as well. Therefore, handle all these cases by providing global state which mirrors the TZ register. BUG=chrome-os-partner:30782 BRANCH=None TEST=Built and ran through ramstage with the MMU enabled Resources are read and set accordingly. Original-Change-Id: Ib76b2641497a29ef2adb75934b2df55ecf0b3e78 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209061 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 0bcbdc56978f6ebe3e7d1b74ed2fd861e03bb562) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9c1beed443a48870ba190427e87caf90caf4ff6b Reviewed-on: http://review.coreboot.org/8648 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See http://review.coreboot.org/8648 for details. -gerrit

1 0

Patch set updated for coreboot: 5560a56 tegra132: Add Trust Zone register access
by Marc Jones 12 Mar '15

12 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8648 -gerrit commit 5560a5653d476b64164809102c323411fd1c8870 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 21 14:24:42 2014 -0500 tegra132: Add Trust Zone register access The Trust Zone carveout registers are only accessible using a secure access mode. The AVP runs as non-secure all the time. In EL3 the CPU is in secure mode, but when the MMU is enabled the page tables dictate if accesses to certain regions are secure or not. However, ramstage is currently being loaded into non-secure memory and the page tables will live in non-secure memory as well. Therefore, handle all these cases by providing global state which mirrors the TZ register. BUG=chrome-os-partner:30782 BRANCH=None TEST=Built and ran through ramstage with the MMU enabled Resources are read and set accordingly. Original-Change-Id: Ib76b2641497a29ef2adb75934b2df55ecf0b3e78 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209061 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 0bcbdc56978f6ebe3e7d1b74ed2fd861e03bb562) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9c1beed443a48870ba190427e87caf90caf4ff6b --- src/soc/nvidia/tegra132/addressmap.c | 55 ++++++++++++++++-------- src/soc/nvidia/tegra132/include/soc/addressmap.h | 9 ++++ src/soc/nvidia/tegra132/ramstage.c | 23 +--------- src/soc/nvidia/tegra132/romstage.c | 11 +++++ 4 files changed, 58 insertions(+), 40 deletions(-) diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c index 7dbab55..6537187 100644 --- a/src/soc/nvidia/tegra132/addressmap.c +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -27,6 +27,9 @@ #include "mc.h" #include "sdram.h" +static uintptr_t tz_base_mib; +static const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; + /* returns total amount of DRAM (in MB) from memory controller registers */ int sdram_size_mb(void) { @@ -71,13 +74,8 @@ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib) switch (id) { case CARVEOUT_TZ: - /* AVP does not have access to the TZ carveout registers. */ - if (context_avp()) - return; - carveout_from_regs(base_mib, size_mib, - read32(&mc->security_cfg0), - 0, - read32(&mc->security_cfg1)); + *base_mib = tz_base_mib; + *size_mib = tz_size_mib; break; case CARVEOUT_SEC: carveout_from_regs(base_mib, size_mib, @@ -102,7 +100,8 @@ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib) } } -static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib) +static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib, + int ignore_tz) { uintptr_t base; uintptr_t end; @@ -128,6 +127,9 @@ static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib) uintptr_t carveout_end; size_t carveout_size; + if (i == CARVEOUT_TZ && ignore_tz) + continue; + carveout_range(i, &carveout_base, &carveout_size); if (carveout_size == 0) @@ -155,14 +157,14 @@ void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib) { *base_mib = 0; *end_mib = 4096; - memory_in_range(base_mib, end_mib); + memory_in_range(base_mib, end_mib, 0); } void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib) { *base_mib = 4096; *end_mib = ~0UL; - memory_in_range(base_mib, end_mib); + memory_in_range(base_mib, end_mib, 0); } uintptr_t framebuffer_attributes(size_t *size_mib) @@ -173,16 +175,33 @@ uintptr_t framebuffer_attributes(size_t *size_mib) /* Place the framebuffer just below the 32-bit addressable limit. */ memory_in_range_below_4gb(&begin, &end); - /* - * Need to take into account that the Trust Zone region is not able to - * be read by the AVP. The Trust Zone region will live just below the - * rest of the carveout regions. - */ - if (context_avp()) - end -= CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; - *size_mib = FB_SIZE_MB; end -= *size_mib; return end; } + +void trustzone_region_init(void) +{ + struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; + uintptr_t end = 4096; + + /* Already has been initialized. */ + if (tz_size_mib != 0 && tz_base_mib != 0) + return; + + /* + * Get memory layout below 4GiB ignoring the TZ carveout because + * that's the one to initialize. + */ + memory_in_range(&tz_base_mib, &end, 1); + tz_base_mib = end - tz_size_mib; + + /* AVP cannot set the TZ registers proper as it is always non-secure. */ + if (context_avp()) + return; + + /* Set the carveout region. */ + write32(tz_base_mib << 20, &mc->security_cfg0); + write32(tz_size_mib, &mc->security_cfg1); +} diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h index 3d0fc59..52e4d54 100644 --- a/src/soc/nvidia/tegra132/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -99,6 +99,15 @@ enum { /* Provided the careout id, obtain the base and size in 1MiB units. */ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib); +/* + * There are complications accessing the Trust Zone carveout region. The + * AVP cannot access these registers and the CPU can't access this register + * as a non-secure access. When the page tables live in non-secure memory + * these registers cannot be accessed either. Thus, this function handles + * both the AVP case and non-secured access case by keeping global state. + */ +void trustzone_region_init(void); + /* Return pointer and size in 1MiB units. */ uintptr_t framebuffer_attributes(size_t *size_mib); diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index ad553d4..b3b4db2 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -17,34 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/io.h> #include <arch/stages.h> #include <soc/addressmap.h> -#include "mc.h" #include "mmu_operations.h" void arm64_soc_init(void) { - struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; - const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; - uintptr_t base; - uintptr_t end; - - if (!tz_size_mib) - return; - - /* - * Ramstage is when the arm64 first gets running. It also is the - * only entity that the capabilities to program the Trust Zone region. - * Therefore configure the region early. Also, the TZ region can only - * live in 32-bit space. - */ - memory_in_range_below_4gb(&base, &end); - - /* Place the TZ area just below current carveout regions. */ - end -= tz_size_mib; - write32(end << 20, &mc->security_cfg0); - write32(tz_size_mib, &mc->security_cfg1); + trustzone_region_init(); tegra132_mmu_init(); } diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 2a1bd46..4b1c843 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -24,6 +24,7 @@ #include <console/console.h> #include <arch/exception.h> +#include <soc/addressmap.h> #include <soc/sdram_configs.h> #include "sdram.h" #include "ccplex.h" @@ -45,6 +46,16 @@ void romstage(void) sdram_init(get_sdram_config()); printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); #endif + + /* + * Trust Zone needs to be initialized after the DRAM initialization + * because carveout registers are programmed during DRAM init. + * cbmem_initialize() is dependent on the Trust Zone region + * initalization because CBMEM lives right below the Trust Zone which + * needs to be properly identified. + */ + trustzone_region_init(); + cbmem_initialize(); ccplex_cpu_prepare();

1 0

Patch merged into coreboot/master: da9b9f3 t132: Add mmu support
by gerrit＠coreboot.org 12 Mar '15

12 Mar '15

the following patch was just integrated into master: commit da9b9f324b7c4aea46c55bdbd1365a018791ee18 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Jul 17 11:42:35 2014 -0700 t132: Add mmu support Add support for mmu initialization and enabling caches. mmu_operations provides functions to add mmap_regions using memrange library and then calls mmu_init for armv8. BUG=chrome-os-partner:30688 BRANCH=None TEST=Compiles rush successfully and boots until depthcharge load. Goes past all the earlier alignment errors. Original-Change-Id: I57c2be80427fa77239093c79ece73e31fd319239 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208762 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit a6141d13d40cfa5a493bde44e69c588dda97e8fd) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I33bf4b2e28b85a3117b566cb8497f2bd5aabb69b Reviewed-on: http://review.coreboot.org/8647 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8647 for details. -gerrit

1 0

Patch merged into coreboot/master: 2486957 armv8: Add mmu support
by gerrit＠coreboot.org 12 Mar '15

12 Mar '15

the following patch was just integrated into master: commit 2486957514ab722aa1a129e306ac0180ed864112 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Jul 17 11:36:08 2014 -0700 armv8: Add mmu support Add support for initializing and enabling mmu for armv8. Using 64KiB granule and 33 bits per VA, thus total VA address space is 6GiB. PA Range is 64GiB. Makes use of memrange library to get a list of all the mmap regions from the SoC to initialize XLAT table. Currently, all calculations in mmu.h are based on the assumptions that max 33 bits are used in VA and granule size is 64KiB. Changes in these assumptions will have to reflect in the dependent calculations as well. BUG=chrome-os-partner:30688 BRANCH=None TEST=Compiles rush successfully and boots until "payload not found". Goes past all the earlier alignment errors. Original-Change-Id: Iac1df15f0b81dcf64484a56b94f51357bcd67cc2 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208761 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 6fe96360c03342115f849074f9e45a2c4e210705) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5360a3be95f198bd0b4f79b62f31228cc7a9c285 Reviewed-on: http://review.coreboot.org/8646 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8646 for details. -gerrit

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2015