coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: aa228d0 Tegra132: Configure CPU clock
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit aa228d08e9b67bd36dd9952e9e0eadc8dbe3a8d9 Author: Jimmy Zhang <jimmzhang(a)nvidia.com> Date: Wed Jul 23 17:42:45 2014 -0700 Tegra132: Configure CPU clock Since CCLK_BURST_POLICY and SUPER_CCLK_DIVIDER are not accesible from AVP, the first place that can change CPU clock is after CPU has been brought up, ie, ramstage in this case. CPU initial clock source is set to PLLP by MTS. BUG=None TEST=Norrin64 and A44 Original-Change-Id: I525bb2fa2be0afba52837bc0178950541535fd22 Original-Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209698 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit ba77e26508bb4a50a08d07ad15632ff1ba501bfa) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Icf2458c491b4b3a553d3e01f88c6f25b25639e89 Reviewed-on: http://review.coreboot.org/8677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8677 for details. -gerrit

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Patch merged into coreboot/master: 6ad6e3d t132: Add monotonic_timer.c to rmodules_arm
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit 6ad6e3d84ab65357ce0cc64ad6ecff1cbd3fcd2c Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 23 14:32:05 2014 -0700 t132: Add monotonic_timer.c to rmodules_arm Update VBOOT_STUB_DEPS to include monotonic_timer.c BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I3cc559fa21c444da1a7976e4952ea4941c2a1428 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209972 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 8096ae56c4df4013cfc798944b98dd1078c8b451) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I68c13617b96fd872d1eaa9278de6647eccb795c3 Reviewed-on: http://review.coreboot.org/8674 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8674 for details. -gerrit

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Patch merged into coreboot/master: a742ef1 rmodules: Make rmodules inclusion for vboot dependent on romstage_arch
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit a742ef1a48cbeb077555318de1f9b3b0722e558b Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 23 11:41:59 2014 -0700 rmodules: Make rmodules inclusion for vboot dependent on romstage_arch Currently, the rmodules inclusion for vboot is dependent on ramstage_arch. This change adds dependency on romstage_arch, since vboot is associated with romstage. Inclusion based on ramstage_arch is left as is in case someone needs it in ramstage. BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for link, rush and nyan Original-Change-Id: Ib62415671c26a4a18c7133d98e8c683414def32b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209568 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 00da67cc02c81d7a6160f7336b33bf53b00e1875) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9df02134af4e396c7257a2db2e2c371cfd1a02bc Reviewed-on: http://review.coreboot.org/8673 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8673 for details. -gerrit

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Patch merged into coreboot/master: fbff908 coreboot classes: Add dynamic classes to coreboot
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit fbff908a7404a38d937d773e24824a52c4df389c Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 22 15:59:16 2014 -0700 coreboot classes: Add dynamic classes to coreboot Provide functionality to create dynamic classes based on program name and the architecture for which the program needs to be compiled/linked. define_class takes program_name and arch as its arguments and adds the program_name to classes-y to create dynamic class and compiler toolset is created for the specified arch. All the files for this program can then be added to program_name-y += .. Ensure that define_class is called before any files are added to the class. Check subdirs-y for order of directory inclusion. One such example of dynamic class is rmodules. Multiple rmodules can be used which need to be compiled for different architectures. With dynamic classes, this is possible. BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for nyan, rush and link. Original-Change-Id: I3e3aadbe723d432b9b3500c44bcff578c98f5643 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209379 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 242bb90d7476c2ee47d60c50ee18785edeb1a295) Some of this cherry-pick had already been committed here: commit 133096b6dc31163f59f658e15f2eb342a0de2ac6 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9f5868d704c4b3251ca6f54afa634588108a788c Reviewed-on: http://review.coreboot.org/8672 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8672 for details. -gerrit

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Patch merged into coreboot/master: 74aa777 soc/ipq806x: Replace GPT with fine grained DGT timer.
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit 74aa7770f6ec4184faff83fce3d2e843e65cf347 Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Mon Jul 14 16:26:11 2014 -0700 soc/ipq806x: Replace GPT with fine grained DGT timer. Support 1MHz libpayload restriction on timer implementation by using DGT (debug) timer instead of GPT (general purpose) timer. BUG=chrome-os-partner:28880 TEST=manual verified DGT timer functions in coreboot and depthcharge. Original-Change-Id: Iab322d7e863e3959c027e9ce876223a64eb7e257 Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201574 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit ddf11eee5ec2d86a62095e932dbec9313b8fb9e1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id73e805801fd8d135b607df9f4f8caf567ec5b83 Reviewed-on: http://review.coreboot.org/8596 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8596 for details. -gerrit

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Patch set updated for coreboot: 55c9291 bootstate: use structure pointers for scheduling callbacks
by Aaron Durbin 17 Mar '15

17 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8699 -gerrit commit 55c929198ac2867b32da116ffdee994bdeaf30f4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 16 17:30:09 2015 -0500 bootstate: use structure pointers for scheduling callbacks The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/ramstage.ld | 1 + src/arch/arm64/ramstage.ld | 2 ++ src/arch/riscv/ramstage.ld | 1 + src/arch/x86/ramstage.ld | 1 + src/cpu/amd/agesa/amd_late_init.c | 6 ++---- src/cpu/amd/pi/amd_late_init.c | 6 ++---- src/drivers/intel/fsp/fsp_util.c | 6 ++---- src/include/bootstate.h | 26 +++++++++++++++++--------- src/lib/dynamic_cbmem.c | 12 +++--------- src/lib/gcov-glue.c | 8 +++----- src/lib/hardwaremain.c | 10 ++++------ src/lib/rmodule.ld | 2 ++ src/mainboard/google/rambi/mainboard.c | 4 +--- src/northbridge/intel/haswell/mrccache.c | 5 +---- src/northbridge/intel/sandybridge/mrccache.c | 5 +---- src/soc/intel/baytrail/dptf.c | 4 +--- src/soc/intel/baytrail/perf_power.c | 6 ++---- src/soc/intel/baytrail/southcluster.c | 8 ++------ src/soc/intel/baytrail/spi.c | 4 +--- src/soc/intel/broadwell/elog.c | 4 +--- src/soc/intel/broadwell/finalize.c | 8 ++------ src/soc/intel/broadwell/spi.c | 4 +--- src/soc/intel/common/mrc_cache.c | 5 +---- src/southbridge/amd/agesa/hudson/pci.c | 5 +---- src/southbridge/amd/cimx/sb800/late.c | 5 +---- src/southbridge/amd/pi/hudson/pci.c | 5 +---- src/southbridge/intel/common/spi.c | 4 +--- src/southbridge/intel/lynxpoint/smi.c | 5 +---- 28 files changed, 59 insertions(+), 103 deletions(-) diff --git a/src/arch/arm/ramstage.ld b/src/arch/arm/ramstage.ld index 5469509..5e0607d 100644 --- a/src/arch/arm/ramstage.ld +++ b/src/arch/arm/ramstage.ld @@ -64,6 +64,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index de13fcc..784e62d 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -69,6 +69,8 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/riscv/ramstage.ld b/src/arch/riscv/ramstage.ld index 5d9ba3e..2e97a7e 100644 --- a/src/arch/riscv/ramstage.ld +++ b/src/arch/riscv/ramstage.ld @@ -69,6 +69,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 0843be7..9c43bd7 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -62,6 +62,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); _bs_init_end = .; *(.rodata) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 53c2759..b41fa5c 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -42,7 +42,5 @@ static void agesawrapper_post_device(void *unused) agesawrapper_amdS3Save(); } -BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + agesawrapper_post_device, NULL); diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c index 4b08d1b..7ef4c63 100644 --- a/src/cpu/amd/pi/amd_late_init.c +++ b/src/cpu/amd/pi/amd_late_init.c @@ -40,7 +40,5 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdS3Save); } -BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + agesawrapper_post_device, NULL); diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 2a53c25..a00cb81 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -318,8 +318,6 @@ static void find_fsp_hob_update_mrc(void *unused) } /* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRIES(fsp_hob_find) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - find_fsp_hob_update_mrc, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + find_fsp_hob_update_mrc, NULL); #endif /* #ifndef __PRE_RAM__ */ diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 202acf7..8b5e4be 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -22,6 +22,9 @@ #if !defined(__SMM__) && !defined(__PRE_RAM__) #include <string.h> +#include <stdlib.h> +#include <stddef.h> +#include <stdint.h> /* Control debugging of the boot state machine. */ #define BOOT_STATE_DEBUG 0 @@ -157,6 +160,10 @@ int boot_state_sched_on_entry(struct boot_state_callback *bscb, boot_state_t state); int boot_state_sched_on_exit(struct boot_state_callback *bscb, boot_state_t state); +/* Schedule an array of entries of size num. */ +struct boot_state_init_entry; +void boot_state_sched_entries(struct boot_state_init_entry *entries, + size_t num); /* Block/Unblock the (state, seq) pair from transitioning. Returns 0 on * success < 0 when the phase of the (state,seq) has already ran. */ @@ -180,15 +187,16 @@ struct boot_state_init_entry { #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init"))) -#define BOOT_STATE_INIT_ENTRIES(name_) \ - static struct boot_state_init_entry name_[] BOOT_STATE_INIT_ATTR - -#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ - { \ - .state = state_, \ - .when = when_, \ - .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ - } +#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ + static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \ + { \ + .state = state_, \ + .when = when_, \ + .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ + }; \ + static struct boot_state_init_entry * \ + bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \ + & func_ ##_## state_ ##_## when_; #endif #endif /* BOOTSTATE_H */ diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index daa3717..3b008c7 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -435,11 +435,7 @@ static void init_cbmem_pre_device(void *unused) cbmem_initialize(); } -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, - init_cbmem_pre_device, NULL), -}; - +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, init_cbmem_pre_device, NULL); #else static void init_cbmem_post_device(void *unused) @@ -450,10 +446,8 @@ static void init_cbmem_post_device(void *unused) cbmem_initialize_empty(); } -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, - init_cbmem_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, + init_cbmem_post_device, NULL); #endif void cbmem_add_bootmem(void) diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index ab9062b..615624f 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -150,8 +150,6 @@ static void coverage_exit(void *unused) __gcov_flush(); } -BOOT_STATE_INIT_ENTRIES(gcov_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, coverage_init, NULL), - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, coverage_exit, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, coverage_exit, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, coverage_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, coverage_exit, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, coverage_exit, NULL); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 32162eb..d16aa09 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -432,18 +432,16 @@ int boot_state_sched_on_exit(struct boot_state_callback *bscb, static void boot_state_schedule_static_entries(void) { - extern struct boot_state_init_entry _bs_init_begin; - extern struct boot_state_init_entry _bs_init_end; - struct boot_state_init_entry *cur; + extern struct boot_state_init_entry *_bs_init_begin[]; + struct boot_state_init_entry **slot; - cur = &_bs_init_begin; + for (slot = &_bs_init_begin[0]; *slot != NULL; slot++) { + struct boot_state_init_entry *cur = *slot; - while (cur != &_bs_init_end) { if (cur->when == BS_ON_ENTRY) boot_state_sched_on_entry(&cur->bscb, cur->state); else boot_state_sched_on_exit(&cur->bscb, cur->state); - cur++; } } diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index c1669be..065b5b6 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -49,6 +49,8 @@ SECTIONS . = ALIGN(8); _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); + LONG(0); _bs_init_end = .; . = ALIGN(8); diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 1290a15..7128448 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -182,6 +182,4 @@ static void edp_vdden_cb(void *unused) ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2); } -BOOT_STATE_INIT_ENTRIES(edp_vdden_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 540bbf6..b66e9fd 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -222,10 +222,7 @@ static void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..127ca3d 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -223,10 +223,7 @@ static void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index 044a807..e875319 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -49,6 +49,4 @@ static void dptf_init(void *unused) reg_script_run(dptf_init_settings); } -BOOT_STATE_INIT_ENTRIES(dptf_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL); diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 2cde77f..dade339 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -288,7 +288,5 @@ static void perf_power(void *unused) reg_script_run(perf_power_settings); } -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index c392447..a635b0d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -568,9 +568,5 @@ static void finalize_chipset(void *unused) outb(APM_CNT_FINALIZE, APM_CNT); } -BOOT_STATE_INIT_ENTRIES(finalize_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - finalize_chipset, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - finalize_chipset, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index a83fb8e..cf40140 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -323,9 +323,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); #endif int spi_claim_bus(struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index a6a2813..79484a9 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -133,6 +133,4 @@ static void pch_log_state(void *unused) pch_log_wake_source(ps); } -BOOT_STATE_INIT_ENTRIES(pch_log) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL) -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL); diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 67cba66..4f7a518 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -119,9 +119,5 @@ static void broadwell_finalize(void *unused) post_code(POST_OS_BOOT); } -BOOT_STATE_INIT_ENTRIES(finalize) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - broadwell_finalize, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - broadwell_finalize, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 4710271..0069d10 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -315,9 +315,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 8f0d18f..5860201 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -303,9 +303,6 @@ static void update_mrc_cache(void *unused) } } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif /* defined(__PRE_RAM__) */ diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 49e2ba6..5858cd2 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -45,10 +45,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 2125027..f4a7aa3 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -326,10 +326,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); /** * @brief SB Cimx entry point sbBeforePciInit wrapper diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index e8836e4..70e2c18 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -48,10 +48,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 1780fc0..416a30f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -366,9 +366,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); #endif int spi_claim_bus(struct spi_slave *slave) diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 94abf5f..18a55f6 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -135,9 +135,6 @@ static void finalize_boot(void *unused) outb(0xcb, 0xb2); } -BOOT_STATE_INIT_ENTRIES(finalize) = { - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, - finalize_boot, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); #endif

1 0

Patch merged into coreboot/master: f69a99d coreboot: x86: enable gc-sections
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit f69a99dbf843da7f4c2b4965004140d2ea83cd67 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 10 11:45:25 2015 -0500 coreboot: x86: enable gc-sections Garbage collected sections allow for trimming the size of the binaries as well as allowing for not needing to config off unused functions. To that end, on a rambi build the following differences are observed: $ diff -up \ <(readelf -l coreboot-builds/google_rambi/cbfs/fallback/ramstage.elf) \ <(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/ramstage.elf) --- /dev/fd/63 2015-03-10 12:07:27.927985430 -0500 +++ /dev/fd/62 2015-03-10 12:07:27.927985430 -0500 @@ -6,9 +6,9 @@ There are 4 program headers, starting at Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x00000000 0x00000000 0x00040 0x00040 RWE 0 - LOAD 0x001040 0x00000040 0x00000040 0x34560 0x34560 RWE 0 - LOAD 0x0355a0 0x000345a0 0x000345a0 0x02578 0x02578 RWE 0 - LOAD 0x037b18 0x00036b18 0x00036b18 0x00000 0x0b560 0 + LOAD 0x001040 0x00000040 0x00000040 0x2cbf8 0x2cbf8 RWE 0 + LOAD 0x02dc38 0x0002cc38 0x0002cc38 0x02208 0x02208 RWE 0 + LOAD 0x02fe40 0x0002ee40 0x0002ee40 0x00000 0x0a888 0 Section to Segment mapping: Segment Sections... $ diff -up \ <(readelf -l coreboot-builds/google_rambi/cbfs/fallback/romstage.elf) \ <(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/romstage.elf) --- /dev/fd/63 2015-03-10 12:08:16.855985880 -0500 +++ /dev/fd/62 2015-03-10 12:08:16.851985880 -0500 @@ -5,8 +5,8 @@ There are 1 program headers, starting at Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align - LOAD 0x000060 0xfff20000 0xfff20000 0x08b81 0x08b81 R E 0x10 + LOAD 0x000060 0xfff20000 0xfff20000 0x06300 0x06300 R E 0x10 Section to Segment mapping: Segment Sections... - 00 .rom .text + 00 .rom The following warnings needed to be applied to CFLAGS_common because for some reason gcc was miraculously emitting the warnings with the unrelated *-sections options: -Wno-unused-but-set-variable Change-Id: I210784fdfc273ce4cb9927352cbd5a51be3c6929 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/8635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8635 for details. -gerrit

1 0

Patch set updated for coreboot: 9ff1994 bootstate: use structure pointers for scheduling callbacks
by Aaron Durbin 17 Mar '15

17 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8699 -gerrit commit 9ff199422a9eb58fb19d771dff2c7accd6e9cb05 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 16 17:30:09 2015 -0500 bootstate: use structure pointers for scheduling callbacks The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/ramstage.ld | 1 + src/arch/arm64/ramstage.ld | 2 ++ src/arch/riscv/ramstage.ld | 1 + src/arch/x86/ramstage.ld | 1 + src/cpu/amd/agesa/amd_late_init.c | 6 ++---- src/cpu/amd/pi/amd_late_init.c | 6 ++---- src/drivers/intel/fsp/fsp_util.c | 6 ++---- src/include/bootstate.h | 26 +++++++++++++++++--------- src/lib/dynamic_cbmem.c | 12 +++--------- src/lib/gcov-glue.c | 8 +++----- src/lib/hardwaremain.c | 10 ++++------ src/lib/rmodule.ld | 2 ++ src/mainboard/google/rambi/mainboard.c | 4 +--- src/northbridge/intel/haswell/mrccache.c | 5 +---- src/northbridge/intel/sandybridge/mrccache.c | 5 +---- src/soc/intel/baytrail/dptf.c | 4 +--- src/soc/intel/baytrail/perf_power.c | 6 ++---- src/soc/intel/baytrail/southcluster.c | 8 ++------ src/soc/intel/baytrail/spi.c | 4 +--- src/soc/intel/broadwell/elog.c | 4 +--- src/soc/intel/broadwell/finalize.c | 8 ++------ src/soc/intel/broadwell/spi.c | 4 +--- src/soc/intel/common/mrc_cache.c | 5 +---- src/southbridge/amd/agesa/hudson/pci.c | 5 +---- src/southbridge/amd/cimx/sb800/late.c | 5 +---- src/southbridge/amd/pi/hudson/pci.c | 5 +---- src/southbridge/intel/common/spi.c | 4 +--- src/southbridge/intel/lynxpoint/smi.c | 5 +---- 28 files changed, 59 insertions(+), 103 deletions(-) diff --git a/src/arch/arm/ramstage.ld b/src/arch/arm/ramstage.ld index 5469509..5e0607d 100644 --- a/src/arch/arm/ramstage.ld +++ b/src/arch/arm/ramstage.ld @@ -64,6 +64,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index de13fcc..784e62d 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -69,6 +69,8 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/riscv/ramstage.ld b/src/arch/riscv/ramstage.ld index 5d9ba3e..2e97a7e 100644 --- a/src/arch/riscv/ramstage.ld +++ b/src/arch/riscv/ramstage.ld @@ -69,6 +69,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 1c8e8dc..cf60dda 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -62,6 +62,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 53c2759..b41fa5c 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -42,7 +42,5 @@ static void agesawrapper_post_device(void *unused) agesawrapper_amdS3Save(); } -BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + agesawrapper_post_device, NULL); diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c index 4b08d1b..7ef4c63 100644 --- a/src/cpu/amd/pi/amd_late_init.c +++ b/src/cpu/amd/pi/amd_late_init.c @@ -40,7 +40,5 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdS3Save); } -BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + agesawrapper_post_device, NULL); diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 2a53c25..a00cb81 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -318,8 +318,6 @@ static void find_fsp_hob_update_mrc(void *unused) } /* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRIES(fsp_hob_find) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - find_fsp_hob_update_mrc, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + find_fsp_hob_update_mrc, NULL); #endif /* #ifndef __PRE_RAM__ */ diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 202acf7..8b5e4be 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -22,6 +22,9 @@ #if !defined(__SMM__) && !defined(__PRE_RAM__) #include <string.h> +#include <stdlib.h> +#include <stddef.h> +#include <stdint.h> /* Control debugging of the boot state machine. */ #define BOOT_STATE_DEBUG 0 @@ -157,6 +160,10 @@ int boot_state_sched_on_entry(struct boot_state_callback *bscb, boot_state_t state); int boot_state_sched_on_exit(struct boot_state_callback *bscb, boot_state_t state); +/* Schedule an array of entries of size num. */ +struct boot_state_init_entry; +void boot_state_sched_entries(struct boot_state_init_entry *entries, + size_t num); /* Block/Unblock the (state, seq) pair from transitioning. Returns 0 on * success < 0 when the phase of the (state,seq) has already ran. */ @@ -180,15 +187,16 @@ struct boot_state_init_entry { #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init"))) -#define BOOT_STATE_INIT_ENTRIES(name_) \ - static struct boot_state_init_entry name_[] BOOT_STATE_INIT_ATTR - -#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ - { \ - .state = state_, \ - .when = when_, \ - .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ - } +#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ + static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \ + { \ + .state = state_, \ + .when = when_, \ + .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ + }; \ + static struct boot_state_init_entry * \ + bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \ + & func_ ##_## state_ ##_## when_; #endif #endif /* BOOTSTATE_H */ diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index daa3717..3b008c7 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -435,11 +435,7 @@ static void init_cbmem_pre_device(void *unused) cbmem_initialize(); } -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, - init_cbmem_pre_device, NULL), -}; - +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, init_cbmem_pre_device, NULL); #else static void init_cbmem_post_device(void *unused) @@ -450,10 +446,8 @@ static void init_cbmem_post_device(void *unused) cbmem_initialize_empty(); } -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, - init_cbmem_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, + init_cbmem_post_device, NULL); #endif void cbmem_add_bootmem(void) diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index ab9062b..615624f 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -150,8 +150,6 @@ static void coverage_exit(void *unused) __gcov_flush(); } -BOOT_STATE_INIT_ENTRIES(gcov_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, coverage_init, NULL), - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, coverage_exit, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, coverage_exit, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, coverage_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, coverage_exit, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, coverage_exit, NULL); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 32162eb..d16aa09 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -432,18 +432,16 @@ int boot_state_sched_on_exit(struct boot_state_callback *bscb, static void boot_state_schedule_static_entries(void) { - extern struct boot_state_init_entry _bs_init_begin; - extern struct boot_state_init_entry _bs_init_end; - struct boot_state_init_entry *cur; + extern struct boot_state_init_entry *_bs_init_begin[]; + struct boot_state_init_entry **slot; - cur = &_bs_init_begin; + for (slot = &_bs_init_begin[0]; *slot != NULL; slot++) { + struct boot_state_init_entry *cur = *slot; - while (cur != &_bs_init_end) { if (cur->when == BS_ON_ENTRY) boot_state_sched_on_entry(&cur->bscb, cur->state); else boot_state_sched_on_exit(&cur->bscb, cur->state); - cur++; } } diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f3e7cba..0124c44 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -47,6 +47,8 @@ SECTIONS . = ALIGN(8); _bs_init_begin = .; *(.bs_init) + LONG(0); + LONG(0); _bs_init_end = .; . = ALIGN(8); diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 1290a15..7128448 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -182,6 +182,4 @@ static void edp_vdden_cb(void *unused) ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2); } -BOOT_STATE_INIT_ENTRIES(edp_vdden_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 540bbf6..b66e9fd 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -222,10 +222,7 @@ static void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..127ca3d 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -223,10 +223,7 @@ static void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index 044a807..e875319 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -49,6 +49,4 @@ static void dptf_init(void *unused) reg_script_run(dptf_init_settings); } -BOOT_STATE_INIT_ENTRIES(dptf_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL); diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 2cde77f..dade339 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -288,7 +288,5 @@ static void perf_power(void *unused) reg_script_run(perf_power_settings); } -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index d0569b4..84052d8 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -569,9 +569,5 @@ static void finalize_chipset(void *unused) outb(APM_CNT_FINALIZE, APM_CNT); } -BOOT_STATE_INIT_ENTRIES(finalize_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - finalize_chipset, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - finalize_chipset, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index a83fb8e..cf40140 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -323,9 +323,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); #endif int spi_claim_bus(struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index a6a2813..79484a9 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -133,6 +133,4 @@ static void pch_log_state(void *unused) pch_log_wake_source(ps); } -BOOT_STATE_INIT_ENTRIES(pch_log) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL) -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL); diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 67cba66..4f7a518 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -119,9 +119,5 @@ static void broadwell_finalize(void *unused) post_code(POST_OS_BOOT); } -BOOT_STATE_INIT_ENTRIES(finalize) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - broadwell_finalize, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - broadwell_finalize, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 4710271..0069d10 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -315,9 +315,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 8f0d18f..5860201 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -303,9 +303,6 @@ static void update_mrc_cache(void *unused) } } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif /* defined(__PRE_RAM__) */ diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 49e2ba6..5858cd2 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -45,10 +45,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 2125027..f4a7aa3 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -326,10 +326,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); /** * @brief SB Cimx entry point sbBeforePciInit wrapper diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index e8836e4..70e2c18 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -48,10 +48,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index d6ab01a..0aee3a0 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -365,9 +365,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 94abf5f..18a55f6 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -135,9 +135,6 @@ static void finalize_boot(void *unused) outb(0xcb, 0xb2); } -BOOT_STATE_INIT_ENTRIES(finalize) = { - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, - finalize_boot, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); #endif

1 0

Patch merged into coreboot/master: 5179419 rockchip/rk3288: Fix whitespace
by gerrit＠coreboot.org 16 Mar '15

16 Mar '15

the following patch was just integrated into master: commit 51794199899521dc3c363fedc8437d8f25b8b7df Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Mar 17 07:11:26 2015 +0200 rockchip/rk3288: Fix whitespace Change-Id: I6c3c1e871de33b4d0e968b254bbcf125cee9fddb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8704 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8704 for details. -gerrit

1 0

Patch set updated for coreboot: 24efe55 PCI subsystem: Drop PCI_64BIT_PREF_MEM option
by Kyösti Mälkki 16 Mar '15

16 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8705 -gerrit commit 24efe5584b41a143d6d37a9df2118edaa346bfbd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Mar 17 06:42:54 2015 +0200 PCI subsystem: Drop PCI_64BIT_PREF_MEM option No board in the tree selects this. It also looks like the implementation was done at chipset level while it should be part of PCI subsystem and resource management. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 5 -- src/device/device.c | 2 +- src/mainboard/asus/kfsn4-dre/Kconfig | 4 -- src/mainboard/asus/m2n-e/Kconfig | 4 -- src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 4 -- src/mainboard/gigabyte/m57sli/Kconfig | 4 -- src/mainboard/msi/ms7260/Kconfig | 4 -- src/mainboard/msi/ms9282/Kconfig | 4 -- src/mainboard/nvidia/l1_2pvv/Kconfig | 4 -- src/mainboard/tyan/s2912/Kconfig | 4 -- src/mainboard/tyan/s2912_fam10/Kconfig | 4 -- src/northbridge/amd/agesa/family10/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family12/northbridge.c | 81 +-------------------- src/northbridge/amd/agesa/family14/northbridge.c | 82 ---------------------- src/northbridge/amd/agesa/family15/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family15rl/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family15tn/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family16kb/northbridge.c | 77 -------------------- src/northbridge/amd/amdfam10/northbridge.c | 76 -------------------- src/northbridge/amd/amdk8/northbridge.c | 68 ------------------ src/northbridge/amd/pi/00630F01/northbridge.c | 77 +------------------- src/northbridge/amd/pi/00730F01/northbridge.c | 78 -------------------- 22 files changed, 3 insertions(+), 887 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 7f43888..ddfcdce 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -205,11 +205,6 @@ config PCI bool default n -config PCI_64BIT_PREF_MEM - bool - depends on PCI - default n - config HYPERTRANSPORT_PLUGIN_SUPPORT bool depends on PCI diff --git a/src/device/device.c b/src/device/device.c index 00e323a..34edcb7 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -610,7 +610,7 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, } } -#if CONFIG_PCI_64BIT_PREF_MEM +#if 0 /* was: CONFIG_PCI_64BIT_PREF_MEM */ #define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM) #else #define MEM_MASK (IORESOURCE_MEM) diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index a7ac369..5957028 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZEK hex default 0x100000 -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 12 diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index 7292bf3..c86de2d 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -65,10 +65,6 @@ config MAINBOARD_PART_NUMBER string default "M2N-E" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index a79c28f..660ac1c 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -45,10 +45,6 @@ config MAINBOARD_PART_NUMBER string default "GA-2761GXDK" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 6ef94ce..3132d37 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -49,10 +49,6 @@ config MAINBOARD_PART_NUMBER string default "GA-M57SLI-S4" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 0e7e592..60ea9ea 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -47,10 +47,6 @@ config MAINBOARD_PART_NUMBER string default "MS-7260" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index f109375..e88f36f 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -41,10 +41,6 @@ config MAINBOARD_PART_NUMBER string default "MS-9282" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 57911f7..7694492 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -51,10 +51,6 @@ config MAINBOARD_PART_NUMBER string default "l1_2pvv" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 26d9a53..8b59eb5 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -46,10 +46,6 @@ config MAINBOARD_PART_NUMBER string default "S2912" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 1dd74ca..1e0d4d0 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -43,10 +43,6 @@ config MAINBOARD_PART_NUMBER string default "S2912 (Fam10)" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 12 diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 8e47c1a..6b2ff63 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -635,29 +635,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void amdfam10_domain_enable_resources(device_t dev) @@ -737,10 +715,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -751,57 +725,6 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index a3b3493..4cd9156 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -509,9 +509,6 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM -//- pci_domain_read_resources(dev); - struct resource *resource; /* Initialize the system-wide I/O space constraints. */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -526,27 +523,7 @@ static void domain_read_resources(device_t dev) resource->limit = 0xdfffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -#else - struct bus *link; - struct resource *resource; - for(link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -556,10 +533,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -570,58 +543,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - -printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); - for(link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for(res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index ff669ef..852780b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -498,29 +498,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for (link = dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0 | (link->link_num << 2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1 | (link->link_num << 2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2 | (link->link_num << 2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void setup_uma_memory(void) @@ -553,10 +531,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -567,62 +541,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1 | (link->link_num << 2)); - mem2 = find_resource(dev, 2 | (link->link_num << 2)); - - printk(BIOS_DEBUG, - "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - (u32) (mem1->base), (u32) (mem1->limit), - (u32) (mem1->size), u32) (mem1->align)); - printk(BIOS_DEBUG, - "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - (u32) (mem2->base), (u32) (mem2->limit), - (u32) (mem2->size), (u32) (mem2->align)); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) - || ((mem1->limit > 0xffffffff) - && (mem2->limit > 0xffffffff))) { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, - "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, - "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 89e1644..aaa63bb 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -668,30 +668,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -792,10 +769,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -806,56 +779,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index f83ff2d..4e77758 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -663,30 +663,7 @@ static void domain_read_resources(struct device *dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(struct device *dev) @@ -787,10 +764,6 @@ static void setup_uma_memory(void) static void domain_set_resources(struct device *dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -801,56 +774,6 @@ static void domain_set_resources(struct device *dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index d878b4f..9eb502a 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -661,30 +661,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -785,10 +762,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -799,56 +772,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index badec55..5178065 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -677,30 +677,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -803,10 +780,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -817,56 +790,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e2b1441..bf8fc7b 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -632,29 +632,8 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for(link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif #if CONFIG_MMCONF_SUPPORT struct resource *res = new_resource(dev, 0xc0010058); res->base = CONFIG_MMCONF_BASE_ADDRESS; @@ -750,10 +729,6 @@ static void setup_uma_memory(void) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -764,57 +739,6 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for(link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for(res = dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a17aa65..b42b6bf 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -667,13 +667,6 @@ static void amdk8_domain_read_resources(device_t dev) } pci_domain_read_resources(dev); - -#if CONFIG_PCI_64BIT_PREF_MEM - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 2); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; -#endif } static void my_tolm_test(void *gp, struct device *dev, struct resource *new) @@ -904,10 +897,6 @@ static void setup_uma_memory(void) static void amdk8_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -917,63 +906,6 @@ static void amdk8_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if 0 - /* Place the IO devices somewhere safe */ - io = find_resource(dev, 0); - io->base = DEVICE_IO_START; -#endif -#if CONFIG_PCI_64BIT_PREF_MEM - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1); - mem2 = find_resource(dev, 2); - -#if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); -#endif - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - -#if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); -#endif - - for(res = dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = my_find_pci_tolm(dev->link_list); // FIXME handle interleaved nodes. If you fix this here, please fix diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index f8b3246..e5fa0cb 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -654,29 +654,8 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ - if (!IS_ENABLED(CONFIG_PCI_64BIT_PREF_MEM)) pci_domain_read_resources(dev); - else { - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } - } + } static void domain_enable_resources(device_t dev) @@ -780,10 +759,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -794,56 +769,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index b10da3d..d33f021 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -663,31 +663,7 @@ static void domain_read_resources(device_t dev) } /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ - -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -796,10 +772,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -810,56 +782,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link);

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coreboot-gerrit March 2015