coreboot-gerrit March 2015

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New patch to review for coreboot: 11c2d69 loaders: add program_loading.h header file
by Aaron Durbin 17 Mar '15

17 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8708 -gerrit commit 11c2d69b36d58e98af04abfbd089d3300d77302c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 17 11:43:44 2015 -0500 loaders: add program_loading.h header file Instead of two headers for payload and ramstage loading combine the 2 files into one. This also allows for easier refactoring by keeping header files consistent. Change-Id: I4a6dffb78ad84c78e6e96c886d361413f9b4a17d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/boot.c | 2 +- src/arch/arm64/boot.c | 2 +- src/arch/riscv/boot.c | 2 +- src/arch/x86/boot/boot.c | 2 +- src/arch/x86/lib/cbfs_and_run.c | 2 +- src/cpu/x86/mirror_payload.c | 2 +- src/include/payload_loader.h | 66 ------------------- src/include/program_loading.h | 87 ++++++++++++++++++++++++++ src/include/ramstage_loader.h | 34 ---------- src/lib/hardwaremain.c | 2 +- src/lib/loaders/cbfs_payload_loader.c | 2 +- src/lib/loaders/cbfs_ramstage_loader.c | 2 +- src/lib/loaders/load_and_run_payload.c | 2 +- src/lib/loaders/load_and_run_ramstage.c | 2 +- src/lib/selfboot.c | 2 +- src/vendorcode/google/chromeos/vboot_handoff.c | 2 +- src/vendorcode/google/chromeos/vboot_loader.c | 2 +- 17 files changed, 101 insertions(+), 114 deletions(-) diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 85b2cce..5217a9f 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -21,7 +21,7 @@ #include <arch/stages.h> #include <cbmem.h> #include <console/console.h> -#include <payload_loader.h> +#include <program_loading.h> void arch_payload_run(const struct payload *payload) { diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 85b2cce..5217a9f 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -21,7 +21,7 @@ #include <arch/stages.h> #include <cbmem.h> #include <console/console.h> -#include <payload_loader.h> +#include <program_loading.h> void arch_payload_run(const struct payload *payload) { diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index ecaf86f..ff65cc3 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -19,7 +19,7 @@ #include <console/console.h> #include <arch/stages.h> -#include <payload_loader.h> +#include <program_loading.h> #include <console/uart.h> void arch_payload_run(const struct payload *payload) diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 29070a0..8f7f0e0 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -1,6 +1,6 @@ #include <console/console.h> #include <arch/stages.h> -#include <payload_loader.h> +#include <program_loading.h> #include <ip_checksum.h> #include <string.h> diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index ca8d61b..d279b72 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -18,7 +18,7 @@ */ #include <arch/stages.h> -#include <ramstage_loader.h> +#include <program_loading.h> void asmlinkage copy_and_run(void) { diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c index edd2641..0ba8d05 100644 --- a/src/cpu/x86/mirror_payload.c +++ b/src/cpu/x86/mirror_payload.c @@ -22,7 +22,7 @@ #include <string.h> #include <console/console.h> #include <bootmem.h> -#include <payload_loader.h> +#include <program_loading.h> void mirror_payload(struct payload *payload) { diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h deleted file mode 100644 index 7a3f045..0000000 --- a/src/include/payload_loader.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef PAYLOAD_LOADER_H -#define PAYLOAD_LOADER_H - -#include <stdint.h> -#include <stddef.h> - -struct buffer_area { - void *data; - size_t size; -}; - -struct payload { - const char *name; - struct buffer_area backing_store; - /* Used when payload wants memory coreboot ramstage is running at. */ - struct buffer_area bounce; - void *entry; -}; - -/* - * Load payload into memory and return pointer to payload structure. Returns - * NULL on error. - */ -struct payload *payload_load(void); - -/* Run the loaded payload. */ -void payload_run(const struct payload *payload); - -/* Mirror the payload to be loaded. */ -void mirror_payload(struct payload *payload); - -/* architecture specific function to run payload. */ -void arch_payload_run(const struct payload *payload); - -/* Payload loading operations. */ -struct payload_loader_ops { - const char *name; - /* - * Fill in payload_backing_store structure. Return 0 on success, < 0 - * on failure. - */ - int (*locate)(struct payload *payload); -}; - -/* Defined in src/lib/selfboot.c */ -void *selfload(struct payload *payload); - -#endif /* PAYLOAD_LOADER_H */ diff --git a/src/include/program_loading.h b/src/include/program_loading.h new file mode 100644 index 0000000..8ceebc1 --- /dev/null +++ b/src/include/program_loading.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef PROGRAM_LOADING_H +#define PROGRAM_LOADING_H + +#include <stdint.h> +#include <stddef.h> + + +/************************ + * RAMSTAGE LOADING * + ************************/ + +struct cbmem_entry; + +/* Run ramstage from romstage. */ +void run_ramstage(void); + +struct ramstage_loader_ops { + const char *name; + void *(*load)(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry); +}; + +/*********************** + * PAYLOAD LOADING * + ***********************/ + +struct buffer_area { + void *data; + size_t size; +}; + +struct payload { + const char *name; + struct buffer_area backing_store; + /* Used when payload wants memory coreboot ramstage is running at. */ + struct buffer_area bounce; + void *entry; +}; + +/* + * Load payload into memory and return pointer to payload structure. Returns + * NULL on error. + */ +struct payload *payload_load(void); + +/* Run the loaded payload. */ +void payload_run(const struct payload *payload); + +/* Mirror the payload to be loaded. */ +void mirror_payload(struct payload *payload); + +/* architecture specific function to run payload. */ +void arch_payload_run(const struct payload *payload); + +/* Payload loading operations. */ +struct payload_loader_ops { + const char *name; + /* + * Fill in payload_backing_store structure. Return 0 on success, < 0 + * on failure. + */ + int (*locate)(struct payload *payload); +}; + +/* Defined in src/lib/selfboot.c */ +void *selfload(struct payload *payload); + + +#endif /* PROGRAM_LOADING_H */ diff --git a/src/include/ramstage_loader.h b/src/include/ramstage_loader.h deleted file mode 100644 index ad085c0..0000000 --- a/src/include/ramstage_loader.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef RAMSTAGE_LOADER_H -#define RAMSTAGE_LOADER_H - -#include <stdint.h> -struct cbmem_entry; - -/* Run ramstage from romstage. */ -void run_ramstage(void); - -struct ramstage_loader_ops { - const char *name; - void *(*load)(uint32_t cbmem_id, const char *name, - const struct cbmem_entry **cbmem_entry); -}; - -#endif /* RAMSTAGE_LOADER_H */ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index d16aa09..9917a69 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -33,7 +33,7 @@ #include <stdlib.h> #include <reset.h> #include <boot/tables.h> -#include <payload_loader.h> +#include <program_loading.h> #include <lib.h> #if CONFIG_HAVE_ACPI_RESUME #include <arch/acpi.h> diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c index 2c1d179..22f4c2f 100644 --- a/src/lib/loaders/cbfs_payload_loader.c +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -18,7 +18,7 @@ */ #include <cbfs.h> -#include <payload_loader.h> +#include <program_loading.h> static int cbfs_locate_payload(struct payload *payload) { diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c index 5d5cc0b..5155aea 100644 --- a/src/lib/loaders/cbfs_ramstage_loader.c +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <cbfs.h> #include <arch/stages.h> -#include <ramstage_loader.h> +#include <program_loading.h> #include <timestamp.h> #if CONFIG_RELOCATABLE_RAMSTAGE diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 2204090..4bb29c1 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <fallback.h> #include <lib.h> -#include <payload_loader.h> +#include <program_loading.h> #include <timestamp.h> extern const struct payload_loader_ops vboot_payload_loader; diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c index 5237e20..b24e29f 100644 --- a/src/lib/loaders/load_and_run_ramstage.c +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -22,7 +22,7 @@ #include <arch/stages.h> #include <cbfs.h> #include <cbmem.h> -#include <ramstage_loader.h> +#include <program_loading.h> #include <romstage_handoff.h> #include <timestamp.h> diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index de059b0..4c5fbad 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -27,7 +27,7 @@ #include <cbfs.h> #include <lib.h> #include <bootmem.h> -#include <payload_loader.h> +#include <program_loading.h> /* from ramstage.ld: */ extern unsigned char _ram_seg; diff --git a/src/vendorcode/google/chromeos/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot_handoff.c index 7ea21ea..4fb3338 100644 --- a/src/vendorcode/google/chromeos/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot_handoff.c @@ -24,7 +24,7 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <payload_loader.h> +#include <program_loading.h> #include "vboot_handoff.h" int vboot_enable_developer(void) diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index daf5260..0294ac6 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -25,9 +25,9 @@ #include <cbmem.h> #include <console/console.h> #include <console/vtxprintf.h> +#include <program_loading.h> #include <tpm.h> #include <reset.h> -#include <ramstage_loader.h> #include <romstage_handoff.h> #include <rmodule.h> #include <string.h>

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Patch set updated for coreboot: 41b6479 bootstate: use structure pointers for scheduling callbacks
by Aaron Durbin 17 Mar '15

17 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8699 -gerrit commit 41b64795091ba1237f41a6c33f4733f2463f3551 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 16 17:30:09 2015 -0500 bootstate: use structure pointers for scheduling callbacks The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/ramstage.ld | 1 + src/arch/arm64/ramstage.ld | 2 ++ src/arch/riscv/ramstage.ld | 1 + src/arch/x86/ramstage.ld | 1 + src/cpu/amd/agesa/amd_late_init.c | 6 ++---- src/cpu/amd/pi/amd_late_init.c | 6 ++---- src/drivers/intel/fsp/fsp_util.c | 6 ++---- src/include/bootstate.h | 26 +++++++++++++++++--------- src/lib/dynamic_cbmem.c | 12 +++--------- src/lib/gcov-glue.c | 8 +++----- src/lib/hardwaremain.c | 10 ++++------ src/lib/rmodule.ld | 2 ++ src/mainboard/google/rambi/mainboard.c | 4 +--- src/northbridge/intel/haswell/mrccache.c | 5 +---- src/northbridge/intel/sandybridge/mrccache.c | 5 +---- src/soc/intel/baytrail/dptf.c | 4 +--- src/soc/intel/baytrail/perf_power.c | 6 ++---- src/soc/intel/baytrail/southcluster.c | 8 ++------ src/soc/intel/baytrail/spi.c | 4 +--- src/soc/intel/broadwell/elog.c | 4 +--- src/soc/intel/broadwell/finalize.c | 8 ++------ src/soc/intel/broadwell/spi.c | 4 +--- src/soc/intel/common/mrc_cache.c | 5 +---- src/southbridge/amd/agesa/hudson/pci.c | 5 +---- src/southbridge/amd/cimx/sb800/late.c | 5 +---- src/southbridge/amd/pi/hudson/pci.c | 5 +---- src/southbridge/intel/common/spi.c | 4 +--- src/southbridge/intel/lynxpoint/smi.c | 5 +---- 28 files changed, 59 insertions(+), 103 deletions(-) diff --git a/src/arch/arm/ramstage.ld b/src/arch/arm/ramstage.ld index 5469509..5e0607d 100644 --- a/src/arch/arm/ramstage.ld +++ b/src/arch/arm/ramstage.ld @@ -64,6 +64,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index de13fcc..784e62d 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -69,6 +69,8 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/riscv/ramstage.ld b/src/arch/riscv/ramstage.ld index 5d9ba3e..2e97a7e 100644 --- a/src/arch/riscv/ramstage.ld +++ b/src/arch/riscv/ramstage.ld @@ -69,6 +69,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 0843be7..9c43bd7 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -62,6 +62,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); _bs_init_end = .; *(.rodata) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 53c2759..b41fa5c 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -42,7 +42,5 @@ static void agesawrapper_post_device(void *unused) agesawrapper_amdS3Save(); } -BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + agesawrapper_post_device, NULL); diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c index 4b08d1b..7ef4c63 100644 --- a/src/cpu/amd/pi/amd_late_init.c +++ b/src/cpu/amd/pi/amd_late_init.c @@ -40,7 +40,5 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdS3Save); } -BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + agesawrapper_post_device, NULL); diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 2a53c25..a00cb81 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -318,8 +318,6 @@ static void find_fsp_hob_update_mrc(void *unused) } /* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRIES(fsp_hob_find) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - find_fsp_hob_update_mrc, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + find_fsp_hob_update_mrc, NULL); #endif /* #ifndef __PRE_RAM__ */ diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 202acf7..8b5e4be 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -22,6 +22,9 @@ #if !defined(__SMM__) && !defined(__PRE_RAM__) #include <string.h> +#include <stdlib.h> +#include <stddef.h> +#include <stdint.h> /* Control debugging of the boot state machine. */ #define BOOT_STATE_DEBUG 0 @@ -157,6 +160,10 @@ int boot_state_sched_on_entry(struct boot_state_callback *bscb, boot_state_t state); int boot_state_sched_on_exit(struct boot_state_callback *bscb, boot_state_t state); +/* Schedule an array of entries of size num. */ +struct boot_state_init_entry; +void boot_state_sched_entries(struct boot_state_init_entry *entries, + size_t num); /* Block/Unblock the (state, seq) pair from transitioning. Returns 0 on * success < 0 when the phase of the (state,seq) has already ran. */ @@ -180,15 +187,16 @@ struct boot_state_init_entry { #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init"))) -#define BOOT_STATE_INIT_ENTRIES(name_) \ - static struct boot_state_init_entry name_[] BOOT_STATE_INIT_ATTR - -#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ - { \ - .state = state_, \ - .when = when_, \ - .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ - } +#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ + static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \ + { \ + .state = state_, \ + .when = when_, \ + .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ + }; \ + static struct boot_state_init_entry * \ + bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \ + & func_ ##_## state_ ##_## when_; #endif #endif /* BOOTSTATE_H */ diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index daa3717..3b008c7 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -435,11 +435,7 @@ static void init_cbmem_pre_device(void *unused) cbmem_initialize(); } -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, - init_cbmem_pre_device, NULL), -}; - +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, init_cbmem_pre_device, NULL); #else static void init_cbmem_post_device(void *unused) @@ -450,10 +446,8 @@ static void init_cbmem_post_device(void *unused) cbmem_initialize_empty(); } -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, - init_cbmem_post_device, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, + init_cbmem_post_device, NULL); #endif void cbmem_add_bootmem(void) diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index ab9062b..615624f 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -150,8 +150,6 @@ static void coverage_exit(void *unused) __gcov_flush(); } -BOOT_STATE_INIT_ENTRIES(gcov_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, coverage_init, NULL), - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, coverage_exit, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, coverage_exit, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, coverage_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, coverage_exit, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, coverage_exit, NULL); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 32162eb..d16aa09 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -432,18 +432,16 @@ int boot_state_sched_on_exit(struct boot_state_callback *bscb, static void boot_state_schedule_static_entries(void) { - extern struct boot_state_init_entry _bs_init_begin; - extern struct boot_state_init_entry _bs_init_end; - struct boot_state_init_entry *cur; + extern struct boot_state_init_entry *_bs_init_begin[]; + struct boot_state_init_entry **slot; - cur = &_bs_init_begin; + for (slot = &_bs_init_begin[0]; *slot != NULL; slot++) { + struct boot_state_init_entry *cur = *slot; - while (cur != &_bs_init_end) { if (cur->when == BS_ON_ENTRY) boot_state_sched_on_entry(&cur->bscb, cur->state); else boot_state_sched_on_exit(&cur->bscb, cur->state); - cur++; } } diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index c1669be..065b5b6 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -49,6 +49,8 @@ SECTIONS . = ALIGN(8); _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); + LONG(0); _bs_init_end = .; . = ALIGN(8); diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 1290a15..7128448 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -182,6 +182,4 @@ static void edp_vdden_cb(void *unused) ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2); } -BOOT_STATE_INIT_ENTRIES(edp_vdden_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 540bbf6..b66e9fd 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -222,10 +222,7 @@ static void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..127ca3d 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -223,10 +223,7 @@ static void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index 044a807..e875319 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -49,6 +49,4 @@ static void dptf_init(void *unused) reg_script_run(dptf_init_settings); } -BOOT_STATE_INIT_ENTRIES(dptf_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL); diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 2cde77f..dade339 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -288,7 +288,5 @@ static void perf_power(void *unused) reg_script_run(perf_power_settings); } -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index c392447..a635b0d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -568,9 +568,5 @@ static void finalize_chipset(void *unused) outb(APM_CNT_FINALIZE, APM_CNT); } -BOOT_STATE_INIT_ENTRIES(finalize_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - finalize_chipset, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - finalize_chipset, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index a83fb8e..cf40140 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -323,9 +323,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); #endif int spi_claim_bus(struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index a6a2813..79484a9 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -133,6 +133,4 @@ static void pch_log_state(void *unused) pch_log_wake_source(ps); } -BOOT_STATE_INIT_ENTRIES(pch_log) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL) -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL); diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 67cba66..4f7a518 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -119,9 +119,5 @@ static void broadwell_finalize(void *unused) post_code(POST_OS_BOOT); } -BOOT_STATE_INIT_ENTRIES(finalize) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - broadwell_finalize, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - broadwell_finalize, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 4710271..0069d10 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -315,9 +315,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 8f0d18f..5860201 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -303,9 +303,6 @@ static void update_mrc_cache(void *unused) } } -BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { - BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); #endif /* defined(__PRE_RAM__) */ diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 49e2ba6..5858cd2 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -45,10 +45,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 2125027..f4a7aa3 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -326,10 +326,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); /** * @brief SB Cimx entry point sbBeforePciInit wrapper diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index e8836e4..70e2c18 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -48,10 +48,7 @@ static void set_pci_irqs(void *unused) * Hook this function into the PCI state machine * on entry into BS_DEV_ENABLE. */ -BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, - set_pci_irqs, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 1780fc0..416a30f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -366,9 +366,7 @@ static void spi_init_cb(void *unused) spi_init(); } -BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); #endif int spi_claim_bus(struct spi_slave *slave) diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 94abf5f..18a55f6 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -135,9 +135,6 @@ static void finalize_boot(void *unused) outb(0xcb, 0xb2); } -BOOT_STATE_INIT_ENTRIES(finalize) = { - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, - finalize_boot, NULL), -}; +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); #endif

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Patch merged into coreboot/master: 425b61e arch/x86/Kconfig: Add license header
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit 425b61e10214f7e4d029b2ec8cbac8913c54dd00 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 15 04:29:35 2015 +0100 arch/x86/Kconfig: Add license header Add license header with copyright of the original authors. Change-Id: I8c55bb38a2a2a387ad2461e11d402c7392fa2497 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/8691 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8691 for details. -gerrit

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Patch merged into coreboot/master: f364fc7 southbridge/amd/pi: Enable early I/O decode to LPC
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit f364fc7682e6ac68e1614e759a3cdeed46dd9e5b Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Mar 13 08:22:17 2015 -0600 southbridge/amd/pi: Enable early I/O decode to LPC The decode of UART addresses down to the LPC bus needs to occur early to allow romstage console messages to be seen. This enables the decode of most of the I/O ports typically seen in a system. Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/8661 for details. -gerrit

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Patch merged into coreboot/master: 68ec2fc ipq806x: Break apart large transfers in spi_xfer()
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit 68ec2fce2bcf0f9d8f02d80feb4d6bc4385e9047 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jul 25 12:59:48 2014 -0700 ipq806x: Break apart large transfers in spi_xfer() The current spi_xfer() function sets the count in hardware and then loops while waiting for the requested number of bytes to be sent or received. However, the number of bytes to be transferred may exceed the maximum count that can be programmed into the controller. This patch re-factors spi_xfer() to split the low-level FIFO handling portions for transmit/receive into their own functions to be called by loops in spi_xfer() which will break large transfers into smaller ones. BUG=chrome-os-partner:30904 BRANCH=storm TEST=built and booted with a >64KB payload on Storm Original-Change-Id: I70743487996cf08cfc602449f2181a7fcd99bfa4 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209838 Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> Original-Tested-by: Trevor Bourget <tbourget(a)codeaurora.org> (cherry picked from commit 5ec28de11f12c2438356f45ce978a17fbb603bf7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0033e0dd96006cfd30a7a4f5e5a052f677e05108 Reviewed-on: http://review.coreboot.org/8676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8676 for details. -gerrit

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Patch merged into coreboot/master: c4f08f7 cbfstool: Add relocation codes for arm mode
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit c4f08f7f9c56f5f988ecdd86323390c0f5b4232b Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 23 13:42:22 2014 -0700 cbfstool: Add relocation codes for arm mode Add relocation codes required for arm mode. These are required by armv4. BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ie7c5b3e07689c85091036a619a65f9fea1918b6b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209973 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit dc5f411f95e02a02b4a4ef4652303ce62aa220c2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ie62ed730080299e474c256371ab88f605b54c10f Reviewed-on: http://review.coreboot.org/8675 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8675 for details. -gerrit

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Patch merged into coreboot/master: c800129 t132: Add TTB_BUFFER to resource reserved
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit c8001290097b5b687953dc54f1ac167b16951668 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 25 14:50:23 2014 -0700 t132: Add TTB_BUFFER to resource reserved TTB_BUFFER holds the MMU tables. Thus, this memory needs to be preserved while performing a wipe in depthcharge. Hence, marking it as reserved BUG=None BRANCH=None TEST=Compiles successfully and boots upto depthcharge. Error wiping memory tables is fixed. Original-Change-Id: Idd5cd0235d50f7b9617df2cead3bf71012e3b630 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210000 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 670e21ed11f985ca6cfef4f051c71b3c06f9c6ff) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ifcbdd4fdaad0bd4bfe384698b13cc5013317345e Reviewed-on: http://review.coreboot.org/8681 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8681 for details. -gerrit

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Patch merged into coreboot/master: f4731af rush: Update rush Kconfig file
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit f4731afb9dd96bf1cb15cc2567a4bac4cf3f0cbe Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 25 14:35:46 2014 -0700 rush: Update rush Kconfig file Update rush Kconfig file to include TPM and RAMSTAGE_INDEX options BUG=None BRANCH=None TEST=Compiles successfully. TPM works. Ramstage boots successfully. Original-Change-Id: Ie55260c710ffcb6a2e04c8658ca6dd3cdec6b6db Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209978 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 0088f5aade8533c6ed235de25934d47cd0743a67) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5c4a54b74546de73eee7e7bae072cc712ce1838f Reviewed-on: http://review.coreboot.org/8680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8680 for details. -gerrit

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Patch merged into coreboot/master: e6ede46 rush: Add ec_dummy file to enable vboot compilation
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit e6ede46c3395f76b9777b6baa052b82000588fb4 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 23 13:48:41 2014 -0700 rush: Add ec_dummy file to enable vboot compilation BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ic11bef85e5c7635000582f87727cd9a33b0b36e3 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209975 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 3d3f0494d8758ef5040384f63d023c042686bd2c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ie15781d10a366b68f0db97378ccb348a4f074995 Reviewed-on: http://review.coreboot.org/8679 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8679 for details. -gerrit

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Patch merged into coreboot/master: 64352a7 rush: Pull in chromeos.c from nyan into rush
by gerrit＠coreboot.org 17 Mar '15

17 Mar '15

the following patch was just integrated into master: commit 64352a7c1b50819828cffdeacd93c757ee91c3ba Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jul 23 13:46:13 2014 -0700 rush: Pull in chromeos.c from nyan into rush Hardcoded values are set for developer,recovery mode. Change as per requirements BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles succesfully for rush Original-Change-Id: Ied506a9d1c4e0ba8ee06d57c6ca8c726220998b5 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209974 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 2e6934d47c5b4bb98e60486202b230bae79d927b) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I36e384b0d331fdd9e3f47954decfddaf4f31aed3 Reviewed-on: http://review.coreboot.org/8678 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8678 for details. -gerrit

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coreboot-gerrit March 2015