coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

1 participants
2443 discussions

Patch set updated for coreboot: f77f776 rush: Add MMC support
by Marc Jones 17 Mar '15

17 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8716 -gerrit commit f77f776c0135b6b37fb57d0c89332dcbf5dffb99 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 25 17:32:54 2014 -0700 rush: Add MMC support BUG=None BRANCH=None TEST=Compiles successfully. Depthcharge is able to see mmc. Original-Change-Id: Ia0c9b432fa447c64fa13e5fae5a66a26bbc86360 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210002 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 4cb05ffa95a2a36c5b4606d2f0efe9e574b84e1d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7f9a27a4c0f0553e78fc1a289bffebbebd37c099 --- src/mainboard/google/rush/mainboard.c | 67 +++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c index 9b8e354..6db314f 100644 --- a/src/mainboard/google/rush/mainboard.c +++ b/src/mainboard/google/rush/mainboard.c @@ -20,8 +20,75 @@ #include <device/device.h> #include <boot/coreboot_tables.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra132/gpio.h> +#include <soc/nvidia/tegra132/clk_rst.h> +#include <soc/addressmap.h> + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void init_mmc(void) +{ + clock_configure_source(sdmmc3, PLLP, 48000); + clock_configure_source(sdmmc4, PLLP, 48000); + + uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, + pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE, + pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE; + + // MMC3 (sdcard reader) + pinmux_set_config(PINMUX_SDMMC3_CLK_INDEX, + PINMUX_SDMMC3_CLK_FUNC_SDMMC3 | pin_none); + pinmux_set_config(PINMUX_SDMMC3_CMD_INDEX, + PINMUX_SDMMC3_CMD_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT0_INDEX, + PINMUX_SDMMC3_DAT0_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT1_INDEX, + PINMUX_SDMMC3_DAT1_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT2_INDEX, + PINMUX_SDMMC3_DAT2_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT3_INDEX, + PINMUX_SDMMC3_DAT3_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_CLK_LB_IN_INDEX, + PINMUX_SDMMC3_CLK_LB_IN_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_CLK_LB_OUT_INDEX, + PINMUX_SDMMC3_CLK_LB_OUT_FUNC_SDMMC3 | pin_down); + + // MMC3 Card Detect pin. + gpio_input_pullup(GPIO(V2)); + // Disable SD card reader power so it can be reset even on warm boot. + // Payloads must enable power before accessing SD card slots. + gpio_output(GPIO(R0), 0); + + // MMC4 (eMMC) + pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX, + PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none); + pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX, + PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX, + PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX, + PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX, + PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX, + PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX, + PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX, + PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX, + PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX, + PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up); + +} + static void mainboard_init(device_t dev) { + clock_enable_clear_reset(CLK_L_SDMMC4, 0, CLK_U_SDMMC3, 0, 0, 0); + + init_mmc(); } static void mainboard_enable(device_t dev)

1 0

Patch set updated for coreboot: 5e916d8 t132: Change romstage base address
by Marc Jones 17 Mar '15

17 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8723 -gerrit commit 5e916d8f5b7f812091b89d90cb3e8255ebfb4298 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 29 18:44:56 2014 -0700 t132: Change romstage base address Romstage was overflowing. So move the base address lower BUG=chrome-os-partner:31032 BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia05034477b51b149c87347ed1880f8e85ecbfbf8 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210434 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 14af527a5d7cbb250e2358340196a9d749ec1683) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib261fdd8b4c7eb4a1660c5d02fbcd3e0e3f34b22 --- src/soc/nvidia/tegra132/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index b746037..2bddf5c 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -41,7 +41,7 @@ config BOOTBLOCK_BASE config ROMSTAGE_BASE hex - default 0x4002c000 + default 0x40025000 config SYS_SDRAM_BASE hex

1 0

Patch set updated for coreboot: ed4e5b5 rush: Add support for chromeos_ec
by Marc Jones 17 Mar '15

17 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8724 -gerrit commit ed4e5b5340f21ba52b7add3d55c2c295db44ea01 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 29 18:47:16 2014 -0700 rush: Add support for chromeos_ec BUG=chrome-os-partner:31032 BRANCH=None TEST=Compiles successfully and ec error fixed while booting. Original-Change-Id: I02172a30863b7b97892289e880c29f2d71220fda Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210436 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 5447adb964276b9e13399ac93140ae763a149aad) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> src/mainboard/google/rush/Makefile.inc Change-Id: I38764a461b4009c6d722ec6fc64fda84a188169f --- src/mainboard/google/rush/Kconfig | 8 ++++++++ src/mainboard/google/rush/Makefile.inc | 2 -- src/mainboard/google/rush/mainboard.c | 9 +++++++++ src/mainboard/google/rush/romstage.c | 24 ++++++++++++++++++++++++ src/mainboard/google/rush_ryu/romstage.c | 4 ++++ src/soc/nvidia/tegra132/include/soc/romstage.h | 1 + src/soc/nvidia/tegra132/romstage.c | 1 + 7 files changed, 47 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index 8c162ec..49e61a4 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -22,6 +22,10 @@ if BOARD_GOOGLE_RUSH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select EC_SOFTWARE_SYNC + select SPI_FLASH select SOC_NVIDIA_TEGRA132 select MAINBOARD_HAS_BOOTBLOCK_INIT select VIRTUAL_DEV_SWITCH @@ -86,4 +90,8 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 1 + endif # BOARD_GOOGLE_RUSH diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc index e4520c1..b66cd55 100644 --- a/src/mainboard/google/rush/Makefile.inc +++ b/src/mainboard/google/rush/Makefile.inc @@ -36,8 +36,6 @@ romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-y += ec_dummy.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += ec_dummy.c \ No newline at end of file diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c index 6db314f..fd8a469 100644 --- a/src/mainboard/google/rush/mainboard.c +++ b/src/mainboard/google/rush/mainboard.c @@ -23,6 +23,7 @@ #include <soc/clock.h> #include <soc/nvidia/tegra132/gpio.h> #include <soc/nvidia/tegra132/clk_rst.h> +#include <soc/nvidia/tegra132/spi.h> #include <soc/addressmap.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; @@ -84,11 +85,19 @@ static void init_mmc(void) } +static void setup_ec_spi(void) +{ + struct tegra_spi_channel *spi; + + spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); +} + static void mainboard_init(device_t dev) { clock_enable_clear_reset(CLK_L_SDMMC4, 0, CLK_U_SDMMC3, 0, 0, 0); init_mmc(); + setup_ec_spi(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c index 7c01a30..5e74e71 100644 --- a/src/mainboard/google/rush/romstage.c +++ b/src/mainboard/google/rush/romstage.c @@ -51,6 +51,30 @@ void mainboard_init_tpm_i2c(void) configure_tpm_i2c_bus(); } +void mainboard_init_ec_spi(void) +{ + clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0); + + // SPI1 MOSI + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 MISO + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 SCLK + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 CS0 + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + + clock_configure_source(sbc1, CLK_M, 500); +} + void mainboard_configure_pmc(void) { } diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c index 9a41247..9235a77 100644 --- a/src/mainboard/google/rush_ryu/romstage.c +++ b/src/mainboard/google/rush_ryu/romstage.c @@ -23,6 +23,10 @@ void mainboard_init_tpm_i2c(void) { } +void mainboard_init_ec_spi(void) +{ +} + void mainboard_configure_pmc(void) { } diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h index f669121..d5fabd2 100644 --- a/src/soc/nvidia/tegra132/include/soc/romstage.h +++ b/src/soc/nvidia/tegra132/include/soc/romstage.h @@ -23,5 +23,6 @@ void mainboard_configure_pmc(void); void mainboard_enable_vdd_cpu(void); void mainboard_init_tpm_i2c(void); +void mainboard_init_ec_spi(void); #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 69271f0..b9932f2 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -68,6 +68,7 @@ void romstage(void) printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); mainboard_init_tpm_i2c(); + mainboard_init_ec_spi(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/ramstage");

1 0

New patch to review for coreboot: b127f87 rush: Add support for chromeos_ec
by Marc Jones 17 Mar '15

17 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8724 -gerrit commit b127f870fbd20063824651d586a8af2884a12eac Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 29 18:47:16 2014 -0700 rush: Add support for chromeos_ec BUG=chrome-os-partner:31032 BRANCH=None TEST=Compiles successfully and ec error fixed while booting. Original-Change-Id: I02172a30863b7b97892289e880c29f2d71220fda Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210436 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 5447adb964276b9e13399ac93140ae763a149aad) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> src/mainboard/google/rush/Makefile.inc Change-Id: I38764a461b4009c6d722ec6fc64fda84a188169f --- src/mainboard/google/rush/Kconfig | 8 ++++++++ src/mainboard/google/rush/Makefile.inc | 2 -- src/mainboard/google/rush/mainboard.c | 9 +++++++++ src/mainboard/google/rush/romstage.c | 24 ++++++++++++++++++++++++ src/soc/nvidia/tegra132/include/soc/romstage.h | 1 + src/soc/nvidia/tegra132/romstage.c | 1 + 6 files changed, 43 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index 8c162ec..49e61a4 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -22,6 +22,10 @@ if BOARD_GOOGLE_RUSH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select EC_SOFTWARE_SYNC + select SPI_FLASH select SOC_NVIDIA_TEGRA132 select MAINBOARD_HAS_BOOTBLOCK_INIT select VIRTUAL_DEV_SWITCH @@ -86,4 +90,8 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 1 + endif # BOARD_GOOGLE_RUSH diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc index e4520c1..b66cd55 100644 --- a/src/mainboard/google/rush/Makefile.inc +++ b/src/mainboard/google/rush/Makefile.inc @@ -36,8 +36,6 @@ romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-y += ec_dummy.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += ec_dummy.c \ No newline at end of file diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c index 6db314f..fd8a469 100644 --- a/src/mainboard/google/rush/mainboard.c +++ b/src/mainboard/google/rush/mainboard.c @@ -23,6 +23,7 @@ #include <soc/clock.h> #include <soc/nvidia/tegra132/gpio.h> #include <soc/nvidia/tegra132/clk_rst.h> +#include <soc/nvidia/tegra132/spi.h> #include <soc/addressmap.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; @@ -84,11 +85,19 @@ static void init_mmc(void) } +static void setup_ec_spi(void) +{ + struct tegra_spi_channel *spi; + + spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); +} + static void mainboard_init(device_t dev) { clock_enable_clear_reset(CLK_L_SDMMC4, 0, CLK_U_SDMMC3, 0, 0, 0); init_mmc(); + setup_ec_spi(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c index 7c01a30..5e74e71 100644 --- a/src/mainboard/google/rush/romstage.c +++ b/src/mainboard/google/rush/romstage.c @@ -51,6 +51,30 @@ void mainboard_init_tpm_i2c(void) configure_tpm_i2c_bus(); } +void mainboard_init_ec_spi(void) +{ + clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0); + + // SPI1 MOSI + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 MISO + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 SCLK + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 CS0 + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + + clock_configure_source(sbc1, CLK_M, 500); +} + void mainboard_configure_pmc(void) { } diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h index f669121..d5fabd2 100644 --- a/src/soc/nvidia/tegra132/include/soc/romstage.h +++ b/src/soc/nvidia/tegra132/include/soc/romstage.h @@ -23,5 +23,6 @@ void mainboard_configure_pmc(void); void mainboard_enable_vdd_cpu(void); void mainboard_init_tpm_i2c(void); +void mainboard_init_ec_spi(void); #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 69271f0..b9932f2 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -68,6 +68,7 @@ void romstage(void) printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); mainboard_init_tpm_i2c(); + mainboard_init_ec_spi(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/ramstage");

1 0

New patch to review for coreboot: 097820a t132: Change romstage base address
by Marc Jones 17 Mar '15

17 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8723 -gerrit commit 097820a1fc1bdcd62f1ec8fcabfc02c5346df6a9 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jul 29 18:44:56 2014 -0700 t132: Change romstage base address Romstage was overflowing. So move the base address lower BUG=chrome-os-partner:31032 BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia05034477b51b149c87347ed1880f8e85ecbfbf8 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210434 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 14af527a5d7cbb250e2358340196a9d749ec1683) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib261fdd8b4c7eb4a1660c5d02fbcd3e0e3f34b22 --- src/soc/nvidia/tegra132/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index b746037..2bddf5c 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -41,7 +41,7 @@ config BOOTBLOCK_BASE config ROMSTAGE_BASE hex - default 0x4002c000 + default 0x40025000 config SYS_SDRAM_BASE hex

1 0

New patch to review for coreboot: 771ec7d Enable publishing of board ID where supported
by Marc Jones 17 Mar '15

17 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8722 -gerrit commit 771ec7d04613916ddab7aba0bf021d5056f10f4a Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Jul 28 17:19:26 2014 -0700 Enable publishing of board ID where supported These boards are supposed to be able to determine the board ID at run time based on the certain GPIO settings. BUG=chrome-os-partner:30489 TEST=verified that all boards build. Checked that storm proto0 reports board ID of 0 on the console Original-Change-Id: Iadd758a799d69e1e34579d7d495378856b64c45b Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210119 (cherry picked from commit f4d41ddf906c1bf0d10da38011998fa0a630c332) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0d5f94d3428157a70f0a9d711b57432e3f796733 --- src/Kconfig | 4 ++-- src/mainboard/google/nyan_big/Kconfig | 2 ++ src/mainboard/google/nyan_blaze/Kconfig | 2 ++ src/mainboard/google/rush/Kconfig | 1 + src/mainboard/google/rush_ryu/Kconfig | 1 + src/mainboard/google/storm/Kconfig | 2 ++ 6 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7beb64c..c223901 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1127,8 +1127,8 @@ config BOARD_ID_SUPPORT config TERTIARY_BOARD_ID bool "Interpret board ID GPIOs as tertiary inputs" - default n if ARCH_X86 - default y if !ARCH_X86 + default n + depends on BOARD_ID_SUPPORT help Consider each GPIO as being in one of thee states: pulled down (0), pulled up (1), or not connected (2) diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index bee9748..2968b01 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -22,6 +22,7 @@ if BOARD_GOOGLE_NYAN_BIG config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_NVIDIA_TEGRA124 + select BOARD_ID_SUPPORT select MAINBOARD_HAS_CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI @@ -33,6 +34,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select VIRTUAL_DEV_SWITCH + select TERTIARY_BOARD_ID config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 1013455..789937f 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -22,6 +22,7 @@ if BOARD_GOOGLE_NYAN_BLAZE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_ARM + select BOARD_ID_SUPPORT select CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI @@ -33,6 +34,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select SPI_FLASH select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B + select TERTIARY_BOARD_ID select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index 8c162ec..87e742e 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -21,6 +21,7 @@ if BOARD_GOOGLE_RUSH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select BOARD_ID_SUPPORT select CHROMEOS select SOC_NVIDIA_TEGRA132 select MAINBOARD_HAS_BOOTBLOCK_INIT diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index 0d93564..c489a80 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -21,6 +21,7 @@ if BOARD_GOOGLE_RUSH_RYU config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select BOARD_ID_SUPPORT select SOC_NVIDIA_TEGRA132 select MAINBOARD_HAS_BOOTBLOCK_INIT select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 10c0f1b..b0c064c 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -22,11 +22,13 @@ if BOARD_GOOGLE_STORM config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_QC_IPQ806X + select BOARD_ID_SUPPORT select BOARD_ROMSIZE_KB_4096 select COMMON_CBFS_SPI_WRAPPER select MAINBOARD_HAS_BOOTBLOCK_INIT select SPI_FLASH select SPI_FLASH_SPANSION + select TERTIARY_BOARD_ID config BOARD_VARIANT_AP148 bool "pick this to build an image for ap148"

1 0

New patch to review for coreboot: a1ea9b7 storm: Add board ID calculation function
by Marc Jones 17 Mar '15

17 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8721 -gerrit commit a1ea9b7c1cf1eefd6bbcbf44a9db435745079d29 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Jul 28 16:47:08 2014 -0700 storm: Add board ID calculation function storm uses three GPIOs in tertiary mode, such that proto0 returns value of 8 when the GPIOs are interpreted as a single tertiary number. Adjust the calculated value to return board ID of 0 on proto0, and monotonously incrementing values on newer boards. BUG=chrome-os-partner:30489 TEST=when enabled, the board ID value of zero is reported on the console. Original-Change-Id: I2ff8fd5cbc8d568877b6f8bf220e146893f1e4be Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210118 (cherry picked from commit 6ba24f31583933f02be111c8767ae9df56537011) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I35ee218df35a0924d4bb8fcbc6c875450a609f24 --- src/mainboard/google/storm/Makefile.inc | 3 +- src/mainboard/google/storm/boardid.c | 50 +++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/Makefile.inc b/src/mainboard/google/storm/Makefile.inc index 4a47c9e..907638a 100644 --- a/src/mainboard/google/storm/Makefile.inc +++ b/src/mainboard/google/storm/Makefile.inc @@ -22,5 +22,6 @@ bootblock-y += cdp.c romstage-y += romstage.c romstage-y += cdp.c -ramstage-y += mainboard.c +ramstage-y += boardid.c ramstage-y += cdp.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c new file mode 100644 index 0000000..7cbb92a --- /dev/null +++ b/src/mainboard/google/storm/boardid.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <boardid.h> +#include <gpiolib.h> +#include <console/console.h> + +/* + * Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30 + * and 68. On proto0 GPIO68 is used and tied low, so it reads as 'zero' by + * gpio_board_id(), whereas the other two pins are not connected and read as + * 'two'. This results in gpio_board_id() returning 8 on proto0. + * + * Three tertitiary signals could represent 27 different values. To make + * calculated board ID value continuous and starting at zero, offset the + * calculated value by 19 (i.e. 27 - 8) and return modulo 27 of the offset + * number. This results in proto0 returning zero as the board ID, the future + * revisions will have the inputs configured to match the actual board + * revision. + */ + +uint8_t board_id(void) +{ + uint8_t bid; + gpio_t hw_rev_gpios[] = {68, 30, 29}; + int offset = 19; + + bid = gpio_board_id(hw_rev_gpios, ARRAY_SIZE(hw_rev_gpios), 1); + bid = (bid + offset) % 27; + printk(BIOS_INFO, "Board ID %d\n", bid); + + return bid; +}

1 0

New patch to review for coreboot: 780326d Include board ID calculations only when necessary
by Marc Jones 17 Mar '15

17 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8720 -gerrit commit 780326da20746ab13f962608428f4ba731294843 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Jul 28 16:08:34 2014 -0700 Include board ID calculations only when necessary For the majority of Chrome OS boards there is no need to include board ID calculation in any stage but ramstage, where the ID should be available for inclusion into the coreboot table. BUG=chrome-os-partner:30489 TEST=build only, no other tests yet Original-Change-Id: Ib9c06698a399d31e79a9b14143343ba2ad46d0fb Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210117 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 27dd40e85bfcd0a38f388bad4d79f5fbb77a7566) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1451d52382bc48cc126d40267e0f61712f4a6d4b --- src/lib/Makefile.inc | 2 +- src/mainboard/google/nyan/Makefile.inc | 1 + src/mainboard/google/nyan_big/Makefile.inc | 2 +- src/mainboard/google/nyan_blaze/Makefile.inc | 2 +- src/mainboard/google/rush/Makefile.inc | 4 ++-- src/mainboard/google/rush_ryu/Makefile.inc | 2 +- 6 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b3f3fbf..00a1ac9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -81,7 +81,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -ramstage--${CONFIG_TERTIARY_BOARD_ID} += tristate_gpios.c +ramstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c romstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += cbmem_common.c dynamic_cbmem.c diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index b66cd55..ace6e32 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -37,5 +37,6 @@ romstage-y += romstage.c romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc index b66cd55..59a1653 100644 --- a/src/mainboard/google/nyan_big/Makefile.inc +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -27,7 +27,6 @@ $(obj)/generated/bct.cfg: subdirs-y += bct -bootblock-y += boardid.c bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c @@ -37,5 +36,6 @@ romstage-y += romstage.c romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index dec8f64..2630dc5 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -27,7 +27,6 @@ $(obj)/generated/bct.cfg: subdirs-y += bct -bootblock-y += boardid.c bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c @@ -40,5 +39,6 @@ romstage-y += romstage.c romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc index e4520c1..ddf6660 100644 --- a/src/mainboard/google/rush/Makefile.inc +++ b/src/mainboard/google/rush/Makefile.inc @@ -27,7 +27,6 @@ $(obj)/generated/bct.cfg: subdirs-y += bct -bootblock-y += boardid.c bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c @@ -38,6 +37,7 @@ romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += ec_dummy.c +ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += ec_dummy.c \ No newline at end of file +ramstage-y += ec_dummy.c diff --git a/src/mainboard/google/rush_ryu/Makefile.inc b/src/mainboard/google/rush_ryu/Makefile.inc index 3c2b5da..9faba25 100644 --- a/src/mainboard/google/rush_ryu/Makefile.inc +++ b/src/mainboard/google/rush_ryu/Makefile.inc @@ -27,7 +27,6 @@ $(obj)/generated/bct.cfg: subdirs-y += bct -bootblock-y += boardid.c bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c @@ -36,4 +35,5 @@ romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c +ramstage-y += boardid.c ramstage-y += mainboard.c

1 0

New patch to review for coreboot: e978c73 Publish the board ID value in coreboot table, when configured
by Marc Jones 17 Mar '15

17 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8719 -gerrit commit e978c734ee5d0759b087795566c7f824b38dd601 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Jul 28 16:03:07 2014 -0700 Publish the board ID value in coreboot table, when configured Board ID value is usually of interest to bootloaders. Instead of duplicating the board ID discovery code in different bootloaders let's determine it in coreboot and publish it through coreboot table, when configured. BUG=chrome-os-partner:30489 TEST=none yet Original-Change-Id: Iee247c44a1c91dbcedcc9058e8742c75ff951f43 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210116 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit b2057a02db9391e2085b138eea843e6bb09d3ea2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia1e36b907ac15b0aafce0711f827cb83622e27bb --- src/Kconfig | 8 ++++++++ src/include/boot/coreboot_tables.h | 8 ++++++++ src/lib/Makefile.inc | 2 +- src/lib/coreboot_table.c | 18 ++++++++++++++++++ 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index ec6a3b3..7beb64c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1117,6 +1117,14 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config BOARD_ID_SUPPORT + bool "Discover board ID and store it in coreboot table" + default n + help + If enabled, coreboot discovers the board id of the hardware it is + running on and reports it through the coreboot table to the rest of + the system. + config TERTIARY_BOARD_ID bool "Interpret board ID GPIOs as tertiary inputs" default n if ARCH_X86 diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 3dc8fb6..fc44a3c 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -254,6 +254,14 @@ struct lb_x86_rom_mtrr { uint32_t index; }; +#define LB_TAG_BOARD_ID 0x0025 +struct lb_board_id { + uint32_t tag; + uint32_t size; + /* Board ID as retrieved from the board revision GPIOs. */ + uint32_t board_id; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 48c06bc..b3f3fbf 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -54,7 +54,6 @@ ifeq ($(CONFIG_COMPILER_GCC),y) romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c endif -romstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c @@ -82,6 +81,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c +ramstage--${CONFIG_TERTIARY_BOARD_ID} += tristate_gpios.c romstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += cbmem_common.c dynamic_cbmem.c diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index abcb0ed..2b484d4 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -26,6 +26,7 @@ #include <boot/coreboot_tables.h> #include <string.h> #include <version.h> +#include <boardid.h> #include <device/device.h> #include <stdlib.h> #include <cbfs.h> @@ -212,6 +213,19 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ +static void lb_board_id(struct lb_header *header) +{ +#if CONFIG_BOARD_ID_SUPPORT + struct lb_board_id *bid; + + bid = (struct lb_board_id *)lb_new_record(header); + + bid->tag = LB_TAG_BOARD_ID; + bid->size = sizeof(*bid); + bid->board_id = board_id(); +#endif +} + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -432,6 +446,10 @@ unsigned long write_coreboot_table( /* pass along the vboot_handoff address. */ lb_vboot_handoff(head); #endif + + /* Add board ID if available */ + lb_board_id(head); + add_cbmem_pointers(head); /* Add board-specific table entries, if any. */

1 0

New patch to review for coreboot: 8b0e4b3 ipq806x: implement GPIO API
by Marc Jones 17 Mar '15

17 Mar '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8718 -gerrit commit 8b0e4b3dd74ce754eede8df6a342e65c2dbaca84 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Jul 25 17:34:42 2014 -0700 ipq806x: implement GPIO API Add implementation of the GPIO API defined in src/include/gpiolib.h. Also, clean up the GPIO driver, make it use pointers instead of integers for register address. This requires a touch in the SPI driver, where the CS GPIO is toggled and in the board function where it enables USB interface. BUG=chrome-os-partner:30489 TEST=tested with the following patches, observed proto0 properly read the board ID. Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210115 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2 --- src/mainboard/google/storm/mainboard.c | 1 + src/soc/qualcomm/ipq806x/gpio.c | 97 +++++++++++++++----------------- src/soc/qualcomm/ipq806x/include/gpio.h | 5 +- src/soc/qualcomm/ipq806x/include/iomap.h | 4 +- src/soc/qualcomm/ipq806x/spi.c | 4 +- 5 files changed, 53 insertions(+), 58 deletions(-) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index bb4cff8..94f3a92 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -40,6 +40,7 @@ static void setup_usb(void) #if !CONFIG_BOARD_VARIANT_AP148 gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE); + gpio_set_out_value(USB_ENABLE_GPIO, 1); #endif usb_clock_config(); diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index ac41e1a..8cce3ba 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -50,20 +50,20 @@ static inline int gpio_not_valid(gpio_t gpio) Function description: configure GPIO functinality Arguments : gpio_t gpio - Gpio number -unsigned int func - Functionality number -unsigned int pull - pull up/down, no pull range(0-3) -unsigned int drvstr - range (0 - 7)-> (2- 16)MA steps of 2 -unsigned int enable - 1 - Disable, 2- Enable. +unsigned func - Functionality number +unsigned pull - pull up/down, no pull range(0-3) +unsigned drvstr - range (0 - 7)-> (2- 16)MA steps of 2 +unsigned enable - 0 Disable, 1 - Enable. Return : None *******************************************************/ -void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, - unsigned int pull, unsigned int drvstr, - unsigned int enable) +void gpio_tlmm_config_set(gpio_t gpio, unsigned func, + unsigned pull, unsigned drvstr, + unsigned enable) { - unsigned int val = 0; + unsigned val = 0; if (gpio_not_valid(gpio)) return; @@ -72,33 +72,33 @@ void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, val |= (func & GPIO_CFG_FUNC_MASK) << GPIO_CFG_FUNC_SHIFT; val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT; val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT; - unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio); - writel(val, addr); + + writel(val, GPIO_CONFIG_ADDR(gpio)); } /******************************************************* Function description: Get GPIO configuration Arguments : gpio_t gpio - Gpio number -unsigned int *func - Functionality number -unsigned int *pull - pull up/down, no pull range(0-3) -unsigned int *drvstr - range (0 - 7)-> (2- 16)MA steps of 2 -unsigned int *enable - 1 - Disable, 2- Enable. +unsigned *func - Functionality number +unsigned *pull - pull up/down, no pull range(0-3) +unsigned *drvstr - range (0 - 7)-> (2- 16)MA steps of 2 +unsigned *enable - 0 - Disable, 1- Enable. Return : None *******************************************************/ -void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, - unsigned int *pull, unsigned int *drvstr, - unsigned int *enable) +void gpio_tlmm_config_get(gpio_t gpio, unsigned *func, + unsigned *pull, unsigned *drvstr, + unsigned *enable) { - unsigned int val; + unsigned val; + void *addr = GPIO_CONFIG_ADDR(gpio); if (gpio_not_valid(gpio)) return; - unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio); val = readl(addr); *pull = (val >> GPIO_CFG_PULL_SHIFT) & GPIO_CFG_PULL_MASK; @@ -108,52 +108,47 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, } /******************************************************* -Function description: configure GPIO IO functinality +Function description: get GPIO IO functinality details Arguments : gpio_t gpio - Gpio number -unsigned int out - Controls value of GPIO output +unsigned *in - Value of GPIO input +unsigned *out - Value of GPIO output Return : None *******************************************************/ - -void gpio_io_config_set(gpio_t gpio, unsigned int out) +int gpio_get_in_value(gpio_t gpio) { - unsigned int val; - if (gpio_not_valid(gpio)) - return; - - unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio); + return -1; - val = readl(addr); - if (out) - val |= (1 << GPIO_IO_OUT_SHIFT); - else - val &= (~(1 << GPIO_IO_OUT_SHIFT)); - writel(val,addr); + return (readl(GPIO_IN_OUT_ADDR(gpio)) >> GPIO_IO_IN_SHIFT) & + GPIO_IO_IN_MASK; } -/******************************************************* -Function description: get GPIO IO functinality details -Arguments : -gpio_t gpio - Gpio number -unsigned int *in - Value of GPIO input -unsigned int *out - Value of GPIO output - -Return : None -*******************************************************/ - -void gpio_io_config_get(gpio_t gpio, unsigned int *in, unsigned int *out) +void gpio_set_out_value(gpio_t gpio, int value) { - unsigned int val; - if (gpio_not_valid(gpio)) return; - unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio); + writel((value & 1) << GPIO_IO_OUT_SHIFT, GPIO_IN_OUT_ADDR(gpio)); +} - val = readl(addr); - *in = (val >> GPIO_IO_IN_SHIFT) & GPIO_IO_IN_MASK; - *out = (val >> GPIO_IO_OUT_SHIFT) & GPIO_IO_OUT_MASK; +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_tlmm_config_set(gpio, GPIO_FUNC_DISABLE, + GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE); } + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_tlmm_config_set(gpio, GPIO_FUNC_DISABLE, + GPIO_PULL_UP, GPIO_2MA, GPIO_DISABLE); +} + +void gpio_input(gpio_t gpio) +{ + gpio_tlmm_config_set(gpio, GPIO_FUNC_DISABLE, + GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); +} + diff --git a/src/soc/qualcomm/ipq806x/include/gpio.h b/src/soc/qualcomm/ipq806x/include/gpio.h index 1f35aa7..276022c 100644 --- a/src/soc/qualcomm/ipq806x/include/gpio.h +++ b/src/soc/qualcomm/ipq806x/include/gpio.h @@ -64,8 +64,8 @@ #define GPIO_16MA 7 /* GPIO TLMM: Status */ -#define GPIO_ENABLE 0 -#define GPIO_DISABLE 1 +#define GPIO_DISABLE 0 +#define GPIO_ENABLE 1 /* GPIO MAX Valid # */ #define GPIO_MAX_NUM 68 @@ -99,7 +99,6 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, unsigned int *enable); void gpio_io_config_set(gpio_t gpio, unsigned int out); -void gpio_io_config_get(gpio_t gpio, unsigned int *in, unsigned int *out); /* Keep this to maintain backwards compatibility with the vendor API. */ static inline void gpio_tlmm_config(unsigned int gpio, unsigned int func, diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h index 69744bc..c9c8fc4 100644 --- a/src/soc/qualcomm/ipq806x/include/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/iomap.h @@ -81,9 +81,9 @@ #define DGT_CLEAR DGT_REG(0x000C) #define DGT_CLK_CTL DGT_REG(0x0010) -#define TLMM_BASE_ADDR 0x00800000 +#define TLMM_BASE_ADDR ((char *)0x00800000) #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) -#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10) +#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) /* Yes, this is not a typo... host2 is actually mapped before host1. */ #define USB_HOST2_XHCI_BASE 0x10000000 diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 2c16cb6..54d54b2 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -279,13 +279,13 @@ static int check_qup_clk_state(unsigned int core_num, int enable) static void CS_change(int port_num, int cs_num, int enable) { unsigned int cs_gpio = cs_gpio_array[port_num][cs_num]; - uint32_t addr = GPIO_IN_OUT_ADDR(cs_gpio); + void *addr = GPIO_IN_OUT_ADDR(cs_gpio); uint32_t val = readl_i(addr); val &= (~(1 << GPIO_OUTPUT)); if (!enable) val |= (1 << GPIO_OUTPUT); - writel_i(val, addr); + writel(val, addr); } /*

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2015