coreboot-gerrit September 2014

coreboot-gerrit@coreboot.org

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580 discussions

Patch merged into coreboot/master: f4ea9b2 towiki.sh: Rename GM45 slot and cpu to correct ones.
by gerrit＠coreboot.org 13 Sep '14

13 Sep '14

the following patch was just integrated into master: commit f4ea9b2551214d5b4cf9ac528c227f2242815383 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Aug 16 17:16:20 2014 +0200 towiki.sh: Rename GM45 slot and cpu to correct ones. Change-Id: Idc8135911549ac39c28932065897ca6643c13656 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6690 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6690 for details. -gerrit

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New patch to review for coreboot: 1012fca to-wiki: Add SANDYBRIDGE_NATIVE to the list of sandybridge names.
by Vladimir Serbinenko 13 Sep '14

13 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6901 -gerrit commit 1012fcab2d36a38179542ac01ed73d144f9a9457 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Sep 13 18:04:01 2014 +0200 to-wiki: Add SANDYBRIDGE_NATIVE to the list of sandybridge names. Change-Id: If13baf5a65f59fe582201b40d7656505fbd69fb8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- 3rdparty | 2 +- util/board_status/to-wiki/towiki.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/3rdparty b/3rdparty index 45f0c04..f37e0e6 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit 45f0c04fd788fb29d9e303b2b2d1657ddb03448a +Subproject commit f37e0e64ac1ac6700a9469f4adc2c391cbd93e43 diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index a0b22da..e1edd8e 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -318,7 +318,7 @@ EOF INTEL_IVYBRIDGE_NATIVE|INTEL_IVYBRIDGE|INTEL_FSP_IVYBRIDGE) cpu_nice="Intel® 3rd Gen (Ivybridge) Core i3/i5/i7" socket_nice="Socket RPGA989";; - INTEL_SANDYBRIDGE) + INTEL_SANDYBRIDGE_NATIVE|INTEL_SANDYBRIDGE) cpu_nice="Intel® 2nd Gen (Sandybridge) Core i3/i5/i7" socket_nice="Socket RPGA989";; *)

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Patch set updated for coreboot: b156969 southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.
by Vladimir Serbinenko 13 Sep '14

13 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5133 -gerrit commit b1569691c7f797adb625dd1f37736a653918eb8d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 15:03:50 2014 +0100 southbridge/bd82x6x: Reserve 16 MiB for flash and not 8. X230 has 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash but address map limits this to 16MiB. Change-Id: Icc39c3c8d45d2d14e437bdfce920f8b4b039789d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/bd82x6x/lpc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 396b771..fa05d54 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -597,8 +597,11 @@ static void pch_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ + res->base = 0xff000000; + /* Some systems (e.g. X230) have 12 MiB flash. + SPI controller supports up to 2 x 16 MiB of flash but + address map limits this to 16MiB. */ + res->size = 0x01000000; /* 16 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

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Patch set updated for coreboot: 69974f5 payloads/external/SeaBIOS: Bump version to 1.7.5
by Edward O'Callaghan 13 Sep '14

13 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6900 -gerrit commit 69974f576e2c551b14d600f7ce387fb5f6cea879 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 20:43:45 2014 +1000 payloads/external/SeaBIOS: Bump version to 1.7.5 Change-Id: Ie4b58b739ea411035b1801348e3e73e607299846 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 02c31e3..0831eea 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 +TAG-$(CONFIG_SEABIOS_STABLE)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2 unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index 28f1181..2e01abc 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -592,7 +592,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "1.7.4" + bool "1.7.5" help Stable SeaBIOS version config SEABIOS_MASTER

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Patch merged into coreboot/master: a71bdc3 intel/gma: consolidate vbt code
by gerrit＠coreboot.org 13 Sep '14

13 Sep '14

the following patch was just integrated into master: commit a71bdc318195b864c427cddc60e69a6145a8ab28 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Aug 30 00:35:39 2014 +0200 intel/gma: consolidate vbt code Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6800 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6800 for details. -gerrit

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New patch to review for coreboot: c7e5660 payloads/external/SeaBIOS: Bump version to 1.7.5
by Edward O'Callaghan 13 Sep '14

13 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6900 -gerrit commit c7e56608a893c52adb146ee0222e750d6ce94043 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 20:43:45 2014 +1000 payloads/external/SeaBIOS: Bump version to 1.7.5 Change-Id: Ie4b58b739ea411035b1801348e3e73e607299846 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 02c31e3..a13857e 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 +TAG-$(CONFIG_SEABIOS_STABLE)=e51488c unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index 28f1181..2e01abc 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -592,7 +592,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "1.7.4" + bool "1.7.5" help Stable SeaBIOS version config SEABIOS_MASTER

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Patch set updated for coreboot: 567fb4c intel/gma: consolidate vbt code
by Vladimir Serbinenko 13 Sep '14

13 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6800 -gerrit commit 567fb4cddda17a20d8f8ebbbd3350eae56ad5d41 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Aug 30 00:35:39 2014 +0200 intel/gma: consolidate vbt code Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/Makefile.inc | 2 +- src/drivers/intel/gma/i915.h | 19 ++++ src/drivers/intel/gma/intel_bios.h | 52 +++++++++ src/drivers/intel/gma/vbt.c | 110 ++++++++++++++++++ src/include/smbios.h | 1 + src/mainboard/google/link/i915.c | 4 +- src/mainboard/google/link/i915io.c | 1 + src/mainboard/lenovo/t530/devicetree.cb | 8 +- src/mainboard/lenovo/x200/devicetree.cb | 8 +- src/mainboard/lenovo/x201/devicetree.cb | 8 +- src/mainboard/lenovo/x220/devicetree.cb | 8 +- src/mainboard/lenovo/x230/devicetree.cb | 8 +- src/mainboard/packardbell/ms2290/devicetree.cb | 8 +- src/northbridge/intel/gm45/chip.h | 7 +- src/northbridge/intel/gm45/gma.c | 126 +++------------------ src/northbridge/intel/nehalem/acpi.c | 1 + src/northbridge/intel/nehalem/chip.h | 7 +- src/northbridge/intel/nehalem/gma.c | 102 +++-------------- src/northbridge/intel/nehalem/gma.h | 52 --------- src/northbridge/intel/sandybridge/acpi.c | 1 + src/northbridge/intel/sandybridge/chip.h | 7 +- src/northbridge/intel/sandybridge/gma.c | 8 +- src/northbridge/intel/sandybridge/gma.h | 56 +-------- .../intel/sandybridge/gma_ivybridge_lvds.c | 110 +++--------------- .../intel/sandybridge/gma_sandybridge_lvds.c | 108 +++--------------- 25 files changed, 288 insertions(+), 534 deletions(-) diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index b19334e..d963df9 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -19,7 +19,7 @@ ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c display.c ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c -ramstage-$(CONFIG_INTEL_EDID) += edid.c +ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c ifeq ($(CONFIG_VGA_ROM_RUN),y) ramstage-$(CONFIG_INTEL_INT15) += int15.c endif diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index bc43fc5..0d5b8af 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef INTEL_I915_H +#define INTEL_I915_H 1 + #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/drm_dp_helper.h> #include <edid.h> @@ -282,6 +285,14 @@ int gtt_poll(u32 reg, u32 mask, u32 value); void gtt_write(u32 reg, u32 data); u32 gtt_read(u32 reg); +struct i915_gpu_controller_info +{ + int use_spread_spectrum_clock; + int lvds_dual_channel; + int link_frequency_270_mhz; + int lvds_num_lanes; +}; + int i915lightup(unsigned int physbase, unsigned int mmio, unsigned int gfx, unsigned int init_fb); int panel_lightup(struct intel_dp *dp, unsigned int init_fb); @@ -289,3 +300,11 @@ void *igd_make_opregion(void); /* display.c */ void compute_display_params(struct intel_dp *dp); + +/* vbt.c */ +struct device; +void +generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, + struct device *dev, const char *idstr); + +#endif diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h index 36426d8..7b5edd3 100644 --- a/src/drivers/intel/gma/intel_bios.h +++ b/src/drivers/intel/gma/intel_bios.h @@ -730,4 +730,56 @@ struct bdb_mipi { u32 clk_lane_switch_cnt; } __attribute__((packed)); +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + #endif /* _I830_BIOS_H_ */ diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c new file mode 100644 index 0000000..1cc4e93 --- /dev/null +++ b/src/drivers/intel/gma/vbt.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013, 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <string.h> +#include <device/pci_rom.h> + +#include "i915.h" +#include "intel_bios.h" + +static size_t generate_vbt(const struct i915_gpu_controller_info *conf, + void *vbt, const char *idstr) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset (head, 0, sizeof (*head)); + + memcpy (head->signature, idstr, 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset (bdb_head, 0, sizeof (*bdb_head)); + memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset (genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} + +void +generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, + struct device *dev, const char *idstr) +{ + optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; + optionrom_pcir_t *pcir; + size_t vbt_size; + size_t fake_oprom_size; + + memset(oh, 0, 8192); + + oh->signature = PCI_ROM_HDR; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->indicator = 0x80; + + vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80), idstr); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; + +} diff --git a/src/include/smbios.h b/src/include/smbios.h index cf9df1a..9060906 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -19,6 +19,7 @@ const char *smbios_mainboard_serial_number(void); const char *smbios_mainboard_version(void); void smbios_mainboard_set_uuid(u8 *uuid); const char *smbios_mainboard_bios_version(void); +u8 smbios_mainboard_enclosure_type(void); #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index c24c4bd..383c891 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -236,8 +236,8 @@ static int run(int index) return i+1; } -int i915lightup(const struct northbridge_intel_sandybridge_config *info, - u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) { static struct edid edid; int edid_ok; diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c index 4bf0e6f..b66771a 100644 --- a/src/mainboard/google/link/i915io.c +++ b/src/mainboard/google/link/i915io.c @@ -18,6 +18,7 @@ */ #include <stdint.h> +#include <stdlib.h> #include "i915io.h" struct iodef iodefs[] = { diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index ec9041d..b44623b 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "1" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 285e30f..376273a 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/intel/gm45 - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 21e328a..7592cb0 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -35,10 +35,10 @@ chip northbridge/intel/nehalem register "gpu_panel_power_backlight_off_delay" = "2500" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" chip ec/lenovo/pmh7 device pnp ff.1 on # dummy diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 96bed1e..dc129c0 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 9dc559c..1886ba9 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index a57a2c1..19f6c9c 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -35,10 +35,10 @@ chip northbridge/intel/nehalem register "gpu_panel_power_backlight_off_delay" = "3000" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gpu_use_spread_spectrum_clock" = "0" - register "gpu_lvds_dual_channel" = "1" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "0" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 90a0e1e..a4a7a75 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -21,11 +21,10 @@ #ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H #define NORTHBRIDGE_INTEL_GM45_CHIP_H +#include <drivers/intel/gma/i915.h> + struct northbridge_intel_gm45_config { - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 12a0b4d..74e16ad 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -39,31 +39,6 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - static struct resource *gtt_res = NULL; void gtt_write(u32 reg, u32 data) @@ -144,7 +119,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -197,7 +172,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -267,7 +242,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -279,10 +254,10 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -299,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); mdelay(1); @@ -310,18 +285,18 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PP_CONTROL, @@ -329,7 +304,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -423,7 +398,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -457,54 +432,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, #endif } -static size_t generate_vbt(const struct northbridge_intel_gm45_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset (head, 0, sizeof (*head)); - - memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset (bdb_head, 0, sizeof (*bdb_head)); - memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset (genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - #endif static void gma_func0_init(struct device *dev) @@ -542,34 +469,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - if (read16(PCI_VGA_RAM_IMAGE_START) != PCI_ROM_HDR) { - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - - memset(oh, 0, 8192); - - oh->signature = PCI_ROM_HDR; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; - } + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); #endif /* Post VBIOS init */ diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 9b7357c..6f694e2 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -31,6 +31,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/intel_bios.h> #include <build.h> #include <arch/acpigen.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index e33d108..1a31238 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,8 +41,5 @@ struct northbridge_intel_nehalem_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index a57bf6b..c3e2a49 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -654,7 +654,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -719,7 +719,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -790,7 +790,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -802,10 +802,10 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -822,12 +822,12 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -837,18 +837,18 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -856,7 +856,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -953,7 +953,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -988,53 +988,6 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, #endif } -static size_t generate_vbt(const struct northbridge_intel_nehalem_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} #endif static void gma_func0_init(struct device *dev) @@ -1072,34 +1025,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) { - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; - } + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); #endif diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h index fdea85a..f0e1c53 100644 --- a/src/northbridge/intel/nehalem/gma.h +++ b/src/northbridge/intel/nehalem/gma.h @@ -118,56 +118,4 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - #endif diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 925812a..c77b5cc 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -33,6 +33,7 @@ #include <arch/acpigen.h> #include "sandybridge.h" #include <cbmem.h> +#include <drivers/intel/gma/intel_bios.h> unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index cc32c37..07809f5 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,8 +41,5 @@ struct northbridge_intel_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f305b81..247c723 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -278,12 +278,12 @@ u32 map_oprom_vendev(u32 vendev) static struct resource *gtt_res = NULL; -static inline u32 gtt_read(u32 reg) +u32 gtt_read(u32 reg) { return read32(gtt_res->base + reg); } -static inline void gtt_write(u32 reg, u32 data) +void gtt_write(u32 reg, u32 data) { write32(gtt_res->base + reg, data); } @@ -295,7 +295,7 @@ static inline void gtt_write_powermeter(const struct gt_powermeter *pm) } #define GTT_RETRY 1000 -static int gtt_poll(u32 reg, u32 mask, u32 value) +int gtt_poll(u32 reg, u32 mask, u32 value) { unsigned try = GTT_RETRY; u32 data; @@ -595,7 +595,7 @@ static void gma_func0_init(struct device *dev) physbase = pci_read_config32(dev, 0x5c) & ~0xf; graphics_base = dev->resource_list[1].base; - int lightup_ok = i915lightup_sandy(conf, physbase, iobase, mmiobase, graphics_base); + int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base); if (lightup_ok) gfx_set_init_done(1); #endif diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index b7502cd..3a73e08 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -114,59 +114,7 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - -struct northbridge_intel_sandybridge_config; +struct i915_gpu_controller_info; -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u32 mmio, u32 lfb); diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 53fbfda..e3e1f4b 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -36,54 +36,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void link_train(u32 mmio) { write32(mmio+0xf000c,0x40); @@ -207,8 +159,8 @@ static void enable_port(u32 mmio) read32(mmio + 0xc4000); } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, - u32 physbase, u16 piobase, u32 mmio, u32 lfb) +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; u8 edid_data[128]; @@ -277,7 +229,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 candp1, candn; u32 best_delta = 0xffffffff; - u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + u32 target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); u32 pixel_p1 = 1; u32 pixel_n = 1; @@ -350,7 +302,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, return 0; } - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -359,7 +311,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 1)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -371,10 +323,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -391,12 +343,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -406,10 +358,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); @@ -418,10 +370,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -429,7 +381,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -526,7 +478,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -562,35 +514,9 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); + return 1; } diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 77c5b6f..08cceea 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -26,7 +26,6 @@ #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> -#include <drivers/intel/gma/intel_bios.h> #include "gma.h" #include "chip.h" #include <pc80/vga.h> @@ -36,54 +35,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void train_link(u32 mmio) { /* Clear interrupts. */ @@ -171,7 +122,7 @@ static void power_port(u32 mmio) read32(mmio + 0x000e1180); // = 0x40000002 } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; @@ -187,7 +138,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -252,7 +203,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -323,7 +274,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -335,10 +286,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -355,12 +306,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -371,18 +322,18 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_DPLL_SEL, 8); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -390,7 +341,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -487,7 +438,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -522,35 +473,8 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); return 1; }

1 0

Patch set updated for coreboot: dea6656 Kconfig: Allow native vga init to be selectable for SeaBIOS payload
by Edward O'Callaghan 13 Sep '14

13 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6891 -gerrit commit dea6656a90a2443ef3445f92cef8ad26ff81049d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 03:43:49 2014 +1000 Kconfig: Allow native vga init to be selectable for SeaBIOS payload Change-Id: I1508f3d3c56cb9afbf4a23355831549552a62866 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile.inc | 4 ++++ payloads/external/SeaBIOS/Makefile.inc | 4 ++++ src/Kconfig | 16 ++++++++++++++++ src/arch/x86/Makefile.inc | 1 + 4 files changed, 25 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index c41945a..882448f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -532,6 +532,10 @@ ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif +ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + @printf " SeaBIOS Adding generated legacy VGA option rom.\n" + $(CBFSTOOL) $@.tmp add -f $(CONFIG_PAYLOAD_VGABIOS_FILE) -n vgaroms/seavgabios.bin -t raw +endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \ diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 21bc9a7..02c31e3 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -37,6 +37,10 @@ endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif +ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + echo "CONFIG_VGA_COREBOOT=y" >> seabios/.config + echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config +endif # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ diff --git a/src/Kconfig b/src/Kconfig index 443732a..28f1181 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -636,6 +636,17 @@ config SEABIOS_MALLOC_UPPERMEMORY hardware. In general, if this is desired, the option will be set to 'N' by the chipset Kconfig. +config SEABIOS_VGA_COREBOOT + prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS + default n + depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT + bool + help + Coreboot can initialize the GPU of some mainboards. + + After initializing the GPU, the information about it can be passed to the payload. + Provide an option rom that implements this legacy VGA BIOS compatibility requirement. + choice prompt "GRUB2 version" default GRUB2_MASTER @@ -683,6 +694,11 @@ config PAYLOAD_FILE depends on PAYLOAD_SEABIOS default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +config PAYLOAD_VGABIOS_FILE + string + depends on PAYLOAD_SEABIOS && SEABIOS_VGA_COREBOOT + default "payloads/external/SeaBIOS/seabios/out/vgabios.bin" + config PAYLOAD_FILE depends on PAYLOAD_FILO default "payloads/external/FILO/filo/build/filo.elf" diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index aa058c0..0a7399e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -349,6 +349,7 @@ seabios: CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ + CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \

1 0

Patch set updated for coreboot: 5959653 intel/gma: consolidate vbt code
by Vladimir Serbinenko 13 Sep '14

13 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6800 -gerrit commit 595965311bd27efda50500551996fe95028dda6f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Aug 30 00:35:39 2014 +0200 intel/gma: consolidate vbt code Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/Makefile.inc | 2 +- src/drivers/intel/gma/i915.h | 19 ++++ src/drivers/intel/gma/intel_bios.h | 52 +++++++++ src/drivers/intel/gma/vbt.c | 110 ++++++++++++++++++ src/include/smbios.h | 1 + src/mainboard/google/link/i915.c | 4 +- src/mainboard/google/link/i915io.c | 1 + src/mainboard/lenovo/x200/devicetree.cb | 8 +- src/mainboard/lenovo/x201/devicetree.cb | 8 +- src/mainboard/lenovo/x220/devicetree.cb | 8 +- src/mainboard/lenovo/x230/devicetree.cb | 8 +- src/mainboard/packardbell/ms2290/devicetree.cb | 8 +- src/northbridge/intel/gm45/chip.h | 7 +- src/northbridge/intel/gm45/gma.c | 126 +++------------------ src/northbridge/intel/nehalem/acpi.c | 1 + src/northbridge/intel/nehalem/chip.h | 7 +- src/northbridge/intel/nehalem/gma.c | 102 +++-------------- src/northbridge/intel/nehalem/gma.h | 52 --------- src/northbridge/intel/sandybridge/acpi.c | 1 + src/northbridge/intel/sandybridge/chip.h | 7 +- src/northbridge/intel/sandybridge/gma.c | 8 +- src/northbridge/intel/sandybridge/gma.h | 56 +-------- .../intel/sandybridge/gma_ivybridge_lvds.c | 110 +++--------------- .../intel/sandybridge/gma_sandybridge_lvds.c | 108 +++--------------- 24 files changed, 284 insertions(+), 530 deletions(-) diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index b19334e..d963df9 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -19,7 +19,7 @@ ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c display.c ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c -ramstage-$(CONFIG_INTEL_EDID) += edid.c +ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c ifeq ($(CONFIG_VGA_ROM_RUN),y) ramstage-$(CONFIG_INTEL_INT15) += int15.c endif diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index bc43fc5..0d5b8af 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef INTEL_I915_H +#define INTEL_I915_H 1 + #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/drm_dp_helper.h> #include <edid.h> @@ -282,6 +285,14 @@ int gtt_poll(u32 reg, u32 mask, u32 value); void gtt_write(u32 reg, u32 data); u32 gtt_read(u32 reg); +struct i915_gpu_controller_info +{ + int use_spread_spectrum_clock; + int lvds_dual_channel; + int link_frequency_270_mhz; + int lvds_num_lanes; +}; + int i915lightup(unsigned int physbase, unsigned int mmio, unsigned int gfx, unsigned int init_fb); int panel_lightup(struct intel_dp *dp, unsigned int init_fb); @@ -289,3 +300,11 @@ void *igd_make_opregion(void); /* display.c */ void compute_display_params(struct intel_dp *dp); + +/* vbt.c */ +struct device; +void +generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, + struct device *dev, const char *idstr); + +#endif diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h index 36426d8..7b5edd3 100644 --- a/src/drivers/intel/gma/intel_bios.h +++ b/src/drivers/intel/gma/intel_bios.h @@ -730,4 +730,56 @@ struct bdb_mipi { u32 clk_lane_switch_cnt; } __attribute__((packed)); +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + #endif /* _I830_BIOS_H_ */ diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c new file mode 100644 index 0000000..1cc4e93 --- /dev/null +++ b/src/drivers/intel/gma/vbt.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013, 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <string.h> +#include <device/pci_rom.h> + +#include "i915.h" +#include "intel_bios.h" + +static size_t generate_vbt(const struct i915_gpu_controller_info *conf, + void *vbt, const char *idstr) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset (head, 0, sizeof (*head)); + + memcpy (head->signature, idstr, 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset (bdb_head, 0, sizeof (*bdb_head)); + memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset (genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} + +void +generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, + struct device *dev, const char *idstr) +{ + optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; + optionrom_pcir_t *pcir; + size_t vbt_size; + size_t fake_oprom_size; + + memset(oh, 0, 8192); + + oh->signature = PCI_ROM_HDR; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->indicator = 0x80; + + vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80), idstr); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; + +} diff --git a/src/include/smbios.h b/src/include/smbios.h index cf9df1a..9060906 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -19,6 +19,7 @@ const char *smbios_mainboard_serial_number(void); const char *smbios_mainboard_version(void); void smbios_mainboard_set_uuid(u8 *uuid); const char *smbios_mainboard_bios_version(void); +u8 smbios_mainboard_enclosure_type(void); #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index c24c4bd..383c891 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -236,8 +236,8 @@ static int run(int index) return i+1; } -int i915lightup(const struct northbridge_intel_sandybridge_config *info, - u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) { static struct edid edid; int edid_ok; diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c index 4bf0e6f..b66771a 100644 --- a/src/mainboard/google/link/i915io.c +++ b/src/mainboard/google/link/i915io.c @@ -18,6 +18,7 @@ */ #include <stdint.h> +#include <stdlib.h> #include "i915io.h" struct iodef iodefs[] = { diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 285e30f..376273a 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/intel/gm45 - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 21e328a..7592cb0 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -35,10 +35,10 @@ chip northbridge/intel/nehalem register "gpu_panel_power_backlight_off_delay" = "2500" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" chip ec/lenovo/pmh7 device pnp ff.1 on # dummy diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 96bed1e..dc129c0 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 9dc559c..1886ba9 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index a57a2c1..19f6c9c 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -35,10 +35,10 @@ chip northbridge/intel/nehalem register "gpu_panel_power_backlight_off_delay" = "3000" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gpu_use_spread_spectrum_clock" = "0" - register "gpu_lvds_dual_channel" = "1" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "0" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 90a0e1e..a4a7a75 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -21,11 +21,10 @@ #ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H #define NORTHBRIDGE_INTEL_GM45_CHIP_H +#include <drivers/intel/gma/i915.h> + struct northbridge_intel_gm45_config { - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 12a0b4d..74e16ad 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -39,31 +39,6 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - static struct resource *gtt_res = NULL; void gtt_write(u32 reg, u32 data) @@ -144,7 +119,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -197,7 +172,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -267,7 +242,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -279,10 +254,10 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -299,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); mdelay(1); @@ -310,18 +285,18 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PP_CONTROL, @@ -329,7 +304,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -423,7 +398,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -457,54 +432,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, #endif } -static size_t generate_vbt(const struct northbridge_intel_gm45_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset (head, 0, sizeof (*head)); - - memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset (bdb_head, 0, sizeof (*bdb_head)); - memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset (genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - #endif static void gma_func0_init(struct device *dev) @@ -542,34 +469,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - if (read16(PCI_VGA_RAM_IMAGE_START) != PCI_ROM_HDR) { - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - - memset(oh, 0, 8192); - - oh->signature = PCI_ROM_HDR; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; - } + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); #endif /* Post VBIOS init */ diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 9b7357c..6f694e2 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -31,6 +31,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/intel_bios.h> #include <build.h> #include <arch/acpigen.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index e33d108..1a31238 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,8 +41,5 @@ struct northbridge_intel_nehalem_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index a57bf6b..c3e2a49 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -654,7 +654,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -719,7 +719,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -790,7 +790,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -802,10 +802,10 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -822,12 +822,12 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -837,18 +837,18 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -856,7 +856,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -953,7 +953,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -988,53 +988,6 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, #endif } -static size_t generate_vbt(const struct northbridge_intel_nehalem_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} #endif static void gma_func0_init(struct device *dev) @@ -1072,34 +1025,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) { - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; - } + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); #endif diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h index fdea85a..f0e1c53 100644 --- a/src/northbridge/intel/nehalem/gma.h +++ b/src/northbridge/intel/nehalem/gma.h @@ -118,56 +118,4 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - #endif diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 925812a..c77b5cc 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -33,6 +33,7 @@ #include <arch/acpigen.h> #include "sandybridge.h" #include <cbmem.h> +#include <drivers/intel/gma/intel_bios.h> unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index cc32c37..07809f5 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,8 +41,5 @@ struct northbridge_intel_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f305b81..247c723 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -278,12 +278,12 @@ u32 map_oprom_vendev(u32 vendev) static struct resource *gtt_res = NULL; -static inline u32 gtt_read(u32 reg) +u32 gtt_read(u32 reg) { return read32(gtt_res->base + reg); } -static inline void gtt_write(u32 reg, u32 data) +void gtt_write(u32 reg, u32 data) { write32(gtt_res->base + reg, data); } @@ -295,7 +295,7 @@ static inline void gtt_write_powermeter(const struct gt_powermeter *pm) } #define GTT_RETRY 1000 -static int gtt_poll(u32 reg, u32 mask, u32 value) +int gtt_poll(u32 reg, u32 mask, u32 value) { unsigned try = GTT_RETRY; u32 data; @@ -595,7 +595,7 @@ static void gma_func0_init(struct device *dev) physbase = pci_read_config32(dev, 0x5c) & ~0xf; graphics_base = dev->resource_list[1].base; - int lightup_ok = i915lightup_sandy(conf, physbase, iobase, mmiobase, graphics_base); + int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base); if (lightup_ok) gfx_set_init_done(1); #endif diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index b7502cd..3a73e08 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -114,59 +114,7 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - -struct northbridge_intel_sandybridge_config; +struct i915_gpu_controller_info; -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u32 mmio, u32 lfb); diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 53fbfda..e3e1f4b 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -36,54 +36,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void link_train(u32 mmio) { write32(mmio+0xf000c,0x40); @@ -207,8 +159,8 @@ static void enable_port(u32 mmio) read32(mmio + 0xc4000); } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, - u32 physbase, u16 piobase, u32 mmio, u32 lfb) +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; u8 edid_data[128]; @@ -277,7 +229,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 candp1, candn; u32 best_delta = 0xffffffff; - u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + u32 target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); u32 pixel_p1 = 1; u32 pixel_n = 1; @@ -350,7 +302,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, return 0; } - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -359,7 +311,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 1)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -371,10 +323,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -391,12 +343,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -406,10 +358,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); @@ -418,10 +370,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -429,7 +381,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -526,7 +478,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -562,35 +514,9 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); + return 1; } diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 77c5b6f..08cceea 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -26,7 +26,6 @@ #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> -#include <drivers/intel/gma/intel_bios.h> #include "gma.h" #include "chip.h" #include <pc80/vga.h> @@ -36,54 +35,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void train_link(u32 mmio) { /* Clear interrupts. */ @@ -171,7 +122,7 @@ static void power_port(u32 mmio) read32(mmio + 0x000e1180); // = 0x40000002 } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; @@ -187,7 +138,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -252,7 +203,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -323,7 +274,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -335,10 +286,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -355,12 +306,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -371,18 +322,18 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_DPLL_SEL, 8); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -390,7 +341,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -487,7 +438,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -522,35 +473,8 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); return 1; }

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New patch to review for coreboot: e15935d lenovo/t530: Fix merge conflict
by Vladimir Serbinenko 13 Sep '14

13 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6899 -gerrit commit e15935d89f2d8ef7e4801950a27be55926237a40 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Sep 13 12:29:54 2014 +0200 lenovo/t530: Fix merge conflict Change-Id: Idfc5efe39f3970ff2c333fd2a6f00ff839a3014f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t530/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index ec9041d..b44623b 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "1" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155"

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coreboot-gerrit September 2014