coreboot-gerrit September 2014

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Patch set updated for coreboot: f351464 intel/gma: consolidate vbt code
by Vladimir Serbinenko 13 Sep '14

13 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6800 -gerrit commit f351464fca7cb0b87962a7326c0f9779016ae460 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Aug 30 00:35:39 2014 +0200 intel/gma: consolidate vbt code Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/Makefile.inc | 3 +- src/drivers/intel/gma/i915.h | 19 ++++ src/drivers/intel/gma/intel_bios.h | 52 +++++++++ src/drivers/intel/gma/vbt.c | 110 ++++++++++++++++++ src/include/smbios.h | 1 + src/mainboard/google/link/i915.c | 4 +- src/mainboard/google/link/i915io.c | 1 + src/mainboard/lenovo/x200/devicetree.cb | 8 +- src/mainboard/lenovo/x201/devicetree.cb | 8 +- src/mainboard/lenovo/x220/devicetree.cb | 8 +- src/mainboard/lenovo/x220/mainboard.c | 1 + src/mainboard/lenovo/x230/devicetree.cb | 8 +- src/mainboard/packardbell/ms2290/devicetree.cb | 8 +- src/northbridge/intel/gm45/chip.h | 7 +- src/northbridge/intel/gm45/gma.c | 126 +++------------------ src/northbridge/intel/nehalem/acpi.c | 1 + src/northbridge/intel/nehalem/chip.h | 7 +- src/northbridge/intel/nehalem/gma.c | 102 +++-------------- src/northbridge/intel/nehalem/gma.h | 52 --------- src/northbridge/intel/sandybridge/acpi.c | 1 + src/northbridge/intel/sandybridge/chip.h | 7 +- src/northbridge/intel/sandybridge/gma.c | 8 +- src/northbridge/intel/sandybridge/gma.h | 56 +-------- .../intel/sandybridge/gma_ivybridge_lvds.c | 110 +++--------------- .../intel/sandybridge/gma_sandybridge_lvds.c | 108 +++--------------- 25 files changed, 286 insertions(+), 530 deletions(-) diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 7a1b97b..3c0a126 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -19,4 +19,5 @@ ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c display.c ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c -ramstage-$(CONFIG_INTEL_EDID) += edid.c +ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c + diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 15a2009..03b83e0 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef INTEL_I915_H +#define INTEL_I915_H 1 + #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/drm_dp_helper.h> #include <edid.h> @@ -277,8 +280,24 @@ int gtt_poll(u32 reg, u32 mask, u32 value); void gtt_write(u32 reg, u32 data); u32 gtt_read(u32 reg); +struct i915_gpu_controller_info +{ + int use_spread_spectrum_clock; + int lvds_dual_channel; + int link_frequency_270_mhz; + int lvds_num_lanes; +}; + int i915lightup(unsigned int physbase, unsigned int mmio, unsigned int gfx, unsigned int init_fb); /* display.c */ void compute_display_params(struct intel_dp *dp); + +/* vbt.c */ +struct device; +void +generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, + struct device *dev, const char *idstr); + +#endif diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h index 36426d8..7b5edd3 100644 --- a/src/drivers/intel/gma/intel_bios.h +++ b/src/drivers/intel/gma/intel_bios.h @@ -730,4 +730,56 @@ struct bdb_mipi { u32 clk_lane_switch_cnt; } __attribute__((packed)); +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + #endif /* _I830_BIOS_H_ */ diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c new file mode 100644 index 0000000..1cc4e93 --- /dev/null +++ b/src/drivers/intel/gma/vbt.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013, 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <string.h> +#include <device/pci_rom.h> + +#include "i915.h" +#include "intel_bios.h" + +static size_t generate_vbt(const struct i915_gpu_controller_info *conf, + void *vbt, const char *idstr) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset (head, 0, sizeof (*head)); + + memcpy (head->signature, idstr, 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset (bdb_head, 0, sizeof (*bdb_head)); + memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset (genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} + +void +generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, + struct device *dev, const char *idstr) +{ + optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; + optionrom_pcir_t *pcir; + size_t vbt_size; + size_t fake_oprom_size; + + memset(oh, 0, 8192); + + oh->signature = PCI_ROM_HDR; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->indicator = 0x80; + + vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80), idstr); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; + +} diff --git a/src/include/smbios.h b/src/include/smbios.h index cf9df1a..9060906 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -19,6 +19,7 @@ const char *smbios_mainboard_serial_number(void); const char *smbios_mainboard_version(void); void smbios_mainboard_set_uuid(u8 *uuid); const char *smbios_mainboard_bios_version(void); +u8 smbios_mainboard_enclosure_type(void); #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 8d94d36..929c1ee 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -236,8 +236,8 @@ static int run(int index) return i+1; } -int i915lightup(const struct northbridge_intel_sandybridge_config *info, - u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) { static struct edid edid; int edid_ok; diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c index abceb05..94adcba 100644 --- a/src/mainboard/google/link/i915io.c +++ b/src/mainboard/google/link/i915io.c @@ -18,6 +18,7 @@ */ #include <stdint.h> +#include <stdlib.h> #include "i915io.h" struct iodef iodefs[] = { diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 285e30f..376273a 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/intel/gm45 - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 21e328a..7592cb0 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -35,10 +35,10 @@ chip northbridge/intel/nehalem register "gpu_panel_power_backlight_off_delay" = "2500" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" chip ec/lenovo/pmh7 device pnp ff.1 on # dummy diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 96bed1e..dc129c0 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 28cd814..7a0b4a9 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -41,6 +41,7 @@ #include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> #include <build.h> +#include <smbios.h> #include <device/azalia_device.h> void mainboard_suspend_resume(void) diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 9dc559c..1886ba9 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index a57a2c1..19f6c9c 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -35,10 +35,10 @@ chip northbridge/intel/nehalem register "gpu_panel_power_backlight_off_delay" = "3000" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gpu_use_spread_spectrum_clock" = "0" - register "gpu_lvds_dual_channel" = "1" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "0" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 90a0e1e..a4a7a75 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -21,11 +21,10 @@ #ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H #define NORTHBRIDGE_INTEL_GM45_CHIP_H +#include <drivers/intel/gma/i915.h> + struct northbridge_intel_gm45_config { - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 12a0b4d..74e16ad 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -39,31 +39,6 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - static struct resource *gtt_res = NULL; void gtt_write(u32 reg, u32 data) @@ -144,7 +119,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -197,7 +172,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -267,7 +242,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -279,10 +254,10 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -299,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); mdelay(1); @@ -310,18 +285,18 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PP_CONTROL, @@ -329,7 +304,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -423,7 +398,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -457,54 +432,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, #endif } -static size_t generate_vbt(const struct northbridge_intel_gm45_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset (head, 0, sizeof (*head)); - - memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset (bdb_head, 0, sizeof (*bdb_head)); - memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset (genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - #endif static void gma_func0_init(struct device *dev) @@ -542,34 +469,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - if (read16(PCI_VGA_RAM_IMAGE_START) != PCI_ROM_HDR) { - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - - memset(oh, 0, 8192); - - oh->signature = PCI_ROM_HDR; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; - } + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); #endif /* Post VBIOS init */ diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 0ede237..40cb6b6 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -31,6 +31,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/intel_bios.h> #include <build.h> #include "nehalem.h" diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index e33d108..1a31238 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,8 +41,5 @@ struct northbridge_intel_nehalem_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index a57bf6b..c3e2a49 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -654,7 +654,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -719,7 +719,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -790,7 +790,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -802,10 +802,10 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -822,12 +822,12 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -837,18 +837,18 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -856,7 +856,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -953,7 +953,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -988,53 +988,6 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, #endif } -static size_t generate_vbt(const struct northbridge_intel_nehalem_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} #endif static void gma_func0_init(struct device *dev) @@ -1072,34 +1025,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) { - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; - } + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); #endif diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h index fdea85a..f0e1c53 100644 --- a/src/northbridge/intel/nehalem/gma.h +++ b/src/northbridge/intel/nehalem/gma.h @@ -118,56 +118,4 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - #endif diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 58e3b54..ea9ff50 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -30,6 +30,7 @@ #include <device/pci_ids.h> #include <build.h> #include "sandybridge.h" +#include <drivers/intel/gma/intel_bios.h> unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index cc32c37..07809f5 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,8 +41,5 @@ struct northbridge_intel_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f305b81..247c723 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -278,12 +278,12 @@ u32 map_oprom_vendev(u32 vendev) static struct resource *gtt_res = NULL; -static inline u32 gtt_read(u32 reg) +u32 gtt_read(u32 reg) { return read32(gtt_res->base + reg); } -static inline void gtt_write(u32 reg, u32 data) +void gtt_write(u32 reg, u32 data) { write32(gtt_res->base + reg, data); } @@ -295,7 +295,7 @@ static inline void gtt_write_powermeter(const struct gt_powermeter *pm) } #define GTT_RETRY 1000 -static int gtt_poll(u32 reg, u32 mask, u32 value) +int gtt_poll(u32 reg, u32 mask, u32 value) { unsigned try = GTT_RETRY; u32 data; @@ -595,7 +595,7 @@ static void gma_func0_init(struct device *dev) physbase = pci_read_config32(dev, 0x5c) & ~0xf; graphics_base = dev->resource_list[1].base; - int lightup_ok = i915lightup_sandy(conf, physbase, iobase, mmiobase, graphics_base); + int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base); if (lightup_ok) gfx_set_init_done(1); #endif diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index b7502cd..3a73e08 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -114,59 +114,7 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - -struct northbridge_intel_sandybridge_config; +struct i915_gpu_controller_info; -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u32 mmio, u32 lfb); diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 53fbfda..e3e1f4b 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -36,54 +36,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void link_train(u32 mmio) { write32(mmio+0xf000c,0x40); @@ -207,8 +159,8 @@ static void enable_port(u32 mmio) read32(mmio + 0xc4000); } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, - u32 physbase, u16 piobase, u32 mmio, u32 lfb) +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; u8 edid_data[128]; @@ -277,7 +229,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 candp1, candn; u32 best_delta = 0xffffffff; - u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + u32 target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); u32 pixel_p1 = 1; u32 pixel_n = 1; @@ -350,7 +302,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, return 0; } - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -359,7 +311,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 1)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -371,10 +323,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -391,12 +343,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -406,10 +358,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); @@ -418,10 +370,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -429,7 +381,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -526,7 +478,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -562,35 +514,9 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); + return 1; } diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 77c5b6f..08cceea 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -26,7 +26,6 @@ #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> -#include <drivers/intel/gma/intel_bios.h> #include "gma.h" #include "chip.h" #include <pc80/vga.h> @@ -36,54 +35,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void train_link(u32 mmio) { /* Clear interrupts. */ @@ -171,7 +122,7 @@ static void power_port(u32 mmio) read32(mmio + 0x000e1180); // = 0x40000002 } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; @@ -187,7 +138,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -252,7 +203,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -323,7 +274,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -335,10 +286,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -355,12 +306,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -371,18 +322,18 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_DPLL_SEL, 8); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -390,7 +341,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -487,7 +438,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -522,35 +473,8 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); return 1; }

1 0

Patch merged into coreboot/master: 75c8387 azalia: Shrink boilerplate
by gerrit＠coreboot.org 13 Sep '14

13 Sep '14

the following patch was just integrated into master: commit 75c83870e51e6bc48a83114c64177432d3204b1f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Sep 5 01:01:31 2014 +0200 azalia: Shrink boilerplate Change-Id: Ib3e09644c0ee71aacb067adaa85653d151b52078 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6840 for details. -gerrit

1 0

Patch merged into coreboot/master: a812643 mainboard/lenovo/t530: Enable PCIe Bridge for discrete graphics
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit a812643723419f4fe3f079731a9d10d2dc083aae Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 06:53:20 2014 +1000 mainboard/lenovo/t530: Enable PCIe Bridge for discrete graphics Change-Id: I80f1e27268d0be58514d110611fd3c18cbe81829 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6895 Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6895 for details. -gerrit

1 0

Patch merged into coreboot/master: cf6f9b9 mainboard/lenovo/t530: Make cdrom drive work by fixing devicetree
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit cf6f9b9464732b9deb862a60d0fa2b1fe1c8ae9f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 06:06:05 2014 +1000 mainboard/lenovo/t530: Make cdrom drive work by fixing devicetree Change-Id: I804aff0fa53609e5fc70301053f075aa54b9bde5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6893 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/6893 for details. -gerrit

1 0

Patch merged into coreboot/master: 4d7d25f payloads/external/SeaBIOS: Allow setting buffers below 0xC0000
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit 4d7d25f38abac4bcd3ea88a50b5f529f1e9ddb44 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Jul 25 14:39:05 2014 -0600 payloads/external/SeaBIOS: Allow setting buffers below 0xC0000 Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is a requirement on the Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB and SATA from bus-mastering into the buffers when they're set in the typical 0xE0000 area. This will be set to Y unless defaulted to N by the mainboard or chipset. Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6364 for details. -gerrit

1 0

New patch to review for coreboot: af8067a mainboard/lenovo/t530: Enable PCIe Bridge for discrete graphics
by Edward O'Callaghan 12 Sep '14

12 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6895 -gerrit commit af8067af29cc70eb3620d99fe562fd9b4c791fd1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 06:53:20 2014 +1000 mainboard/lenovo/t530: Enable PCIe Bridge for discrete graphics Change-Id: I80f1e27268d0be58514d110611fd3c18cbe81829 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 7d9754f..ec9041d 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -40,7 +40,7 @@ chip northbridge/intel/sandybridge device domain 0 on device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH

1 0

New patch to review for coreboot: 9eafba5 mainboard/lenovo/t530: Fix KB in SeaBIOS payload
by Edward O'Callaghan 12 Sep '14

12 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6894 -gerrit commit 9eafba5d4348e0fe5eaeae3705b8abf970678a1c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 06:09:12 2014 +1000 mainboard/lenovo/t530: Fix KB in SeaBIOS payload We boot too quick!!! The EC is a old fart that takes too long to init, leaving the keyboard borked in SeaBIOS. Add a delay to work around this for now. Change-Id: I23771953bf34a8d928cfe7272199d7d91d71a1d5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index c34b647..c984b4c 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -80,4 +80,10 @@ config MAINBOARD_VENDOR string default "LENOVO" +# Workaround slow EC for keyboard to work +# in SeaBIOS payload. +config SEABIOS_PS2_TIMEOUT + int + default 1000 + endif # BOARD_LENOVO_T530

1 0

New patch to review for coreboot: 6af3f3d mainboard/lenovo/t530: Make cdrom drive work by fixing devicetree
by Edward O'Callaghan 12 Sep '14

12 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6893 -gerrit commit 6af3f3d389b41f1572f22e31a18e36e14459e1ce Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 06:06:05 2014 +1000 mainboard/lenovo/t530: Make cdrom drive work by fixing devicetree Change-Id: I804aff0fa53609e5fc70301053f075aa54b9bde5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index b22d405..7d9754f 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -61,8 +61,8 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "2" register "gpi8_routing" = "2" - # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) - register "sata_port_map" = "0x7" + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) + register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3"

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Patch merged into coreboot/master: b3997ba arm: Remove some pointless CFLAGS
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit b3997ba6f2ba26e0dfa851caed98f030ac25ffd0 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Nov 12 14:46:07 2013 -0800 arm: Remove some pointless CFLAGS This patch removes the -ffixed-r8 CFLAG from the coreboot and libpayload Makefiles. This seems to be a relic from U-Boot, which uses that register to keep it's global data structure pointer. There's no reason for us to throw away a perfectly fine register on this already pretty constrained architecture. Also removed a config.h inclusion from the Makefile because that should really be done inside the C files. Change-Id: Ia176c0f323c1be07cddf88fa5488788786a27cdf Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177110 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 2a81112abde284ba09020db6afa363169911a7f6) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6880 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6880 for details. -gerrit

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Patch merged into coreboot/master: 8f50e53 cbfstool: Fix architecture check when adding payload
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit 8f50e53a4bb4c6f4b95398bb57d58f32fecdad93 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 13 14:34:57 2013 -0800 cbfstool: Fix architecture check when adding payload In the process of rewriting cbfstool for ARM and using a new internal API a regression was introduced that would silently let you add an ARM payload into an x86 CBFS image and the other way around. This patch fixes cbfstool to produce an error in that case again. Change-Id: I37ee65a467d9658d0846c2cf43b582e285f1a8f8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/176711 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 8f74f3f5227e440ae46b59f8fd692f679f3ada2d) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6879 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6879 for details. -gerrit

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coreboot-gerrit September 2014