coreboot-gerrit September 2014

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Patch set updated for coreboot: f663213 i945 : Some fix for 945G/945GZ/945GC
by HAOUAS Elyes 13 Sep '14

13 Sep '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6813 -gerrit commit f663213e65b4c2899c8cc73c22a3414d918a282f Author: Elyes <ehaouas(a)noos.fr> Date: Sun Aug 31 11:13:47 2014 +0200 i945 : Some fix for 945G/945GZ/945GC Change-Id: Icbf691f33222445e7fcd670e0c6e6c4a9dcaf0aa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/Kconfig | 3 ++- src/northbridge/intel/i945/acpi.c | 2 +- src/northbridge/intel/i945/early_init.c | 16 +++++++++++++--- src/northbridge/intel/i945/gma.c | 16 ++++++++++++++-- src/northbridge/intel/i945/northbridge.c | 8 +++++++- src/northbridge/intel/i945/raminit.c | 28 ++++++++++++++-------------- 6 files changed, 51 insertions(+), 22 deletions(-) diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 360b2ab..99ea1fd 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -41,7 +41,8 @@ config BOOTBLOCK_NORTHBRIDGE_INIT config VGA_BIOS_ID string - default "8086,27a2" + default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM + default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC config CHANNEL_XOR_RANDOMIZATION bool diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index e05bd58..46ca36a 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -36,7 +36,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - dev = dev_find_device(0x8086, 0x27a0, 0); + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return current; diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ce10b..f3f0f00 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -131,6 +131,9 @@ static void i945_detect_chipset(void) case 0: printk(BIOS_DEBUG, "up to DDR2-667"); break; + case 2: + printk(BIOS_DEBUG, "up to DDR2-667"); + break; case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; @@ -194,7 +197,7 @@ static void i945_setup_bars(void) /* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); - if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ + if ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; } while (!(reg8 & 0x80)); @@ -226,6 +229,8 @@ static void i945_setup_egress_port(void) reg32 &= 0xffffff00; if ((MCHBAR32(CLKCFG) & 7) == 1) reg32 |= 0x0d; /* 533MHz */ + if ((MCHBAR32(CLKCFG) & 7) == 2) + reg32 |= 0x14; /* 800MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) reg32 |= 0x10; /* 667MHz */ EPBAR32(0x2c) = reg32; @@ -242,6 +247,11 @@ static void i945_setup_egress_port(void) EPBAR32(EPVC1IST + 4) = 0x009c009c; } + if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ + EPBAR32(EPVC1IST + 0) = 0x00f000f0; + EPBAR32(EPVC1IST + 4) = 0x00f000f0; + } + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0; @@ -425,9 +435,9 @@ static void i945_setup_dmi_rcrb(void) reg32 = DMIBAR32(0x204); reg32 &= ~0x3ff; #if 1 - reg32 |= 0x13f; /* for x4 DMI only */ + reg32 |= 0x13f; /* for x4 DMI only */ #else - reg32 |= 0x1e4; /* for x2 DMI only */ + reg32 |= 0x1e4; /* for x2 DMI only */ #endif DMIBAR32(0x204) = reg32; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 9b0dbd2..b1c9a3b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -499,6 +499,18 @@ static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; +static const unsigned short i945_gma_func0_ids[] = { + 0x27a2, + 0x2772, + 0 +}; + +static const unsigned short i945_gma_func1_ids[] = { + 0x27a6, + 0x2776, + 0 +}; + static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -524,11 +536,11 @@ static struct device_operations gma_func1_ops = { static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a2, + .devices = i945_gma_func0_ids, }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a6, + .devices = i945_gma_func1_ids, }; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 68d6d91..f666d49 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -267,10 +267,16 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, }; +static const unsigned short i945_pci_ids[] = { + 0x27a0, + 0x2770, + 0 +}; + static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a0, + .devices = i945_pci_ids, }; static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e823bab..beb3e77 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -113,6 +113,10 @@ static int memclk(void) offset++; #endif switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { +// FIXME: +// chip i945G/GZ/GC/P/PL & RAM at 667 we have MCHBAR32(0x0c00)= 0x20000032 +// chip i945G/GZ/GC/P/PL & RAM at 533 we have MCHBAR32(0x0c00)= 0x00000022 +// I945G/GZ/GC/P/PL support all frequency, so we probably can set it to already detected lowest RAM frequency. for exemple sysinfo->memory_frequency; case 1: return 400; case 2: return 533; case 3: return 667; @@ -121,29 +125,22 @@ static int memclk(void) return -1; } -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 400; - case 1: return 533; - case 3: return 667; - default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); - } - return 0xffff; -} -#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC -static u16 fsbclk(void) -{ - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 1066; + case 0: + #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM + return 400; + #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + return 1066; + #endif case 1: return 533; case 2: return 800; + case 3: return 667; default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); } return 0xffff; } -#endif static int sdram_capabilities_max_supported_memory_frequency(void) { @@ -2264,6 +2261,9 @@ static void sdram_program_clock_crossing(void) 0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ +//FIXME: value found for 82945G/GZ/GC/P/PL & DDR667 FSB800 : +// 0x04020130, 0x00000008, /* DDR667 FSB800 */ +// and not this one below 0x04020180, 0x00000008, /* DDR667 FSB800 */ 0x00020904, 0x00000000, /* DDR400 FSB1066 */

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Patch merged into coreboot/master: 85620db arm: Move exception_init() close to console_init()
by gerrit＠coreboot.org 13 Sep '14

13 Sep '14

the following patch was just integrated into master: commit 85620db107d587a8341987162d403f4b7aee9a81 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Nov 13 18:22:15 2013 -0800 arm: Move exception_init() close to console_init() This patch adds stub implementations of exception_init() to all archs so that it can be called from src/lib/hardwaremain.c. It also moves/adds all other invocations of exception_init() (which needs to be rerun in every stage) close to console_init(), in the hopes that it will be less likely overlooked when creating future boards. Also added (an ineffective) one to the armv4 bootblock implementations for consistency and in case we want to implement it later. Change-Id: Iecad10172d25f6c1fc54b0fec8165d7ef60e3414 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176764 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 2960623f4a59d841a13793ee906db8d1b1c16c5d) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6884 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6884 for details. -gerrit

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New patch to review for coreboot: ebdb4c0 libpayload: x86: Add support for catching processor exceptions.
by Isaac Christensen 13 Sep '14

13 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6898 -gerrit commit ebdb4c06f96abd8ce16b0b1d082bc9d8a091d815 Author: Gabe Black <gabeblack(a)google.com> Date: Sat Dec 7 04:25:01 2013 -0800 libpayload: x86: Add support for catching processor exceptions. This functionality is already available for ARM, so lets add it to x86 as well. We'll want to be able to hook exceptions when running as a remote GDB target. Change-Id: I42f640b08eb9eb86a1bcab3c327f7780191a2eb5 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/179601 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 5b8cf0c9f70a7e14766a2b095e6739a8d6321a34) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/arch/x86/Makefile.inc | 1 + payloads/libpayload/arch/x86/exception.c | 199 ++++++++++++++++ payloads/libpayload/arch/x86/exception_asm.S | 291 +++++++++++++++++++++++ payloads/libpayload/arch/x86/main.c | 3 + payloads/libpayload/include/arm/arch/exception.h | 2 +- payloads/libpayload/include/exception.h | 37 +++ 6 files changed, 532 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/x86/Makefile.inc b/payloads/libpayload/arch/x86/Makefile.inc index 8efbc12..549a630 100644 --- a/payloads/libpayload/arch/x86/Makefile.inc +++ b/payloads/libpayload/arch/x86/Makefile.inc @@ -32,6 +32,7 @@ libc-y += main.c sysinfo.c libc-y += timer.c coreboot.c util.S libc-y += exec.S virtual.c libc-y += string.c +libc-y += exception_asm.S exception.c libcbfs-$(CONFIG_LP_CBFS) += rom_media.c diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c new file mode 100644 index 0000000..a9a65ca --- /dev/null +++ b/payloads/libpayload/arch/x86/exception.c @@ -0,0 +1,199 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <exception.h> +#include <libpayload.h> +#include <stdint.h> + +uint8_t exception_stack[0x1000] __attribute__((aligned(8))); +extern void *exception_stack_end; + +struct exception_state +{ + u32 eax; + u32 ecx; + u32 edx; + u32 ebx; + u32 esp; + u32 ebp; + u32 esi; + u32 edi; + u32 eip; + u32 eflags; + u32 cs; + u32 ss; + u32 ds; + u32 es; + u32 fs; + u32 gs; + u32 error_code; + u32 vector; +} __attribute__((packed)); + +struct exception_info +{ + const char *name; + void (*error_code_printer)(u32 code); +}; + +static void print_segment_error_code(u32 code) +{ + printf("%#x - descriptor %#x in the ", code, (code >> 3) & 0x1f); + if (code & (0x1 << 1)) { + printf("IDT"); + } else { + if (code & 0x04) + printf("LDT"); + else + printf("GDT"); + } + if (code & (0x1 << 0)) + printf(", external to the CPU"); + else + printf(", internal to the CPU"); +} + +static void print_page_fault_error_code(u32 code) +{ + printf("%#x -", code); + if (code & (0x1 << 0)) + printf(" page protection"); + else + printf(" page not present"); + if (code & (0x1 << 1)) + printf(", write"); + else + printf(", read"); + if (code & (0x1 << 2)) + printf(", user"); + else + printf(", supervisor"); + if (code & (0x1 << 3)) + printf(", reserved bits set"); + if (code & (0x1 << 4)) + printf(", instruction fetch"); +} + +static void print_raw_error_code(u32 code) +{ + printf("%#x", code); +} + +static struct exception_info exceptions[] = { + [0] = { .name = "divide by zero" }, + [1] = { .name = "debug" }, + [2] = { .name = "non-maskable-interrupt" }, + [3] = { .name = "breakpoint" }, + [4] = { .name = "overflow" }, + [5] = { .name = "bound range" }, + [6] = { .name = "invalid opcode" }, + [7] = { .name = "device not available" }, + [8] = { .name = "double fault", + .error_code_printer = &print_raw_error_code }, + [10] = { .name = "invalid tss", + .error_code_printer = &print_segment_error_code }, + [11] = { .name = "segment not present", + .error_code_printer = &print_segment_error_code }, + [12] = { .name = "stack", + .error_code_printer = &print_segment_error_code }, + [13] = { .name = "general protection", + .error_code_printer = &print_segment_error_code }, + [14] = { .name = "page fault", + .error_code_printer = &print_page_fault_error_code }, + [16] = { .name = "x87 floating point" }, + [17] = { .name = "alignment check", + .error_code_printer = &print_raw_error_code }, + [18] = { .name = "machine check" }, + [19] = { .name = "SIMD floating point" }, + [30] = { .name = "security", + .error_code_printer = &print_raw_error_code }, +}; + +static void dump_stack(uintptr_t addr, size_t bytes) +{ + int i, j; + const int line = 8; + uint32_t *ptr = (uint32_t *)(addr & ~(line * sizeof(*ptr) - 1)); + + printf("Dumping stack:\n"); + for (i = bytes / sizeof(*ptr); i >= 0; i -= line) { + printf("%p: ", ptr + i); + for (j = i; j < i + line; j++) + printf("%08x ", *(ptr + j)); + printf("\n"); + } +} + +void exception_handler(void); +void exception_handler(void) +{ + struct exception_state *state = + (void *)((u8 *)exception_stack_end - sizeof(*state)); + + struct exception_info *info = NULL; + if (state->vector < ARRAY_SIZE(exceptions)) + info = &exceptions[state->vector]; + + if (info) + printf("Exception %d (%s)\n", state->vector, info->name); + else + printf("Unrecognized exception %d\n", state->vector); + if (info->error_code_printer) { + printf("Error code: "); + info->error_code_printer(state->error_code); + printf("\n"); + } + printf("EIP: 0x%08x\n", state->eip); + printf("CS: 0x%04x\n", state->cs); + printf("EFLAGS: 0x%08x\n", state->eflags); + printf("EAX: 0x%08x\n", state->eax); + printf("ECX: 0x%08x\n", state->ecx); + printf("EDX: 0x%08x\n", state->edx); + printf("EBX: 0x%08x\n", state->ebx); + printf("ESP: 0x%08x\n", state->esp); + printf("EBP: 0x%08x\n", state->ebp); + printf("ESI: 0x%08x\n", state->esi); + printf("EDI: 0x%08x\n", state->edi); + printf("DS: 0x%04x\n", state->ds); + printf("ES: 0x%04x\n", state->es); + printf("SS: 0x%04x\n", state->ss); + printf("FS: 0x%04x\n", state->fs); + printf("GS: 0x%04x\n", state->gs); + + dump_stack(state->esp, 512); + + halt(); +} + +void exception_init_asm(void); +void exception_init(void) +{ + exception_stack_end = exception_stack + sizeof(exception_stack); + exception_init_asm(); +} diff --git a/payloads/libpayload/arch/x86/exception_asm.S b/payloads/libpayload/arch/x86/exception_asm.S new file mode 100644 index 0000000..c56a7a0 --- /dev/null +++ b/payloads/libpayload/arch/x86/exception_asm.S @@ -0,0 +1,291 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + .align 4 + .global exception_stack_end +exception_stack_end: + .long 0 + +/* Some temporary variables which are used while saving exception state. */ +vector: + .long 0 +error_code: + .long 0 +old_esp: + .long 0 +old_eax: + .long 0 + + .align 8 + +/* + * Each exception vector has a small stub associated with it which sets aside + * the error code, if any, records which vector we entered from, and calls + * the common exception entry point. Some exceptions have error codes and some + * don't, so we have a macro for each type. + */ + + .macro stub num +exception_stub_\num: + movl $0, error_code + movl $\num, vector + jmp exception_common + .endm + + .macro stub_err num +exception_stub_\num: + popl error_code + movl $\num, vector + jmp exception_common + .endm + + stub 0 + stub 1 + stub 2 + stub 3 + stub 4 + stub 5 + stub 6 + stub 7 + stub_err 8 + stub 9 + stub_err 10 + stub_err 11 + stub_err 12 + stub_err 13 + stub_err 14 + stub 15 + stub 16 + stub_err 17 + stub 18 + stub 19 + stub 20 + stub 21 + stub 22 + stub 23 + stub 24 + stub 25 + stub 26 + stub 27 + stub 28 + stub 29 + stub_err 30 + stub 31 + +exception_common: + /* + * Save off the stack pointer and old eax value and install the + * exception stack. eax points to the old stack which has the + * exception ip, cs, and flags. + */ + mov %esp, old_esp + addl $12, old_esp + mov %eax, old_eax + mov %esp, %eax + mov exception_stack_end, %esp + + /* + * Push values onto the top of the exception stack to form an + * exception state structure. + */ + pushl vector + pushl error_code + pushl %gs + pushl %fs + pushl %es + pushl %ds + pushl %ss + pushl 4(%eax) + pushl 8(%eax) + pushl (%eax) + pushl %edi + pushl %esi + pushl %ebp + pushl old_esp + pushl %ebx + pushl %edx + pushl %ecx + pushl old_eax + + /* + * Call the C exception handler. It will find the exception state on + * the exception stack. Not passing parameters means we don't have to + * worry about what ABI is being used. + */ + call exception_handler + + /* + * Restore state from the exception state structure, including any + * changes that might have been made. + */ + popl old_eax + popl %ecx + popl %edx + popl %ebx + popl old_esp + + mov old_esp, %eax + subl $12, %eax + + popl %ebp + popl %esi + popl %edi + popl (%eax) + popl 8(%eax) + popl 4(%eax) + popl %ss + popl %ds + popl %es + popl %fs + popl %gs + + mov %eax, %esp + mov old_eax, %eax + + /* Return from the exception. */ + iretl + +/* + * We need segment selectors for the IDT, so we need to know where things are + * in the GDT. We set one up here which is pretty standard and largely copied + * from coreboot. + */ + .align 8 +gdt: + /* selgdt 0, unused */ + .word 0x0000, 0x0000 + .byte 0x00, 0x00, 0x00, 0x00 + + /* selgdt 8, unused */ + .word 0x0000, 0x0000 + .byte 0x00, 0x00, 0x00, 0x00 + + /* selgdt 0x10, flat 4GB code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 + + /* selgdt 0x18, flat 4GB data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 +gdt_end: + +/* GDT pointer for use with lgdt */ +gdt_ptr: + .word gdt_end - gdt - 1 + .long gdt + + /* + * Record the target and construct the actual entry at init time. This + * is necessary because the linker doesn't want to construct the entry + * for us. + */ + .macro interrupt_gate target + .long \target + .long \target + .endm + + .align 8 + .global idt +idt: + interrupt_gate exception_stub_0 + interrupt_gate exception_stub_1 + interrupt_gate exception_stub_2 + interrupt_gate exception_stub_3 + interrupt_gate exception_stub_4 + interrupt_gate exception_stub_5 + interrupt_gate exception_stub_6 + interrupt_gate exception_stub_7 + interrupt_gate exception_stub_8 + interrupt_gate exception_stub_9 + interrupt_gate exception_stub_10 + interrupt_gate exception_stub_11 + interrupt_gate exception_stub_12 + interrupt_gate exception_stub_13 + interrupt_gate exception_stub_14 + interrupt_gate exception_stub_15 + interrupt_gate exception_stub_16 + interrupt_gate exception_stub_17 + interrupt_gate exception_stub_18 + interrupt_gate exception_stub_19 + interrupt_gate exception_stub_20 + interrupt_gate exception_stub_21 + interrupt_gate exception_stub_22 + interrupt_gate exception_stub_23 + interrupt_gate exception_stub_24 + interrupt_gate exception_stub_25 + interrupt_gate exception_stub_26 + interrupt_gate exception_stub_27 + interrupt_gate exception_stub_28 + interrupt_gate exception_stub_29 + interrupt_gate exception_stub_30 + interrupt_gate exception_stub_31 +idt_end: + +/* IDT pointer for use with lidt */ +idt_ptr: + .word idt_end - idt - 1 + .long idt + + .global exception_init_asm +exception_init_asm: + /* Save eax so we can use it as a temporary variable. */ + pushl %eax + + /* Install the GDT. */ + lgdt gdt_ptr + /* Load the segment registers from it. */ + ljmp $0x10, $1f +1: movl $0x18, %eax + movl %eax, %ds + movl %eax, %es + movl %eax, %ss + movl %eax, %fs + movl %eax, %gs + + /* + * Loop over the entries which start out as two copies of the target + * address. We can turn them into real interrupt gates by selectively + * replacing certain bit fields. + */ + movl $idt, %eax +1: + andl $0x0000ffff, (%eax) + orl $0x00100000, (%eax) + andl $0xffff0000, 4(%eax) + orl $0x0000ee00, 4(%eax) + addl $8, %eax + cmp $idt_end, %eax + jne 1b + + /* Install the IDT. */ + lidt idt_ptr + + /* Restore eax and return to the caller. */ + popl %eax + ret diff --git a/payloads/libpayload/arch/x86/main.c b/payloads/libpayload/arch/x86/main.c index c788f0f..ee52a93 100644 --- a/payloads/libpayload/arch/x86/main.c +++ b/payloads/libpayload/arch/x86/main.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <exception.h> #include <libpayload.h> unsigned long loader_eax; /**< The value of EAX passed from the loader */ @@ -54,6 +55,8 @@ void start_main(void) console_init(); #endif + exception_init(); + /* * Any other system init that has to happen before the * user gets control goes here. diff --git a/payloads/libpayload/include/arm/arch/exception.h b/payloads/libpayload/include/arm/arch/exception.h index 57076bd..a0d9413 100644 --- a/payloads/libpayload/include/arm/arch/exception.h +++ b/payloads/libpayload/include/arm/arch/exception.h @@ -30,9 +30,9 @@ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H +#include <exception.h> #include <stdint.h> -void exception_init(void); void set_vbar(uint32_t vbar); #endif diff --git a/payloads/libpayload/include/exception.h b/payloads/libpayload/include/exception.h new file mode 100644 index 0000000..6d118e7 --- /dev/null +++ b/payloads/libpayload/include/exception.h @@ -0,0 +1,37 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _EXCEPTION_H +#define _EXCEPTION_H + +#include <stdint.h> + +void exception_init(void); + +#endif

1 0

New patch to review for coreboot: 9545045 libpayload: Add a timer_us() function.
by Isaac Christensen 13 Sep '14

13 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6897 -gerrit commit 95450457945f3b6713bb6f73353ebda7e7b4fe1d Author: Gabe Black <gabeblack(a)google.com> Date: Fri Dec 6 23:30:10 2013 -0800 libpayload: Add a timer_us() function. This function returns the number of microseconds scaled from the number of raw timer ticks. It accepts a base parameter which is subtracted from the current time, which makes it easy to keep track of relative times. Change-Id: I55f2f9e90c0e12cda430bbe88b044f12b0b563c8 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/179600 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 4dd549e18d170dbf918c5b4b11bbe1f4e99b6695) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/include/libpayload.h | 1 + payloads/libpayload/libc/time.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 48a034b..15ffefb 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -422,6 +422,7 @@ int lib_get_sysinfo(void); unsigned int get_cpu_speed(void); uint64_t timer_hz(void); uint64_t timer_raw_value(void); +uint64_t timer_us(uint64_t base); /* Generic. */ void ndelay(unsigned int n); void udelay(unsigned int n); diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index ec1c85c..0d81634 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -189,3 +189,20 @@ void delay(unsigned int s) { _delay((uint64_t)s * timer_hz()); } + +u64 timer_us(u64 base) +{ + static u64 hz; + + // Only check timer_hz once. Assume it doesn't change. + if (hz == 0) { + hz = timer_hz(); + if (hz < 1000000) { + printf("Timer frequency %lld is too low, " + "must be at least 1MHz.\n", hz); + halt(); + } + } + + return timer_raw_value() / (hz / 1000000) - base; +}

1 0

New patch to review for coreboot: b7d3da7 cbfstool: add aarch64 as a name
by Isaac Christensen 13 Sep '14

13 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6896 -gerrit commit b7d3da7278655ae46f65e16420f035f86f09dd3c Author: Ronald G. Minnich <rminnich(a)google.com> Date: Tue Nov 12 09:03:33 2013 -0800 cbfstool: add aarch64 as a name The aarch64 is not really an arm variant, it's sufficiently different that it can be considered (for purposes of cbfs, certainly) to be a new architecture. Add a constant in cbfs.h and strings to correspond to it. Note that with the new cbfstool support that we added earlier, the actual use of aarch64 ELF files actually "just works" (at least when tested earlier). Change-Id: Ib4900900d99c9aae6eef858d8ee097709368c4d4 Reviewed-on: https://chromium-review.googlesource.com/180221 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Ronald Minnich <rminnich(a)chromium.org> Tested-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit f836e14695827b2667804bc1058e08ec7b297921) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- util/cbfstool/cbfs.h | 1 + util/cbfstool/cbfstool.c | 2 +- util/cbfstool/common.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 6a54bc8..348a4da 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -52,6 +52,7 @@ struct cbfs_header { #define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF #define CBFS_ARCHITECTURE_X86 0x00000001 #define CBFS_ARCHITECTURE_ARM 0x00000010 +#define CBFS_ARCHITECTURE_AARCH64 0x0000aa64 #define CBFS_FILE_MAGIC "LARCHIVE" diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 937b610..5281ebc 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -586,7 +586,7 @@ static void usage(char *name) "Updates the FIT table with microcode entries\n" "\n" "ARCHes:\n" - " arm, x86\n" + " aarch64, arm, x86\n" "TYPEs:\n", name, name ); print_supported_filetypes(); diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index a28e741..d05ad0d 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -130,6 +130,7 @@ static struct { uint32_t arch; const char *name; } arch_names[] = { + { CBFS_ARCHITECTURE_AARCH64, "aarch64" }, { CBFS_ARCHITECTURE_ARM, "arm" }, { CBFS_ARCHITECTURE_X86, "x86" }, { CBFS_ARCHITECTURE_UNKNOWN, "unknown" }

1 0

Patch set updated for coreboot: 41d49b7 arm: Move exception_init() close to console_init()
by Isaac Christensen 13 Sep '14

13 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6884 -gerrit commit 41d49b770f8a14b72be7f5610ba8fb65e47f2b5e Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Nov 13 18:22:15 2013 -0800 arm: Move exception_init() close to console_init() This patch adds stub implementations of exception_init() to all archs so that it can be called from src/lib/hardwaremain.c. It also moves/adds all other invocations of exception_init() (which needs to be rerun in every stage) close to console_init(), in the hopes that it will be less likely overlooked when creating future boards. Also added (an ineffective) one to the armv4 bootblock implementations for consistency and in case we want to implement it later. Change-Id: Iecad10172d25f6c1fc54b0fec8165d7ef60e3414 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176764 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 2960623f4a59d841a13793ee906db8d1b1c16c5d) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/arch/arm/armv4/bootblock_simple.c | 5 +++- src/arch/arm/armv7/Makefile.inc | 2 ++ src/arch/arm/armv7/bootblock_simple.c | 2 ++ src/arch/arm/include/arch/exception.h | 38 ----------------------------- src/arch/arm/include/armv4/arch/exception.h | 35 ++++++++++++++++++++++++++ src/arch/arm/include/armv7/arch/exception.h | 38 +++++++++++++++++++++++++++++ src/arch/x86/include/arch/exception.h | 35 ++++++++++++++++++++++++++ src/lib/hardwaremain.c | 2 ++ src/mainboard/google/nyan/romstage.c | 3 +-- src/mainboard/google/pit/mainboard.c | 5 ---- src/mainboard/google/pit/romstage.c | 2 ++ src/mainboard/google/snow/mainboard.c | 5 ---- src/mainboard/google/snow/romstage.c | 2 ++ src/soc/nvidia/tegra124/bootblock.c | 5 +++- 14 files changed, 127 insertions(+), 52 deletions(-) diff --git a/src/arch/arm/armv4/bootblock_simple.c b/src/arch/arm/armv4/bootblock_simple.c index 9917dbb..80401b3 100644 --- a/src/arch/arm/armv4/bootblock_simple.c +++ b/src/arch/arm/armv4/bootblock_simple.c @@ -19,6 +19,7 @@ * MA 02110-1301 USA */ +#include <arch/exception.h> #include <arch/hlt.h> #include <arch/stages.h> #include <bootblock_common.h> @@ -33,8 +34,10 @@ void main(void) bootblock_cpu_init(); bootblock_mainboard_init(); - if (CONFIG_BOOTBLOCK_CONSOLE) + if (CONFIG_BOOTBLOCK_CONSOLE) { console_init(); + exception_init(); + } entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 2eb1af0..2cc42bb 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -34,6 +34,8 @@ bootblock-$(CONFIG_BOOTBLOCK_SIMPLE) += bootblock_simple.c endif bootblock-y += cache.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception_asm.S bootblock-y += mmu.c CFLAGS_bootblock += $(armv7_flags) diff --git a/src/arch/arm/armv7/bootblock_simple.c b/src/arch/arm/armv7/bootblock_simple.c index f447034..5cd5970 100644 --- a/src/arch/arm/armv7/bootblock_simple.c +++ b/src/arch/arm/armv7/bootblock_simple.c @@ -20,6 +20,7 @@ */ #include <arch/cache.h> +#include <arch/exception.h> #include <arch/hlt.h> #include <arch/stages.h> #include <bootblock_common.h> @@ -54,6 +55,7 @@ void main(void) #if CONFIG_BOOTBLOCK_CONSOLE console_init(); + exception_init(); #endif entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); diff --git a/src/arch/arm/include/arch/exception.h b/src/arch/arm/include/arch/exception.h deleted file mode 100644 index 57076bd..0000000 --- a/src/arch/arm/include/arch/exception.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _ARCH_EXCEPTION_H -#define _ARCH_EXCEPTION_H - -#include <stdint.h> - -void exception_init(void); -void set_vbar(uint32_t vbar); - -#endif diff --git a/src/arch/arm/include/armv4/arch/exception.h b/src/arch/arm/include/armv4/arch/exception.h new file mode 100644 index 0000000..a426c52 --- /dev/null +++ b/src/arch/arm/include/armv4/arch/exception.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_EXCEPTION_H +#define _ARCH_EXCEPTION_H + +static void exception_init(void) { /* not implemented */ } + +#endif diff --git a/src/arch/arm/include/armv7/arch/exception.h b/src/arch/arm/include/armv7/arch/exception.h new file mode 100644 index 0000000..57076bd --- /dev/null +++ b/src/arch/arm/include/armv7/arch/exception.h @@ -0,0 +1,38 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_EXCEPTION_H +#define _ARCH_EXCEPTION_H + +#include <stdint.h> + +void exception_init(void); +void set_vbar(uint32_t vbar); + +#endif diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h new file mode 100644 index 0000000..a426c52 --- /dev/null +++ b/src/arch/x86/include/arch/exception.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_EXCEPTION_H +#define _ARCH_EXCEPTION_H + +static void exception_init(void) { /* not implemented */ } + +#endif diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 277d9b7..9038f57 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -22,6 +22,7 @@ * C Bootstrap code for the coreboot */ +#include <arch/exception.h> #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> @@ -469,6 +470,7 @@ void main(void) acpi_is_wakeup(); #endif + exception_init(); threads_initialize(); /* Schedule the static boot state entries. */ diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index e789556..ea40388 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -95,6 +95,7 @@ void main(void) configure_l2actlr(); console_init(); + exception_init(); mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); @@ -106,8 +107,6 @@ void main(void) dcache_invalidate_all(); dcache_mmu_enable(); - exception_init(); - /* For quality of the user experience, it's important to get * the video going ASAP. Because there are long delays in some * of the powerup steps, we do some very early setup here in diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index c0650d8..c07db7b 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -27,7 +27,6 @@ #include <vbe.h> #include <boot/coreboot_tables.h> #include <arch/cache.h> -#include <arch/exception.h> #include <soc/samsung/exynos5420/tmu.h> #include <soc/samsung/exynos5420/clk.h> #include <soc/samsung/exynos5420/cpu.h> @@ -472,10 +471,6 @@ static void mainboard_enable(device_t dev) mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); tlb_invalidate_all(); - /* this is going to move, but we must have it now and we're - * not sure where */ - exception_init(); - const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; const unsigned lr_frame_size = 256; diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 1393ba8..16dc997 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -25,6 +25,7 @@ #include <cbmem.h> #include <arch/cache.h> +#include <arch/exception.h> #include <soc/samsung/exynos5420/i2c.h> #include <soc/samsung/exynos5420/clk.h> #include <soc/samsung/exynos5420/cpu.h> @@ -242,6 +243,7 @@ void main(void) exynos_pinmux_uart3(); console_init(); + exception_init(); if (power_init_failed) die("Failed to intialize power.\n"); diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 99a4e30..0b6cf4a 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -27,7 +27,6 @@ #include <vbe.h> #include <boot/coreboot_tables.h> #include <arch/cache.h> -#include <arch/exception.h> #include <soc/samsung/exynos5250/tmu.h> #include <soc/samsung/exynos5250/clk.h> #include <soc/samsung/exynos5250/gpio.h> @@ -338,10 +337,6 @@ static void mainboard_enable(device_t dev) dcache_invalidate_all(); dcache_mmu_enable(); - /* this is going to move, but we must have it now and we're - * not sure where */ - exception_init(); - const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; const unsigned lr_frame_size = 256; diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index ac469ba..9b35c4a 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include <arch/cache.h> +#include <arch/exception.h> #include <soc/samsung/exynos5250/i2c.h> #include <soc/samsung/exynos5250/clk.h> #include <soc/samsung/exynos5250/cpu.h> @@ -151,6 +152,7 @@ void main(void) mem = setup_clock(); console_init(); + exception_init(); setup_power(is_resume); setup_memory(mem, is_resume); diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index dbdcfa5..0e10a2b 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/exception.h> #include <arch/hlt.h> #include <bootblock_common.h> #include <cbfs.h> @@ -47,8 +48,10 @@ void main(void) pinmux_set_config(PINMUX_UART2_RTS_N_INDEX, PINMUX_UART2_RTS_N_FUNC_UB3); - if (CONFIG_BOOTBLOCK_CONSOLE) + if (CONFIG_BOOTBLOCK_CONSOLE) { console_init(); + exception_init(); + } clock_init();

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Patch merged into coreboot/master: 813f305 arm: Put exception_stack into BSS
by gerrit＠coreboot.org 13 Sep '14

13 Sep '14

the following patch was just integrated into master: commit 813f305e26755aba6826c0f5baf60a65cafbefd6 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Nov 13 12:49:45 2013 -0800 arm: Put exception_stack into BSS "Hey guys, I have this awesome idea! How about we put a huge array filled with 0xa5 into the data segment of our uncompressed romstage for no particular reason? Give our SPI driver something to do so it doesn't get too bored, you know?" Guess it pays off to just hexdump our image and sanity-check it top to bottom every once in a while... Also reduces the size because 8K is crazy just to print a bunch of registers (256 bytes ought to be enough for anybody). Old-Change-Id: Icec0a711a1b5140d2ebcd98338ec638a4b6262fa Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176762 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 61c360a1c3f445535c9ff383a389e643cfe4527c) arm: Remove exception_test() The exception_test() mechanism might have been useful when exceptions were first implemented, but now that they are pretty stable it's really not necessary anymore (especially not on every single boot in production Chromebooks). It forces a simple unaligned access, and as we start having exceptions in stages that might not have paging turned on yet, it's better to remove that completely. Also removed the duplicated implementations of SCTLR-stuff and switched to the existing ones in cache.h. Old-Change-Id: I85e66269f5e2f2dfd3e8aaaa18441493514b62f8 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177101 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit d0706b848572fbea26e0e432ec5827503b9603c9) Squashed 2 exception related commits. Change-Id: Id2c115ee39a0732c375472afc0194436e2f5e069 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/6885 for details. -gerrit

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Patch merged into coreboot/master: edf6b57 tegra124/nyan: display, clock, and other updates
by gerrit＠coreboot.org 13 Sep '14

13 Sep '14

the following patch was just integrated into master: commit edf6b57f73e3cafaecd67a71fdf7313e75c1b3e8 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Oct 25 17:49:26 2013 -0700 tegra124/nyan: display, clock, and other updates tegra124: Set Tx FIFO threshold value to recommended setting Reviewed-on: https://chromium-review.googlesource.com/175200 (cherry picked from commit c8f086711c6ae2db70fc8e0d84b54f5952fbe0ad) tegra124: add CLK_X definitions Reviewed-on: https://chromium-review.googlesource.com/175220 (cherry picked from commit 3f8a844bd2f151e06d82d1a7fac4492c6bc9417d) tegra124: fix incorrect struct member in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/175270 (cherry picked from commit 967193d5984a086c297988caa580b61cb4d0414c) tegra124: add the _x clocks to clock_enable_clear_reset Reviewed-on: https://chromium-review.googlesource.com/175539 (cherry picked from commit df4c515d73b02061e5c98f51efd50e04b10d63f5) tegra124: add clock support code for graphics. Reviewed-on: https://chromium-review.googlesource.com/175162 (cherry picked from commit b8eb6ab4cdc5a583636c10fa05f947a244f94819) tegra124: Clean up some #defines for DMA Reviewed-on: https://chromium-review.googlesource.com/175631 (cherry picked from commit 1a0a900f2d060916c9878781b82113b16a7945d9) tegra124: enable flow control for APBDMA in SPI driver Reviewed-on: https://chromium-review.googlesource.com/175630 (cherry picked from commit 873e6f9e95f6cb0162fa06216682fbc71ab0202d) nyan: move clock setup for the display out of dca_init Reviewed-on: https://chromium-review.googlesource.com/175656 (cherry picked from commit 32dd9947a60298ff9488c911629802c257ed6afc) tegra124: more display PLL setup and clock hardcode removal. Reviewed-on: https://chromium-review.googlesource.com/175732 (cherry picked from commit 80402876b5daa9e9389fd4fab5f539d89c37fa7f) tegra124: move dp.c from tegra to tegra124 Reviewed-on: https://chromium-review.googlesource.com/175830 (cherry picked from commit e98be569b0ba7f4d565ce677343a317db08344e0) tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb Reviewed-on: https://chromium-review.googlesource.com/175889 (cherry picked from commit 4e513196b0014c5a82079f3aa87c2efbeb645484) tegra: get rid of struct members that are not used Reviewed-on: https://chromium-review.googlesource.com/176023 (cherry picked from commit 032b8a0c9fe0152ebc27344e93128865ecb918a6) tegra124: Increase SCLK (AVP) to 300MHz Reviewed-on: https://chromium-review.googlesource.com/175489 (cherry picked from commit 7e082f2c2f030950d652f1f87f637e15dee38552) tegra124: Address old main CPU starting review feedback. Reviewed-on: https://chromium-review.googlesource.com/175933 (cherry picked from commit 1d76ac71bd839dff9198e65132ec25212dd55ffd) tegra124: Revise clock source configuration for irregular peripherals. Reviewed-on: https://chromium-review.googlesource.com/176109 (cherry picked from commit 1021c215190602a2b8c1ab97d6c8313d89597d99) nyan: add timestamps in romstage Reviewed-on: https://chromium-review.googlesource.com/176172 (cherry picked from commit cd626aa10b56cd4da6ebda36fe487e44b08f3935) tegra124: Allow enabling clock output for external peripherals. Reviewed-on: https://chromium-review.googlesource.com/176108 (cherry picked from commit ea9fb6393ee80da77c9fbc30f605859c7009c9ed) nyan: Enable and configure clocks for I2S and audio codec. Reviewed-on: https://chromium-review.googlesource.com/176104 (cherry picked from commit 1fb659b3e73285ff8218c0f229734edd3b979ca4) tegra124: Fix typo in pinmux name. Reviewed-on: https://chromium-review.googlesource.com/176215 (cherry picked from commit c7915ad41a3f1d1452aa6d6d287aaa8eb9e85c34) nyan: Add pinmux settings for audio peripherals. Reviewed-on: https://chromium-review.googlesource.com/176212 (cherry picked from commit 37412f3201590e47a06d4678fa833164d370b41c) nyan: De-array-ify the PMIC setup code. Reviewed-on: https://chromium-review.googlesource.com/176903 (cherry picked from commit 86ab1ce9fbf6d5362af1ee37de1394412366f247) nyan: Add a kconfig for building for the original nyans in pixel cases. Reviewed-on: https://chromium-review.googlesource.com/176904 (cherry picked from commit 1d05fd5bc40d727826510ec81496ce4a49e257ed) nyan: Set the CPU voltage differently depending on which PMIC is in use. Reviewed-on: https://chromium-review.googlesource.com/176905 (cherry picked from commit 31507f6a575220737ee5683b312cd162600f89cc) nyan: Increase the CPU voltage to 1.2V. Reviewed-on: https://chromium-review.googlesource.com/176906 (cherry picked from commit fe4795e66b515c2523df09a8800ecac9a3f63557) tegra124: Flesh out/tidy up the flow controller constants. Reviewed-on: https://chromium-review.googlesource.com/177085 (cherry picked from commit b50d315506a5ab9c81b6bbaf8cf580dbb3e78794) tegra124: When leaving the bootblock/AVP, really stop the AVP. Reviewed-on: https://chromium-review.googlesource.com/177086 (cherry picked from commit 06c10df889d4d935bc99792df860d93766ae44dd) nyan: Set SPI4 speed to 33MHz Reviewed-on: https://chromium-review.googlesource.com/177038 (cherry picked from commit c98de65482fabdb5c76944fe3bf762191b3a0a55) nyan: Do console_init() in romstage Reviewed-on: https://chromium-review.googlesource.com/176763 (cherry picked from commit 0bec32e09eab28bc5ea49b7896a8b6f489143b03) nyan: Add a prompt to the CONFIG_NYAN_IN_A_PIXEL option. Reviewed-on: https://chromium-review.googlesource.com/177486 (cherry picked from commit 7cbb801d000dac4b39f76266ebef2585fe48faba) nyan: Separate the SDRAM BCT config for the two nyans, and turn down norrin. Reviewed-on: https://chromium-review.googlesource.com/177487 (cherry picked from commit 6b119685f6626d79d924af9f856ebb90af45a73f) tegra124: Bump up HCLK and PCLK Reviewed-on: https://chromium-review.googlesource.com/177563 (cherry picked from commit c25337dac8c3ecdd8ffe5b4d11acebb216132405) nyan: Add some code for reading the board ID. Reviewed-on: https://chromium-review.googlesource.com/177488 (cherry picked from commit 5fccbce99e7db312e2e3caf806c438c9b04c0a8f) nyan: Use the board ID to decide how to initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/177489 (cherry picked from commit 677bdb9df55248da3a0c6be0089098f6d6807d3c) nyan: Create kconfig variables for each SDRAM config. Reviewed-on: https://chromium-review.googlesource.com/177580 (cherry picked from commit d7ddcf262a321f06289c4f2b2a6b43982dd96377) tegra124: Mux some unused pins away from UARTA, and pull up the serial RX line. Reviewed-on: https://chromium-review.googlesource.com/177637 (cherry picked from commit bd533cc109b0acf3495b04fa6622e250ba454fe9) tegra124: Initialize the MCR when setting up the UART. Reviewed-on: https://chromium-review.googlesource.com/177638 (cherry picked from commit 38c84786fc3e8fab913aebca176ac7b038cb0be6) tegra124: fix SPI AHB burst length Reviewed-on: https://chromium-review.googlesource.com/177564 (cherry picked from commit f29235263202c9b4a3dbb65da5727c8eefe44315) tegra124: remove unneeded debug print in SPI code Reviewed-on: https://chromium-review.googlesource.com/177833 (cherry picked from commit 34a50040268dbde1c326d315f8042a3905ddfb06) nyan: Set up the SOC and TPM reset pin. Reviewed-on: https://chromium-review.googlesource.com/177965 (cherry picked from commit b81a5bd15a2979ee009b9f7bc4a39a304e6a759a) tegra124: Allow some time for packets to appear in Rx FIFO Reviewed-on: https://chromium-review.googlesource.com/177832 (cherry picked from commit 8f70a25b1eea865a448525749ac18393f5b9ad84) nyan: PMIC: Slam default init values for SDOs/LDOs in AS3722 Reviewed-on: https://chromium-review.googlesource.com/178226 (cherry picked from commit c536b0d82fd6fffbc0e2448e0d19d3f06df5d86a) nyan: change devicetree for the new display settings. Reviewed-on: https://chromium-review.googlesource.com/177958 (cherry picked from commit 43abed730f222c8a685c250a58c981268994a65d) nyan: Switch USB VBUS GPIOs from outputs to pulled-up inputs Reviewed-on: https://chromium-review.googlesource.com/178914 (cherry picked from commit e47b6a609b9d23694a466b56960d9d14ca5d6242) Tegra124: nyan: Disable VPR Reviewed-on: https://chromium-review.googlesource.com/179327 (cherry picked from commit 441aa276446141f1b92ed8fb98c9578597487f4d) tegra124: norrin: fix display issue Reviewed-on: https://chromium-review.googlesource.com/179745 (cherry picked from commit c1c1ae69f6058ed901f532e2c532d1e6ba1f81fb) tegra124: Add iRAM layout information. Reviewed-on: https://chromium-review.googlesource.com/179814 (cherry picked from commit d00f135c93a52ad4dced2edecb74e2dfc54bb2fa) tegra124: Run bootblock and ROM stage out of DRAM. Reviewed-on: https://chromium-review.googlesource.com/179822 (cherry picked from commit 2d3ec06ec39a489d02e798bb22bce4d7465b20ce) nyan: clean up a comment regarding video Reviewed-on: https://chromium-review.googlesource.com/180161 (cherry picked from commit 03b5e88a66b9c96df2ef3d9ce5ba4a62a8bb2447) tegra124: norrin: the first step to clean up display code Reviewed-on: https://chromium-review.googlesource.com/180135 (cherry picked from commit 9d0c12dfef28a1161604df9b3fcc113049b2747d) Squashed 49 commits for tegra124/nyan. Change-Id: Id67bfee725e703d3e2d8ac17f40844dc193e901d Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/6883 for details. -gerrit

1 0

Patch set updated for coreboot: faffc03 intelgfx: consolidate vbt code
by Vladimir Serbinenko 13 Sep '14

13 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6800 -gerrit commit faffc03834ee6c18a2adba8b892f9b32b072eafa Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Aug 30 00:35:39 2014 +0200 intelgfx: consolidate vbt code Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/Makefile.inc | 2 +- src/drivers/intel/gma/i915.h | 19 ++++ src/drivers/intel/gma/intel_bios.h | 52 +++++++++ src/drivers/intel/gma/vbt.c | 110 ++++++++++++++++++ src/include/smbios.h | 1 + src/mainboard/google/link/i915.c | 4 +- src/mainboard/google/link/i915io.c | 1 + src/mainboard/lenovo/x200/devicetree.cb | 8 +- src/mainboard/lenovo/x201/devicetree.cb | 8 +- src/mainboard/lenovo/x220/devicetree.cb | 8 +- src/mainboard/lenovo/x230/devicetree.cb | 8 +- src/mainboard/packardbell/ms2290/devicetree.cb | 8 +- src/northbridge/intel/gm45/chip.h | 7 +- src/northbridge/intel/gm45/gma.c | 126 +++------------------ src/northbridge/intel/nehalem/acpi.c | 1 + src/northbridge/intel/nehalem/chip.h | 7 +- src/northbridge/intel/nehalem/gma.c | 102 +++-------------- src/northbridge/intel/nehalem/gma.h | 52 --------- src/northbridge/intel/sandybridge/acpi.c | 1 + src/northbridge/intel/sandybridge/chip.h | 7 +- src/northbridge/intel/sandybridge/gma.c | 8 +- src/northbridge/intel/sandybridge/gma.h | 56 +-------- .../intel/sandybridge/gma_ivybridge_lvds.c | 110 +++--------------- .../intel/sandybridge/gma_sandybridge_lvds.c | 108 +++--------------- 24 files changed, 284 insertions(+), 530 deletions(-) diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index b19334e..d963df9 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -19,7 +19,7 @@ ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c display.c ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c -ramstage-$(CONFIG_INTEL_EDID) += edid.c +ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c ifeq ($(CONFIG_VGA_ROM_RUN),y) ramstage-$(CONFIG_INTEL_INT15) += int15.c endif diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index bc43fc5..0d5b8af 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef INTEL_I915_H +#define INTEL_I915_H 1 + #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/drm_dp_helper.h> #include <edid.h> @@ -282,6 +285,14 @@ int gtt_poll(u32 reg, u32 mask, u32 value); void gtt_write(u32 reg, u32 data); u32 gtt_read(u32 reg); +struct i915_gpu_controller_info +{ + int use_spread_spectrum_clock; + int lvds_dual_channel; + int link_frequency_270_mhz; + int lvds_num_lanes; +}; + int i915lightup(unsigned int physbase, unsigned int mmio, unsigned int gfx, unsigned int init_fb); int panel_lightup(struct intel_dp *dp, unsigned int init_fb); @@ -289,3 +300,11 @@ void *igd_make_opregion(void); /* display.c */ void compute_display_params(struct intel_dp *dp); + +/* vbt.c */ +struct device; +void +generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, + struct device *dev, const char *idstr); + +#endif diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h index 36426d8..7b5edd3 100644 --- a/src/drivers/intel/gma/intel_bios.h +++ b/src/drivers/intel/gma/intel_bios.h @@ -730,4 +730,56 @@ struct bdb_mipi { u32 clk_lane_switch_cnt; } __attribute__((packed)); +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + #endif /* _I830_BIOS_H_ */ diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c new file mode 100644 index 0000000..1cc4e93 --- /dev/null +++ b/src/drivers/intel/gma/vbt.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013, 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <string.h> +#include <device/pci_rom.h> + +#include "i915.h" +#include "intel_bios.h" + +static size_t generate_vbt(const struct i915_gpu_controller_info *conf, + void *vbt, const char *idstr) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset (head, 0, sizeof (*head)); + + memcpy (head->signature, idstr, 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset (bdb_head, 0, sizeof (*bdb_head)); + memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset (genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} + +void +generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, + struct device *dev, const char *idstr) +{ + optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; + optionrom_pcir_t *pcir; + size_t vbt_size; + size_t fake_oprom_size; + + memset(oh, 0, 8192); + + oh->signature = PCI_ROM_HDR; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->indicator = 0x80; + + vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80), idstr); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; + +} diff --git a/src/include/smbios.h b/src/include/smbios.h index cf9df1a..9060906 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -19,6 +19,7 @@ const char *smbios_mainboard_serial_number(void); const char *smbios_mainboard_version(void); void smbios_mainboard_set_uuid(u8 *uuid); const char *smbios_mainboard_bios_version(void); +u8 smbios_mainboard_enclosure_type(void); #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index c24c4bd..383c891 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -236,8 +236,8 @@ static int run(int index) return i+1; } -int i915lightup(const struct northbridge_intel_sandybridge_config *info, - u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) { static struct edid edid; int edid_ok; diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c index 4bf0e6f..b66771a 100644 --- a/src/mainboard/google/link/i915io.c +++ b/src/mainboard/google/link/i915io.c @@ -18,6 +18,7 @@ */ #include <stdint.h> +#include <stdlib.h> #include "i915io.h" struct iodef iodefs[] = { diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 285e30f..376273a 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/intel/gm45 - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 21e328a..7592cb0 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -35,10 +35,10 @@ chip northbridge/intel/nehalem register "gpu_panel_power_backlight_off_delay" = "2500" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" chip ec/lenovo/pmh7 device pnp ff.1 on # dummy diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 96bed1e..dc129c0 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 9dc559c..1886ba9 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index a57a2c1..19f6c9c 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -35,10 +35,10 @@ chip northbridge/intel/nehalem register "gpu_panel_power_backlight_off_delay" = "3000" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gpu_use_spread_spectrum_clock" = "0" - register "gpu_lvds_dual_channel" = "1" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "0" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 90a0e1e..a4a7a75 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -21,11 +21,10 @@ #ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H #define NORTHBRIDGE_INTEL_GM45_CHIP_H +#include <drivers/intel/gma/i915.h> + struct northbridge_intel_gm45_config { - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 12a0b4d..74e16ad 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -39,31 +39,6 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - static struct resource *gtt_res = NULL; void gtt_write(u32 reg, u32 data) @@ -144,7 +119,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -197,7 +172,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -267,7 +242,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -279,10 +254,10 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -299,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); mdelay(1); @@ -310,18 +285,18 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PP_CONTROL, @@ -329,7 +304,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -423,7 +398,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -457,54 +432,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, #endif } -static size_t generate_vbt(const struct northbridge_intel_gm45_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset (head, 0, sizeof (*head)); - - memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset (bdb_head, 0, sizeof (*bdb_head)); - memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset (genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - #endif static void gma_func0_init(struct device *dev) @@ -542,34 +469,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - if (read16(PCI_VGA_RAM_IMAGE_START) != PCI_ROM_HDR) { - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - - memset(oh, 0, 8192); - - oh->signature = PCI_ROM_HDR; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; - } + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); #endif /* Post VBIOS init */ diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 9b7357c..6f694e2 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -31,6 +31,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/intel_bios.h> #include <build.h> #include <arch/acpigen.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index e33d108..1a31238 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,8 +41,5 @@ struct northbridge_intel_nehalem_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index a57bf6b..c3e2a49 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -654,7 +654,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -719,7 +719,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -790,7 +790,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -802,10 +802,10 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -822,12 +822,12 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -837,18 +837,18 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -856,7 +856,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -953,7 +953,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -988,53 +988,6 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, #endif } -static size_t generate_vbt(const struct northbridge_intel_nehalem_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} #endif static void gma_func0_init(struct device *dev) @@ -1072,34 +1025,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) { - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; - } + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); #endif diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h index fdea85a..f0e1c53 100644 --- a/src/northbridge/intel/nehalem/gma.h +++ b/src/northbridge/intel/nehalem/gma.h @@ -118,56 +118,4 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - #endif diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 925812a..c77b5cc 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -33,6 +33,7 @@ #include <arch/acpigen.h> #include "sandybridge.h" #include <cbmem.h> +#include <drivers/intel/gma/intel_bios.h> unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index cc32c37..07809f5 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,8 +41,5 @@ struct northbridge_intel_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f305b81..247c723 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -278,12 +278,12 @@ u32 map_oprom_vendev(u32 vendev) static struct resource *gtt_res = NULL; -static inline u32 gtt_read(u32 reg) +u32 gtt_read(u32 reg) { return read32(gtt_res->base + reg); } -static inline void gtt_write(u32 reg, u32 data) +void gtt_write(u32 reg, u32 data) { write32(gtt_res->base + reg, data); } @@ -295,7 +295,7 @@ static inline void gtt_write_powermeter(const struct gt_powermeter *pm) } #define GTT_RETRY 1000 -static int gtt_poll(u32 reg, u32 mask, u32 value) +int gtt_poll(u32 reg, u32 mask, u32 value) { unsigned try = GTT_RETRY; u32 data; @@ -595,7 +595,7 @@ static void gma_func0_init(struct device *dev) physbase = pci_read_config32(dev, 0x5c) & ~0xf; graphics_base = dev->resource_list[1].base; - int lightup_ok = i915lightup_sandy(conf, physbase, iobase, mmiobase, graphics_base); + int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base); if (lightup_ok) gfx_set_init_done(1); #endif diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index b7502cd..3a73e08 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -114,59 +114,7 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - -struct northbridge_intel_sandybridge_config; +struct i915_gpu_controller_info; -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u32 mmio, u32 lfb); diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 53fbfda..e3e1f4b 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -36,54 +36,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void link_train(u32 mmio) { write32(mmio+0xf000c,0x40); @@ -207,8 +159,8 @@ static void enable_port(u32 mmio) read32(mmio + 0xc4000); } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, - u32 physbase, u16 piobase, u32 mmio, u32 lfb) +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; u8 edid_data[128]; @@ -277,7 +229,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 candp1, candn; u32 best_delta = 0xffffffff; - u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + u32 target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); u32 pixel_p1 = 1; u32 pixel_n = 1; @@ -350,7 +302,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, return 0; } - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -359,7 +311,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 1)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -371,10 +323,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -391,12 +343,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -406,10 +358,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); @@ -418,10 +370,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -429,7 +381,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -526,7 +478,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -562,35 +514,9 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); + return 1; } diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 77c5b6f..08cceea 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -26,7 +26,6 @@ #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> -#include <drivers/intel/gma/intel_bios.h> #include "gma.h" #include "chip.h" #include <pc80/vga.h> @@ -36,54 +35,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void train_link(u32 mmio) { /* Clear interrupts. */ @@ -171,7 +122,7 @@ static void power_port(u32 mmio) read32(mmio + 0x000e1180); // = 0x40000002 } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; @@ -187,7 +138,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -252,7 +203,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -323,7 +274,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -335,10 +286,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -355,12 +306,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -371,18 +322,18 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_DPLL_SEL, 8); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -390,7 +341,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -487,7 +438,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -522,35 +473,8 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); return 1; }

1 0

Patch set updated for coreboot: 177c5ba intelgfx: consolidate vbt code
by Vladimir Serbinenko 13 Sep '14

13 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6800 -gerrit commit 177c5ba1310d59475edfc0ef0827b987e853a0f5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Aug 30 00:35:39 2014 +0200 intelgfx: consolidate vbt code Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/Makefile.inc | 2 +- src/drivers/intel/gma/i915.h | 19 ++++ src/drivers/intel/gma/intel_bios.h | 52 +++++++++ src/drivers/intel/gma/vbt.c | 110 ++++++++++++++++++ src/include/smbios.h | 1 + src/mainboard/google/link/i915.c | 4 +- src/mainboard/google/link/i915io.c | 1 + src/mainboard/lenovo/x200/devicetree.cb | 8 +- src/mainboard/lenovo/x201/devicetree.cb | 8 +- src/mainboard/lenovo/x220/devicetree.cb | 8 +- src/mainboard/lenovo/x220/mainboard.c | 1 + src/mainboard/lenovo/x230/devicetree.cb | 8 +- src/mainboard/packardbell/ms2290/devicetree.cb | 8 +- src/northbridge/intel/gm45/chip.h | 7 +- src/northbridge/intel/gm45/gma.c | 126 +++------------------ src/northbridge/intel/nehalem/acpi.c | 1 + src/northbridge/intel/nehalem/chip.h | 7 +- src/northbridge/intel/nehalem/gma.c | 102 +++-------------- src/northbridge/intel/nehalem/gma.h | 52 --------- src/northbridge/intel/sandybridge/acpi.c | 1 + src/northbridge/intel/sandybridge/chip.h | 7 +- src/northbridge/intel/sandybridge/gma.c | 8 +- src/northbridge/intel/sandybridge/gma.h | 56 +-------- .../intel/sandybridge/gma_ivybridge_lvds.c | 110 +++--------------- .../intel/sandybridge/gma_sandybridge_lvds.c | 108 +++--------------- 25 files changed, 285 insertions(+), 530 deletions(-) diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index b19334e..d963df9 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -19,7 +19,7 @@ ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c display.c ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c -ramstage-$(CONFIG_INTEL_EDID) += edid.c +ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c ifeq ($(CONFIG_VGA_ROM_RUN),y) ramstage-$(CONFIG_INTEL_INT15) += int15.c endif diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index bc43fc5..0d5b8af 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef INTEL_I915_H +#define INTEL_I915_H 1 + #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/drm_dp_helper.h> #include <edid.h> @@ -282,6 +285,14 @@ int gtt_poll(u32 reg, u32 mask, u32 value); void gtt_write(u32 reg, u32 data); u32 gtt_read(u32 reg); +struct i915_gpu_controller_info +{ + int use_spread_spectrum_clock; + int lvds_dual_channel; + int link_frequency_270_mhz; + int lvds_num_lanes; +}; + int i915lightup(unsigned int physbase, unsigned int mmio, unsigned int gfx, unsigned int init_fb); int panel_lightup(struct intel_dp *dp, unsigned int init_fb); @@ -289,3 +300,11 @@ void *igd_make_opregion(void); /* display.c */ void compute_display_params(struct intel_dp *dp); + +/* vbt.c */ +struct device; +void +generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, + struct device *dev, const char *idstr); + +#endif diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h index 36426d8..7b5edd3 100644 --- a/src/drivers/intel/gma/intel_bios.h +++ b/src/drivers/intel/gma/intel_bios.h @@ -730,4 +730,56 @@ struct bdb_mipi { u32 clk_lane_switch_cnt; } __attribute__((packed)); +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + #endif /* _I830_BIOS_H_ */ diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c new file mode 100644 index 0000000..1cc4e93 --- /dev/null +++ b/src/drivers/intel/gma/vbt.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013, 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <string.h> +#include <device/pci_rom.h> + +#include "i915.h" +#include "intel_bios.h" + +static size_t generate_vbt(const struct i915_gpu_controller_info *conf, + void *vbt, const char *idstr) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset (head, 0, sizeof (*head)); + + memcpy (head->signature, idstr, 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset (bdb_head, 0, sizeof (*bdb_head)); + memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset (genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} + +void +generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, + struct device *dev, const char *idstr) +{ + optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; + optionrom_pcir_t *pcir; + size_t vbt_size; + size_t fake_oprom_size; + + memset(oh, 0, 8192); + + oh->signature = PCI_ROM_HDR; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->indicator = 0x80; + + vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80), idstr); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; + +} diff --git a/src/include/smbios.h b/src/include/smbios.h index cf9df1a..9060906 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -19,6 +19,7 @@ const char *smbios_mainboard_serial_number(void); const char *smbios_mainboard_version(void); void smbios_mainboard_set_uuid(u8 *uuid); const char *smbios_mainboard_bios_version(void); +u8 smbios_mainboard_enclosure_type(void); #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index c24c4bd..383c891 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -236,8 +236,8 @@ static int run(int index) return i+1; } -int i915lightup(const struct northbridge_intel_sandybridge_config *info, - u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) { static struct edid edid; int edid_ok; diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c index 4bf0e6f..b66771a 100644 --- a/src/mainboard/google/link/i915io.c +++ b/src/mainboard/google/link/i915io.c @@ -18,6 +18,7 @@ */ #include <stdint.h> +#include <stdlib.h> #include "i915io.h" struct iodef iodefs[] = { diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 285e30f..376273a 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/intel/gm45 - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 21e328a..7592cb0 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -35,10 +35,10 @@ chip northbridge/intel/nehalem register "gpu_panel_power_backlight_off_delay" = "2500" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" chip ec/lenovo/pmh7 device pnp ff.1 on # dummy diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 96bed1e..dc129c0 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 87fedfe..6b8423c 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -38,6 +38,7 @@ #include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> #include <build.h> +#include <smbios.h> void mainboard_suspend_resume(void) { diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 9dc559c..1886ba9 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms - register "gpu_use_spread_spectrum_clock" = "1" - register "gpu_lvds_dual_channel" = "0" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "0" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index a57a2c1..19f6c9c 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -35,10 +35,10 @@ chip northbridge/intel/nehalem register "gpu_panel_power_backlight_off_delay" = "3000" register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - register "gpu_use_spread_spectrum_clock" = "0" - register "gpu_lvds_dual_channel" = "1" - register "gpu_link_frequency_270_mhz" = "1" - register "gpu_lvds_num_lanes" = "4" + register "gfx.use_spread_spectrum_clock" = "0" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 90a0e1e..a4a7a75 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -21,11 +21,10 @@ #ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H #define NORTHBRIDGE_INTEL_GM45_CHIP_H +#include <drivers/intel/gma/i915.h> + struct northbridge_intel_gm45_config { - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 12a0b4d..74e16ad 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -39,31 +39,6 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - static struct resource *gtt_res = NULL; void gtt_write(u32 reg, u32 data) @@ -144,7 +119,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -197,7 +172,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -267,7 +242,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -279,10 +254,10 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -299,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); mdelay(1); @@ -310,18 +285,18 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PP_CONTROL, @@ -329,7 +304,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -423,7 +398,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); @@ -457,54 +432,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, #endif } -static size_t generate_vbt(const struct northbridge_intel_gm45_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset (head, 0, sizeof (*head)); - - memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset (bdb_head, 0, sizeof (*bdb_head)); - memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset (genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - #endif static void gma_func0_init(struct device *dev) @@ -542,34 +469,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - if (read16(PCI_VGA_RAM_IMAGE_START) != PCI_ROM_HDR) { - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - - memset(oh, 0, 8192); - - oh->signature = PCI_ROM_HDR; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; - } + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); #endif /* Post VBIOS init */ diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 9b7357c..6f694e2 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -31,6 +31,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/intel_bios.h> #include <build.h> #include <arch/acpigen.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index e33d108..1a31238 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,8 +41,5 @@ struct northbridge_intel_nehalem_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index a57bf6b..c3e2a49 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -654,7 +654,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -719,7 +719,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -790,7 +790,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -802,10 +802,10 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -822,12 +822,12 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -837,18 +837,18 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -856,7 +856,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -953,7 +953,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -988,53 +988,6 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, #endif } -static size_t generate_vbt(const struct northbridge_intel_nehalem_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} #endif static void gma_func0_init(struct device *dev) @@ -1072,34 +1025,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) { - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; - } + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); #endif diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h index fdea85a..f0e1c53 100644 --- a/src/northbridge/intel/nehalem/gma.h +++ b/src/northbridge/intel/nehalem/gma.h @@ -118,56 +118,4 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - #endif diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 925812a..c77b5cc 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -33,6 +33,7 @@ #include <arch/acpigen.h> #include "sandybridge.h" #include <cbmem.h> +#include <drivers/intel/gma/intel_bios.h> unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index cc32c37..07809f5 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,8 +41,5 @@ struct northbridge_intel_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ - int gpu_use_spread_spectrum_clock; - int gpu_lvds_dual_channel; - int gpu_link_frequency_270_mhz; - int gpu_lvds_num_lanes; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f305b81..247c723 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -278,12 +278,12 @@ u32 map_oprom_vendev(u32 vendev) static struct resource *gtt_res = NULL; -static inline u32 gtt_read(u32 reg) +u32 gtt_read(u32 reg) { return read32(gtt_res->base + reg); } -static inline void gtt_write(u32 reg, u32 data) +void gtt_write(u32 reg, u32 data) { write32(gtt_res->base + reg, data); } @@ -295,7 +295,7 @@ static inline void gtt_write_powermeter(const struct gt_powermeter *pm) } #define GTT_RETRY 1000 -static int gtt_poll(u32 reg, u32 mask, u32 value) +int gtt_poll(u32 reg, u32 mask, u32 value) { unsigned try = GTT_RETRY; u32 data; @@ -595,7 +595,7 @@ static void gma_func0_init(struct device *dev) physbase = pci_read_config32(dev, 0x5c) & ~0xf; graphics_base = dev->resource_list[1].base; - int lightup_ok = i915lightup_sandy(conf, physbase, iobase, mmiobase, graphics_base); + int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base); if (lightup_ok) gfx_set_init_done(1); #endif diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index b7502cd..3a73e08 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -114,59 +114,7 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -/* Intel Video BIOS (Option ROM) */ -typedef struct { - u16 signature; - u8 size; - u8 reserved[21]; - u16 pcir_offset; - u16 vbt_offset; -} __attribute__((packed)) optionrom_header_t; - -#define OPROM_SIGNATURE 0xaa55 - -typedef struct { - u32 signature; - u16 vendor; - u16 device; - u16 reserved1; - u16 length; - u8 revision; - u8 classcode[3]; - u16 imagelength; - u16 coderevision; - u8 codetype; - u8 indicator; - u16 reserved2; -} __attribute__((packed)) optionrom_pcir_t; - -typedef struct { - u8 hdr_signature[20]; - u16 hdr_version; - u16 hdr_size; - u16 hdr_vbt_size; - u8 hdr_vbt_checksum; - u8 hdr_reserved; - u32 hdr_vbt_datablock; - u32 hdr_aim[4]; - u8 datahdr_signature[16]; - u16 datahdr_version; - u16 datahdr_size; - u16 datahdr_datablocksize; - u8 coreblock_id; - u16 coreblock_size; - u16 coreblock_biossize; - u8 coreblock_biostype; - u8 coreblock_releasestatus; - u8 coreblock_hwsupported; - u8 coreblock_integratedhw; - u8 coreblock_biosbuild[4]; - u8 coreblock_biossignon[155]; -} __attribute__((packed)) optionrom_vbt_t; - -#define VBT_SIGNATURE 0x54425624 - -struct northbridge_intel_sandybridge_config; +struct i915_gpu_controller_info; -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u32 mmio, u32 lfb); diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 53fbfda..e3e1f4b 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -36,54 +36,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void link_train(u32 mmio) { write32(mmio+0xf000c,0x40); @@ -207,8 +159,8 @@ static void enable_port(u32 mmio) read32(mmio + 0xc4000); } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, - u32 physbase, u16 piobase, u32 mmio, u32 lfb) +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; u8 edid_data[128]; @@ -277,7 +229,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 candp1, candn; u32 best_delta = 0xffffffff; - u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + u32 target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); u32 pixel_p1 = 1; u32 pixel_n = 1; @@ -350,7 +302,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, return 0; } - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -359,7 +311,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 1)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -371,10 +323,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -391,12 +343,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -406,10 +358,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, | ((pixel_m1 - 2) << 8) | pixel_m2); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); @@ -418,10 +370,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -429,7 +381,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -526,7 +478,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -562,35 +514,9 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); + return 1; } diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 77c5b6f..08cceea 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -26,7 +26,6 @@ #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> -#include <drivers/intel/gma/intel_bios.h> #include "gma.h" #include "chip.h" #include <pc80/vga.h> @@ -36,54 +35,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void train_link(u32 mmio) { /* Clear interrupts. */ @@ -171,7 +122,7 @@ static void power_port(u32 mmio) read32(mmio + 0x000e1180); // = 0x40000002 } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; @@ -187,7 +138,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -252,7 +203,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -323,7 +274,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -335,10 +286,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -355,12 +306,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -371,18 +322,18 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_DPLL_SEL, 8); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -390,7 +341,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -487,7 +438,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -522,35 +473,8 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); return 1; }

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coreboot-gerrit September 2014