coreboot-gerrit September 2014

coreboot-gerrit@coreboot.org

1 participants
580 discussions

Patch merged into coreboot/master: 1b54cc9 stack check: cosmetics
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit 1b54cc919c362c63630bf134329d7f547ed586fe Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 13 15:41:13 2013 -0800 stack check: cosmetics Print a space after a full stop. Change-Id: Ic7d0522ae35079b64ce61956d06ea59843ef9d80 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/176756 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit c7ff63038b6888b17a96783b1169c5f335022b24) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6878 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/6878 for details. -gerrit

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Patch merged into coreboot/master: 07e6bd2 lenovo/t530: Enable wake on LID and Fn key
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit 07e6bd2a5576aea1479a96b12824a794035e5d0f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Sep 12 04:01:31 2014 +1000 lenovo/t530: Enable wake on LID and Fn key Change-Id: I09a8fe94b33c3cc1da62f7a5a527944638bd6f0c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6877 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/6877 for details. -gerrit

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Patch merged into coreboot/master: 3a677db lenovo/t530: Apply ME workaround for S3 resume
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit 3a677dbd86716ef27ad02daea09f249cd184f293 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Sep 12 03:53:43 2014 +1000 lenovo/t530: Apply ME workaround for S3 resume Upon S3 resume, the machine powers off due to the ME not being awake yet. Change-Id: I0255dd0fa6b4cb3b539e11a69a618c770c44f4b0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6876 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/6876 for details. -gerrit

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Patch merged into coreboot/master: 2fc3b62 tegra124/nyan: various fixes and additions
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit 2fc3b6281f9ac461da7dc5f916cc3e3e51e51ae6 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Oct 21 21:43:03 2013 +0800 tegra124/nyan: various fixes and additions Tegra124: SDMMC: Configure base clock frequency. Reviewed-on: https://chromium-review.googlesource.com/173841 (cherry picked from commit d3157e9a380cfb018cc69a1f23f277c3c5b680a6) Tegra124: SDMMC: Configure pinmux for MMC 3/4. Reviewed-on: https://chromium-review.googlesource.com/174011 (cherry picked from commit 55af9a86a56d6bc0ce9bcff4fd5226a60ae2033b) tegra124: Move DMA-related #defines and definitions to header Reviewed-on: https://chromium-review.googlesource.com/174444 (cherry picked from commit 9d917927a5b7151958289469b9049ac91efa41e3) tegra124: Assign console address for kernel. Reviewed-on: https://chromium-review.googlesource.com/174486 (cherry picked from commit 36e9370f30bd173879958d164156997841ec4e9c) nyan: Fix up the gpio indices in chromeos.c. Reviewed-on: https://chromium-review.googlesource.com/174418 (cherry picked from commit fba4ae1080c19f11abe1205b871ada14db996c61) Nyan: turn on the backlight. Reviewed-on: https://chromium-review.googlesource.com/174533 (cherry picked from commit 12649c9611981dd8d6567ba0238c8b8247c52215) tegra124: Fix the disp1 source field. Reviewed-on: https://chromium-review.googlesource.com/174701 (cherry picked from commit eed380e09075e1eef0bde7d1bb15c4343f30bfe0) nyan: set up the aux channel i2c interface Reviewed-on: https://chromium-review.googlesource.com/174620 (cherry picked from commit ea81cb44a1c11cd78643c69ac818304cd393749e) tegra124: fix typos in the clock code. Reviewed-on: https://chromium-review.googlesource.com/174684 (cherry picked from commit 72365c33693db4eb6e01032938221f592b7e5a02) tegra124: Revamp clock source/divisor configuration Reviewed-on: https://chromium-review.googlesource.com/174804 (cherry picked from commit 3f31a634f69595bcc6a473301d1492c97a767809) tegra: Add gpio_output_open_drain() function Reviewed-on: https://chromium-review.googlesource.com/174650 (cherry picked from commit bc1c28926810e722e9b82339ea0585d083e3fa8c) tegra124: add nvidia-generated files Reviewed-on: https://chromium-review.googlesource.com/174610 (cherry picked from commit 7706f3200f7fc11b7a443f336bff6a37afa94652) nyan: Ignore the dev mode GPIO. Reviewed-on: https://chromium-review.googlesource.com/174837 (cherry picked from commit 9513e608f3063fdb3e9d8bd04e6e5fe35a5bfcee) Tegra124: Add support for the ARM architectural timer. Reviewed-on: https://chromium-review.googlesource.com/174835 (cherry picked from commit 25a91fcf7e79cc450caa59bc6b65f954bb96ac6c) nyan: Initialize the ARM architectural timer in the RAM stage. Reviewed-on: https://chromium-review.googlesource.com/174836 (cherry picked from commit 581f592c12de91c0cf8279ede2850e38dd0cd2e8) tegra124: nyan: Move mainboard level clock stuff into the mainboard source. Reviewed-on: https://chromium-review.googlesource.com/174843 (cherry picked from commit 5ab100b0bad22814261f9b755b59394562c9145a) tegra124: add some explanatory text about U7.1 computations. Reviewed-on: https://chromium-review.googlesource.com/173910 (cherry picked from commit 822cad0ceeceeb5160c8216e05eec13fd04a6413) Set the EC SPI clock source to PLLP and divide down to around 5MHz Reviewed-on: https://chromium-review.googlesource.com/173954 (cherry picked from commit c0e22d76d3887ca1f727443a47db38dec12c0b74) nyan: Move non-essential configuration out of bootblock and into ram stage. Reviewed-on: https://chromium-review.googlesource.com/174844 (cherry picked from commit dad7f68c76f7b83edacd8b22c9dbd3f0ff027397) tegra124: clocks: Save some IOs in clock_enable_clear_reset. Reviewed-on: https://chromium-review.googlesource.com/174845 (cherry picked from commit 81b977a2758d42471667e2cbe31f160dfda5bca4) tegra124: re-write SPI driver w/ full duplex support Reviewed-on: https://chromium-review.googlesource.com/174446 (cherry picked from commit 51c9a34240d6a068780a7d1c27b032b56b2d3e54) tegra124: move SPI-related structures from .c to .h Reviewed-on: https://chromium-review.googlesource.com/174637 (cherry picked from commit 36760a4463c2c33f494ca7ea5a36810fa4502058) tegra124: add frame header info to SPI channel struct Reviewed-on: https://chromium-review.googlesource.com/174638 (cherry picked from commit e24773eb946e2c4cb5e828f055d45d92bd1a4f9f) tegra124: re-factor tegra_spi_init() Reviewed-on: https://chromium-review.googlesource.com/174639 (cherry picked from commit 88354b996459a702c36604f5f92c24e63df8de7e) nyan: Set CrOS EC frame header parameters for SPI Reviewed-on: https://chromium-review.googlesource.com/174710 (cherry picked from commit 29173ba5863eebb2864a8384435cde2f0d5ca233) tegra124: Add Rx frame header support to SPI code Reviewed-on: https://chromium-review.googlesource.com/174711 (cherry picked from commit 1d1630e770804649ef74d31db194d3bde9968832) tegra124: add support for the Serial Output Resource (sor) Reviewed-on: https://chromium-review.googlesource.com/174612 (cherry picked from commit 3eebd10afea4498380582e04560af89126911ed9) nyan: tegra124: Enable I, D and L2 caches in romstage. Reviewed-on: https://chromium-review.googlesource.com/173777 (cherry picked from commit 74512b7ecfbd50f01a25677307084699ee8c6007) tegra and tegra124: Bring up graphics Reviewed-on: https://chromium-review.googlesource.com/174613 (cherry picked from commit 7e944208a176cdac44a31e2a9961c8bd5dc4ece8) nyan: Move the DMA memory region. Reviewed-on: https://chromium-review.googlesource.com/174953 (cherry picked from commit c66e22859252eaebceb07a3118ac61f4cf6289eb) tegra124: Increase CBFS cache buffer size Reviewed-on: https://chromium-review.googlesource.com/174950 (cherry picked from commit 6dbb4e5f0d66c68df45ac73e3f223b856b715026) tegra124: Add USB PLL, PHY and EHCI setup code Reviewed-on: https://chromium-review.googlesource.com/174651 (cherry picked from commit ecd5c398ff6748a7d40089019471357b58d3a6ea) tegra124: add in some undocument clock source and PLL registers Reviewed-on: https://chromium-review.googlesource.com/174948 (cherry picked from commit 73fcc4981da6e4415b514eaafb42bc265ab0cd9a) tegra124: small cleanups of the code Reviewed-on: https://chromium-review.googlesource.com/174995 (cherry picked from commit 7256aba07e9567ef8d73f05e1f80c4d45fd57bda) Squashed 34 commits for tegra124 / nyan support. Change-Id: I050c7ad962e0d24550b0b33c9318e89c80d01f00 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6870 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6870 for details. -gerrit

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Patch merged into coreboot/master: bca446d panther: update chromeos.c
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit bca446d47162233232209b04d1c8f78a01fcd41f Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Thu Sep 11 11:02:29 2014 -0600 panther: update chromeos.c The google mainboards were updated to unconditionally include chromeos.c except for panther. Change-Id: I35bbd56326ee0f94ee542bae28f9c23980e9a9ed Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6874 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/6874 for details. -gerrit

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Patch merged into coreboot/master: 3f0f300 cpu/intel/fsp_model_206ax/model_206ax_init.c: Correct comment
by gerrit＠coreboot.org 12 Sep '14

12 Sep '14

the following patch was just integrated into master: commit 3f0f300bcf16c91c3b7763051be648caf778ec69 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jul 8 23:15:20 2014 +0200 cpu/intel/fsp_model_206ax/model_206ax_init.c: Correct comment Currently there is no way to enable or disable VMX during runtime using CMOS/NVRAM. It is only possible to configure it during build time by setting the Kconfig option `CONFIG_ENABLE_VMX`. So update the comment accordingly. Change-Id: I4e3294cb39a40cf30d294fd566bc97420592262f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6228 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6228 for details. -gerrit

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Patch set updated for coreboot: 1a71894 Kconfig: Allow native vga init to be selectable for SeaBIOS payload
by Edward O'Callaghan 12 Sep '14

12 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6891 -gerrit commit 1a71894622523493f65b60d6d86857243fecc288 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 03:43:49 2014 +1000 Kconfig: Allow native vga init to be selectable for SeaBIOS payload Change-Id: I1508f3d3c56cb9afbf4a23355831549552a62866 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile.inc | 4 ++++ payloads/external/SeaBIOS/Makefile.inc | 4 ++++ src/Kconfig | 16 ++++++++++++++++ src/arch/x86/Makefile.inc | 1 + 4 files changed, 25 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index c41945a..882448f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -532,6 +532,10 @@ ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif +ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + @printf " SeaBIOS Adding generated legacy VGA option rom.\n" + $(CBFSTOOL) $@.tmp add -f $(CONFIG_PAYLOAD_VGABIOS_FILE) -n vgaroms/seavgabios.bin -t raw +endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \ diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 97f9d56..ee83530 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -34,6 +34,10 @@ endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif +ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + echo "CONFIG_VGA_COREBOOT=y" >> seabios/.config + echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config +endif # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ diff --git a/src/Kconfig b/src/Kconfig index 97a4799..835f7e6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -623,6 +623,17 @@ config SEABIOS_THREAD_OPTIONROMS variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option. +config SEABIOS_VGA_COREBOOT + prompt "Provide an option rom that implements legacy VGA BIOS compatibility for coreboot initialized GPUs" if PAYLOAD_SEABIOS + default n + depends on !VGA_BIOS && MAINBOARD_HAS_NATIVE_VGA_INIT + bool + help + Coreboot can initialize the GPU of some mainboards. + + After initializing the GPU, the information about it is passed to the payload. + + choice prompt "GRUB2 version" default GRUB2_MASTER @@ -670,6 +681,11 @@ config PAYLOAD_FILE depends on PAYLOAD_SEABIOS default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +config PAYLOAD_VGABIOS_FILE + string + depends on PAYLOAD_SEABIOS && SEABIOS_VGA_COREBOOT + default "payloads/external/SeaBIOS/seabios/out/vgabios.bin" + config PAYLOAD_FILE depends on PAYLOAD_FILO default "payloads/external/FILO/filo/build/filo.elf" diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 036dc1a..32fc52e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -349,6 +349,7 @@ seabios: CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ + CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ OUT=$(abspath $(obj)) IASL="$(IASL)"

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Patch set updated for coreboot: 77f15ee Kconfig: Allow native vga init to be selectable for SeaBIOS payload
by Edward O'Callaghan 12 Sep '14

12 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6891 -gerrit commit 77f15ee36e45c125cbc1c9ec1417007066537f4d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 03:43:49 2014 +1000 Kconfig: Allow native vga init to be selectable for SeaBIOS payload Change-Id: I1508f3d3c56cb9afbf4a23355831549552a62866 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile.inc | 4 ++++ payloads/external/SeaBIOS/Makefile.inc | 4 ++++ src/Kconfig | 16 ++++++++++++++++ src/arch/x86/Makefile.inc | 1 + 4 files changed, 25 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index c41945a..2e5e786 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -532,6 +532,10 @@ ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif +ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + @printf " SeaBIOS Adding generated legacy VGA option rom.\n" + $(CBFSTOOL) $@.tmp add -f $(PAYLOAD_VGABIOS_FILE) -n vgaroms/seavgabios.bin -t raw +endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \ diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 97f9d56..ee83530 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -34,6 +34,10 @@ endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif +ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + echo "CONFIG_VGA_COREBOOT=y" >> seabios/.config + echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config +endif # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ diff --git a/src/Kconfig b/src/Kconfig index 97a4799..069bf82 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -623,6 +623,17 @@ config SEABIOS_THREAD_OPTIONROMS variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option. +config SEABIOS_VGA_COREBOOT + prompt "Provide an option rom that implements legacy VGA BIOS compatibility for coreboot initialized GPUs" if PAYLOAD_SEABIOS + default n + depends on !CONFIG_VGA_BIOS && CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT + bool + help + Coreboot can initialize the GPU of some mainboards. + + After initializing the GPU, the information about it is passed to the payload. + + choice prompt "GRUB2 version" default GRUB2_MASTER @@ -670,6 +681,11 @@ config PAYLOAD_FILE depends on PAYLOAD_SEABIOS default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +config PAYLOAD_VGABIOS_FILE + string + depends on PAYLOAD_SEABIOS && SEABIOS_VGA_COREBOOT + default "payloads/external/SeaBIOS/seabios/out/vgabios.bin" + config PAYLOAD_FILE depends on PAYLOAD_FILO default "payloads/external/FILO/filo/build/filo.elf" diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 036dc1a..32fc52e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -349,6 +349,7 @@ seabios: CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ + CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ OUT=$(abspath $(obj)) IASL="$(IASL)"

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New patch to review for coreboot: c0d70a9 exynos5250: Fix PMU register address map
by Isaac Christensen 12 Sep '14

12 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6892 -gerrit commit c0d70a9516f751c20ba1200e4a6e38c1298beabb Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Dec 9 15:42:53 2013 -0800 exynos5250: Fix PMU register address map Patch 12b121f3fef61d introduced an off-by-one error in the offsets of the PMU register struct, which put both the newly added register and the PSHOLD that comes after it in the wrong place. This patch corrects the offsets (5420 had already been correct). Change-Id: I1d9d31a6a73ee91890824e94fbd247d5feb4f6ae Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179411 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 5fdc74bc18bcb1066a0ce3ba94829af1b175173b) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/soc/samsung/exynos5250/power.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/samsung/exynos5250/power.h b/src/soc/samsung/exynos5250/power.h index 5ea73c7..aa93893 100644 --- a/src/soc/samsung/exynos5250/power.h +++ b/src/soc/samsung/exynos5250/power.h @@ -58,8 +58,8 @@ struct exynos5_power { uint32_t inform0; /* 0x0800 */ uint32_t inform1; /* 0x0804 */ uint8_t reserved6[0x1f8]; - uint32_t pmu_debug; /* 0x0A00*/ - uint8_t reserved7[0x2728]; + uint32_t pmu_debug; /* 0x0a00 */ + uint8_t reserved7[0x2724]; uint32_t padret_uart_opt; /* 0x3128 */ uint8_t reserved8[0x1e0]; uint32_t ps_hold_ctrl; /* 0x330c */

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Patch set updated for coreboot: dea0ec5 Kconfig: Allow native vga init to be selectable for SeaBIOS payload
by Edward O'Callaghan 12 Sep '14

12 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6891 -gerrit commit dea0ec5cad8af212f8525d499779cf9bfc9ea268 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 03:43:49 2014 +1000 Kconfig: Allow native vga init to be selectable for SeaBIOS payload Change-Id: I1508f3d3c56cb9afbf4a23355831549552a62866 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/external/SeaBIOS/Makefile.inc | 3 +++ src/Kconfig | 11 +++++++++++ src/arch/x86/Makefile.inc | 1 + 3 files changed, 15 insertions(+) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 97f9d56..7fe9751 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -34,6 +34,9 @@ endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif +ifneq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + echo "# CONFIG_VGA_COREBOOT is not set" >> seabios/.config +endif # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ diff --git a/src/Kconfig b/src/Kconfig index 97a4799..aaea0d9 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -623,6 +623,17 @@ config SEABIOS_THREAD_OPTIONROMS variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option. +config SEABIOS_VGA_COREBOOT + prompt "Provide an option rom that implements legacy VGA BIOS compatibility for coreboot initialized GPUs" if PAYLOAD_SEABIOS + default n + depends on !CONFIG_VGA_BIOS && CONFIG_NATIVE_VGA + bool + help + Coreboot can initialize the GPU of some mainboards. + + After initializing the GPU, the information about it is passed to the payload. + + choice prompt "GRUB2 version" default GRUB2_MASTER diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 036dc1a..32fc52e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -349,6 +349,7 @@ seabios: CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ + CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ OUT=$(abspath $(obj)) IASL="$(IASL)"

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coreboot-gerrit September 2014