coreboot-gerrit September 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: d84afd3 arm: Remove CAR_MIGRATE Kconfig and associated cruft
by gerrit＠coreboot.org 15 Sep '14

15 Sep '14

the following patch was just integrated into master: commit d84afd3e61af870e01b5be66530ea5df4469b0c8 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Nov 13 16:06:34 2013 -0800 arm: Remove CAR_MIGRATE Kconfig and associated cruft This is essentially a revert of commit 10bd772d. The CAR_MIGRATE mechanism is only useful to migrate variables from a special region (e.g. cache as RAM) into DRAM-backed CBMEM between different parts of the romstage (it does not persist into ramstage). Since ARM devices use SRAM for which there is no reason to become inaccessible in later parts of the romstage, this mechanism isn't useful for them. Removing it makes the romstage.ld script much simpler, which has the nice side-effect of putting the BSS at the end of the memory image (so that cbfstool can actually figure out that it doesn't need to be part of the ROM image). Old-Change-Id: I50e91d8bd51b5deb19446d9da48699edecbef6ea Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176761 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit ebfd698e57c902e2f39a0cfc1bc2b02665e47ec6) console: Make cbmem depend on x86. The cbmem implementation isn't supported on anything other than x86 right now and actually causes memory corruption on ARM machines. Until that's fixed, this will prevent people from turning it on and causing hard to track down errors. Old-Change-Id: I00e8aacf008acfe2f76d4eab82570f7c1cc89cab Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/191107 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit e54f16e346a7f2c66d802fb78a6b24e53b732b83) Squashed two related commits for cbmem support on arm. Change-Id: I2be48cea348ee5dc8ca3632d743500aa111bab08 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6888 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6888 for details. -gerrit

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Patch merged into coreboot/master: 7c7b5ff libpayload: Add a new "die" function to fatally signal programming errors.
by gerrit＠coreboot.org 15 Sep '14

15 Sep '14

the following patch was just integrated into master: commit 7c7b5ffabbaa55faa17adb18ebbd1de79a9c61eb Author: Gabe Black <gabeblack(a)google.com> Date: Sat Nov 23 00:38:49 2013 -0800 libpayload: Add a new "die" function to fatally signal programming errors. If a programming error is detected, die can be used to print a message and stop execution similar to failing an assert. There's also a "die_if" function which is conditional. die functions, like asserts, should be used to trap programming errors and not when the hardware does something wrong. If all code was written perfectly, no die function would ever be called. In other words, it would be appropriate to use die if a function was called with a value that was out of bounds or if malloc failed. It wouldn't be appropriate if an external device doesn't respond. In the future, the die family of functions might print a stack trace or show other debugging info. Old-Change-Id: I653fc8cb0b4e459522f1b86f7fac280836d57916 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/178000 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 59df109d56a0f5346562de9b3124666a4443adf0) libpayload: Fix the license in some files which were accidentally made GPL. Some files were accidentally made GPL when they were added to libpayload. This change changes them over to a BSD license to be in line with the intended license of libpayload. Old-Change-Id: Ia95ac4951b173dcb93cb489705680e7313df3c92 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/182202 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 5f47600e50e82de226f2fa6ea81d4a3d1c56277b) Squashed the initial patch for "die" functions and a later update to the license header. Change-Id: I3a62cd820e676f4458e61808733d81edd3d76e87 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6889 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/6889 for details. -gerrit

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Patch set updated for coreboot: 69eee96 Kconfig: Allow native vga init to be selectable for SeaBIOS payload
by Edward O'Callaghan 15 Sep '14

15 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6891 -gerrit commit 69eee9697c5965e6395ab3252ab11663fb1db8a1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 03:43:49 2014 +1000 Kconfig: Allow native vga init to be selectable for SeaBIOS payload Change-Id: I1508f3d3c56cb9afbf4a23355831549552a62866 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile.inc | 4 ++++ payloads/external/SeaBIOS/Makefile.inc | 4 ++++ src/Kconfig | 16 ++++++++++++++++ src/arch/x86/Makefile.inc | 1 + 4 files changed, 25 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index c41945a..882448f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -532,6 +532,10 @@ ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif +ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + @printf " SeaBIOS Adding generated legacy VGA option rom.\n" + $(CBFSTOOL) $@.tmp add -f $(CONFIG_PAYLOAD_VGABIOS_FILE) -n vgaroms/seavgabios.bin -t raw +endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \ diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index da454528..0831eea 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -37,6 +37,10 @@ endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif +ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) + echo "CONFIG_VGA_COREBOOT=y" >> seabios/.config + echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config +endif # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ diff --git a/src/Kconfig b/src/Kconfig index 327e1bf..2e01abc 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -636,6 +636,17 @@ config SEABIOS_MALLOC_UPPERMEMORY hardware. In general, if this is desired, the option will be set to 'N' by the chipset Kconfig. +config SEABIOS_VGA_COREBOOT + prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS + default n + depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT + bool + help + Coreboot can initialize the GPU of some mainboards. + + After initializing the GPU, the information about it can be passed to the payload. + Provide an option rom that implements this legacy VGA BIOS compatibility requirement. + choice prompt "GRUB2 version" default GRUB2_MASTER @@ -683,6 +694,11 @@ config PAYLOAD_FILE depends on PAYLOAD_SEABIOS default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +config PAYLOAD_VGABIOS_FILE + string + depends on PAYLOAD_SEABIOS && SEABIOS_VGA_COREBOOT + default "payloads/external/SeaBIOS/seabios/out/vgabios.bin" + config PAYLOAD_FILE depends on PAYLOAD_FILO default "payloads/external/FILO/filo/build/filo.elf" diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index aa058c0..0a7399e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -349,6 +349,7 @@ seabios: CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ + CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \

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Patch set updated for coreboot: aec9026 i945 : Some fix for 945G/945GZ/945GC
by HAOUAS Elyes 14 Sep '14

14 Sep '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6813 -gerrit commit aec9026122c774e3fcf1d0e94b74a4690d164285 Author: Elyes <ehaouas(a)noos.fr> Date: Sun Aug 31 11:13:47 2014 +0200 i945 : Some fix for 945G/945GZ/945GC Change-Id: Icbf691f33222445e7fcd670e0c6e6c4a9dcaf0aa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/Kconfig | 3 ++- src/northbridge/intel/i945/acpi.c | 2 +- src/northbridge/intel/i945/early_init.c | 16 +++++++++--- src/northbridge/intel/i945/gma.c | 16 ++++++++++-- src/northbridge/intel/i945/northbridge.c | 8 +++++- src/northbridge/intel/i945/raminit.c | 44 +++++++++++++++++++------------- 6 files changed, 63 insertions(+), 26 deletions(-) diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 360b2ab..99ea1fd 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -41,7 +41,8 @@ config BOOTBLOCK_NORTHBRIDGE_INIT config VGA_BIOS_ID string - default "8086,27a2" + default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM + default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC config CHANNEL_XOR_RANDOMIZATION bool diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index e05bd58..46ca36a 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -36,7 +36,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - dev = dev_find_device(0x8086, 0x27a0, 0); + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return current; diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ce10b..f3f0f00 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -131,6 +131,9 @@ static void i945_detect_chipset(void) case 0: printk(BIOS_DEBUG, "up to DDR2-667"); break; + case 2: + printk(BIOS_DEBUG, "up to DDR2-667"); + break; case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; @@ -194,7 +197,7 @@ static void i945_setup_bars(void) /* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); - if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ + if ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; } while (!(reg8 & 0x80)); @@ -226,6 +229,8 @@ static void i945_setup_egress_port(void) reg32 &= 0xffffff00; if ((MCHBAR32(CLKCFG) & 7) == 1) reg32 |= 0x0d; /* 533MHz */ + if ((MCHBAR32(CLKCFG) & 7) == 2) + reg32 |= 0x14; /* 800MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) reg32 |= 0x10; /* 667MHz */ EPBAR32(0x2c) = reg32; @@ -242,6 +247,11 @@ static void i945_setup_egress_port(void) EPBAR32(EPVC1IST + 4) = 0x009c009c; } + if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ + EPBAR32(EPVC1IST + 0) = 0x00f000f0; + EPBAR32(EPVC1IST + 4) = 0x00f000f0; + } + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0; @@ -425,9 +435,9 @@ static void i945_setup_dmi_rcrb(void) reg32 = DMIBAR32(0x204); reg32 &= ~0x3ff; #if 1 - reg32 |= 0x13f; /* for x4 DMI only */ + reg32 |= 0x13f; /* for x4 DMI only */ #else - reg32 |= 0x1e4; /* for x2 DMI only */ + reg32 |= 0x1e4; /* for x2 DMI only */ #endif DMIBAR32(0x204) = reg32; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 9b0dbd2..b1c9a3b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -499,6 +499,18 @@ static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; +static const unsigned short i945_gma_func0_ids[] = { + 0x27a2, + 0x2772, + 0 +}; + +static const unsigned short i945_gma_func1_ids[] = { + 0x27a6, + 0x2776, + 0 +}; + static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -524,11 +536,11 @@ static struct device_operations gma_func1_ops = { static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a2, + .devices = i945_gma_func0_ids, }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a6, + .devices = i945_gma_func1_ids, }; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 68d6d91..f666d49 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -267,10 +267,16 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, }; +static const unsigned short i945_pci_ids[] = { + 0x27a0, + 0x2770, + 0 +}; + static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a0, + .devices = i945_pci_ids, }; static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e823bab..43349ac 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -121,29 +121,22 @@ static int memclk(void) return -1; } -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 400; - case 1: return 533; - case 3: return 667; - default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); - } - return 0xffff; -} -#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC -static u16 fsbclk(void) -{ - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 1066; + case 0: + #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM + return 400; + #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + return 1066; + #endif case 1: return 533; case 2: return 800; + case 3: return 667; default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); } return 0xffff; } -#endif static int sdram_capabilities_max_supported_memory_frequency(void) { @@ -1965,6 +1958,7 @@ static void sdram_program_pll_settings(struct sys_info *sysinfo) case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */ case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */ case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */ + case 800: MCHBAR8(CPCTL) = 0x02; break; /* FSB800 */ } MCHBAR16(CPCTL) &= ~(1 << 11); @@ -2122,8 +2116,22 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) switch (sysinfo->memory_frequency) { case 400: clkcfg |= (2 << 4); break; - case 533: clkcfg |= (3 << 4); break; - case 667: clkcfg |= (4 << 4); break; + case 533: + #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM + clkcfg |= (3 << 4); + break; + #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + clkcfg |= (2 << 4); + break; + #endif + case 667: + #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM + clkcfg |= (4 << 4); + break; + #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + clkcfg |= (3 << 4); + break; + #endif default: die("Target Memory Frequency Error"); } @@ -2264,7 +2272,7 @@ static void sdram_program_clock_crossing(void) 0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ - 0x04020180, 0x00000008, /* DDR667 FSB800 */ + 0x04020130, 0x00000008, /* DDR667 FSB800 */ 0x00020904, 0x00000000, /* DDR400 FSB1066 */ 0x02010804, 0x00000000, /* DDR533 FSB1066 */ @@ -2445,7 +2453,7 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo) reg32 = MCHBAR32(DCC); #if CONFIG_CHANNEL_XOR_RANDOMIZATION - reg32 &= ~(1 << 10); + reg32 &= ~(2 << 9); reg32 |= (1 << 9); #else reg32 &= ~(1 << 9);

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New patch to review for coreboot: 656f55b mainboard/lenovo/t530: Make native VGA init 'user-friendly'
by Edward O'Callaghan 14 Sep '14

14 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6903 -gerrit commit 656f55bfb1d5b1e2fe39eb829eced5524605c67a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Sep 15 05:53:57 2014 +1000 mainboard/lenovo/t530: Make native VGA init 'user-friendly' Default to do native VGA init since this machine is a laptop and the user would likely want to use it as such. Also, if you know what this is you know how to turn it off if you want to. Change-Id: I55f91a48affbd0ec93b0bb0c88c531d15c32ba21 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index c34b647..6d411b8 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select IVYBRIDGE_LVDS + select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE

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Patch merged into coreboot/master: aca67ed payloads/external/SeaBIOS: Bump version to 1.7.5
by gerrit＠coreboot.org 14 Sep '14

14 Sep '14

the following patch was just integrated into master: commit aca67ed0d218fb551ef29416f079d548e77fc26f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Sep 13 20:43:45 2014 +1000 payloads/external/SeaBIOS: Bump version to 1.7.5 Change-Id: Ie4b58b739ea411035b1801348e3e73e607299846 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6900 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/6900 for details. -gerrit

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Patch merged into coreboot/master: eb67a04 cbmemc: Bump default to 128K
by gerrit＠coreboot.org 14 Sep '14

14 Sep '14

the following patch was just integrated into master: commit eb67a04cb3c1c6149eb54a7e015d53e6e5e17de8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Sep 13 20:55:58 2014 +0200 cbmemc: Bump default to 128K board_status shows that truncation of few KiB is pretty common. So bump this value. Change-Id: I78a16974846a59ee4eae782380e6d01d2fa324f2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6902 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6902 for details. -gerrit

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Patch merged into coreboot/master: 0650cd0 southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.
by gerrit＠coreboot.org 13 Sep '14

13 Sep '14

the following patch was just integrated into master: commit 0650cd0bad2816886745c4a7ffe0e7a1aefb9957 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 15:03:50 2014 +0100 southbridge/bd82x6x: Reserve 16 MiB for flash and not 8. X230 has 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash but address map limits this to 16MiB. Change-Id: Icc39c3c8d45d2d14e437bdfce920f8b4b039789d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/5133 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5133 for details. -gerrit

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New patch to review for coreboot: 8742359 cbmemc: Bump default to 128K
by Vladimir Serbinenko 13 Sep '14

13 Sep '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6902 -gerrit commit 874235900a6d14897e5838f4120f30f8a3ff0246 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Sep 13 20:55:58 2014 +0200 cbmemc: Bump default to 128K board_status shows that truncation of few KiB is pretty common. So bump this value. Change-Id: I78a16974846a59ee4eae782380e6d01d2fa324f2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/console/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index c7c3ea5..f5528ed 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -177,10 +177,10 @@ config CONSOLE_CBMEM config CONSOLE_CBMEM_BUFFER_SIZE depends on CONSOLE_CBMEM hex "Room allocated for console output in CBMEM" - default 0x10000 + default 0x20000 help Space allocated for console output storage in CBMEM. The default - value (64K or 0x10000 bytes) is large enough to accommodate + value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. config CONSOLE_CAR_BUFFER_SIZE

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Patch merged into coreboot/master: 7699833 to-wiki: Add IVYBRIDGE_NATIVE to the list of ivybridge names.
by gerrit＠coreboot.org 13 Sep '14

13 Sep '14

the following patch was just integrated into master: commit 76998336aa82b692c1b0cf1e2427602b5b655fac Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Aug 16 19:14:02 2014 +0200 to-wiki: Add IVYBRIDGE_NATIVE to the list of ivybridge names. Change-Id: I6e63abd9491a76e362347b7616e00104305827ee Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6691 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6691 for details. -gerrit

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coreboot-gerrit September 2014