coreboot-gerrit September 2014

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New patch to review for coreboot: b668ae6 arm: Move libgcc assembly macros to arch/asm.h
by Isaac Christensen 16 Sep '14

16 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6917 -gerrit commit b668ae6c58bb0f555ed603ad38123273b1b38579 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Dec 12 20:24:48 2013 -0800 arm: Move libgcc assembly macros to arch/asm.h libgcc/macros.h contains some useful assembly macros that are common in Linux kernel code and facilitate things such as unified ARM/THUMB assembly. This patch moves it to a more general place where it can be used by other code as well. Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182178 Reviewed-by: Vincent Palatin <vpalatin(a)chromium.org> (cherry picked from commit a780670def94a969829811fa8cf257f12b88f085) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/arch/arm/head.S | 20 ++++++------- payloads/libpayload/arch/arm/util.S | 8 ++--- payloads/libpayload/include/arm/arch/asm.h | 47 ++++++++++++++++++++++++++++++ src/arch/arm/armv4/Makefile.inc | 3 +- src/arch/arm/armv4/bootblock.S | 16 +++------- src/arch/arm/armv7/Makefile.inc | 2 +- src/arch/arm/armv7/bootblock.S | 6 ++-- src/arch/arm/include/arch/asm.h | 47 ++++++++++++++++++++++++++++++ src/soc/nvidia/tegra124/bootblock_asm.S | 16 +++------- 9 files changed, 122 insertions(+), 43 deletions(-) diff --git a/payloads/libpayload/arch/arm/head.S b/payloads/libpayload/arch/arm/head.S index 7a706e3..0d23c72 100644 --- a/payloads/libpayload/arch/arm/head.S +++ b/payloads/libpayload/arch/arm/head.S @@ -27,17 +27,16 @@ * SUCH DAMAGE. */ - .global _entry, _leave - .text - .align 4 +#include <arch/asm.h> 1: +.align 4 .word _stack /* * Our entry point */ -_entry: +ENTRY(_entry) /* TODO: disable interrupts */ @@ -46,14 +45,15 @@ _entry: /* Setup new stack */ ldr sp, 1b - /* TODO: Save old stack pointer */ + /* TODO: Save old stack pointer and link register */ /* Let's rock. */ - b start_main + bl start_main - /* %eax has the return value - pass it on unmolested */ -_leave: - /* TODO: restore old stack pointer. */ + /* %r0 has the return value - pass it on unmolested */ + + /* TODO: restore old stack pointer and link register */ /* Return to the original context. */ - mov pc, lr + bx lr +ENDPROC(_entry) diff --git a/payloads/libpayload/arch/arm/util.S b/payloads/libpayload/arch/arm/util.S index e3f173e..7c14a39 100644 --- a/payloads/libpayload/arch/arm/util.S +++ b/payloads/libpayload/arch/arm/util.S @@ -27,11 +27,9 @@ * SUCH DAMAGE. */ - .global halt - .text - .align 4 +#include <arch/asm.h> /* This function puts the system into a halt. */ - .type halt, function -halt: +ENTRY(halt) b halt +ENDPROC(halt) diff --git a/payloads/libpayload/include/arm/arch/asm.h b/payloads/libpayload/include/arm/arch/asm.h new file mode 100644 index 0000000..1c3f7a2 --- /dev/null +++ b/payloads/libpayload/include/arm/arch/asm.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARM_ASM_H +#define __ARM_ASM_H + +#if defined __arm__ +# define ARM(x...) x +# define THUMB(x...) +#elif defined __thumb__ +# define ARM(x...) +# define THUMB(x...) x +#else +# error Not in ARM or thumb mode! +#endif + +#define ALIGN .align 0 + +#define ENDPROC(name) \ + .type name, %function; \ + END(name) + +#define ENTRY(name) \ + .globl name; \ + ALIGN; \ + name: + +#define END(name) \ + .size name, .-name + +#endif /* __ARM_ASM_H */ diff --git a/src/arch/arm/armv4/Makefile.inc b/src/arch/arm/armv4/Makefile.inc index d054b31..aa78868 100644 --- a/src/arch/arm/armv4/Makefile.inc +++ b/src/arch/arm/armv4/Makefile.inc @@ -19,7 +19,8 @@ ## ############################################################################### -armv4_flags = -marm -march=armv4t -I$(src)/arch/arm/include/armv4/ +armv4_flags = -marm -march=armv4t -I$(src)/arch/arm/include/armv4/ \ + -D__COREBOOT_ARM_ARCH__=4 ############################################################################### # bootblock diff --git a/src/arch/arm/armv4/bootblock.S b/src/arch/arm/armv4/bootblock.S index 3ba2a88..58a34cf 100644 --- a/src/arch/arm/armv4/bootblock.S +++ b/src/arch/arm/armv4/bootblock.S @@ -29,19 +29,10 @@ * MA 02111-1307 USA */ -.section ".start", "a", %progbits -.globl _start -_start: b reset - .balignl 16,0xdeadbeef - -_cbfs_master_header: - /* The CBFS master header is inserted by cbfstool at the first - * aligned offset after the above anchor string is found. - * Hence, we leave some space for it. - */ - .skip 128 @ Assumes 64-byte alignment +#include <arch/asm.h> -reset: +.section ".start", "a", %progbits +ENTRY(_start) /* * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are @@ -84,6 +75,7 @@ call_bootblock: * wrapper which is currently broken. */ bl main +ENDPROC(_start) /* we do it this way because it's a 32-bit constant and * in some cases too far away to be loaded as just an offset diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 2cc42bb..033d498 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -20,7 +20,7 @@ ############################################################################### armv7_flags = -march=armv7-a -mthumb -mthumb-interwork \ - -I$(src)/arch/arm/include/armv7/ + -I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7 ############################################################################### # bootblock diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index cfe65e5..a8d0973 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -29,9 +29,10 @@ * MA 02111-1307 USA */ +#include <arch/asm.h> + .section ".start", "a", %progbits -.globl _start -_start: +ENTRY(_start) /* * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are @@ -89,6 +90,7 @@ call_bootblock: wait_for_interrupt: wfi mov pc, lr @ back to my caller +ENDPROC(_start) /* we do it this way because it's a 32-bit constant and * in some cases too far away to be loaded as just an offset diff --git a/src/arch/arm/include/arch/asm.h b/src/arch/arm/include/arch/asm.h new file mode 100644 index 0000000..1c3f7a2 --- /dev/null +++ b/src/arch/arm/include/arch/asm.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARM_ASM_H +#define __ARM_ASM_H + +#if defined __arm__ +# define ARM(x...) x +# define THUMB(x...) +#elif defined __thumb__ +# define ARM(x...) +# define THUMB(x...) x +#else +# error Not in ARM or thumb mode! +#endif + +#define ALIGN .align 0 + +#define ENDPROC(name) \ + .type name, %function; \ + END(name) + +#define ENTRY(name) \ + .globl name; \ + ALIGN; \ + name: + +#define END(name) \ + .size name, .-name + +#endif /* __ARM_ASM_H */ diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S index 3ba2a88..58a34cf 100644 --- a/src/soc/nvidia/tegra124/bootblock_asm.S +++ b/src/soc/nvidia/tegra124/bootblock_asm.S @@ -29,19 +29,10 @@ * MA 02111-1307 USA */ -.section ".start", "a", %progbits -.globl _start -_start: b reset - .balignl 16,0xdeadbeef - -_cbfs_master_header: - /* The CBFS master header is inserted by cbfstool at the first - * aligned offset after the above anchor string is found. - * Hence, we leave some space for it. - */ - .skip 128 @ Assumes 64-byte alignment +#include <arch/asm.h> -reset: +.section ".start", "a", %progbits +ENTRY(_start) /* * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are @@ -84,6 +75,7 @@ call_bootblock: * wrapper which is currently broken. */ bl main +ENDPROC(_start) /* we do it this way because it's a 32-bit constant and * in some cases too far away to be loaded as just an offset

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New patch to review for coreboot: e443a44 rambi/baytrail: ACPI, GPIO, audio, misc updates
by Isaac Christensen 16 Sep '14

16 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6916 -gerrit commit e443a44d5681e35fc1938554e7ed7b85768d4dc2 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Thu Jan 16 17:52:21 2014 -0800 rambi/baytrail: ACPI, GPIO, audio, misc updates rambi: Change RAM_ID GPIOs to GPIO_INPUT Reviewed-on: https://chromium-review.googlesource.com/182934 (cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0) baytrail: initialize rtc device Reviewed-on: https://chromium-review.googlesource.com/183051 (cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821) baytrail: Set SOC power budget values for SdpProfile 2&3 Reviewed-on: https://chromium-review.googlesource.com/183101 (cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55) baytrail: Set PMC PTPS register correctly Reviewed-on: https://chromium-review.googlesource.com/183280 (cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad) baytrail: update to version 809 microcode for c0 Reviewed-on: https://chromium-review.googlesource.com/183256 (cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e) baytrail: Add a shared GNVS init function Reviewed-on: https://chromium-review.googlesource.com/183332 (cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c) baytrail: Add basic support for ACPI System Wake Source Reviewed-on: https://chromium-review.googlesource.com/183333 (cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619) baytrail: allow configuration of io hole size Reviewed-on: https://chromium-review.googlesource.com/183269 (cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919) baytrail: add in C0 stepping idenitification support. Reviewed-on: https://chromium-review.googlesource.com/183594 (cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4) baytrail: add option for enabling PS2 mode Reviewed-on: https://chromium-review.googlesource.com/183595 (cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f) rambi: enable PS2 mode for VNN and VCC Reviewed-on: https://chromium-review.googlesource.com/183596 (cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9) baytrail: add config option for disabling slp_x stretching Reviewed-on: https://chromium-review.googlesource.com/183587 (cherry picked from commit f99804c2649bef436644dd300be2a595659ceece) rambi: disable slp_x stretching after sus fail Reviewed-on: https://chromium-review.googlesource.com/183588 (cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880) baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI Reviewed-on: https://chromium-review.googlesource.com/183597 (cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906) rambi: fix trackpad and touchscreen wake sources Reviewed-on: https://chromium-review.googlesource.com/183598 (cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5) baytrail: Add support for LPE device in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184006 (cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f) rambi: Add LPE GPIOs for Jack/Mic detect Reviewed-on: https://chromium-review.googlesource.com/184007 (cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578) rambi: Set TSRx passive threshold to 60C Reviewed-on: https://chromium-review.googlesource.com/184008 (cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee) baytrail: DPTF: Add PPCC object for power limit information Reviewed-on: https://chromium-review.googlesource.com/184158 (cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b) baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant Reviewed-on: https://chromium-review.googlesource.com/184442 (cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd) rambi: Move the CPU passive/critical threshold config to DPTF Reviewed-on: https://chromium-review.googlesource.com/184443 (cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac) baytrail: Fix XHCI controller reset on resume Reviewed-on: https://chromium-review.googlesource.com/184500 (cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd) baytrail: update lpe audio firmware location Reviewed-on: https://chromium-review.googlesource.com/184481 (cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6) rambi: Put LPSS devices in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184530 (cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1) baytrail: initialize HDA device and HDMI codec Reviewed-on: https://chromium-review.googlesource.com/184710 (cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961) baytrail: provide GPIO_ACPI_WAKE configuration Reviewed-on: https://chromium-review.googlesource.com/184718 (cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b) rambi: configure wake pins as just wake sources Reviewed-on: https://chromium-review.googlesource.com/184719 (cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115) baytrail: I2C: Add config data to ACPI Device Reviewed-on: https://chromium-review.googlesource.com/184922 (cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8) Squashed 28 commits for rambi and baytrail. Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/rambi/acpi/dptf.asl | 14 +- src/mainboard/google/rambi/acpi/mainboard.asl | 14 + src/mainboard/google/rambi/acpi/thermal.asl | 245 - src/mainboard/google/rambi/acpi_tables.c | 21 +- src/mainboard/google/rambi/devicetree.cb | 8 + src/mainboard/google/rambi/dsdt.asl | 2 - src/mainboard/google/rambi/gpio.c | 12 +- src/mainboard/google/rambi/irqroute.h | 1 + src/mainboard/google/rambi/onboard.h | 4 +- src/mainboard/google/rambi/thermal.h | 32 - src/soc/intel/baytrail/Makefile.inc | 2 + src/soc/intel/baytrail/acpi.c | 30 + src/soc/intel/baytrail/acpi/dptf/cpu.asl | 35 + src/soc/intel/baytrail/acpi/globalnvs.asl | 1 + src/soc/intel/baytrail/acpi/lpe.asl | 119 + src/soc/intel/baytrail/acpi/lpss.asl | 42 + src/soc/intel/baytrail/acpi/platform.asl | 6 + src/soc/intel/baytrail/acpi/southcluster.asl | 3 + src/soc/intel/baytrail/baytrail/acpi.h | 2 + src/soc/intel/baytrail/baytrail/gpio.h | 28 +- src/soc/intel/baytrail/baytrail/hda_verb.h | 39 + src/soc/intel/baytrail/baytrail/iosf.h | 9 + src/soc/intel/baytrail/baytrail/lpc.h | 2 + src/soc/intel/baytrail/baytrail/mrc_wrapper.h | 3 +- src/soc/intel/baytrail/baytrail/nvs.h | 8 +- src/soc/intel/baytrail/baytrail/pmc.h | 30 +- src/soc/intel/baytrail/chip.h | 7 + src/soc/intel/baytrail/dptf.c | 6 +- src/soc/intel/baytrail/elog.c | 4 + src/soc/intel/baytrail/gfx.c | 2 +- src/soc/intel/baytrail/gpio.c | 4 +- src/soc/intel/baytrail/hda.c | 121 + src/soc/intel/baytrail/hda_verb.c | 253 + src/soc/intel/baytrail/lpe.c | 104 +- .../intel/baytrail/microcode/M0C3068_00000808.h | 12800 ------------------- .../intel/baytrail/microcode/M0C3068_00000809.h | 12800 +++++++++++++++++++ src/soc/intel/baytrail/microcode/microcode_blob.c | 2 +- src/soc/intel/baytrail/pmutil.c | 4 +- src/soc/intel/baytrail/ramstage.c | 38 +- src/soc/intel/baytrail/romstage/pmc.c | 36 +- src/soc/intel/baytrail/romstage/raminit.c | 5 + src/soc/intel/baytrail/southcluster.c | 37 + src/soc/intel/baytrail/xhci.c | 42 +- 43 files changed, 13804 insertions(+), 13173 deletions(-) diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl index afb20de..51237dc 100644 --- a/src/mainboard/google/rambi/acpi/dptf.asl +++ b/src/mainboard/google/rambi/acpi/dptf.asl @@ -1,16 +1,19 @@ +#define DPTF_CPU_PASSIVE 60 +#define DPTF_CPU_CRITICAL 70 + #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 40 +#define DPTF_TSR0_PASSIVE 60 #define DPTF_TSR0_CRITICAL 70 #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_PASSIVE 60 #define DPTF_TSR1_CRITICAL 70 #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 35 +#define DPTF_TSR2_PASSIVE 60 #define DPTF_TSR2_CRITICAL 70 #undef DPTF_ENABLE_CHARGER @@ -22,6 +25,11 @@ Name (DTRT, Package () { /* CPU Effect on Temp Sensor 0 */ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 50, 0, 0, 0, 0 }, +#endif + /* CPU Effect on Temp Sensor 1 */ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 }, diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 501bbf7..1f5b7a1 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -360,3 +360,17 @@ Scope (\_SB.I2C6) Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) } } + +Scope (\_SB.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveHigh, Exclusive, PullNone,, + "\\_SB.GPSC") { 14 } + + /* Mic Detect (index 1) */ + GpioInt (Edge, ActiveHigh, Exclusive, PullNone,, + "\\_SB.GPSC") { 15 } + }) +} diff --git a/src/mainboard/google/rambi/acpi/thermal.asl b/src/mainboard/google/rambi/acpi/thermal.asl deleted file mode 100644 index 36310e4..0000000 --- a/src/mainboard/google/rambi/acpi/thermal.asl +++ /dev/null @@ -1,245 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 0 seconds - Name (_TZP, 0) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - Method (_TMP, 0, Serialized) - { - Return (CTOK (30)) - } - - Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { - Return (CTOK (\F0OF)) - } Else { - Return (CTOK (\F0ON)) - } - } - - Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { - Return (CTOK (\F1OF)) - } Else { - Return (CTOK (\F1ON)) - } - } - - Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { - Return (CTOK (\F2OF)) - } Else { - Return (CTOK (\F2ON)) - } - } - - Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { - Return (CTOK (\F3OF)) - } Else { - Return (CTOK (\F3ON)) - } - } - - Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { - Return (CTOK (\F4OF)) - } Else { - Return (CTOK (\F4ON)) - } - } - - Name (_AL0, Package () { FAN0 }) - Name (_AL1, Package () { FAN1 }) - Name (_AL2, Package () { FAN2 }) - Name (_AL3, Package () { FAN3 }) - Name (_AL4, Package () { FAN4 }) - - PowerResource (FNP0, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 0)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (0, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (1, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - PowerResource (FNP1, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 1)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (1, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (2, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - PowerResource (FNP2, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 2)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (2, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (3, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - PowerResource (FNP3, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 3)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (3, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (4, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - PowerResource (FNP4, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 4)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (4, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (4, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - Device (FAN0) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 0) - Name (_PR0, Package () { FNP0 }) - } - - Device (FAN1) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 1) - Name (_PR0, Package () { FNP1 }) - } - - Device (FAN2) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 2) - Name (_PR0, Package () { FNP2 }) - } - - Device (FAN3) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 3) - Name (_PR0, Package () { FNP3 }) - } - - Device (FAN4) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 4) - Name (_PR0, Package () { FNP4 }) - } - } -} diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 7c0c646..890e1df 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -30,19 +30,15 @@ #include <device/pci_ids.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <baytrail/acpi.h> #include <baytrail/nvs.h> #include <baytrail/iomap.h> -#include "thermal.h" - extern const unsigned char AmlCode[]; static void acpi_create_gnvs(global_nvs_t *gnvs) { - gnvs->pcnt = dev_count_cpu(); + acpi_init_gnvs(gnvs); /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -52,26 +48,11 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* Top of Low Memory (start of resource allocation) */ - gnvs->tolm = nc_read_top_of_low_memory(); - /* TPM Present */ gnvs->tpmp = 1; /* Enable DPTF */ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tact = ACTIVE_TEMPERATURE; gnvs->dpte = 1; - -#if CONFIG_CHROMEOS - chromeos_init_vboot(&(gnvs->chromeos)); - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index fe5ec7b..79a2d22 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -33,6 +33,7 @@ chip soc/intel/baytrail # Enable devices in ACPI mode register "scc_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" # Enable PIPEA as DP_C register "gpu_pipea_hotplug" = "6" # 6ms Pulse @@ -44,6 +45,13 @@ chip soc/intel/baytrail register "gpu_pipea_light_off_delay" = "2000" # 200ms register "gpu_pipea_backlight_pwm" = "0x400" + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 4165087..01b816b 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -35,8 +35,6 @@ DefinitionBlock( // global NVS and variables #include <soc/intel/baytrail/acpi/globalnvs.asl> - //#include "acpi/thermal.asl" - #include <soc/intel/baytrail/acpi/cpu.asl> Scope (\_SB) { diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index d551a15..a3c0d2d 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -163,9 +163,9 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { /* SSUS GPIOs */ static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_ACPI_SCI, /* S500 - PCH_WAKE# */ - GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */ - GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ @@ -200,9 +200,9 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_NC, /* S534 - NC */ GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ GPIO_NC, /* S536 - NC */ - GPIO_FUNC0, /* S537 - RAM_ID0 */ - GPIO_FUNC0, /* S538 - RAM_ID1 */ - GPIO_FUNC0, /* S539 - RAM_ID2 */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ GPIO_NC, /* S540 - NC */ GPIO_NC, /* S541 - NC */ GPIO_NC, /* S542 - NC */ diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h index 7339793..0f4ca17 100644 --- a/src/mainboard/google/rambi/irqroute.h +++ b/src/mainboard/google/rambi/irqroute.h @@ -19,6 +19,7 @@ #include <soc/intel/baytrail/baytrail/irq.h> #include <soc/intel/baytrail/baytrail/pci_devs.h> +#include <soc/intel/baytrail/baytrail/pmc.h> #define PCI_DEV_PIRQ_ROUTES \ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ diff --git a/src/mainboard/google/rambi/onboard.h b/src/mainboard/google/rambi/onboard.h index 8fb7a3f..18ceca3 100644 --- a/src/mainboard/google/rambi/onboard.h +++ b/src/mainboard/google/rambi/onboard.h @@ -24,13 +24,13 @@ #define BOARD_TRACKPAD_NAME "trackpad" #define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) -#define BOARD_TRACKPAD_WAKE_GPIO 1 /* GPSSUS1 */ +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) #define BOARD_TRACKPAD_I2C_BUS 0 #define BOARD_TRACKPAD_I2C_ADDR 0x4b #define BOARD_TOUCHSCREEN_NAME "touchscreen" #define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) -#define BOARD_TOUCHSCREEN_WAKE_GPIO 2 /* GPSSUS2 */ +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) #define BOARD_TOUCHSCREEN_I2C_BUS 5 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ diff --git a/src/mainboard/google/rambi/thermal.h b/src/mainboard/google/rambi/thermal.h deleted file mode 100644 index 2432b8d..0000000 --- a/src/mainboard/google/rambi/thermal.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef BAYLEYBAY_THERMAL_H -#define BAYLEYBAY_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 95 - -/* Passive cooling policy threshold */ -#define PASSIVE_TEMPERATURE 0 - -/* Temperature which OS will throttle CPU (when using a Fan) */ -#define ACTIVE_TEMPERATURE 80 - -#endif diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index d4f653e..ce1f243 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -49,6 +49,8 @@ ramstage-y += perf_power.c ramstage-y += stage_cache.c romstage-y += stage_cache.c ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += hda.c +ramstage-y += hda_verb.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 89ab929..1ab1eb3 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -22,6 +22,7 @@ #include <arch/acpigen.h> #include <arch/io.h> #include <arch/smp/mpspec.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <console/console.h> @@ -39,6 +40,9 @@ #include <baytrail/pattrs.h> #include <baytrail/pmc.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> + #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ @@ -74,6 +78,32 @@ static acpi_cstate_t cstate_map[] = { } }; +void acpi_init_gnvs(global_nvs_t *gnvs) +{ + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + + /* Top of Low Memory (start of resource allocation) */ + gnvs->tolm = nc_read_top_of_low_memory(); + +#if CONFIG_CONSOLE_CBMEM + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + +#if CONFIG_CHROMEOS + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); +#if CONFIG_EC_GOOGLE_CHROMEEC + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif +#endif +} + static int acpi_sci_irq(void) { const unsigned long actl = ILB_BASE_ADDRESS + ACTL; diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl index f82c348..93d434b 100644 --- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -123,4 +123,39 @@ Device (TCPU) Return (0) } } + + Name (PPCC, Package () + { + 0x2, // Revision + Package () { // Power Limit 1 + 0, // PowerLimitIndex, 0 for Power Limit 1 + 1600, // PowerLimitMinimum + 6200, // PowerLimitMaximum + 1000, // TimeWindowMinimum + 1000, // TimeWindowMaximum + 200 // StepSize + }, + Package () { // Power Limit 2 + 1, // PowerLimitIndex, 1 for Power Limit 2 + 8000, // PowerLimitMinimum + 8000, // PowerLimitMaximum + 1000, // TimeWindowMinimum + 1000, // TimeWindowMaximum + 1000 // StepSize + } + }) + +#ifdef DPTF_CPU_CRITICAL + Method (_CRT) + { + Return (^^CTOK (DPTF_CPU_CRITICAL)) + } +#endif + +#ifdef DPTF_CPU_PASSIVE + Method (_PSV) + { + Return (^^CTOK (DPTF_CPU_PASSIVE)) + } +#endif } diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index b384cea..a201c03 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -52,6 +52,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TPMP, 8, // 0x12 - TPM Present and Enabled TLVL, 8, // 0x13 - Throttle Level PPCM, 8, // 0x14 - Maximum P-state usable by OS + PM1I, 32, // 0x15 - System Wake Source - PM1 Index /* Device Config */ Offset (0x20), diff --git a/src/soc/intel/baytrail/acpi/lpe.asl b/src/soc/intel/baytrail/acpi/lpe.asl new file mode 100644 index 0000000..71a2746 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/lpe.asl @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LPEA) +{ + Name (_HID, "80860F28") + Name (_CID, "80860F28") + Name (_UID, 1) + Name (_DDN, "Low Power Audio Controller") + Name (_PR0, Package () { PLPE }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0) + Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1) + Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_DMA0_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_DMA1_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_SSP0_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_SSP1_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_SSP2_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_IPC2HOST_IRQ + } + }) + + Method (_CRS) + { + /* Update BAR0 from NVS */ + CreateDwordField (^RBUF, ^BAR0._BAS, BAS0) + Store (\LPB0, BAS0) + + /* Update BAR1 from NVS */ + CreateDwordField (^RBUF, ^BAR1._BAS, BAS1) + Store (\LPB1, BAS1) + + /* Update LPE FW from NVS */ + CreateDwordField (^RBUF, ^BAR2._BAS, BAS2) + Store (\LPFW, BAS2) + + /* Append any Mainboard defined GPIOs */ + If (CondRefOf (^GBUF, Local0)) { + ConcatenateResTemplate (^RBUF, Local0, Local1) + Return (Local1) + } + + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\LPEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, LPB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + PowerResource (PLPE, 0, 0) + { + Method (_STA) + { + Return (1) + } + + Method (_OFF) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_ON) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } +} diff --git a/src/soc/intel/baytrail/acpi/lpss.asl b/src/soc/intel/baytrail/acpi/lpss.asl index f56c6a8..0f8f746 100644 --- a/src/soc/intel/baytrail/acpi/lpss.asl +++ b/src/soc/intel/baytrail/acpi/lpss.asl @@ -89,6 +89,12 @@ Device (I2C1) Name (_UID, 1) Name (_DDN, "I2C Controller #1") + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (RBUF, ResourceTemplate() { Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) @@ -142,6 +148,12 @@ Device (I2C2) Name (_UID, 2) Name (_DDN, "I2C Controller #2") + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (RBUF, ResourceTemplate() { Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) @@ -195,6 +207,12 @@ Device (I2C3) Name (_UID, 3) Name (_DDN, "I2C Controller #3") + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (RBUF, ResourceTemplate() { Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) @@ -248,6 +266,12 @@ Device (I2C4) Name (_UID, 4) Name (_DDN, "I2C Controller #4") + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (RBUF, ResourceTemplate() { Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) @@ -301,6 +325,12 @@ Device (I2C5) Name (_UID, 5) Name (_DDN, "I2C Controller #5") + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (RBUF, ResourceTemplate() { Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) @@ -354,6 +384,12 @@ Device (I2C6) Name (_UID, 6) Name (_DDN, "I2C Controller #6") + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (RBUF, ResourceTemplate() { Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) @@ -407,6 +443,12 @@ Device (I2C7) Name (_UID, 7) Name (_DDN, "I2C Controller #7") + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + Name (RBUF, ResourceTemplate() { Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl index e6aaf75..e32880e 100644 --- a/src/soc/intel/baytrail/acpi/platform.asl +++ b/src/soc/intel/baytrail/acpi/platform.asl @@ -70,3 +70,9 @@ Method(_WAK,1) { Return(Package(){0,0}) } + +Method (_SWS) +{ + /* Index into PM1 for device that caused wake */ + Return (\PM1I) +} diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 61642a5..fac252f 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -268,4 +268,7 @@ Scope (\_SB) // SCC Devices #include "scc.asl" + + // LPE Device + #include "lpe.asl" } diff --git a/src/soc/intel/baytrail/baytrail/acpi.h b/src/soc/intel/baytrail/baytrail/acpi.h index 3ad5593..279c2cb 100644 --- a/src/soc/intel/baytrail/baytrail/acpi.h +++ b/src/soc/intel/baytrail/baytrail/acpi.h @@ -21,9 +21,11 @@ #define _BAYTRAIL_ACPI_H_ #include <arch/acpi.h> +#include <baytrail/nvs.h> void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); +void acpi_init_gnvs(global_nvs_t *gnvs); #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index e7cc344..05fcf7d 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -229,7 +229,7 @@ #define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 10K) /* ACPI GPIO routing. Assume everything is externally pulled and negative edge - * triggered. */ + * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ #define GPIO_ACPI_SCI \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ @@ -237,6 +237,15 @@ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT, \ .tne = 1, \ + .sci = 1, \ + .wake_en = 1, } +#define GPIO_ACPI_WAKE \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = 1, \ .wake_en = 1, } #define GPIO_ACPI_SMI \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ @@ -281,14 +290,15 @@ struct soc_gpio_map { u32 pad_conf0; u32 pad_conf1; u32 pad_val; - u8 use_sel : 1; - u8 io_sel : 1; - u8 gp_lvl : 1; - u8 tpe : 1; - u8 tne : 1; - u8 wake_en : 1; - u8 smi : 1; - u8 is_gpio : 1; + u32 use_sel : 1; + u32 io_sel : 1; + u32 gp_lvl : 1; + u32 tpe : 1; + u32 tne : 1; + u32 wake_en : 1; + u32 smi : 1; + u32 is_gpio : 1; + u32 sci : 1; } __attribute__ ((packed)); struct soc_gpio_config { diff --git a/src/soc/intel/baytrail/baytrail/hda_verb.h b/src/soc/intel/baytrail/baytrail/hda_verb.h new file mode 100644 index 0000000..9c505d6 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/hda_verb.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BAYTRAIL_HDA_VERB_H +#define BAYTRAIL_HDA_VERB_H + +#include <stdint.h> + +#define HDA_GCAP_REG 0x00 +#define HDA_GCTL_REG 0x08 +#define HDA_GCTL_CRST (1 << 0) +#define HDA_STATESTS_REG 0x0e +#define HDA_IC_REG 0x60 +#define HDA_IR_REG 0x64 +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) + +int hda_codec_detect(u32 base); +int hda_codec_write(u32 base, u32 size, const u32 *data); +int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data); + +#endif diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index e936072..f61582c 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -231,6 +231,8 @@ void iosf_ssus_write(int reg, uint32_t val); # define SB_BIOS_CONFIG_PDM_MODE (1 << 16) # define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) # define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) +# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3) +# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2) # define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) # define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) #define BIOS_RESET_CPL 0x05 @@ -329,4 +331,11 @@ void iosf_ssus_write(int reg, uint32_t val); #define USHPHY_REE_DAC_CONTROL 0x80b8 #define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 +/* + * LPE Registers + */ +#define LPE_PCICFGCTR1 0x0500 +# define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0) +# define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1) + #endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/lpc.h b/src/soc/intel/baytrail/baytrail/lpc.h index 71391ad..31de310 100644 --- a/src/soc/intel/baytrail/baytrail/lpc.h +++ b/src/soc/intel/baytrail/baytrail/lpc.h @@ -36,6 +36,7 @@ #define RID_A_STEPPING_START 1 #define RID_B_STEPPING_START 5 +#define RID_C_STEPPING_START 0xe enum baytrail_stepping { STEP_A0, STEP_A1, @@ -43,6 +44,7 @@ enum baytrail_stepping { STEP_B1, STEP_B2, STEP_B3, + STEP_C0, }; #endif /* _BAYTRAIL_LPC_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/mrc_wrapper.h b/src/soc/intel/baytrail/baytrail/mrc_wrapper.h index 2074100..893debc 100644 --- a/src/soc/intel/baytrail/baytrail/mrc_wrapper.h +++ b/src/soc/intel/baytrail/baytrail/mrc_wrapper.h @@ -28,7 +28,7 @@ #ifndef _MRC_WRAPPER_H_ #define _MRC_WRAPPER_H_ -#define MRC_PARAMS_VER 2 +#define MRC_PARAMS_VER 3 #define NUM_CHANNELS 2 @@ -79,6 +79,7 @@ struct mrc_params { int txe_size_mb; /* TXE memory size in megabytes. */ int rmt_enabled; /* Enable RMT training + prints. */ + int io_hole_mb; /* Size of IO hole in MiB. */ /* Outputs */ void *txe_base_address; diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index dbf72e2..c5defac 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef _BAYTRAIL_NVS_H_ +#define _BAYTRAIL_NVS_H_ + #include <vendorcode/google/chromeos/gnvs.h> #include <baytrail/device_nvs.h> @@ -40,7 +43,8 @@ typedef struct { u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tlvl; /* 0x13 - Throttle Level */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ - u8 rsvd1[11]; + u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */ + u8 rsvd1[7]; /* Device Config */ u8 s5u0; /* 0x20 - Enable USB0 in S5 */ @@ -70,3 +74,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index ccbeed8..1af7ab8 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -200,14 +200,22 @@ #define CORE_GPIO_EN2 (1 << 26) #define CORE_GPIO_EN1 (1 << 25) #define CORE_GPIO_EN0 (1 << 24) -#define SUS_GPIO_EN7 (1 << 23) -#define SUS_GPIO_EN6 (1 << 22) -#define SUS_GPIO_EN5 (1 << 21) -#define SUS_GPIO_EN4 (1 << 20) -#define SUS_GPIO_EN3 (1 << 19) -#define SUS_GPIO_EN2 (1 << 18) -#define SUS_GPIO_EN1 (1 << 17) -#define SUS_GPIO_EN0 (1 << 16) +#define SUS_GPIO_EN7_BIT 23 +#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) +#define SUS_GPIO_EN6_BIT 22 +#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) +#define SUS_GPIO_EN5_BIT 21 +#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) +#define SUS_GPIO_EN4_BIT 20 +#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) +#define SUS_GPIO_EN3_BIT 19 +#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) +#define SUS_GPIO_EN2_BIT 18 +#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) +#define SUS_GPIO_EN1_BIT 17 +#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) +#define SUS_GPIO_EN0_BIT 16 +#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) #define PME_B0_EN (1 << 13) #define BATLOW_EN (1 << 10) #define PCI_EXP_EN (1 << 9) @@ -217,6 +225,8 @@ #define PCIE_WAKE0_EN (1 << 3) #define SWGPE_EN (1 << 2) #define HOT_PLUG_EN (1 << 1) +#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT +#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) #define SMI_EN 0x30 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic #define USB_EN (1 << 17) // Legacy USB2 SMI logic @@ -250,6 +260,8 @@ # define RST_CPU (1 << 2) # define SYS_RST (1 << 1) +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) + /* Track power state from reset to log events. */ struct chipset_power_state { uint16_t pm1_sts; @@ -286,4 +298,6 @@ void southcluster_log_state(void); static inline void southcluster_log_state(void) {} #endif +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + #endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 955ecb0..0a57885 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -31,6 +31,13 @@ struct soc_intel_baytrail_config { uint8_t ide_legacy_combined; uint8_t clkreq_enable; + /* VR low power settings -- enable PS2 mode for gfx and core */ + int vnn_ps2_enable; + int vcc_ps2_enable; + + /* Disable SLP_X stretching after SUS power well loss. */ + int disable_slp_x_stretch_sus_fail; + /* USB Port Disable mask */ uint16_t usb2_port_disable_mask; uint16_t usb3_port_disable_mask; diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index 691e220..044a807 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -30,15 +30,15 @@ static const struct reg_script dptf_init_settings[] = { REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 90 << 24), /* Tj_max=90C */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 0x00000000), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029), - /* ratio 10 = 1333mhz for 2.5W fanless */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000A00), + /* ratio 11 = 1466mhz for mid and entry celeron */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000B00), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002), REG_SCRIPT_END, }; diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index c31bb00..df907a7 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -42,6 +42,10 @@ static void log_power_and_resets(const struct chipset_power_state *ps) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); } + if (ps->gen_pmcon1 & RPS) { + elog_add_event(ELOG_TYPE_RTC_RESET); + } + if (ps->tco_sts & SECOND_TO_STS) { elog_add_event(ELOG_TYPE_TCO_RESET); } diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 9207cfe..4ed08c9 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -142,7 +142,7 @@ static const struct reg_script gfx_init_script[] = { /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */ /* SDP Profile 4 == 0x11940, others 0xcf08 */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0x11940), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08), /* GfxPause */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388), diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index aa49591..78aeb17 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -182,13 +182,13 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, /* SMI takes precedence and wake_en implies SCI. */ if (sus[i].smi) { route_reg |= ROUTE_SMI << (2 * i); - } else if (sus[i].wake_en) { + } else if (sus[i].sci) { route_reg |= ROUTE_SCI << (2 * i); } if (core[i].smi) { route_reg |= ROUTE_SMI << (2 * (i + 8)); - } else if (core[i].wake_en) { + } else if (core[i].sci) { route_reg |= ROUTE_SCI << (2 * (i + 8)); } } diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c new file mode 100644 index 0000000..a99e743 --- /dev/null +++ b/src/soc/intel/baytrail/hda.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <baytrail/hda_verb.h> +#include <baytrail/iomap.h> +#include <baytrail/iosf.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> + +static const struct reg_script init_ops[] = { + /* Set up VC0 and VC1. */ + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x24, 0x80000019), + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x28, 0x81000022), + /* Enable VCi */ + REG_PCI_WRITE32(0x120, 0x81000022), + /* Enable no snoop traffic. */ + REG_PCI_OR16(0x78, 1 << 11), + /* Configure HDMI codec connection. */ + REG_PCI_OR32(0xc4, 1 << 1), + REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00), + /* Configure internal settings. */ + REG_PCI_OR32(0xc0, 0x7 << 21), + REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)), + REG_PCI_WRITE32(0xc8, 0x82a30000), + REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0), + /* Disable docking. */ + REG_PCI_RMW8(0x4d, ~(1 << 7), 0), + REG_SCRIPT_END, +}; + +static const uint32_t hdmi_codec_verb_table[] = { + /* coreboot specific header */ + 0x80862882, /* vid did for hdmi codec */ + 0x00000000, /* subsystem id */ + 0x00000003, /* number of jacks */ + + /* pin widget 5 - port B */ + 0x20471c10, + 0x20471d00, + 0x20471e56, + 0x20471f18, + + /* pin widget 6 - port C */ + 0x20571c20, + 0x20571d00, + 0x20571e56, + 0x20571f18, + + /* pin widget 7 - port D */ + 0x20671c30, + 0x20671d00, + 0x20671e56, + 0x20671f58, +}; + +static void hda_init(device_t dev) +{ + struct resource *res; + int codec_mask; + int i; + + reg_script_run_on_dev(dev, init_ops); + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res == NULL) + return; + + codec_mask = hda_codec_detect(res->base); + + printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask); + if (!codec_mask) + return; + + for (i = 3; i >= 0; i--) { + if (!((1 << i) & codec_mask)) + continue; + hda_codec_init(res->base, i, sizeof(hdmi_codec_verb_table), + hdmi_codec_verb_table); + } +} + +static const struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = hda_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = HDA_DEVID, +}; diff --git a/src/soc/intel/baytrail/hda_verb.c b/src/soc/intel/baytrail/hda_verb.c new file mode 100644 index 0000000..ae71b89 --- /dev/null +++ b/src/soc/intel/baytrail/hda_verb.c @@ -0,0 +1,253 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <delay.h> +#include <baytrail/hda_verb.h> + +/** + * Set bits in a register and wait for status + */ +static int set_bits(u32 port, u32 mask, u32 val) +{ + u32 reg32; + int count; + + /* Write (val & mask) to port */ + val &= mask; + reg32 = read32(port); + reg32 &= ~mask; + reg32 |= val; + write32(port, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(port); + reg32 &= mask; + } while ((reg32 != val) && --count); + + /* Timeout occurred */ + if (!count) + return -1; + return 0; +} + +/** + * Probe for supported codecs + */ +int hda_codec_detect(u32 base) +{ + u8 reg8; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + goto no_codec; + + /* Write back the value once reset bit is set. */ + write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); + + /* Read in Codec location (BAR + 0xe)[2..0]*/ + reg8 = read8(base + HDA_STATESTS_REG); + reg8 &= 0x0f; + if (!reg8) + goto no_codec; + + return reg8; + +no_codec: + /* Codec Not found */ + /* Put HDA back in reset (BAR + 0x8) [0] */ + set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); + printk(BIOS_DEBUG, "HDA: No codec!\n"); + return 0; +} + +/** + * Wait 50usec for the codec to indicate it is ready + * no response would imply that the codec is non-operative + */ +static int hda_wait_for_ready(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + + while(timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if (!(reg32 & HDA_ICII_BUSY)) + return 0; + udelay(1); + } + + return -1; +} + +/** + * Wait 50usec for the codec to indicate that it accepted + * the previous command. No response would imply that the code + * is non-operative + */ +static int hda_wait_for_valid(u32 base) +{ + u32 reg32; + + /* Send the verb to the codec */ + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32); + + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + while(timeout--) { + reg32 = read32(base + HDA_ICII_REG); + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == + HDA_ICII_VALID) + return 0; + udelay(1); + } + + return -1; +} + +/** + * Find a specific entry within a verb table + * + * @verb_table_bytes: verb table size in bytes + * @verb_table_data: verb table data + * @viddid: vendor/device to search for + * @verb_out: pointer to entry within table + * + * Returns size of the entry within the verb table, + * Returns 0 if the entry is not found + * + * The HDA verb table is composed of dwords. A set of 4 dwords is + * grouped together to form a "jack" descriptor. + * Bits 31:28 - Codec Address + * Bits 27:20 - NID + * Bits 19:8 - Verb ID + * Bits 7:0 - Payload + * + * coreboot groups different codec verb tables into a single table + * and prefixes each with a specific header consisting of 3 + * dword entries: + * 1 - Codec Vendor/Device ID + * 2 - Subsystem ID + * 3 - Number of jacks (groups of 4 dwords) for this codec + */ +static u32 hda_find_verb(u32 verb_table_bytes, + const u32 *verb_table_data, + u32 viddid, const u32 ** verb) +{ + int idx=0; + + while (idx < (verb_table_bytes / sizeof(u32))) { + u32 verb_size = 4 * verb_table_data[idx+2]; // in u32 + if (verb_table_data[idx] != viddid) { + idx += verb_size + 3; // skip verb + header + continue; + } + *verb = &verb_table_data[idx+3]; + return verb_size; + } + + /* Not all codecs need to load another verb */ + return 0; +} + +/** + * Write a supplied verb table + */ +int hda_codec_write(u32 base, u32 size, const u32 *data) +{ + int i; + + for (i = 0; i < size; i++) { + if (hda_wait_for_ready(base) < 0) + return -1; + + write32(base + HDA_IC_REG, data[i]); + + if (hda_wait_for_valid(base) < 0) + return -1; + } + + return 0; +} + +/** + * Initialize codec, then find the verb table and write it + */ +int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data) +{ + const u32 *verb; + u32 reg32, size; + int rc; + + printk(BIOS_DEBUG, "HDA: Initializing codec #%d\n", addr); + + if (!verb_size || !verb_data) { + printk(BIOS_DEBUG, "HDA: No verb list!\n"); + return -1; + } + + /* 1 */ + if (hda_wait_for_ready(base) < 0) { + printk(BIOS_DEBUG, " codec not ready.\n"); + return -1; + } + + reg32 = (addr << 28) | 0x000f0000; + write32(base + HDA_IC_REG, reg32); + + if (hda_wait_for_valid(base) < 0) { + printk(BIOS_DEBUG, " codec not valid.\n"); + return -1; + } + + /* 2 */ + reg32 = read32(base + HDA_IR_REG); + printk(BIOS_DEBUG, "HDA: codec viddid: %08x\n", reg32); + + size = hda_find_verb(verb_size, verb_data, reg32, &verb); + if (!size) { + printk(BIOS_DEBUG, "HDA: No verb table entry found\n"); + return -1; + } + + /* 3 */ + rc = hda_codec_write(base, size, verb); + + if (rc < 0) + printk(BIOS_DEBUG, "HDA: verb not loaded\n"); + else + printk(BIOS_DEBUG, "HDA: verb loaded.\n"); + + return rc; +} diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 24daf55..581f42b 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -18,12 +18,18 @@ */ #include <arch/io.h> +#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <reg_script.h> #include <baytrail/iomap.h> +#include <baytrail/iosf.h> +#include <baytrail/lpc.h> +#include <baytrail/nvs.h> +#include <baytrail/pattrs.h> #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> #include <baytrail/ramstage.h> @@ -34,8 +40,52 @@ * address. Just take 1MiB @ 512MiB. */ #define FIRMWARE_PHYS_BASE (512 << 20) #define FIRMWARE_PHYS_LENGTH (1 << 20) -#define FIRMWARE_REG_BASE 0xa8 -#define FIRMWARE_REG_LENGTH 0xac +#define FIRMWARE_PCI_REG_BASE 0xa8 +#define FIRMWARE_PCI_REG_LENGTH 0xac +#define FIRMWARE_REG_BASE_C0 0x144000 +#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) + +static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +{ + struct resource *res; + + res = find_resource(dev, index); + if (res) + *field = res->base; +} + +static void lpe_enable_acpi_mode(device_t dev) +{ + static const struct reg_script ops[] = { + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, + LPE_PCICFGCTR1_PCI_CFG_DIS | + LPE_PCICFGCTR1_ACPI_INT_EN), + REG_SCRIPT_END + }; + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0, BAR1, and firmware base to ACPI NVS */ + assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); + assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); + assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); + + /* Device is enabled in ACPI mode */ + gnvs->dev.lpe_en = 1; + + /* Put device in ACPI mode */ + reg_script_run_on_dev(dev, ops); +} static void setup_codec_clock(device_t dev) { @@ -75,38 +125,54 @@ static void setup_codec_clock(device_t dev) write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } +static void lpe_stash_firmware_info(device_t dev) +{ + struct resource *res; + struct resource *mmio; + const struct pattrs *pattrs = pattrs_get(); + + res = find_resource(dev, FIRMWARE_PCI_REG_BASE); + if (res == NULL) { + printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); + return; + } + + /* Continue using old way of informing firmware address / size. */ + pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); + pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); + + /* C0 and later steppings use an offset in the MMIO space. */ + if (pattrs->stepping >= STEP_C0) { + mmio = find_resource(dev, PCI_BASE_ADDRESS_0); + write32(mmio->base + FIRMWARE_REG_BASE_C0, res->base); + write32(mmio->base + FIRMWARE_REG_LENGTH_C0, res->size); + } +} + static void lpe_init(device_t dev) { + struct soc_intel_baytrail_config *config = dev->chip_info; + + lpe_stash_firmware_info(dev); + setup_codec_clock(dev); + + if (config->lpe_acpi_mode) + lpe_enable_acpi_mode(dev); } static void lpe_read_resources(device_t dev) { pci_dev_read_resources(dev); - reserved_ram_resource(dev, FIRMWARE_REG_BASE, + reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE >> 10, FIRMWARE_PHYS_LENGTH >> 10); } -static void lpe_set_resources(device_t dev) -{ - struct resource *res; - - pci_dev_set_resources(dev); - - res = find_resource(dev, FIRMWARE_REG_BASE); - if (res == NULL) { - printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); - return; - } - pci_write_config32(dev, FIRMWARE_REG_BASE, res->base); - pci_write_config32(dev, FIRMWARE_REG_LENGTH, res->size); -} - static const struct device_operations device_ops = { .read_resources = lpe_read_resources, - .set_resources = lpe_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpe_init, .enable = NULL, diff --git a/src/soc/intel/baytrail/microcode/M0C3068_00000808.h b/src/soc/intel/baytrail/microcode/M0C3068_00000808.h deleted file mode 100644 index 90e879e..0000000 --- a/src/soc/intel/baytrail/microcode/M0C3068_00000808.h +++ /dev/null @@ -1,12800 +0,0 @@ -0x000000001, -0x000000808, -0x012192013, -0x000030678, -0x074029804, -0x000000001, -0x00000000c, -0x00000c7d0, -0x00000c800, -0x000000000, -0x000000000, -0x000000000, -0x000000000, -0x0000000a1, -0x000020001, -0x000000808, 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+0x033e588ac, +0x044e6a54d, +0x097ea7cbc, +0x0fd268ffc, +0x0ad1057d3, +0x0a620c30c, +0x0d55bd51b, +0x01e9a624c, +0x03b65b3af, +0x03b1103d3, +0x0f36dac3a, +0x075d1cd18, +0x0762dbfad, +0x02ba7ac2d, +0x02048d012, +0x00b0105f2, +0x0f0922446, +0x0980859cf, +0x0a98d0106, +0x01da79f70, +0x0e4732a10, +0x033a56fb2, +0x00620759a, +0x08991fbf0, +0x0c2b9f566, +0x0bfc02f28, +0x0965eae5f, +0x052a0ade5, +0x0d3f3263a, +0x02915166d, +0x0ad54a16f, +0x0e4a51b57, +0x0f204112c, +0x01bbd9c4b, +0x03fc0e950, +0x0a0ed5d96, +0x01815d23c, +0x03037f836, +0x0b1657293, +0x0a5997409, +0x0fb42864d, +0x0f63e152a, +0x02458c4b3, +0x01cc0c532, +0x0e0525e21, +0x0fa659a49, +0x0185f582f, +0x034f60f6f, +0x029512785, +0x07fdfa2fe, +0x01ba6dbb8, +0x04793286c, +0x060c8a906, +0x0b44f2fcd, +0x01a966cce, +0x082778ea0, +0x01a34ec33, +0x0e91e88f5, +0x0aa9c3a91, +0x03d0306c5, +0x05390ba4a, +0x06c47c818, +0x08aa62865, +0x09f2bb8cb, +0x0ad146079, +0x0ea2fb56d, +0x085358978, +0x02887b115, +0x0616d7a80, +0x0b8c31679, +0x013c0d624, +0x07ca847b9, +0x042a0777b, +0x0371aa20e, +0x0e7c491fb, +0x04b04a37c, +0x0879e8afe, +0x05bbcaba4, +0x0c1b007d7, +0x0b049b805, +0x0b0aa9d74, +0x01992611b, +0x019e336e6, +0x002c51547, +0x08c626122, +0x04910a3cb, +0x0f9eab2ba, +0x011be92fb, +0x0b9d8b14d, +0x01456bb60, +0x0d542dd59, +0x005373f9c, +0x02ae04058, +0x0a2685ac1, +0x071ccbf09, +0x0bf29cf36, +0x0382e2017, +0x038d65080, +0x02d0309b4, +0x0a23966cf, +0x053fa6cfd, +0x0b81df379, +0x0493cb602, +0x0325f736b, +0x08f304e73, +0x061e18ea2, +0x073e062f0, +0x0451fee6c, +0x035dbda8d, +0x046809af3, +0x08872f13e, +0x05a047bba, +0x0c18df364, +0x037b9f254, +0x0e0777def, +0x04f46b1e5, +0x0883fe357, +0x0fdee1972, +0x0372e1f64, +0x096b6999e, +0x0314455a3, +0x053b70ac7, +0x0e33c4bc9, +0x0c74e1f64, +0x06ea747af, +0x0ca7171a1, +0x0eb336239, +0x04b1021ed, +0x052a52882, +0x0f6ea1f29, +0x04d0e0a93, +0x09c38ce8a, +0x0abe2019a, +0x0e3bbbc1c, +0x0b4d20602, +0x016e73795, +0x08cae088a, +0x01e1b7d43, +0x0d796233f, +0x09a67cb87, +0x01319264b, +0x0b889a538, +0x0956e0fd8, +0x0ad14b74d, +0x06da9bdc0, +0x0f69833ed, +0x0654dd802, +0x0f5830f30, +0x0c81ffb88, +0x070eee5c2, +0x079c70279, +0x0d8a65893, +0x0acfa6398, +0x0ef8a890d, +0x0b7d09f00, +0x066f30070, +0x0d83519c6, +0x07594d01f, +0x0d278d570, +0x0cb7b6f2f, +0x07fbce02a, +0x05a91916a, +0x0a605057e, +0x07272b57c, +0x0315c6c77, +0x0a020959f, +0x0db47f6aa, +0x0856160eb, +0x0f25a51a8, +0x0016e0628, +0x05a0402ea, +0x0250ed6a8, +0x075757cde, +0x042923a1b, +0x010d400bc, +0x0c6d21368, +0x0e33779c0, +0x0d6ab5c7a, +0x03183f426, +0x096cee925, +0x0476900ab, +0x082a2eb8d, +0x03fa66597, +0x076a67f52, +0x090b4fe45, +0x0219cee8c, +0x06c404cc9, +0x0972ff755, +0x0e1b4fdb2, +0x071ca1662, +0x0e60f043a, +0x0260a85cd, +0x0547f5609, +0x0440a7b30, +0x062465349, +0x0617f95ab, +0x0f8804b93, +0x0ced794e2, +0x04df24aa9, +0x0ab5e781c, +0x01aee3538, +0x0bf364342, +0x04e150596, +0x0db277447, +0x001fbe86f, +0x0cbf438fe, +0x0ecbdeff9, +0x085b7e1a3, +0x02c66a4e0, +0x04f76dd76, +0x06fefdb81, +0x0067dda68, +0x0bbad69a0, +0x0a39d22be, +0x04e6bc4f9, +0x05d01be22, +0x090f3fbb1, +0x0dc25b922, +0x07591f31d, +0x014f3fc26, +0x0c81a5b22, +0x0e37cf8f1, +0x073a57cc9, +0x00bf26904, +0x0b634f5a1, +0x087f2d0c1, +0x0ab6b71ba, +0x0f711c3c2, +0x097075cf3, +0x0f0e5ed8b, +0x0f9e2d4eb, +0x03268bde5, +0x0785b5758, +0x0c6aa3a40, +0x002fd63db, +0x0732db9fe, +0x001a65a9c, +0x043875705, +0x09fb028a2, +0x064101c44, +0x0517a1549, +0x0c2536e8b, +0x02cc97f8b, +0x0c6c0b81f, +0x0ba49e820, +0x0585cae8c, +0x0b54e7571, +0x0d1e80340, +0x0491f2f83, +0x06329a210, +0x0c15cf2a9, +0x0cbac617c, +0x0acc6bf82, +0x0bb5fa672, +0x0b99d3323, +0x0b3258254, +0x0cb705d96, +0x01a518bc7, +0x0cb565bb6, +0x0c76c4be2, +0x0736e7a23, +0x068c82a1b, +0x0904c0288, +0x046f41ccd, +0x075b969da, +0x07b2002cd, +0x019affc03, +0x0b64bfbe6, +0x0e7e6deb3, +0x01b205623, +0x032c312ea, +0x038080b9c, +0x0ae617e3c, +0x07979f54f, +0x05612aeeb, +0x0eddcdf5b, +0x0b065c808, +0x0d39eba9d, +0x023fd6c12, +0x01b109a29, +0x0ad2b3905, +0x00abd1493, +0x03aca4092, +0x0c41cceb6, +0x06cf04a7b, +0x0ea9da8d8, +0x0d753e29c, +0x0366ee0a0, +0x0f77f22ca, +0x072321684, +0x05f51f15f, +0x0c913b25a, +0x0327ba842, +0x072b470df, +0x0adcb73c2, +0x00b2f75ed, +0x08ff9320a, +0x074374ab9, +0x007da44e9, +0x09462ae12, +0x0a24b8d58, +0x0caf9694d, +0x079348b5f, +0x03f145936, +0x0f20714a4, +0x0d8196462, +0x0b5429ce4, +0x0da94dcb6, +0x0f052e0fc, +0x0a134377f, +0x02e20bc6a, +0x0274ab0bb, +0x0547ffcd0, +0x0f427b3c6, +0x09507a811, +0x056b1a42e, +0x0dd4dda39, +0x0cdf0d0cd, +0x0370e385b, +0x08d371c63, +0x03d69c1b3, +0x0b80c102f, +0x03791a8ac, +0x00eef0952, +0x033dea3a9, +0x06b866cd4, diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c index 74f7beb..d127142 100644 --- a/src/soc/intel/baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/baytrail/microcode/microcode_blob.c @@ -1,4 +1,4 @@ unsigned microcode[] = { #include "M0C3067_0000031E.h" -#include "M0C3068_00000808.h" +#include "M0C3068_00000809.h" }; diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 5d37a13..aee3726 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -358,7 +358,7 @@ void clear_pmc_status(void) prsts = read32(PMC_BASE_ADDRESS + PRSTS); gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); - /* Clear the status bits. */ - write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1); + /* Clear the status bits. The RPS field is cleared on a 0 write. */ + write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS); write32(PMC_BASE_ADDRESS + PRSTS, prsts); } diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9fe6c27..e8f441f 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -36,6 +36,7 @@ #include <baytrail/nvs.h> #include <baytrail/pattrs.h> #include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> #include <baytrail/ramstage.h> /* Global PATTRS */ @@ -71,7 +72,9 @@ static inline void fill_in_msr(msr_t *msr, int idx) } } -static const char *stepping_str[] = { "A0", "A1", "B0", "B1", "B2", "B3" }; +static const char *stepping_str[] = { + "A0", "A1", "B0", "B1", "B2", "B3", "C0" +}; static void fill_in_pattrs(void) { @@ -83,7 +86,10 @@ static void fill_in_pattrs(void) dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); attrs->revid = pci_read_config8(dev, REVID); /* The revision to stepping IDs have two values per metal stepping. */ - if (attrs->revid >= RID_B_STEPPING_START) { + if (attrs->revid >= RID_C_STEPPING_START) { + attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; + attrs->stepping += STEP_C0; + } else if (attrs->revid >= RID_B_STEPPING_START) { attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; attrs->stepping += STEP_B0; } else { @@ -131,6 +137,32 @@ static inline void set_acpi_sleep_type(int val) #endif } +/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ +static void s3_save_acpi_wake_source(global_nvs_t *gnvs) +{ + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + uint16_t pm1; + + if (!ps) + return; + + pm1 = ps->pm1_sts & ps->pm1_en; + + /* Scan for first set bit in PM1 */ + for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) { + if (pm1 & 1) + break; + pm1 >>= 1; + } + + /* If unable to determine then return -1 */ + if (gnvs->pm1i >= 16) + gnvs->pm1i = -1; + + printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n", + gnvs->pm1i); +} + static void s3_resume_prepare(void) { global_nvs_t *gnvs; @@ -148,6 +180,8 @@ static void s3_resume_prepare(void) } set_acpi_sleep_type(3); + + s3_save_acpi_wake_source(gnvs); } void baytrail_init_pre_device(void) diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 49a8011..c58a42c 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -19,11 +19,16 @@ #include <stddef.h> #include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> #include <baytrail/iomap.h> #include <baytrail/iosf.h> +#include <baytrail/lpc.h> #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> #include <baytrail/romstage.h> +#include "../chip.h" void tco_disable(void) { @@ -38,13 +43,34 @@ void tco_disable(void) void punit_init(void) { uint32_t reg; + uint8_t rid; + const struct device *dev; + const struct soc_intel_baytrail_config *cfg = NULL; + rid = pci_read_config8(IOSF_PCI_DEV, REVID); + dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)); + + if (dev) + cfg = dev->chip_info; + + reg = iosf_punit_read(SB_BIOS_CONFIG); /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ - reg = SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; - pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); - reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | - IOSF_REG(SB_BIOS_CONFIG) | IOSF_BYTE_EN_2; - pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); + reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; + /* Configure VR low power mode for C0 and above. */ + if (rid >= RID_C_STEPPING_START && cfg != NULL && + (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) { + printk(BIOS_DEBUG, "Enabling VR PS2 mode: "); + if (cfg->vnn_ps2_enable) { + reg |= SB_BIOS_CONFIG_PS2_EN_VNN; + printk(BIOS_DEBUG, "VNN "); + } + if (cfg->vcc_ps2_enable) { + reg |= SB_BIOS_CONFIG_PS2_EN_VCC; + printk(BIOS_DEBUG, "VCC "); + } + printk(BIOS_DEBUG, "\n"); + } + iosf_punit_write(SB_BIOS_CONFIG, reg); /* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE; diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 752a49b..a18f312 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -121,6 +121,11 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) mp->console_out = &send_to_console; mp->prev_sleep_state = prev_sleep_state; mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); + + /* Default to 2GiB IO hole. */ + if (!mp->io_hole_mb) + mp->io_hole_mb = 2048; + if (recovery_mode_enabled()) { printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); } else if (!mrc_cache_get_current(&cache)) { diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index b7cf4e5..bcce792 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -20,10 +20,12 @@ #include <stdint.h> #include <arch/io.h> +#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include <baytrail/iomap.h> @@ -33,6 +35,7 @@ #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> #include <baytrail/ramstage.h> +#include "chip.h" static inline void add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) @@ -117,13 +120,36 @@ static void sc_read_resources(device_t dev) sc_add_io_resources(dev); } +static void sc_rtc_init(void) +{ + uint32_t gen_pmcon1; + int rtc_fail; + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps != NULL) { + gen_pmcon1 = ps->gen_pmcon1; + } else { + gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + } + + rtc_fail = !!(gen_pmcon1 & RPS); + + if (rtc_fail) { + printk(BIOS_DEBUG, "RTC failure.\n"); + } + + rtc_init(rtc_fail); +} + static void sc_init(device_t dev) { int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + const unsigned long gen_pmcon1 = PMC_BASE_ADDRESS + GEN_PMCON1; const unsigned long actl = ILB_BASE_ADDRESS + ACTL; const struct baytrail_irq_route *ir = &global_baytrail_irq_route; + struct soc_intel_baytrail_config *config = dev->chip_info; /* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) { @@ -136,6 +162,17 @@ static void sc_init(device_t dev) /* Route SCI to IRQ9 */ write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); + + sc_rtc_init(); + + if (config->disable_slp_x_stretch_sus_fail) { + printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); + write32(gen_pmcon1, + read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); + } else { + write32(gen_pmcon1, + read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); + } } /* diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index e3facb9..8d076c2 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/acpi.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -86,10 +87,6 @@ const struct reg_script xhci_init_script[] = { REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), /* BAR + 0x8060[25]=1b */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), - /* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040), - /* BAR + 0x80e0 toggle bit 24=0 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0), /* BAR + 0x80f0[20]=0b */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0), /* BAR + 0x8008[19]=1b (to enable LPM) */ @@ -110,6 +107,28 @@ const struct reg_script xhci_init_script[] = { REG_SCRIPT_END }; +const struct reg_script xhci_init_boot_script[] = { + /* Setup USB3 phy */ + REG_SCRIPT_NEXT(usb3_phy_script), + /* Initialize host controller */ + REG_SCRIPT_NEXT(xhci_init_script), + /* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040), + /* BAR + 0x80e0 toggle bit 24=0 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0), + REG_SCRIPT_END +}; + +const struct reg_script xhci_init_resume_script[] = { + /* Setup USB3 phy */ + REG_SCRIPT_NEXT(usb3_phy_script), + /* Initialize host controller */ + REG_SCRIPT_NEXT(xhci_init_script), + /* BAR + 0x80e0[16,9,6]=001b, leave bit 24=0 to prevent HC reset */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01010200, 0x00000040), + REG_SCRIPT_END +}; + const struct reg_script xhci_clock_gating_script[] = { /* ConfigureXhciClockGating() */ /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ @@ -165,6 +184,9 @@ static void xhci_route_all(device_t dev) /* Route ports to XHCI controller */ reg_script_run_on_dev(dev, xhci_route_all_script); + if (acpi_slp_type == 3) + return; + /* Reset enabled USB3 ports */ port_disabled = pci_read_config32(dev, XHCI_USB3PDO); for (port = 0; port < BYTM_USB3_PORT_COUNT; port++) { @@ -178,10 +200,6 @@ static void xhci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { - /* Setup USB3 phy */ - REG_SCRIPT_NEXT(usb3_phy_script), - /* Initialize host controller */ - REG_SCRIPT_NEXT(xhci_init_script), /* Initialize clock gating */ REG_SCRIPT_NEXT(xhci_clock_gating_script), /* Finalize XHCC1 and XHCC2 */ @@ -203,7 +221,13 @@ static void xhci_init(device_t dev) REG_SCRIPT_END }; - /* Initialize XHCI controller */ + /* Initialize XHCI controller for boot or resume path */ + if (acpi_slp_type == 3) + reg_script_run_on_dev(dev, xhci_init_resume_script); + else + reg_script_run_on_dev(dev, xhci_init_boot_script); + + /* Finalize Initialization */ reg_script_run_on_dev(dev, xhci_hc_init); /* Route all ports to XHCI if requested */

1 0

New patch to review for coreboot: e6ecc42 coreboot arm64: Add support for arm64 into coreboot framework
by Isaac Christensen 16 Sep '14

16 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6915 -gerrit commit e6ecc42e3636de22d2e68ec233928dddeea6cbb5 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Apr 28 16:39:40 2014 -0700 coreboot arm64: Add support for arm64 into coreboot framework Add support for enabling different coreboot stages (bootblock, romstage and ramstage) to have arm64 architecture. Most of the files have been copied over from arm/ or arm64-generic work. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/197397 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 033ba96516805502673ac7404bc97e6ce4e2a934) This patch is essentially a squash of aarch64 changes made by these patches: d955885 coreboot: Rename coreboot_ram stage to ramstage a492761 cbmem console: Locate the preram console with a symbol instead of a sect 96e7f0e aarch64: Enable early icache and migrate SCTLR from EL3 3f854dc aarch64: Pass coreboot table in jmp_to_elf_entry ab3ecaf aarch64/foundation-armv8: Set up RAM area and enter ramstage 25fd2e9 aarch64: Remove CAR definitions from early_variables.h 65bf77d aarch64/foundation-armv8: Enable DYNAMIC_CBMEM 9484873 aarch64: Change default exception level to EL2 7a152c3 aarch64: Fix formatting of exception registers dump 6946464 aarch64: Implement basic exception handling c732a9d aarch64/foundation-armv8: Basic bootblock implementation 3bc412c aarch64: Comment out some parts of code to allow build ab5be71 Add initial aarch64 support Change-Id: Icd59bec55c963a471a50e30972a8092e4c9d2fb2 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- Makefile.inc | 5 +- src/Kconfig | 6 + src/arch/arm64/Kconfig | 14 ++ src/arch/arm64/Makefile.inc | 137 ++++++++++++++ src/arch/arm64/armv8/Kconfig | 9 + src/arch/arm64/armv8/Makefile.inc | 74 ++++++++ src/arch/arm64/armv8/bootblock.S | 101 ++++++++++ src/arch/arm64/armv8/bootblock_simple.c | 73 +++++++ src/arch/arm64/armv8/cache.c | 148 +++++++++++++++ src/arch/arm64/armv8/cpu.S | 131 +++++++++++++ src/arch/arm64/armv8/exception.c | 129 +++++++++++++ src/arch/arm64/armv8/exception_asm.S | 103 ++++++++++ src/arch/arm64/boot.c | 33 ++++ src/arch/arm64/bootblock.ld | 59 ++++++ src/arch/arm64/cbmem.c | 30 +++ src/arch/arm64/cpu.c | 42 +++++ src/arch/arm64/div0.c | 33 ++++ src/arch/arm64/eabi_compat.c | 28 +++ src/arch/arm64/early_console.c | 75 ++++++++ src/arch/arm64/id.S | 20 ++ src/arch/arm64/include/arch/asm.h | 38 ++++ src/arch/arm64/include/arch/boot/boot.h | 8 + src/arch/arm64/include/arch/byteorder.h | 27 +++ src/arch/arm64/include/arch/early_variables.h | 35 ++++ src/arch/arm64/include/arch/hlt.h | 9 + src/arch/arm64/include/arch/io.h | 137 ++++++++++++++ src/arch/arm64/include/arch/pci_ops.h | 29 +++ src/arch/arm64/include/arch/stages.h | 29 +++ src/arch/arm64/include/armv8/arch/barrier.h | 52 +++++ src/arch/arm64/include/armv8/arch/cache.h | 262 ++++++++++++++++++++++++++ src/arch/arm64/include/armv8/arch/cpu.h | 52 +++++ src/arch/arm64/include/armv8/arch/exception.h | 38 ++++ src/arch/arm64/include/armv8/arch/rules.h | 34 ++++ src/arch/arm64/include/bootblock_common.h | 11 ++ src/arch/arm64/include/clocks.h | 44 +++++ src/arch/arm64/include/smp/spinlock.h | 6 + src/arch/arm64/include/stdint.h | 60 ++++++ src/arch/arm64/memcpy.S | 52 +++++ src/arch/arm64/memmove.S | 55 ++++++ src/arch/arm64/memset.S | 52 +++++ src/arch/arm64/ramstage.ld | 136 +++++++++++++ src/arch/arm64/romstage.ld | 89 +++++++++ src/arch/arm64/stages.c | 53 ++++++ src/arch/arm64/tables.c | 83 ++++++++ src/arch/arm64/timestamp.c | 29 +++ toolchain.inc | 3 + util/cbfstool/common.c | 2 +- 47 files changed, 2673 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index c41945a..382eead 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -68,7 +68,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs subdirs-y := src/lib src/console src/device src/ec src/southbridge src/soc subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool -subdirs-y += src/arch/arm src/arch/x86 +subdirs-y += src/arch/arm src/arch/arm64 src/arch/x86 subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += site-local @@ -565,6 +565,9 @@ bootsplash.jpg-type := bootsplash ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y) ROMSTAGE_ELF := romstage.elf endif +ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) +ROMSTAGE_ELF := romstage.elf +endif ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) ROMSTAGE_ELF := romstage_xip.elf endif diff --git a/src/Kconfig b/src/Kconfig index 327e1bf..afcaab6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -214,8 +214,13 @@ config ARCH_ARM bool default n +config ARCH_ARM64 + bool + default n + source src/arch/x86/Kconfig source src/arch/arm/Kconfig +source src/arch/arm64/Kconfig source src/vendorcode/Kconfig @@ -274,6 +279,7 @@ config TPM default n select LPC_TPM if ARCH_X86 select I2C_TPM if ARCH_ARM + select I2C_TPM if ARCH_ARM64 help Enable this option to enable TPM support in coreboot. diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig new file mode 100644 index 0000000..dc0e332 --- /dev/null +++ b/src/arch/arm64/Kconfig @@ -0,0 +1,14 @@ +config ARCH_BOOTBLOCK_ARM64 + bool + default n + select ARCH_ARM64 + +config ARCH_ROMSTAGE_ARM64 + bool + default n + +config ARCH_RAMSTAGE_ARM64 + bool + default n + +source src/arch/arm64/armv8/Kconfig diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc new file mode 100644 index 0000000..64370d4 --- /dev/null +++ b/src/arch/arm64/Makefile.inc @@ -0,0 +1,137 @@ +################################################################################ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2012-2013 The ChromiumOS Authors +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## Copyright (C) 2009-2010 coresystems GmbH +## Copyright (C) 2009 Ronald G. Minnich +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +################################################################################ + +################################################################################ +# Take care of subdirectories +################################################################################ + +subdirs-y += armv8/ + +################################################################################ +# ARM specific options +################################################################################ + +ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) +CBFSTOOL_PRE1_OPTS = -m arm64 -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET) +endif + +################################################################################ +# bootblock +################################################################################ + +ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM64),y) + +bootblock-y += div0.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c + +bootblock-y += id.S +$(obj)/arch/arm64/id.bootblock.o: $(obj)/build.h + +bootblock-y += stages.c +bootblock-y += eabi_compat.c + +bootblock-y += memset.S +bootblock-y += memcpy.S +bootblock-y += memmove.S + +# Build the bootblock + +$(objcbfs)/bootblock.debug: $(src)/arch/arm64/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $(obj)/config.h + @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD_bootblock) -nostdlib -m armelf_linux_eabi --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/arm64/bootblock.ld +else + $(CC_bootblock) $(CFLAGS_bootblock) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm64/bootblock.ld -Wl,--start-group $(bootblock-objs) -Wl,--end-group +endif + +endif # CONFIG_ARCH_BOOTBLOCK_ARM64 + +################################################################################ +# romstage +################################################################################ + +ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) + +romstage-y += stages.c +romstage-y += div0.c +romstage-y += early_console.c +romstage-y += eabi_compat.c +romstage-y += memset.S +romstage-y += memcpy.S +romstage-y += memmove.S +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c + +# Build the romstage + +$(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm64/romstage.ld $(obj)/ldoptions + @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/arm64/romstage.ld +else + $(CC_romstage) $(CFLAGS_romstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm64/romstage.ld -Wl,--start-group $(romstage-objs) -Wl,--end-group +endif + +endif # CONFIG_ARCH_ROMSTAGE_ARM64 + +################################################################################ +# ramstage +################################################################################ + +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) + +ramstage-y += stages.c +ramstage-y += div0.c +ramstage-y += cpu.c +ramstage-y += eabi_compat.c +ramstage-y += boot.c +ramstage-y += tables.c +ramstage-y += memset.S +ramstage-y += memcpy.S +ramstage-y += memmove.S + +rmodules_$(ARCH-ramstage-y) += memset.S +rmodules_$(ARCH-ramstage-y) += memcpy.S +rmodules_$(ARCH-ramstage-y) += memmove.S +rmodules_$(ARCH-ramstage-y) += eabi_compat.c + +VBOOT_STUB_DEPS += $(obj)/arch/arm64/eabi_compat.rmodules.o + +$(eval $(call create_class_compiler,rmodules,arm64)) + +ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c + +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c + +# Build the ramstage + +$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm64/ramstage.ld $(obj)/ldoptions + @printf " CC $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD_ramstage) -nostdlib -m armelf_linux_eabi --gc-sections -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm64/ramstage.ld +else + $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) -Wl,--end-group -T $(src)/arch/arm64/ramstage.ld +endif + +endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig new file mode 100644 index 0000000..fc2e668 --- /dev/null +++ b/src/arch/arm64/armv8/Kconfig @@ -0,0 +1,9 @@ +config ARCH_BOOTBLOCK_ARM_V8_64 + def_bool n + select ARCH_BOOTBLOCK_ARM64 +config ARCH_ROMSTAGE_ARM_V8_64 + def_bool n + select ARCH_ROMSTAGE_ARM64 +config ARCH_RAMSTAGE_ARM_V8_64 + def_bool n + select ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc new file mode 100644 index 0000000..973b391 --- /dev/null +++ b/src/arch/arm64/armv8/Makefile.inc @@ -0,0 +1,74 @@ +################################################################################ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 The ChromiumOS Authors +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +################################################################################ + +armv8_flags = -march=armv8-a -I$(src)/arch/arm64/include/armv8/ -D__COREBOOT_ARM_ARCH__=8 + +armv8_asm_flags = $(armv8_flags) + +################################################################################ +## bootblock +################################################################################ +ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM_V8_64),y) + +ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y) +bootblock-y += bootblock.S +endif +bootblock-$(CONFIG_ARM_BOOTBLOCK_SIMPLE) += bootblock_simple.c +bootblock-$(CONFIG_ARM_BOOTBLOCK_NORMAL) += bootblock_normal.c +bootblock-y += cache.c +bootblock-y += cpu.S +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception.c +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception_asm.S + +bootblock-c-ccopts += $(armv8_flags) +bootblock-S-ccopts += $(armv8_asm_flags) + +endif + +################################################################################ +## romstage +################################################################################ +ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM_V8_64),y) + +romstage-y += cache.c +romstage-y += cpu.S +romstage-y += exception.c +romstage-y += exception_asm.S + +romstage-c-ccopts += $(armv8_flags) +romstage-S-ccopts += $(armv8_asm_flags) + +endif + +################################################################################ +## ramstage +################################################################################ +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM_V8_64),y) + +ramstage-y += cache.c +ramstage-y += cpu.S +ramstage-y += exception.c +ramstage-y += exception_asm.S + +ramstage-c-ccopts += $(armv8_flags) +ramstage-S-ccopts += $(armv8_asm_flags) + +endif diff --git a/src/arch/arm64/armv8/bootblock.S b/src/arch/arm64/armv8/bootblock.S new file mode 100644 index 0000000..e65515f --- /dev/null +++ b/src/arch/arm64/armv8/bootblock.S @@ -0,0 +1,101 @@ +/* + * Early initialization code for aarch64 (a.k.a. armv8) + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.section ".start", "a", %progbits +.globl _start +_start: b reset + .balignl 16,0xdeadbeef + +_cbfs_master_header: + /* The CBFS master header is inserted by cbfstool at the first + * aligned offset after the above anchor string is found. + * Hence, we leave some space for it. + * Assumes 64-byte alignment. + */ + .skip 128 + +reset: + /* + * Set the cpu to SVC32 mode and unmask aborts. Aborts might happen + * before logging is turned on and may crash the machine, but at least + * the problem will show up near the code that causes it. + */ + /* FIXME: Not using supervisor mode, does it apply for aarch64? */ + + msr daifclr, #0xc /* Unmask Debug and System exceptions */ + msr daifset, #0x3 /* Mask IRQ, FIQ */ + + bl arm_init_caches + + /* + * Initialize the stack to a known value. This is used to check for + * stack overflow later in the boot process. + */ + ldr x0, .Stack + ldr x1, .Stack_size + sub x0, x0, x1 + ldr x1, .Stack + ldr x2, =0xdeadbeefdeadbeef +init_stack_loop: + str x2, [x0] + add x0, x0, #8 + cmp x0, x1 + bne init_stack_loop + +/* Set stackpointer in internal RAM to call bootblock main() */ +call_bootblock: + ldr x0, .Stack /* Set up stack pointer */ + mov sp, x0 + ldr x0, =0x00000000 + + sub sp, sp, #16 + + /* + * Switch to EL2 already because Linux requires to be + * in EL1 or EL2, see its "Booting AArch64 Linux" doc + */ + bl switch_el3_to_el2 + bl main + +.align 3 +.Stack: + .word CONFIG_STACK_TOP +.align 3 +.Stack_size: + .word CONFIG_STACK_SIZE + .section ".id", "a", %progbits + + .globl __id_start +__id_start: +ver: + .asciz COREBOOT_VERSION +vendor: + .asciz CONFIG_MAINBOARD_VENDOR +part: + .asciz CONFIG_MAINBOARD_PART_NUMBER +.long __id_end - ver /* Reverse offset to the vendor id */ +.long __id_end - vendor /* Reverse offset to the vendor id */ +.long __id_end - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ + .globl __id_end + +__id_end: +.previous diff --git a/src/arch/arm64/armv8/bootblock_simple.c b/src/arch/arm64/armv8/bootblock_simple.c new file mode 100644 index 0000000..d8339d1 --- /dev/null +++ b/src/arch/arm64/armv8/bootblock_simple.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <bootblock_common.h> +#include <arch/cache.h> +#include <arch/hlt.h> +#include <arch/stages.h> +#include <arch/exception.h> +#include <cbfs.h> +#include <console/console.h> + +static int boot_cpu(void) +{ + /* + * FIXME: This is a stub for now. All non-boot CPUs should be + * waiting for an interrupt. We could move the chunk of assembly + * which puts them to sleep in here... + */ + return 1; +} + +void main(void) +{ + const char *stage_name = CONFIG_CBFS_PREFIX"/romstage"; + void *entry = NULL; + + /* Globally disable MMU, caches, and branch prediction (these should + * be disabled by default on reset) */ + dcache_mmu_disable(); + + /* + * Re-enable icache and branch prediction. MMU and dcache will be + * set up later. + * + * Note: If booting from USB, we need to disable branch prediction + * before copying from USB into RAM (FIXME: why?) + */ + + if (boot_cpu()) { + //bootblock_cpu_init(); + //bootblock_mainboard_init(); + } + +#ifdef CONFIG_BOOTBLOCK_CONSOLE + console_init(); + exception_init(); +#endif + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name); + + printk(BIOS_SPEW, "stage_name %s, entry %p\n", stage_name, entry); + + if (entry) stage_exit(entry); + hlt(); +} diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c new file mode 100644 index 0000000..a0eff46 --- /dev/null +++ b/src/arch/arm64/armv8/cache.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.c: Cache maintenance routines for ARMv8 (aarch64) + * + * Reference: ARM Architecture Reference Manual, ARMv8-A edition + */ + +#include <stdint.h> + +#include <arch/cache.h> + +void tlb_invalidate_all(void) +{ + /* TLBIALL includes dTLB and iTLB on systems that have them. */ + tlbiall(current_el()); + dsb(); + isb(); +} + +unsigned int dcache_line_bytes(void) +{ + uint32_t ccsidr; + static unsigned int line_bytes = 0; + + if (line_bytes) + return line_bytes; + + ccsidr = read_ccsidr(); + /* [2:0] - Indicates (Log2(number of words in cache line)) - 4 */ + line_bytes = 1 << ((ccsidr & 0x7) + 4); /* words per line */ + line_bytes *= sizeof(uint32_t); /* bytes per word */ + + return line_bytes; +} + +enum dcache_op { + OP_DCCSW, + OP_DCCISW, + OP_DCISW, + OP_DCCIVAC, + OP_DCCVAC, + OP_DCIVAC, +}; + +/* + * Do a dcache operation by virtual address. This is useful for maintaining + * coherency in drivers which do DMA transfers and only need to perform + * cache maintenance on a particular memory range rather than the entire cache. + */ +static void dcache_op_va(void const *addr, size_t len, enum dcache_op op) +{ + uint64_t line, linesize; + + linesize = dcache_line_bytes(); + line = (uint64_t)addr & ~(linesize - 1); + + dsb(); + while ((void *)line < addr + len) { + switch(op) { + case OP_DCCIVAC: + dccivac(line); + break; + case OP_DCCVAC: + dccvac(line); + break; + case OP_DCIVAC: + dcivac(line); + break; + default: + break; + } + line += linesize; + } + isb(); +} + +void dcache_clean_by_va(void const *addr, size_t len) +{ + dcache_op_va(addr, len, OP_DCCVAC); +} + +void dcache_clean_invalidate_by_va(void const *addr, size_t len) +{ + dcache_op_va(addr, len, OP_DCCIVAC); +} + +void dcache_invalidate_by_va(void const *addr, size_t len) +{ + dcache_op_va(addr, len, OP_DCIVAC); +} + +/* + * CAUTION: This implementation assumes that coreboot never uses non-identity + * page tables for pages containing executed code. If you ever want to violate + * this assumption, have fun figuring out the associated problems on your own. + */ +void dcache_mmu_disable(void) +{ + uint32_t sctlr; + + flush_dcache_all(); + sctlr = read_sctlr(current_el()); + sctlr &= ~(SCTLR_C | SCTLR_M); + write_sctlr(sctlr, current_el()); +} + +void dcache_mmu_enable(void) +{ + uint32_t sctlr; + + sctlr = read_sctlr(current_el()); + sctlr |= SCTLR_C | SCTLR_M; + write_sctlr(sctlr, current_el()); +} + +void cache_sync_instructions(void) +{ + flush_dcache_all(); /* includes trailing DSB (in assembly) */ + iciallu(); /* includes BPIALLU (architecturally) */ + dsb(); + isb(); +} diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S new file mode 100644 index 0000000..1eecc2b --- /dev/null +++ b/src/arch/arm64/armv8/cpu.S @@ -0,0 +1,131 @@ +/* + * Based on arch/arm/include/asm/cacheflush.h + * + * Copyright (C) 1999-2002 Russell King. + * Copyright (C) 2012 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <arch/asm.h> + +/* + * flush_dcache_all() + * + * Flush the whole D-cache. + * + * Corrupted registers: x0-x7, x9-x11 + * From: Linux arch/arm64/mm/cache.S + */ +ENTRY(flush_dcache_all) + dsb sy // ensure ordering with previous memory accesses + mrs x0, clidr_el1 // read clidr + and x3, x0, #0x7000000 // extract loc from clidr + lsr x3, x3, #23 // left align loc bit field + cbz x3, finished // if loc is 0, then no need to clean + mov x10, #0 // start clean at cache level 0 +loop1: + add x2, x10, x10, lsr #1 // work out 3x current cache level + lsr x1, x0, x2 // extract cache type bits from clidr + and x1, x1, #7 // mask of the bits for current cache only + cmp x1, #2 // see what cache we have at this level + b.lt skip // skip if no cache, or just i-cache + mrs x9, daif // make CSSELR and CCSIDR access atomic + msr csselr_el1, x10 // select current cache level in csselr + isb // isb to sych the new cssr&csidr + mrs x1, ccsidr_el1 // read the new ccsidr + msr daif, x9 + and x2, x1, #7 // extract the length of the cache lines + add x2, x2, #4 // add 4 (line length offset) + mov x4, #0x3ff + and x4, x4, x1, lsr #3 // find maximum number on the way size + clz x5, x4 // find bit position of way size increment + mov x7, #0x7fff + and x7, x7, x1, lsr #13 // extract max number of the index size +loop2: + mov x9, x4 // create working copy of max way size +loop3: + lsl x6, x9, x5 + orr x11, x10, x6 // factor way and cache number into x11 + lsl x6, x7, x2 + orr x11, x11, x6 // factor index number into x11 + dc cisw, x11 // clean & invalidate by set/way + subs x9, x9, #1 // decrement the way + b.ge loop3 + subs x7, x7, #1 // decrement the index + b.ge loop2 +skip: + add x10, x10, #2 // increment cache number + cmp x3, x10 + b.gt loop1 +finished: + mov x10, #0 // swith back to cache level 0 + msr csselr_el1, x10 // select current cache level in csselr + dsb sy + isb + ret +ENDPROC(flush_dcache_all) + +/* + * Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a + * known state regarding caches/SCTLR. Completely cleans and invalidates + * icache/dcache, disables MMU and dcache (if active), and enables unaligned + * accesses, icache and branch prediction (if inactive). Clobbers x4 and x5. + */ +ENTRY(arm_init_caches) + /* w4: SCTLR, return address: x8 (stay valid for the whole function) */ + mov x8, x30 + /* XXX: Assume that we always start running at EL3 */ + mrs x4, sctlr_el3 + + /* FIXME: How to enable branch prediction on ARMv8? */ + + /* Flush and invalidate dcache */ + bl flush_dcache_all + + /* Deactivate MMU (0), Alignment Check (1) and DCache (2) */ + and x4, x4, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2) + /* Activate ICache (12) already for speed */ + orr x4, x4, #(1 << 12) + msr sctlr_el3, x4 + + /* Invalidate icache and TLB for good measure */ + ic iallu + tlbi alle3 + dsb sy + isb + + ret x8 +ENDPROC(arm_init_caches) + +/* Based on u-boot transition.S */ +ENTRY(switch_el3_to_el2) + mov x0, #0x5b1 /* Non-secure EL0/EL1 | HVC | 64bit EL2 */ + msr scr_el3, x0 + msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */ + mov x0, #0x33ff + msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */ + + /* Return to the EL2_SP2 mode from EL3 */ + mov x0, sp + msr sp_el2, x0 /* Migrate SP */ + mrs x0, vbar_el3 + msr vbar_el2, x0 /* Migrate VBAR */ + mrs x0, sctlr_el3 + msr sctlr_el2, x0 /* Migrate SCTLR */ + mov x0, #0x3c9 + msr spsr_el3, x0 /* EL2_SP2 | D | A | I | F */ + msr elr_el3, x30 + eret +ENDPROC(switch_el3_to_el2) diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c new file mode 100644 index 0000000..31e3131 --- /dev/null +++ b/src/arch/arm64/armv8/exception.c @@ -0,0 +1,129 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <stdint.h> +#include <types.h> +#include <arch/cache.h> +#include <arch/exception.h> +#include <console/console.h> + +void exception_sync_el0(uint64_t *regs, uint64_t esr); +void exception_irq_el0(uint64_t *regs, uint64_t esr); +void exception_fiq_el0(uint64_t *regs, uint64_t esr); +void exception_serror_el0(uint64_t *regs, uint64_t esr); +void exception_sync(uint64_t *regs, uint64_t esr); +void exception_irq(uint64_t *regs, uint64_t esr); +void exception_fiq(uint64_t *regs, uint64_t esr); +void exception_serror(uint64_t *regs, uint64_t esr); + +static void print_regs(uint64_t *regs) +{ + int i; + + /* ELR contains the restart PC at target exception level */ + printk(BIOS_ERR, "ELR = 0x%016llx ", regs[0]); + printk(BIOS_ERR, "X00 = 0x%016llx\n", regs[1]); + + for (i = 2; i < 31; i+=2) { + printk(BIOS_ERR, "X%02d = 0x%016llx ", i - 1, regs[i]); + printk(BIOS_ERR, "X%02d = 0x%016llx\n", i, regs[i + 1]); + } +} + +void exception_sync_el0(uint64_t *regs, uint64_t esr) +{ + printk(BIOS_ERR, "exception _sync_el0 (ESR = 0x%08llx)\n", esr); + print_regs(regs); + die("exception"); +} + +void exception_irq_el0(uint64_t *regs, uint64_t esr) +{ + printk(BIOS_ERR, "exception _irq_el0 (ESR = 0x%08llx)\n", esr); + print_regs(regs); + die("exception"); +} + +void exception_fiq_el0(uint64_t *regs, uint64_t esr) +{ + printk(BIOS_ERR, "exception _fiq_el0 (ESR = 0x%08llx)\n", esr); + print_regs(regs); + die("exception"); +} + +void exception_serror_el0(uint64_t *regs, uint64_t esr) +{ + printk(BIOS_ERR, "exception _serror_el0 (ESR = 0x%08llx)\n", esr); + print_regs(regs); + die("exception"); +} + +void exception_sync(uint64_t *regs, uint64_t esr) +{ + printk(BIOS_ERR, "exception _sync (ESR = 0x%08llx)\n", esr); + print_regs(regs); + die("exception"); +} + +void exception_irq(uint64_t *regs, uint64_t esr) +{ + printk(BIOS_ERR, "exception _irq (ESR = 0x%08llx)\n", esr); + print_regs(regs); + die("exception"); +} + +void exception_fiq(uint64_t *regs, uint64_t esr) +{ + printk(BIOS_ERR, "exception _fiq (ESR = 0x%08llx)\n", esr); + print_regs(regs); + die("exception"); +} + +void exception_serror(uint64_t *regs, uint64_t esr) +{ + printk(BIOS_ERR, "exception _serror (ESR = 0x%08llx)\n", esr); + print_regs(regs); + die("exception"); +} + +void exception_init(void) +{ + //uint32_t sctlr = read_sctlr(); + /* Handle exceptions in ARM mode. */ + //sctlr &= ~SCTLR_TE; + /* Set V=0 in SCTLR so VBAR points to the exception vector table. */ + //sctlr &= ~SCTLR_V; + /* Enforce alignment temporarily. */ + //write_sctlr(sctlr); + + extern uint32_t exception_table[]; + set_vbar((uintptr_t)exception_table); + + printk(BIOS_DEBUG, "Exception handlers installed.\n"); +} diff --git a/src/arch/arm64/armv8/exception_asm.S b/src/arch/arm64/armv8/exception_asm.S new file mode 100644 index 0000000..b1f1a94 --- /dev/null +++ b/src/arch/arm64/armv8/exception_asm.S @@ -0,0 +1,103 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/asm.h> + + .text + + .align 11 + .global exception_table +exception_table: + .align 7 + bl exception_prologue + bl exception_sync_el0 + .align 7 + bl exception_prologue + bl exception_irq_el0 + .align 7 + bl exception_prologue + bl exception_fiq_el0 + .align 7 + bl exception_prologue + bl exception_serror_el0 + .align 7 + bl exception_prologue + bl exception_sync + .align 7 + bl exception_prologue + bl exception_irq + .align 7 + bl exception_prologue + bl exception_fiq + .align 7 + bl exception_prologue + bl exception_serror + +/* + * Save state (register file + ELR) to stack + * and set arguments x0 and x1 for exception call + */ +ENTRY(exception_prologue) + stp x29, x30, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + stp x17, x18, [sp, #-16]! + stp x15, x16, [sp, #-16]! + stp x13, x14, [sp, #-16]! + stp x11, x12, [sp, #-16]! + stp x9, x10, [sp, #-16]! + stp x7, x8, [sp, #-16]! + stp x5, x6, [sp, #-16]! + stp x3, x4, [sp, #-16]! + stp x1, x2, [sp, #-16]! + + /* FIXME: Don't assume always running in EL2 */ + mrs x1, elr_el2 + stp x1, x0, [sp, #-16]! + + mrs x1, esr_el2 + mov x0, sp + + ret +ENDPROC(exception_prologue) + + .global exception_stack_end +exception_stack_end: + .quad 0 + +exception_handler: + .word 0 + + .global set_vbar +set_vbar: + msr vbar_el2, x0 + ret diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c new file mode 100644 index 0000000..6fb0e65 --- /dev/null +++ b/src/arch/arm64/boot.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <console/console.h> + +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) +{ + void (*doit)(void *) = entry; + void *cb_tables = cbmem_find(CBMEM_ID_CBTABLE); + + printk(BIOS_SPEW, "entry = %p\n", entry); + cache_sync_instructions(); + doit(cb_tables); +} diff --git a/src/arch/arm64/bootblock.ld b/src/arch/arm64/bootblock.ld new file mode 100644 index 0000000..acce1f1 --- /dev/null +++ b/src/arch/arm64/bootblock.ld @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +INCLUDE ldoptions + +PHDRS +{ + to_load PT_LOAD; +} + +ENTRY(_start) +TARGET(binary) +SECTIONS +{ + . = CONFIG_BOOTBLOCK_BASE; + + .bootblock . : { + *(.text._start); + KEEP(*(.id)); + *(.text); + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.data); + *(.data.*); + *(.bss); + *(.bss.*); + *(.sbss); + *(.sbss.*); + } : to_load = 0xff + + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.ARM.*) + } +} diff --git a/src/arch/arm64/cbmem.c b/src/arch/arm64/cbmem.c new file mode 100644 index 0000000..b33e9b8 --- /dev/null +++ b/src/arch/arm64/cbmem.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> + +unsigned long get_top_of_ram(void); + +unsigned long get_top_of_ram(void) +{ + return CONFIG_RAMTOP; +} + +void *cbmem_top(void) +{ + return (void *)get_top_of_ram(); +} diff --git a/src/arch/arm64/cpu.c b/src/arch/arm64/cpu.c new file mode 100644 index 0000000..f90c759 --- /dev/null +++ b/src/arch/arm64/cpu.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include <stdlib.h> +#include <arch/cpu.h> + +/* Return the cpu struct which is at the high memory address of the stack. + */ +struct cpu_info *cpu_info(void) +{ + uintptr_t addr = ALIGN((uintptr_t)__builtin_frame_address(0), + CONFIG_STACK_SIZE); + addr -= sizeof(struct cpu_info); + return (void *)addr; +} + diff --git a/src/arch/arm64/div0.c b/src/arch/arm64/div0.c new file mode 100644 index 0000000..ab06ad3 --- /dev/null +++ b/src/arch/arm64/div0.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <console/console.h> + +void __div0(void); // called from asm so no need for a prototype in a header + +/* Replacement (=dummy) for GNU/Linux division-by zero handler */ +/* recursion is ok here because we have no formats ... */ +void __div0 (void) +{ + printk(BIOS_EMERG, "DIVIDE BY ZERO! continuing ... \n"); +} diff --git a/src/arch/arm64/eabi_compat.c b/src/arch/arm64/eabi_compat.c new file mode 100644 index 0000000..c27c54e --- /dev/null +++ b/src/arch/arm64/eabi_compat.c @@ -0,0 +1,28 @@ +/* + * Utility functions needed for (some) EABI conformant tool chains. + * + * (C) Copyright 2009 Wolfgang Denk <wd(a)denx.de> + * + * This program is Free Software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + */ + +#include <console/console.h> + +int raise (int signum) __attribute__((used)); +int raise (int signum) +{ + return 0; +} + +void __aeabi_unwind_cpp_pr0(void) __attribute__((used)); +void __aeabi_unwind_cpp_pr0(void) +{ +}; + +void __aeabi_unwind_cpp_pr1(void) __attribute__((used)); +void __aeabi_unwind_cpp_pr1(void) +{ +}; diff --git a/src/arch/arm64/early_console.c b/src/arch/arm64/early_console.c new file mode 100644 index 0000000..aa287a3 --- /dev/null +++ b/src/arch/arm64/early_console.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/vtxprintf.h> + +/* FIXME: need to make console driver more generic */ +void console_tx_byte(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + +#if CONFIG_CONSOLE_SERIAL8250MEM + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_byte(byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(0, byte); +#endif +#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) + cbmemc_tx_byte(byte); +#endif +} + +void console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250MEM + uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); +#endif +#if CONFIG_CONSOLE_SERIAL_UART + uart_tx_flush(); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif +} + +int do_printk(int msg_level, const char *fmt, ...) +{ + va_list args; + int i; + + if (msg_level > console_loglevel) { + return 0; + } + + va_start(args, fmt); + i = vtxprintf(console_tx_byte, fmt, args); + va_end(args); + + console_tx_flush(); + + return i; +} diff --git a/src/arch/arm64/id.S b/src/arch/arm64/id.S new file mode 100644 index 0000000..a588f1e --- /dev/null +++ b/src/arch/arm64/id.S @@ -0,0 +1,20 @@ +#include <build.h> + + .section ".id", "a", %progbits + + .globl __id_start +__id_start: +ver: + .asciz COREBOOT_VERSION +vendor: + .asciz CONFIG_MAINBOARD_VENDOR +part: + .asciz CONFIG_MAINBOARD_PART_NUMBER +.long __id_end - ver /* Reverse offset to the vendor id */ +.long __id_end - vendor /* Reverse offset to the vendor id */ +.long __id_end - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ + .globl __id_end + +__id_end: +.previous diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h new file mode 100644 index 0000000..7760bad --- /dev/null +++ b/src/arch/arm64/include/arch/asm.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARM_ARM64_ASM_H +#define __ARM_ARM64_ASM_H + +#define ALIGN .align 0 + +#define ENDPROC(name) \ + .type name, %function; \ + END(name) + +#define ENTRY(name) \ + .section .text.name, "ax", %progbits; \ + .global name; \ + ALIGN; \ + name: + +#define END(name) \ + .size name, .-name + +#endif /* __ARM_ARM64_ASM_H */ diff --git a/src/arch/arm64/include/arch/boot/boot.h b/src/arch/arm64/include/arch/boot/boot.h new file mode 100644 index 0000000..16763c6 --- /dev/null +++ b/src/arch/arm64/include/arch/boot/boot.h @@ -0,0 +1,8 @@ +#ifndef ASM_ARM64_BOOT_H +#define ASM_ARM64_BOOT_H + +#define ELF_CLASS ELFCLASS64 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_AARCH64 + +#endif /* ASM_ARM_BOOT_H */ diff --git a/src/arch/arm64/include/arch/byteorder.h b/src/arch/arm64/include/arch/byteorder.h new file mode 100644 index 0000000..8dc069f --- /dev/null +++ b/src/arch/arm64/include/arch/byteorder.h @@ -0,0 +1,27 @@ +#ifndef _BYTEORDER_H +#define _BYTEORDER_H + +#define __LITTLE_ENDIAN 1234 + +#include <stdint.h> +#include <swab.h> + +#define cpu_to_le64(x) ((uint64_t)(x)) +#define le64_to_cpu(x) ((uint64_t)(x)) +#define cpu_to_le32(x) ((uint32_t)(x)) +#define le32_to_cpu(x) ((uint32_t)(x)) +#define cpu_to_le16(x) ((uint16_t)(x)) +#define le16_to_cpu(x) ((uint16_t)(x)) +#define cpu_to_be64(x) swab64(x) +#define be64_to_cpu(x) swab64(x) +#define cpu_to_be32(x) swab32((x)) +#define be32_to_cpu(x) swab32((x)) +#define cpu_to_be16(x) swab16((x)) +#define be16_to_cpu(x) swab16((x)) + +#define ntohll(x) be64_to_cpu(x) +#define htonll(x) cpu_to_be64(x) +#define ntohl(x) be32_to_cpu(x) +#define htonl(x) cpu_to_be32(x) + +#endif /* _BYTEORDER_H */ diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h new file mode 100644 index 0000000..3d9fa26 --- /dev/null +++ b/src/arch/arm64/include/arch/early_variables.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef ARCH_EARLY_VARIABLES_H +#define ARCH_EARLY_VARIABLES_H + +#if CONFIG_CAR_MIGRATION + #error "This is ARM, silly... we don't have CAR here." +#endif + +#define CAR_GLOBAL + +#define CAR_MIGRATE(migrate_fn_) +static inline void *car_get_var_ptr(void *var) { return var; } +#define car_get_var(var) (var) +#define car_set_var(var, val) do { (var) = (val); } while (0) +static inline void car_migrate_variables(void) { } + +#endif diff --git a/src/arch/arm64/include/arch/hlt.h b/src/arch/arm64/include/arch/hlt.h new file mode 100644 index 0000000..285b6f8 --- /dev/null +++ b/src/arch/arm64/include/arch/hlt.h @@ -0,0 +1,9 @@ +#ifndef ARCH_HLT_H +#define ARCH_HLT_H + +static inline __attribute__((always_inline)) void hlt(void) +{ + for (;;) ; +} + +#endif /* ARCH_HLT_H */ diff --git a/src/arch/arm64/include/arch/io.h b/src/arch/arm64/include/arch/io.h new file mode 100644 index 0000000..49d851d --- /dev/null +++ b/src/arch/arm64/include/arch/io.h @@ -0,0 +1,137 @@ +/* + * Based on (linux) arch/arm/include/asm/io.h + * + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * Copyright 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __ASM_ARM_IO_H +#define __ASM_ARM_IO_H + +#include <types.h> +#include <arch/byteorder.h> +#include <arch/barrier.h> + +/* + * Generic IO read/write. These perform native-endian accesses. + */ +static inline void __raw_writeb(u8 val, volatile void *addr) +{ + asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void __raw_writew(u16 val, volatile void *addr) +{ + asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void __raw_writel(u32 val, volatile void *addr) +{ + asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void __raw_writeq(u64 val, volatile void *addr) +{ + asm volatile("str %0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline u8 __raw_readb(const volatile void *addr) +{ + u8 val; + asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline u16 __raw_readw(const volatile void *addr) +{ + u16 val; + asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline u32 __raw_readl(const volatile void *addr) +{ + u32 val; + asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline u64 __raw_readq(const volatile void *addr) +{ + u64 val; + asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +/* IO barriers */ +#define __iormb() rmb() +#define __iowmb() wmb() + +#define mmiowb() do { } while (0) + +/* + * Relaxed I/O memory access primitives. These follow the Device memory + * ordering rules but do not guarantee any ordering relative to Normal memory + * accesses. + */ +#define readb_relaxed(c) ({ u8 __u = __raw_readb(c); __u; }) +#define readw_relaxed(c) ({ u16 __u = le16_to_cpu((__force __le16)__raw_readw(c)); __u; }) +#define readl_relaxed(c) ({ u32 __u = le32_to_cpu((__force __le32)__raw_readl(c)); __u; }) + +#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) +#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) +#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) + +/* + * I/O memory access primitives. Reads are ordered relative to any + * following Normal memory access. Writes are ordered relative to any prior + * Normal memory access. + */ +#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) +#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) +#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) + +#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); }) +#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) +#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) + +#define inb_p(addr) inb(addr) +#define inw_p(addr) inw(addr) +#define inl_p(addr) inl(addr) + +#define outb_p(x, addr) outb((x), (addr)) +#define outw_p(x, addr) outw((x), (addr)) +#define outl_p(x, addr) outl((x), (addr)) + +#define insb_p(port,to,len) insb(port,to,len) +#define insw_p(port,to,len) insw(port,to,len) +#define insl_p(port,to,len) insl(port,to,len) + +#define outsb_p(port,from,len) outsb(port,from,len) +#define outsw_p(port,from,len) outsw(port,from,len) +#define outsl_p(port,from,len) outsl(port,from,len) + +/* + * String version of I/O memory access operations. + */ +extern void __memcpy_fromio(void *, const volatile void *, size_t); +extern void __memcpy_toio(volatile void *, const void *, size_t); +extern void __memset_io(volatile void *, int, size_t); + +#define memset_io(c,v,l) __memset_io((c),(v),(l)) +#define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l)) +#define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l)) + +#endif /* __ASM_ARM_IO_H */ diff --git a/src/arch/arm64/include/arch/pci_ops.h b/src/arch/arm64/include/arch/pci_ops.h new file mode 100644 index 0000000..26a2c9b --- /dev/null +++ b/src/arch/arm64/include/arch/pci_ops.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ARCH_ARM64_PCI_OPS_H +#define ARCH_ARM64_PCI_OPS_H + +/* V8 has PCI in some form. We will need to fill this in. */ +static inline const struct pci_bus_operations *pci_config_default(void) +{ + return NULL; +} + +#endif diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h new file mode 100644 index 0000000..e7a2401 --- /dev/null +++ b/src/arch/arm64/include/arch/stages.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 The ChromiumOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARCH_STAGES_H +#define __ARCH_STAGES_H + +extern void main(void); + +void stage_entry(void) __attribute__((section(".text.stage_entry.aarch64"))); +void stage_exit(void *); +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); + +#endif diff --git a/src/arch/arm64/include/armv8/arch/barrier.h b/src/arch/arm64/include/armv8/arch/barrier.h new file mode 100644 index 0000000..dfcf5a5 --- /dev/null +++ b/src/arch/arm64/include/armv8/arch/barrier.h @@ -0,0 +1,52 @@ +/* + * Based on arch/arm/include/asm/barrier.h + * + * Copyright (C) 2012 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __ASM_ARM_BARRIER_H +#define __ASM_ARM_BARRIER_H + +#ifndef __ASSEMBLY__ + +#define sev() asm volatile("sev" : : : "memory") +#define wfe() asm volatile("wfe" : : : "memory") +#define wfi() asm volatile("wfi" : : : "memory") + +#define isb() asm volatile("isb" : : : "memory") +#define dsb() asm volatile("dsb sy" : : : "memory") + +#define mb() dsb() +#define rmb() asm volatile("dsb ld" : : : "memory") +#define wmb() asm volatile("dsb st" : : : "memory") + +#ifndef CONFIG_SMP +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#else +#define smp_mb() asm volatile("dmb ish" : : : "memory") +#define smp_rmb() asm volatile("dmb ishld" : : : "memory") +#define smp_wmb() asm volatile("dmb ishst" : : : "memory") +#endif + +#define read_barrier_depends() do { } while(0) +#define smp_read_barrier_depends() do { } while(0) + +#define set_mb(var, value) do { var = value; smp_mb(); } while (0) +#define nop() asm volatile("nop"); + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARM_BARRIER_H */ diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h new file mode 100644 index 0000000..325b857 --- /dev/null +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -0,0 +1,262 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.h: Cache maintenance API for ARM64 + */ + +#ifndef ARM_ARM64_CACHE_H +#define ARM_ARM64_CACHE_H + +#include <config.h> +#include <stddef.h> +#include <stdint.h> + +/* SCTLR_ELx common bits */ +#define SCTLR_M (1 << 0) /* MMU enable */ +#define SCTLR_A (1 << 1) /* Alignment check enable */ +#define SCTLR_C (1 << 2) /* Data/unified cache enable */ +#define SCTLR_SA (1 << 3) /* Stack alignment check enable */ +#define SCTLR_I (1 << 12) /* Instruction cache enable */ +#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ +#define SCTLR_EE (1 << 25) /* Exception endianness */ + +/* SCTLR_EL1 bits */ +#define SCTLR_EL1_CP15B (1 << 5) /* CP15 barrier enable */ +#define SCTLR_EL1_ITD (1 << 7) /* IT disable */ +#define SCTLR_EL1_SED (1 << 8) /* SETEND disable */ +#define SCTLR_EL1_UMA (1 << 9) /* User mask access */ +#define SCTLR_EL1_DZE (1 << 14) /* DC ZVA instruction at EL0 */ +#define SCTLR_EL1_UCT (1 << 15) /* CTR_EL0 register EL0 access */ +#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */ +#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */ +#define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */ +#define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */ + +/* + * Utility macro to choose an instruction according to the exception + * level (EL) passed, which number is concatenated between insa and insb parts + */ +#define SWITCH_EL(insa, insb, el) if (el == 1) asm volatile(insa "1" insb); \ + else if (el == 2) asm volatile (insa "2" insb); \ + else asm volatile (insa "3" insb) + +/* get current exception level (EL1-EL3) */ +static inline uint32_t current_el(void) +{ + uint32_t el; + asm volatile ("mrs %0, CurrentEL" : "=r" (el)); + return el >> 2; +} + +/* + * Sync primitives + */ + +/* data memory barrier */ +static inline void dmb(void) +{ + asm volatile ("dmb sy" : : : "memory"); +} + +/* data sync barrier */ +static inline void dsb(void) +{ + asm volatile ("dsb sy" : : : "memory"); +} + +/* instruction sync barrier */ +static inline void isb(void) +{ + asm volatile ("isb sy" : : : "memory"); +} + +/* + * Low-level TLB maintenance operations + */ + +/* invalidate entire unified TLB */ +static inline void tlbiall(uint32_t el) +{ + SWITCH_EL("tlbi alle", : : : "memory", el); +} + +/* invalidate unified TLB by VA, all ASID (EL1) */ +static inline void tlbivaa(uint64_t va) +{ + asm volatile("tlbi vaae1, %0" : : "r" (va) : "memory"); +} + +/* write translation table base register 0 (TTBR0_ELx) */ +static inline void write_ttbr0(uint64_t val, uint32_t el) +{ + SWITCH_EL("msr ttbr0_el", ", %0" : : "r" (val) : "memory", el); +} + +/* read translation control register (TCR_ELx) */ +static inline uint64_t read_tcr(uint32_t el) +{ + uint64_t val = 0; + SWITCH_EL("mrs %0, tcr_el", : "=r" (val), el); + return val; +} + +/* write translation control register (TCR_ELx) */ +static inline void write_tcr(uint64_t val, uint32_t el) +{ + SWITCH_EL("msr tcr_el", ", %0" : : "r" (val) : "memory", el); +} + +/* + * Low-level cache maintenance operations + */ + +/* data cache clean and invalidate by VA to PoC */ +static inline void dccivac(uint64_t va) +{ + asm volatile ("dc civac, %0" : : "r" (va) : "memory"); +} + +/* data cache clean and invalidate by set/way */ +static inline void dccisw(uint64_t val) +{ + asm volatile ("dc cisw, %0" : : "r" (val) : "memory"); +} + +/* data cache clean by VA to PoC */ +static inline void dccvac(uint64_t va) +{ + asm volatile ("dc cvac, %0" : : "r" (va) : "memory"); +} + +/* data cache clean by set/way */ +static inline void dccsw(uint64_t val) +{ + asm volatile ("dc csw, %0" : : "r" (val) : "memory"); +} + +/* data cache invalidate by VA to PoC */ +static inline void dcivac(uint64_t va) +{ + asm volatile ("dc ivac, %0" : : "r" (va) : "memory"); +} + +/* data cache invalidate by set/way */ +static inline void dcisw(uint64_t val) +{ + asm volatile ("dc isw, %0" : : "r" (val) : "memory"); +} + +/* instruction cache invalidate all */ +static inline void iciallu(void) +{ + asm volatile ("ic iallu" : : : "memory"); +} + +/* + * Cache registers functions + */ + +/* read cache level ID register (CLIDR_EL1) */ +static inline uint32_t read_clidr(void) +{ + uint32_t val = 0; + asm volatile ("mrs %0, clidr_el1" : "=r" (val)); + return val; +} + +/* read cache size ID register register (CCSIDR_EL1) */ +static inline uint32_t read_ccsidr(void) +{ + uint32_t val = 0; + asm volatile ("mrs %0, ccsidr_el1" : "=r" (val)); + return val; +} + +/* read cache size selection register (CSSELR_EL1) */ +static inline uint32_t read_csselr(void) +{ + uint32_t val = 0; + asm volatile ("mrs %0, csselr_el1" : "=r" (val)); + return val; +} + +/* write to cache size selection register (CSSELR_EL1) */ +static inline void write_csselr(uint32_t val) +{ + /* + * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd) + * Bit 0 - 0 = data or unified cache, 1 = instruction cache + */ + asm volatile ("msr csselr_el1, %0" : : "r" (val)); + isb(); /* ISB to sync the change to CCSIDR_EL1 */ +} + +/* read system control register (SCTLR_ELx) */ +static inline uint32_t read_sctlr(uint32_t el) +{ + uint32_t val; + SWITCH_EL("mrs %0, sctlr_el", : "=r" (val), el); + return val; +} + +/* write system control register (SCTLR_ELx) */ +static inline void write_sctlr(uint32_t val, uint32_t el) +{ + SWITCH_EL("msr sctlr_el", ", %0" : : "r" (val) : "cc", el); + isb(); +} + + +/* dcache clean by virtual address to PoC */ +void dcache_clean_by_va(void const *addr, size_t len); + +/* dcache clean and invalidate by virtual address to PoC */ +void dcache_clean_invalidate_by_va(void const *addr, size_t len); + +/* dcache invalidate by virtual address to PoC */ +void dcache_invalidate_by_va(void const *addr, size_t len); + +/* dcache invalidate all */ +void flush_dcache_all(void); + +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + +/* dcache and MMU disable */ +void dcache_mmu_disable(void); + +/* dcache and MMU enable */ +void dcache_mmu_enable(void); + +/* perform all icache/dcache maintenance needed after loading new code */ +void cache_sync_instructions(void); + +/* tlb invalidate all */ +void tlb_invalidate_all(void); + +#endif /* ARM_ARM64_CACHE_H */ diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h new file mode 100644 index 0000000..5a8f145 --- /dev/null +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef __ARCH_CPU_H__ +#define __ARCH_CPU_H__ + +#define asmlinkage + +#if !defined(__PRE_RAM__) +#include <device/device.h> + +struct cpu_driver { + struct device_operations *ops; + struct cpu_device_id *id_table; +}; + +struct thread; + +struct cpu_info { + device_t cpu; + unsigned long index; +#if CONFIG_COOP_MULTITASKING + struct thread *thread; +#endif +}; + +struct cpuinfo_arm { + uint8_t arm; /* CPU family */ + uint8_t arm_vendor; /* CPU vendor */ + uint8_t arm_model; +}; + +#endif + +struct cpu_info *cpu_info(void); +#endif /* __ARCH_CPU_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h new file mode 100644 index 0000000..5987d85 --- /dev/null +++ b/src/arch/arm64/include/armv8/arch/exception.h @@ -0,0 +1,38 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_EXCEPTION_H +#define _ARCH_EXCEPTION_H + +#include <stdint.h> + +void exception_init(void); +void set_vbar(uint64_t vbar); + +#endif diff --git a/src/arch/arm64/include/armv8/arch/rules.h b/src/arch/arm64/include/armv8/arch/rules.h new file mode 100644 index 0000000..a790365 --- /dev/null +++ b/src/arch/arm64/include/armv8/arch/rules.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_RULES_H +#define _ARCH_RULES_H + +/* For romstage and ramstage always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. + * + * For ramstage individual source file may define __SIMPLE_DEVICE__ + * before including any header files to force that particular source + * be built with simple device model. + */ + +#if defined(__PRE_RAM__) +#define __SIMPLE_DEVICE__ +#endif + +#endif /* _ARCH_RULES_H */ diff --git a/src/arch/arm64/include/bootblock_common.h b/src/arch/arm64/include/bootblock_common.h new file mode 100644 index 0000000..2fa705f --- /dev/null +++ b/src/arch/arm64/include/bootblock_common.h @@ -0,0 +1,11 @@ +#ifdef CONFIG_BOOTBLOCK_CPU_INIT +#include CONFIG_BOOTBLOCK_CPU_INIT +#endif + +#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT +#include CONFIG_BOOTBLOCK_MAINBOARD_INIT +#else +static void bootblock_mainboard_init(void) +{ +} +#endif diff --git a/src/arch/arm64/include/clocks.h b/src/arch/arm64/include/clocks.h new file mode 100644 index 0000000..8f35303 --- /dev/null +++ b/src/arch/arm64/include/clocks.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Standard clock speeds */ + +/* + * We define some commonly-used clock speeds to avoid error since long + * numbers are hard to read. + * + * The format of the label is + * CLK_x_yU where: + * x is the integer speed + * y is the fractional part which can be omitted if 0 + * U is the units (blank for Hz, K or M for KHz and MHz) + * + * Please order the items by increasing Hz + */ +enum { + CLK_32768 = 32768, + CLK_20M = 20000000, + CLK_24M = 24000000, + CLK_144M = 144000000, + CLK_216M = 216000000, + CLK_300M = 300000000, +}; + diff --git a/src/arch/arm64/include/smp/spinlock.h b/src/arch/arm64/include/smp/spinlock.h new file mode 100644 index 0000000..8a89d1f --- /dev/null +++ b/src/arch/arm64/include/smp/spinlock.h @@ -0,0 +1,6 @@ +#ifndef ARCH_SMP_SPINLOCK_H +#define ARCH_SMP_SPINLOCK_H + +#error "spinlocks: implement this for ARM64" + +#endif diff --git a/src/arch/arm64/include/stdint.h b/src/arch/arm64/include/stdint.h new file mode 100644 index 0000000..2907d8e --- /dev/null +++ b/src/arch/arm64/include/stdint.h @@ -0,0 +1,60 @@ +#ifndef ARM64_STDINT_H +#define ARM64_STDINT_H + +/* Exact integral types */ +typedef unsigned char uint8_t; +typedef signed char int8_t; + +typedef unsigned short uint16_t; +typedef signed short int16_t; + +typedef unsigned int uint32_t; +typedef signed int int32_t; + +typedef unsigned long long uint64_t; +typedef signed long long int64_t; + +/* Small types */ +typedef unsigned char uint_least8_t; +typedef signed char int_least8_t; + +typedef unsigned short uint_least16_t; +typedef signed short int_least16_t; + +typedef unsigned int uint_least32_t; +typedef signed int int_least32_t; + +typedef unsigned long long uint_least64_t; +typedef signed long long int_least64_t; + +/* Fast Types */ +typedef unsigned char uint_fast8_t; +typedef signed char int_fast8_t; + +typedef unsigned int uint_fast16_t; +typedef signed int int_fast16_t; + +typedef unsigned int uint_fast32_t; +typedef signed int int_fast32_t; + +typedef unsigned long long uint_fast64_t; +typedef signed long long int_fast64_t; + +typedef long long int intmax_t; +typedef unsigned long long uintmax_t; + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; + + +/* Types for `void *' pointers. */ +typedef s64 intptr_t; +typedef u64 uintptr_t; + +#endif /* ARM64_STDINT_H */ diff --git a/src/arch/arm64/memcpy.S b/src/arch/arm64/memcpy.S new file mode 100644 index 0000000..ccad4cf --- /dev/null +++ b/src/arch/arm64/memcpy.S @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2013 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <arch/asm.h> + +/* + * Copy a buffer from src to dest (alignment handled by the hardware) + * + * Parameters: + * x0 - dest + * x1 - src + * x2 - n + * Returns: + * x0 - dest + */ +ENTRY(memcpy) + mov x4, x0 + subs x2, x2, #8 + b.mi 2f +1: ldr x3, [x1], #8 + subs x2, x2, #8 + str x3, [x4], #8 + b.pl 1b +2: adds x2, x2, #4 + b.mi 3f + ldr w3, [x1], #4 + sub x2, x2, #4 + str w3, [x4], #4 +3: adds x2, x2, #2 + b.mi 4f + ldrh w3, [x1], #2 + sub x2, x2, #2 + strh w3, [x4], #2 +4: adds x2, x2, #1 + b.mi 5f + ldrb w3, [x1] + strb w3, [x4] +5: ret +ENDPROC(memcpy) diff --git a/src/arch/arm64/memmove.S b/src/arch/arm64/memmove.S new file mode 100644 index 0000000..1f9e263 --- /dev/null +++ b/src/arch/arm64/memmove.S @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <arch/asm.h> +/* + * Move a buffer from src to test (alignment handled by the hardware). + * If dest <= src, call memcpy, otherwise copy in reverse order. + * + * Parameters: + * x0 - dest + * x1 - src + * x2 - n + * Returns: + * x0 - dest + */ +ENTRY(memmove) + cmp x0, x1 + b.ls memcpy + add x4, x0, x2 + add x1, x1, x2 + subs x2, x2, #8 + b.mi 2f +1: ldr x3, [x1, #-8]! + subs x2, x2, #8 + str x3, [x4, #-8]! + b.pl 1b +2: adds x2, x2, #4 + b.mi 3f + ldr w3, [x1, #-4]! + sub x2, x2, #4 + str w3, [x4, #-4]! +3: adds x2, x2, #2 + b.mi 4f + ldrh w3, [x1, #-2]! + sub x2, x2, #2 + strh w3, [x4, #-2]! +4: adds x2, x2, #1 + b.mi 5f + ldrb w3, [x1, #-1] + strb w3, [x4, #-1] +5: ret +ENDPROC(memmove) diff --git a/src/arch/arm64/memset.S b/src/arch/arm64/memset.S new file mode 100644 index 0000000..0cea55d --- /dev/null +++ b/src/arch/arm64/memset.S @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2013 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <arch/asm.h> + +/* + * Fill in the buffer with character c (alignment handled by the hardware) + * + * Parameters: + * x0 - buf + * x1 - c + * x2 - n + * Returns: + * x0 - buf + */ +ENTRY(memset) + mov x4, x0 + and w1, w1, #0xff + orr w1, w1, w1, lsl #8 + orr w1, w1, w1, lsl #16 + orr x1, x1, x1, lsl #32 + subs x2, x2, #8 + b.mi 2f +1: str x1, [x4], #8 + subs x2, x2, #8 + b.pl 1b +2: adds x2, x2, #4 + b.mi 3f + sub x2, x2, #4 + str w1, [x4], #4 +3: adds x2, x2, #2 + b.mi 4f + sub x2, x2, #2 + strh w1, [x4], #2 +4: adds x2, x2, #1 + b.mi 5f + strb w1, [x4] +5: ret +ENDPROC(memset) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld new file mode 100644 index 0000000..e878820 --- /dev/null +++ b/src/arch/arm64/ramstage.ld @@ -0,0 +1,136 @@ +/* + * Memory map: + * + * CONFIG_RAMBASE : text segment + * : rodata segment + * : data segment + * : bss segment + * : stack + * : heap + */ +/* + * Copyright 2013 Google Inc. + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add ramstage cross the vga font buffer handling + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +INCLUDE ldoptions + +ENTRY(stage_entry) + +PHDRS +{ + to_load PT_LOAD; +} + +SECTIONS +{ + . = CONFIG_SYS_SDRAM_BASE; + /* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ + .text : { + _text = .; + _start = .; + *(.text.stage_entry.aarch64); + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; + } : to_load + + .ctors : { + . = ALIGN(0x100); + __CTOR_LIST__ = .; + *(.ctors); + LONG(0); + __CTOR_END__ = .; + } + + .rodata : { + _rodata = .; + . = ALIGN(4); + console_drivers = .; + *(.rodata.console_drivers) + econsole_drivers = . ; + . = ALIGN(4); + pci_drivers = . ; + *(.rodata.pci_driver) + epci_drivers = . ; + cpu_drivers = . ; + *(.rodata.cpu_driver) + ecpu_drivers = . ; + _bs_init_begin = .; + *(.bs_init) + _bs_init_end = .; + *(.rodata) + *(.rodata.*) + /* kevinh/Ispiri - Added an align, because the objcopy tool + * incorrectly converts sections that are not long word aligned. + */ + . = ALIGN(4); + + _erodata = .; + } + /* After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data : { + _data = .; + *(.data) + _edata = .; + } + + /* bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + _bss = .; + .bss . : { + *(.bss) + *(.sbss) + *(COMMON) + } + _ebss = .; + _end = .; + + /* coreboot really "ends" here. Only heap and stack are placed after + * this line. + */ + + _heap = .; + .heap . : { + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . = CONFIG_HEAP_SIZE ; + . = ALIGN(4); + } + _eheap = .; + + _stack = CONFIG_STACK_BOTTOM; + _estack = CONFIG_STACK_TOP; + + /* The ram segment. This includes all memory used by the memory + * resident copy of coreboot, except the tables that are produced on + * the fly, but including stack and heap. + */ + _ram_seg = _text; + _eram_seg = _eheap; + + /* Discard the sections we don't need/want */ + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/arch/arm64/romstage.ld b/src/arch/arm64/romstage.ld new file mode 100644 index 0000000..d05fdd1 --- /dev/null +++ b/src/arch/arm64/romstage.ld @@ -0,0 +1,89 @@ +/* + * Memory map: + * + * CONFIG_ROMSTAGE_BASE : text segment + * : rodata segment + * : data segment + * : bss segment + * : stack + * : heap + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add ramstage cross the vga font buffer handling + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +/* + INCLUDE ldoptions + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +INCLUDE ldoptions + +PHDRS +{ + to_load PT_LOAD; +} + +ENTRY(stage_entry) + +SECTIONS +{ + . = CONFIG_ROMSTAGE_BASE; + + .romtext . : { + _start = .; + *(.text.stage_entry.aarch64); + *(.text.startup); + *(.text); + *(.text.*); + } : to_load + + .romdata . : { + *(.rodata); + *(.rodata.*); + *(.machine_param); + *(.data); + *(.data.*); + . = ALIGN(8); + _erom = .; + } + + __image_copy_end = .; + + /* bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + .bss . : { + . = ALIGN(8); + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + _ebss = .; + } + + _end = .; + + preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + + /* Discard the sections we don't need/want */ + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.eh_frame); + } +} diff --git a/src/arch/arm64/stages.c b/src/arch/arm64/stages.c new file mode 100644 index 0000000..e1ab21a --- /dev/null +++ b/src/arch/arm64/stages.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * This file contains entry/exit functions for each stage during coreboot + * execution (bootblock entry and ramstage exit will depend on external + * loading). + * + * Entry points must be placed at the location the previous stage jumps + * to (the lowest address in the stage image). This is done by giving + * stage_entry() its own section in .text and placing it first in the + * linker script. + */ + +#include <arch/stages.h> +#include <arch/cache.h> + +void stage_entry(void) +{ + main(); +} + +/* we had marked 'doit' as 'noreturn'. + * There is no apparent harm in leaving it as something we can return from, and in the one + * case where we call a payload, the payload is allowed to return. + * Hence, leave it as something we can return from. + */ +void stage_exit(void *addr) +{ + void (*doit)(void) = addr; + /* + * Most stages load code so we need to sync caches here. Should maybe + * go into cbfs_load_stage() instead... + */ + cache_sync_instructions(); + doit(); +} diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c new file mode 100644 index 0000000..49fab9f --- /dev/null +++ b/src/arch/arm64/tables.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2005 Steve Magnani + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <boot/coreboot_tables.h> +#include <string.h> +#include <cbmem.h> +#include <lib.h> + +#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) + +#if ! CONFIG_DYNAMIC_CBMEM +/* + * TODO: "High" tables are a convention used on x86. Maybe we can + * clean up that naming at some point. + */ +uint64_t high_tables_base = 0; +uint64_t high_tables_size; +#endif + +void cbmem_arch_init(void) +{ +} + +struct lb_memory *write_tables(void) +{ + unsigned long table_pointer, new_table_pointer; + +#if ! CONFIG_DYNAMIC_CBMEM + if (!high_tables_base) { + printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); + } + + printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); +#endif + + post_code(0x9d); + + table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, + MAX_COREBOOT_TABLE_SIZE); + if (!table_pointer) { + printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); + return NULL; + } + + new_table_pointer = write_coreboot_table(0UL, 0UL, + table_pointer, table_pointer); + + if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) { + printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n", + new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE); + } + + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + new_table_pointer - table_pointer); + + post_code(0x9e); + + /* Print CBMEM sections */ + cbmem_list(); + + return get_lb_mem(); +} diff --git a/src/arch/arm64/timestamp.c b/src/arch/arm64/timestamp.c new file mode 100644 index 0000000..e6a8159 --- /dev/null +++ b/src/arch/arm64/timestamp.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <timestamp.h> +#include <timer.h> + +uint64_t timestamp_get(void) +{ + struct mono_time timestamp; + timer_monotonic_get(&timestamp); + return (uint64_t)timestamp.microseconds; +} + diff --git a/toolchain.inc b/toolchain.inc index 326e474..89173d1 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -56,12 +56,15 @@ COREBOOT_STANDARD_STAGES := bootblock romstage ramstage ARCHDIR-i386 := x86 ARCHDIR-x86_32 := x86 ARCHDIR-arm := arm +ARCHDIR-arm64 := arm64 CFLAGS_arm += \ -mno-unaligned-access\ -mthumb\ -mthumb-interwork +CFLAGS_arm64 := -ffunction-sections -fdata-sections + toolchain_to_dir = \ $(foreach arch,$(ARCH_SUPPORTED),\ $(eval CPPFLAGS_$(arch) += \ diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 07a098e..7347fcb 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -130,7 +130,7 @@ static struct { uint32_t arch; const char *name; } arch_names[] = { - { CBFS_ARCHITECTURE_AARCH64, "aarch64" }, + { CBFS_ARCHITECTURE_AARCH64, "arm64" }, { CBFS_ARCHITECTURE_ARM, "arm" }, { CBFS_ARCHITECTURE_X86, "x86" }, { CBFS_ARCHITECTURE_UNKNOWN, "unknown" }

1 0

Patch set updated for coreboot: 93b0e49 tegra124/nyan: memory and display updates
by Isaac Christensen 15 Sep '14

15 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6914 -gerrit commit 93b0e49a26e423ac08fd34d3685b05a7654d3a27 Author: Andrew Bresticker <abrestic(a)chromium.org> Date: Wed Dec 18 22:41:34 2013 -0800 tegra124/nyan: memory and display updates tegra124: use pll_c_out1 as sclk parent Reviewed-on: https://chromium-review.googlesource.com/180865 (cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f) tegra124: take LP cluster out of reset Reviewed-on: https://chromium-review.googlesource.com/180866 (cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3) tegra124: norrin: display code clean up Reviewed-on: https://chromium-review.googlesource.com/181003 (cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17) tegra124: Change the display hack to use window A Reviewed-on: https://chromium-review.googlesource.com/182001 (cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a) tegra124: norrin: Initialize frame buffer Reviewed-on: https://chromium-review.googlesource.com/182090 (cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167) nyan: do not enable pull-ups on SPI1 (EC) data pins Reviewed-on: https://chromium-review.googlesource.com/181063 (cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c) tegra124: Add source for the LP0 resume blob. Reviewed-on: https://chromium-review.googlesource.com/183152 (cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b) tegra124: Revise Memory Controller registers structure definition. Reviewed-on: https://chromium-review.googlesource.com/182992 (cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1) tegra124: Add more PMC register details. Reviewed-on: https://chromium-review.googlesource.com/183231 (cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829) tegra124: Add SDRAM configuration header file from cbootimage. Reviewed-on: https://chromium-review.googlesource.com/182613 (cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4) tegra124: Revise sdram_param.h for Coreboot. Reviewed-on: https://chromium-review.googlesource.com/182614 (cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8) tegra124: Fix EMC base address. Reviewed-on: https://chromium-review.googlesource.com/183602 (cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e) tegra124: Add EMC registers definition. Reviewed-on: https://chromium-review.googlesource.com/183622 (cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a) tegra124: Never touch MEM(MC)/EMC clocks in ramstage. Reviewed-on: https://chromium-review.googlesource.com/183623 (cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023) tegra124: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/183833 (cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d) tegra124: Allow setting PLLM (clock for SDRAM). Reviewed-on: https://chromium-review.googlesource.com/183621 (cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683) tegra124: SDRAM Initialization. Reviewed-on: https://chromium-review.googlesource.com/182615 (cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce) tegra124: Get RAM_CODE for SDRAM initialization. Reviewed-on: https://chromium-review.googlesource.com/183781 (cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8) Squashed 18 nyan/tegra commits for memory and display. Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/nyan/bct/spi.cfg | 17 + src/mainboard/google/nyan/mainboard.c | 17 +- src/soc/nvidia/tegra124/Makefile.inc | 2 + src/soc/nvidia/tegra124/clk_rst.h | 25 +- src/soc/nvidia/tegra124/clock.c | 74 +- src/soc/nvidia/tegra124/display.c | 15 +- src/soc/nvidia/tegra124/displayhack.c | 303 +++------ src/soc/nvidia/tegra124/dp.c | 197 +++--- src/soc/nvidia/tegra124/emc.h | 323 +++++++++ src/soc/nvidia/tegra124/include/soc/addressmap.h | 2 +- src/soc/nvidia/tegra124/include/soc/clock.h | 3 + src/soc/nvidia/tegra124/include/soc/display.h | 17 +- src/soc/nvidia/tegra124/lp0/Makefile | 58 ++ src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 627 +++++++++++++++++ src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld | 73 ++ src/soc/nvidia/tegra124/mc.h | 127 +++- src/soc/nvidia/tegra124/pmc.h | 206 +++++- src/soc/nvidia/tegra124/sdram.c | 611 +++++++++++++++++ src/soc/nvidia/tegra124/sdram.h | 28 + src/soc/nvidia/tegra124/sdram_param.h | 816 +++++++++++++++++++++++ 20 files changed, 3173 insertions(+), 368 deletions(-) diff --git a/src/mainboard/google/nyan/bct/spi.cfg b/src/mainboard/google/nyan/bct/spi.cfg index b348ed8..7d05363 100644 --- a/src/mainboard/google/nyan/bct/spi.cfg +++ b/src/mainboard/google/nyan/bct/spi.cfg @@ -14,3 +14,20 @@ DeviceParam[0].SpiFlashParams.ClockDivider = 0x16; DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0; +DevType[1] = NvBootDevType_Spi; +DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[1].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0; + +DevType[2] = NvBootDevType_Spi; +DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[2].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0; + +DevType[3] = NvBootDevType_Spi; +DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[3].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0; diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 1229e74..6fa8a95 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -89,11 +89,11 @@ static void setup_pinmux(void) // SPI1 MOSI pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | - PINMUX_PULL_UP | + PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE); // SPI1 MISO pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | - PINMUX_PULL_UP | + PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE); // SPI1 SCLK pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | @@ -216,9 +216,9 @@ static void setup_kernel_info(void) // Not strictly info, but kernel graphics driver needs this region locked down struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE; - writel(0, &mc->mc_vpr_bom); - writel(0, &mc->mc_vpr_size); - writel(1, &mc->mc_vpr_ctrl); + writel(0, &mc->video_protect_bom); + writel(0, &mc->video_protect_size_mb); + writel(1, &mc->video_protect_reg_ctrl); } static void setup_ec_spi(void) @@ -243,14 +243,17 @@ static void mainboard_init(device_t dev) * conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out * of reset and clock-enabled, otherwise reading AHUB devices (In our * case, I2S/APBIF/AUDIO<XBAR>) will hang. + * + * Note that CLK_H_MEM (MC) and CLK_H_EMC should be already either + * initialized by BootROM, or in romstage SDRAM initialization. */ clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 | CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 | CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 | CLK_L_HOST1X, - CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 | - CLK_H_PMC | CLK_H_MEM | CLK_H_USB3, + CLK_H_I2C2 | CLK_H_SBC1 | CLK_H_PMC | + CLK_H_USB3, CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3, diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index b743570..7a6bced 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -20,10 +20,12 @@ endif romstage-y += cbfs.c romstage-y += cbmem.c +romstage-y += clock.c romstage-y += early_display.c romstage-y += dma.c romstage-y += i2c.c romstage-y += monotonic_timer.c +romstage-y += sdram.c romstage-y += spi.c romstage-y += ../tegra/gpio.c romstage-y += ../tegra/i2c.c diff --git a/src/soc/nvidia/tegra124/clk_rst.h b/src/soc/nvidia/tegra124/clk_rst.h index 156e9a6..efceec5 100644 --- a/src/soc/nvidia/tegra124/clk_rst.h +++ b/src/soc/nvidia/tegra124/clk_rst.h @@ -352,10 +352,20 @@ check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644); #define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT) /* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */ -#define PLLCMX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) +#define PLLCX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) +#define PLLM_BASE_DIVP_MASK (0x1U << PLL_BASE_DIVP_SHIFT) #define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT) #define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT) +/* PLLM specific registers */ +#define PLLM_MISC1_SETUP_SHIFT 0 +#define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT 28 +#define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT 29 +#define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT 30 +#define PLLM_MISC2_KCP_SHIFT 1 +#define PLLM_MISC2_KVCO_SHIFT 0 +#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) + /* Generic, indiscriminate divisor mask. May catch some innocent bystander bits * on the side that we don't particularly care about. */ #define PLL_BASE_DIV_MASK (0xffffff) @@ -414,6 +424,8 @@ check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644); #define CLK_SOURCE_SHIFT 29 #define CLK_SOURCE_MASK (0x7 << CLK_SOURCE_SHIFT) +#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16) + #define CLK_UART_DIV_OVERRIDE (1 << 24) /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ @@ -525,4 +537,15 @@ enum { CRC_RST_CPUG_CLR_PDBG = 0x1 << 30, }; +// RST_CPULP_CMPLX_CLR +enum { + CRC_RST_CPULP_CLR_CPU0 = 0x1 << 0, + CRC_RST_CPULP_CLR_DBG0 = 0x1 << 12, + CRC_RST_CPULP_CLR_CORE0 = 0x1 << 16, + CRC_RST_CPULP_CLR_CX0 = 0x1 << 20, + CRC_RST_CPULP_CLR_L2 = 0x1 << 24, + CRC_RST_CPULP_CLR_NONCPU = 0x1 << 29, + CRC_RST_CPULP_CLR_PDBG = 0x1 << 30, +}; + #endif /* _TEGRA124_CLK_RST_H_ */ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index d98da29..a642a7b 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -327,6 +327,63 @@ void clock_external_output(int clk_id) } } +/* Start PLLM for SDRAM. */ +void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, + u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, + u32 same_freq) +{ + u32 misc1 = ((setup << PLLM_MISC1_SETUP_SHIFT) | + (ph45 << PLLM_MISC1_PD_LSHIFT_PH45_SHIFT) | + (ph90 << PLLM_MISC1_PD_LSHIFT_PH90_SHIFT) | + (ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)), + misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) | + (kcp << PLLM_MISC2_KCP_SHIFT)), + base; + + if (same_freq) + emc_source |= CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; + else + emc_source &= ~CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; + + /* + * Note PLLM_BASE.PLLM_OUT1_RSTN must be in RESET_ENABLE mode, and + * PLLM_BASE.ENABLE must be in DISABLE state (both are the default + * values after coldboot reset). + */ + + writel(misc1, &clk_rst->pllm_misc1); + writel(misc2, &clk_rst->pllm_misc2); + + /* PLLM.BASE needs BYPASS=0, different from general init_pll */ + base = readl(&clk_rst->pllm_base); + base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK | + PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS); + base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | + (p << PLL_BASE_DIVP_SHIFT)); + writel(base, &clk_rst->pllm_base); + + setbits_le32(&clk_rst->pllm_base, PLL_BASE_ENABLE); + /* stable_time is required, before we can start to check lock. */ + udelay(stable_time); + + while (!(readl(&clk_rst->pllm_base) & PLL_BASE_LOCK)) { + udelay(1); + } + /* + * After PLLM reports being locked, we have to delay 10us before + * enabling PLLM_OUT. + */ + udelay(10); + + /* Put OUT1 out of reset state (start to output). */ + setbits_le32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE); + + /* Enable and start MEM(MC) and EMC. */ + clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); + writel(emc_source, &clk_rst->clk_src_emc); + udelay(IO_STABILIZATION_DELAY); +} + void clock_cpu0_config_and_reset(void *entry) { void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; @@ -357,6 +414,7 @@ void clock_cpu0_config_and_reset(void *entry) // Enable other CPU related clocks. setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); // Disable the reset on the non-CPU parts of the fast cluster. write32(CRC_RST_CPUG_CLR_NONCPU, @@ -372,6 +430,15 @@ void clock_cpu0_config_and_reset(void *entry) CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, &clk_rst->rst_cpug_cmplx_clr); + + // Disable the reset on the non-CPU parts of the slow cluster. + write32(CRC_RST_CPULP_CLR_NONCPU, + &clk_rst->rst_cpulp_cmplx_clr); + // Disable the various resets on the LP CPU. + write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | + CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | + CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG, + &clk_rst->rst_cpulp_cmplx_clr); } void clock_halt_avp(void) @@ -401,11 +468,10 @@ void clock_init(void) * features section in the TRM). */ write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT, &clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */ - write32(0 << SCLK_DIVIDEND_SHIFT | - (CEIL_DIV(TEGRA_PLLC_KHZ, 300000) - 1) << SCLK_DIVISOR_SHIFT - | SCLK_DIV_ENB, &clk_rst->super_sclk_div); + write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | + PLL_OUT_CLKEN | PLL_OUT_RSTN, &clk_rst->pllc_out); write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | - SCLK_SOURCE_PLLC_OUT0 << SCLK_RUN_SHIFT, + SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */ /* Change the oscillator drive strength (from U-Boot -- why?) */ diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 0572ce3..ba357fd 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -301,11 +301,6 @@ void display_startup(device_t dev) /* init dc_a */ init_dca_regs(); - /* init sor */ - init_sor_regs(); - - /* init dpaux */ - init_dpaux_regs(); /* power up perip */ dp_io_powerup(); @@ -313,13 +308,9 @@ void display_startup(device_t dev) /* bringup dp */ dp_bringup(framebuffer_base_mb*MiB); - { u16 *cp = (void *)(framebuffer_base_mb*MiB); - for(i = 0; i < 1048576*8; i++) - if (i % (1376 / 2) < 688 / 2) - cp[i] = 0x222; - else - cp[i] = 0x888; - } + /* init frame buffer */ + memset((void *)(framebuffer_base_mb*MiB), 0x00, + framebuffer_size_mb*MiB); /* tell depthcharge ... */ diff --git a/src/soc/nvidia/tegra124/displayhack.c b/src/soc/nvidia/tegra124/displayhack.c index 0f70e92..af0ac16 100644 --- a/src/soc/nvidia/tegra124/displayhack.c +++ b/src/soc/nvidia/tegra124/displayhack.c @@ -46,11 +46,6 @@ void debug_dpaux_print(u32 addr, u32 size); int dpaux_write(u32 addr, u32 size, u32 data); int dpaux_read(u32 addr, u32 size, u8 * data); -void init_dca_regs(void) -{ - printk(BIOS_SPEW, "%s: entry\n", __func__); - -#if 1 #define DCA_WRITE(reg, val) \ { \ WRITEL(val, (void *)(TEGRA_ARM_DISPLAYA + (reg<<2))); \ @@ -63,17 +58,31 @@ void init_dca_regs(void) _reg_val |= val; \ WRITEL(_reg_val, (void *)(TEGRA_ARM_DISPLAYA + (reg<<2))); \ } -#else // read back -#define DCA_WRITE(reg, val) \ + +#define SOR_WRITE(reg, val) \ + { \ + WRITEL(val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ + } + +#define SOR_READ(reg) READL((void *)(TEGRA_ARM_SOR + (reg<<2))) + +#define SOR_READ_M_WRITE(reg, mask, val) \ + { \ + u32 _reg_val; \ + _reg_val = READL((void *)(TEGRA_ARM_SOR + (reg<<2))); \ + _reg_val &= ~mask; \ + _reg_val |= val; \ + WRITEL(_reg_val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ + } + +#define DPAUX_WRITE(reg, val) \ { \ - printk(BIOS_SPEW,"DCA_WRITE: addr %#x = %#x\n", - (unsigned int) (TEGRA_ARM_DISPLAYA + (reg<<2)), val); \ - WRITEL(val, (void *)(TEGRA_ARM_DISPLAYA + (reg<<2))); \ - printk(BIOS_SPEW,"reads as %#x\n", \ - (unsigned int)READL( (void *)(TEGRA_ARM_DISPLAYA + (reg<<2)))); \ + WRITEL(val, (void *)(TEGRA_ARM_DPAUX + (reg<<2))); \ } -#endif +#define DPAUX_READ(reg) READL((void *)(TEGRA_ARM_DPAUX + (reg<<2))) +void init_dca_regs(void) +{ DCA_WRITE (DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x000000F0); DCA_WRITE (DC_WIN_A_WIN_OPTIONS_0, 0x00000000); DCA_WRITE (DC_WIN_A_BYTE_SWAP_0, 0x00000000); @@ -105,86 +114,20 @@ void init_dca_regs(void) DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE1_0, 0x00000000); DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE2_0, 0x00510104); DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE3_0, 0x00000555); - - printk(BIOS_SPEW, "initial DCA done\n"); -} - -void init_sor_regs(void) -{ - - printk(BIOS_SPEW, "JZ: %s: entry\n", __func__); - -#if 1 -#define SOR_WRITE(reg, val) \ - { \ - WRITEL(val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ - } - -#define SOR_READ(reg) READL( (void *)(TEGRA_ARM_SOR + (reg<<2))) - -#else // read back -#define SOR_WRITE(reg, val) \ - { \ - printk(BIOS_SPEW,"SOR_WRITE: addr %#x = %#x\n", - (unsigned int) (TEGRA_ARM_SOR + (reg<<2)), val); \ - WRITEL(val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ - printk(BIOS_SPEW,"= %#x\n", \ - (unsigned int)READL( (void *)(TEGRA_ARM_SOR + (reg<<2)))); \ - } -#endif -#define SOR_READ_M_WRITE(reg, mask, val) \ - { \ - u32 _reg_val; \ - _reg_val = READL( (void *)(TEGRA_ARM_SOR + (reg<<2))); \ - _reg_val &= ~mask; \ - _reg_val |= val; \ - WRITEL(_reg_val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ - } - - printk(BIOS_SPEW, "initial SOR done\n"); -} - -void init_dpaux_regs(void) -{ - - printk(BIOS_SPEW, "%s: entry\n", __func__); - -#if 1 -#define DPAUX_WRITE(reg, val) \ - { \ - WRITEL(val, (void *)(TEGRA_ARM_DPAUX + (reg<<2))); \ - } -#define DPAUX_READ(reg) READL( (void *)(TEGRA_ARM_DPAUX + (reg<<2))) - -#else // read back -#define DPAUX_WRITE(reg, val) \ - { \ - printk(BIOS_SPEW,"DPAUX_WRITE: addr %#x = %#x\n", (unsigned int) - (TEGRA_ARM_DPAUX + (reg<<2)), val); \ - WRITEL(val, (void *)(TEGRA_ARM_DPAUX + (reg<<2))); \ - printk(BIOS_SPEW,"= %#x\n", \ - (unsigned int)READL( (void *)(TEGRA_ARM_DPAUX + (reg<<2)))); \ - } -#endif - - printk(BIOS_SPEW, "initial DPAUX done\n"); } static int dp_poll_register(void *addr, u32 exp_val, u32 mask, u32 timeout_ms) { - u32 reg_val = 0; - printk(BIOS_SPEW, "JZ: %s: enter, addr %#x: exp_val: %#x, mask: %#x\n", - __func__, (unsigned int)addr, exp_val, mask); do { - udelay(1); + udelay(1000); reg_val = READL(addr); } while (((reg_val & mask) != exp_val) && (--timeout_ms > 0)); if ((reg_val & mask) == exp_val) return 0; /* success */ - printk(BIOS_SPEW, "poll_register %p: timeout\n", addr); + printk(BIOS_WARNING, "poll_register %p: timeout\n", addr); return timeout_ms; } @@ -196,15 +139,10 @@ static void dp_io_set_dpd(u32 power_down) * 1: into deep power down */ u32 val_reg; -#define DP_LVDS_SHIFT 25 -#define DP_LVDS (1 << DP_LVDS_SHIFT) val_reg = READL((void *)(0x7000e400 + 0x1c4)); /* APBDEV_PMC_IO_DPD2_STATUS_0 */ - printk(BIOS_SPEW, "JZ: %s: enter, into dpd %d, cur_status: %#x\n", - __func__, power_down, val_reg); - if ((((val_reg & DP_LVDS) >> DP_LVDS_SHIFT) & 1) == power_down) { - printk(BIOS_SPEW, "PAD already POWER=%d\n", 1 - power_down); + printk(BIOS_DEBUG, "PAD already POWER=%d\n", 1 - power_down); return; } @@ -212,14 +150,11 @@ static void dp_io_set_dpd(u32 power_down) WRITEL((DP_LVDS | ((1 + power_down) << 30)), (void *)(0x7000e400 + 0x1c0)); dp_poll_register((void *)(0x7000e400 + 0x1C4), 0, DP_LVDS, 1000); - //APBDEV_PMC_IO_DPD2_STATUS_0 + /* APBDEV_PMC_IO_DPD2_STATUS_0 */ } void dp_io_powerup(void) { - - printk(BIOS_SPEW, "%s: entry\n", __func__); - SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, (6 << 2) | 2);//select PLLDP, lowest speed(6x) SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, 0x00800000); //set PDCAL SOR_WRITE(SOR_NV_PDISP_SOR_PLL0_0, 0x050003D5); //set PWR,VCOPD @@ -227,14 +162,21 @@ void dp_io_powerup(void) SOR_WRITE(SOR_NV_PDISP_SOR_PLL2_0, 0x01C20000); //set AUX1,6,7,8; clr AUX2 SOR_WRITE(SOR_NV_PDISP_SOR_PLL3_0, 0x38002220); + /* Deassert E_DPD to enable core logic circuits, and wait for > 5us */ dp_io_set_dpd(0); - udelay(1); //Deassert E_DPD to enable core logic circuits, and wait for > 5us + udelay(10); + /* Deassert PDBG to enable bandgap, and wait for > 20us. */ SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL2_0, SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD, (0 << SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT)); - udelay(20); //Deassert PDBG to enable bandgap, and wait for > 20us. + udelay(25); + /* + * Enable the PLL/charge-pump/VCO, and wait for >200us for the PLL to + * lock. Input Clock must be running and stable before PDPLL + * de-assertion. + */ SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL0_0, SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD, (0 << SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT)); @@ -244,10 +186,8 @@ void dp_io_powerup(void) SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL2_0, SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD, (0 << SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT)); - udelay(200); - //Enable the PLL/charge-pump/VCO, and wait for >200us for the PLL to - //lock. Input Clock must be running and stable before PDPLL - //de-assertion. + udelay(210); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL2_0, SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD, (0 << SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT)); @@ -256,7 +196,6 @@ void dp_io_powerup(void) (1 << SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT)); udelay(100); - printk(BIOS_SPEW, "%s: exit\n", __func__); } static int dpaux_check(u32 bytes, u32 data, u32 mask) @@ -268,18 +207,19 @@ static int dpaux_check(u32 bytes, u32 data, u32 mask) DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W0, 0); status = dpaux_read(0x202, bytes, buf); if (status != 0) - printk(BIOS_SPEW, "******AuxRead Error:%04x: status %08x\n", 0x202, - status); + printk(BIOS_ERR, "******AuxRead Error:%04x: status %08x\n", + 0x202, status); else { temp = DPAUX_READ(DPAUX_DP_AUXDATA_READ_W0); if ((temp & mask) != (data & mask)) { - printk(BIOS_SPEW, "AuxCheck ERROR:(r_data) %08x & (mask) %08x != " - "(data) %08x & (mask) %08x\n", temp, mask, data, mask); + printk(BIOS_ERR, "AuxCheck ERROR:(r_data) %08x &" + " (mask) %08x != (data) %08x & (mask) %08x\n", + temp, mask, data, mask); return -1; } else { - printk(BIOS_SPEW, - "AuxCheck PASS:(bytes=%d,data=%08x,mask=%08x):0x%08x\n", - bytes, data, mask, temp); + printk(BIOS_DEBUG, "AuxCheck PASS:(bytes=%d, " + "data=%08x, mask=%08x):0x%08x\n", + bytes, data, mask, temp); return 0; } } @@ -304,8 +244,6 @@ static int dpaux_check(u32 bytes, u32 data, u32 mask) */ static void pattern_level(u32 current, u32 preemph, u32 postcur) { - printk(BIOS_SPEW, "set level:%d %d %d\n", current, preemph, postcur); - //calibrating required if (current == 0) SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0, 0x20202020); @@ -355,7 +293,7 @@ static int dp_training(u32 level, u32 check, u32 speed) wcfg = wcfg | 0x20; wcfg = wcfg | (wcfg << 8) | (wcfg << 16) | (wcfg << 24); dpaux_write(0x103, 4, wcfg); - udelay(50); //100us + udelay(100); DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W0, 0); if (!dpaux_check(2, check, check)) cnt = 100; @@ -366,7 +304,7 @@ static int dp_training(u32 level, u32 check, u32 speed) if (cfg == cfg_d) { ++cnt; if (cnt > 5) - printk(BIOS_SPEW, "link training FAILED\n"); + printk(BIOS_ERR, "Error: link training FAILED\n"); } else { cnt = 0; cfg_d = cfg; @@ -396,10 +334,7 @@ void dp_link_training(u32 lanes, u32 speed) u32 mask, level; u32 reg_val; - printk(BIOS_SPEW, "%s: entry, lanes: %d, speed: %d\n", __func__, lanes, - speed); - - printk(BIOS_SPEW, "\nLink training start\n"); + printk(BIOS_DEBUG, "\nLink training start\n"); switch (lanes) { case 1: @@ -412,21 +347,22 @@ void dp_link_training(u32 lanes, u32 speed) lane_on = 0x0f; break; default: - printk(BIOS_SPEW, "dp: invalid lane count: %d\n", lanes); + printk(BIOS_DEBUG, "dp: invalid lane count: %d\n", + lanes); return; } SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, (0x008000000 | lane_on)); SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, - SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD, - (6 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT)); + SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD, + (6 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT)); SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, - SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD, - (1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT)); + SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD, + (1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT)); SOR_WRITE(SOR_NV_PDISP_SOR_LVDS_0, 0); SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, ((speed << 2) | 2)); - udelay(100); + udelay(100 * 1000); sor_clock_start(); @@ -434,34 +370,34 @@ void dp_link_training(u32 lanes, u32 speed) (((0xF >> (4 - lanes)) << 16) | 1)); SOR_WRITE(SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0, 0x80100000); - printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0.DONE\n"); + printk(BIOS_DEBUG, "Polling SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0.DONE\n"); dp_poll_register((void *)0x54540084, 0x00000000, 0x80000000, 1000); debug_dpaux_print(0x202, 4); - printk(BIOS_SPEW, "set link rate and lane number: %dMHz, %d lanes\n", + printk(BIOS_DEBUG, "set link rate and lane number: %dMHz, %d lanes\n", (speed * 27), lanes); dpaux_write(0x100, 2, ((lanes << 8) | speed)); - printk(BIOS_SPEW, "precharge lane 10us\n"); + printk(BIOS_DEBUG, "precharge lane 10us\n"); reg_val = SOR_READ(SOR_NV_PDISP_SOR_DP_PADCTL0_0); SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, (0x000000f0 | reg_val)); - udelay(100); + udelay(100 * 1000); SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, reg_val); - printk(BIOS_SPEW, "link training cr start\n"); + printk(BIOS_DEBUG, "link training cr start\n"); SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x41414141); dpaux_write(0x102, 1, 0x21); mask = 0x0000ffff >> ((4 - lanes) * 4); level = 0; level = dp_training(level, 0x1111 & mask, speed); - printk(BIOS_SPEW, "level:%x\n", level); + printk(BIOS_DEBUG, "level:%x\n", level); debug_dpaux_print(0x210, 16); - printk(BIOS_SPEW, "link training eq start\n"); + printk(BIOS_DEBUG, "link training eq start\n"); if (speed == 20) { SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x43434343); dpaux_write(0x102, 1, 0x23); @@ -471,7 +407,7 @@ void dp_link_training(u32 lanes, u32 speed) } level = dp_training(level, (0x7777 & mask) | 0x10000, speed); - printk(BIOS_SPEW, "level:%x\n", level); + printk(BIOS_DEBUG, "level:%x\n", level); debug_dpaux_print(0x210, 16); @@ -482,8 +418,7 @@ void dp_link_training(u32 lanes, u32 speed) debug_dpaux_print(0x200, 16); debug_dpaux_print(0x210, 16); - printk(BIOS_SPEW, "Link training done\n\n"); - printk(BIOS_SPEW, "%s: exit\n", __func__); + printk(BIOS_DEBUG, "Link training done\n\n"); } static u32 div_f(u32 a, u32 b, u32 one) @@ -492,23 +427,10 @@ static u32 div_f(u32 a, u32 b, u32 one) return (d); } -u32 dp_setup_timing(u32 panel_id, u32 width, u32 height); -u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) +u32 dp_setup_timing(u32 width, u32 height) { u32 pclk_freq = 0; - /////////////////////////////////////////// - // set up clocks, using PLLD2 - // format: pclk , PLL , panel - //2560x1440: 241.5 , 483/2, dp VESA.red. - //1920x1080: 148.5 , 594/4, dp CEA - //1600x1200: 161.0 , 483/3, dp VESA - //1280x 720: 74.25 , 594/8, dp CEA - // 1024x768: 63.5 , 508/8, dp VESA - // 800x600: 38.25 , 459/12, dp VESA - // 720x480: 27.00 , 594/22, dp CEA - // 640x480: 23.75 , 475/20, dp VESA - u32 PLL_FREQ = (12 / 12 * 283) / 1 / 2; /* 141.5 */ u32 PLL_DIV = 2; u32 SYNC_WIDTH = (8 << 16) | 46; @@ -529,14 +451,6 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) u32 PCLK_FREQ_I, PCLK_FREQ_F; u32 FRATE_I, FRATE_F; - printk(BIOS_SPEW, "%s: entry\n", __func__); - - if (panel_id != 5) { - printk(BIOS_SPEW, "%s: Unsupported panel_id: %d, format=%dx%d\n", - __func__, panel_id, width, height); - return pclk_freq; - } - PLL_FREQ = PLL_FREQ * 1000000; pclk_freq = PLL_FREQ / PLL_DIV; PLL_FREQ_I = PLL_FREQ / 1000000; @@ -545,19 +459,19 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) PCLK_FREQ_F = div_f(PLL_FREQ, PLL_DIV * 1000000, 100); FRATE_I = PLL_FREQ / (PLL_DIV * TOTAL_PIXELS); FRATE_F = div_f(PLL_FREQ, (PLL_DIV * TOTAL_PIXELS), 100); - //bug 1021453 + /* nv_bug 1021453 */ BACK_PORCH = BACK_PORCH - 0x10000; FRONT_PORCH = FRONT_PORCH + 0x10000; - printk(BIOS_SPEW, "ACTIVE: %dx%d\n", (DISP_ACTIVE & 0xFFFF), + printk(BIOS_DEBUG, "ACTIVE: %dx%d\n", (DISP_ACTIVE & 0xFFFF), (DISP_ACTIVE >> 16)); - printk(BIOS_SPEW, "TOTAL: %dx%d\n", (DISP_TOTAL & 0xffff), + printk(BIOS_DEBUG, "TOTAL: %dx%d\n", (DISP_TOTAL & 0xffff), (DISP_TOTAL >> 16)); - printk(BIOS_SPEW, "PLL Freq: %d.%d MHz\n", PLL_FREQ_I, PLL_FREQ_F); - printk(BIOS_SPEW, "Pclk Freq: %d.%d MHz\n", PCLK_FREQ_I, + printk(BIOS_DEBUG, "PLL Freq: %d.%d MHz\n", PLL_FREQ_I, PLL_FREQ_F); + printk(BIOS_DEBUG, "Pclk Freq: %d.%d MHz\n", PCLK_FREQ_I, PCLK_FREQ_F); - printk(BIOS_SPEW, "Frame Rate: %d.%d Hz\n", FRATE_I, FRATE_F); - printk(BIOS_SPEW, "\n"); + printk(BIOS_DEBUG, "Frame Rate: %d.%d Hz\n", FRATE_I, FRATE_F); + printk(BIOS_DEBUG, "\n"); DCA_WRITE(DC_CMD_STATE_ACCESS_0, 0x00000004); DCA_WRITE(DC_DISP_DISP_CLOCK_CONTROL_0, SHIFT_CLK_DIVIDER); @@ -569,9 +483,6 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) DCA_WRITE(DC_DISP_DISP_ACTIVE_0, DISP_ACTIVE); DCA_WRITE(DC_DISP_FRONT_PORCH_0, FRONT_PORCH); - printk(BIOS_SPEW, - "JZ: sync_width: %d, back_porch: %d, disp_active: %d, front_porch: %d\n", - SYNC_WIDTH, BACK_PORCH, DISP_ACTIVE, FRONT_PORCH); //REG(DC_DISP_DISP_WIN_OPTIONS_0, SOR_ENABLE , 1) DCA_READ_M_WRITE(DC_DISP_DISP_WIN_OPTIONS_0, DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD, @@ -611,7 +522,6 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD, (SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 << SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT)); - printk(BIOS_SPEW, "%s: exit\n", __func__); return pclk_freq; } @@ -623,7 +533,9 @@ static u32 calc_config(u32 ts, u32 a, u32 b, u32 bpp) u32 act_frac; u32 err; u32 water_mark; - printk(BIOS_SPEW, "calc_config ts %d a %d b %d bpp %d\n", ts, a, b, bpp); + + printk(BIOS_DEBUG, "calc_config ts %d a %d b %d bpp %d\n", + ts, a, b, bpp); if (diff != 0) { if (diff > (b / 2)) { diff = b - diff; @@ -669,7 +581,7 @@ static u32 calc_config(u32 ts, u32 a, u32 b, u32 bpp) (water_mark << SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT)); - printk(BIOS_SPEW, + printk(BIOS_DEBUG, "SOR_DP_CONFIG0:TU,CNT,POL,FRAC,WMK,ERR=%d,%d,%d,%d,%d,%d/%d\n", ts, act_cnt, act_pol, act_frac, water_mark, err, b); } @@ -687,7 +599,8 @@ static u32 dp_buf_config(u32 pclkfreq, u32 linkfreq, u32 lanes, u32 bpp) u32 min_err = 1000000000; u32 ts = 64; u32 c_err; - printk(BIOS_SPEW, "dp buf config pclkfreq %d linkfreq %d lanes %d bpp %d\n", + + printk(BIOS_DEBUG, "dp buf config pclkfreq %d linkfreq %d lanes %d bpp %d\n", pclkfreq, linkfreq, lanes, bpp); for (i = 2; i <= 7; ++i) { while (((pf / i * i) == pf) && ((lf / i * i) == lf)) { @@ -698,9 +611,9 @@ static u32 dp_buf_config(u32 pclkfreq, u32 linkfreq, u32 lanes, u32 bpp) a = pf * bpp / 8; b = lf * lanes; - printk(BIOS_SPEW, "ratio:%d/%d\n", a, b); + printk(BIOS_DEBUG, "ratio:%d/%d\n", a, b); if (a > (b * 98 / 100)) - printk(BIOS_SPEW, "Error:link speed not enough\n"); + printk(BIOS_ERR, "Error:link speed not enough\n"); //search best tusize //min_err = 1000000000; @@ -727,10 +640,11 @@ static u32 dp_buf_config(u32 pclkfreq, u32 linkfreq, u32 lanes, u32 bpp) return (tusize); } +/* void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, u32 lane_count, u32 enhanced_framing, u32 panel_edp, u32 pclkfreq, u32 linkfreq); - +*/ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, u32 lane_count, u32 enhanced_framing, u32 panel_edp, u32 pclkfreq, u32 linkfreq) @@ -738,8 +652,8 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, u32 tusize; u32 linkctl; - printk(BIOS_SPEW, "%s: entry, winb: 0x%08x ", __func__, winb_addr); - printk(BIOS_SPEW, " panel_bpp %d\n", panel_bpp); + printk(BIOS_DEBUG, "%s: winb: 0x%08x, panel_bpp %d ", + __func__, winb_addr, panel_bpp); if (panel_bpp == 18) { //0x54540010 @@ -755,37 +669,25 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT)); } -#define SRC_BPP 16 -#define COLORDEPTH 0x6 - -#define BLUE 0xFF0000 -#define GREEN 0x00FF00 -#define RED 0x0000FF -#define YELLOW 0x00FFFF -#define BLACK 0x000000 -#define WHITE 0xFFFFFF -#define GREY 0x55aa00 - - DCA_WRITE(DC_B_WIN_BD_SIZE_0, ((height << 16) | width)); - DCA_WRITE(DC_B_WIN_BD_PRESCALED_SIZE_0, + DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000010); + DCA_WRITE(DC_WIN_A_SIZE_0, ((height << 16) | width)); + DCA_WRITE(DC_WIN_A_PRESCALED_SIZE_0, ((height << 16) | (width * SRC_BPP / 8))); - DCA_WRITE(DC_B_WIN_BD_LINE_STRIDE_0, + DCA_WRITE(DC_WIN_A_LINE_STRIDE_0, ((width * SRC_BPP / 8 + 31) / 32 * 32)); - DCA_WRITE(DC_B_WIN_BD_COLOR_DEPTH_0, COLORDEPTH); - DCA_WRITE(DC_B_WINBUF_BD_START_ADDR_0, winb_addr); - DCA_WRITE(DC_B_WIN_BD_DDA_INCREMENT_0, 0x10001000); + DCA_WRITE(DC_WIN_A_COLOR_DEPTH_0, COLORDEPTH); + DCA_WRITE(DC_WINBUF_A_START_ADDR_LO_0, winb_addr); + DCA_WRITE(DC_WIN_A_DDA_INCREMENT_0, 0x10001000); SOR_WRITE(SOR_NV_PDISP_SOR_CRC_CNTRL_0, 0x00000001); DCA_WRITE(DC_COM_CRC_CONTROL_0, 0x00000009); //CRC_ALWAYS+CRC_ENABLE DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE2_0, 0x00000000); DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE3_0, 0x00000000); DCA_WRITE(DC_DISP_DISP_SIGNAL_OPTIONS0_0, 0x00000000); - // DCA_WRITE (DC_DISP_BLEND_BACKGROUND_COLOR_0 ,WHITE ); - DCA_WRITE(DC_DISP_BLEND_BACKGROUND_COLOR_0, YELLOW); + DCA_WRITE(DC_DISP_BLEND_BACKGROUND_COLOR_0, COLOR_WHITE); DCA_WRITE(DC_CMD_DISPLAY_COMMAND_0, 0x00000020); SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0, 0x00000e48); - dpaux_write(0x101, 1, (enhanced_framing << 7) | lane_count); if (panel_edp) dpaux_write(0x10A, 1, 1); @@ -793,8 +695,6 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, tusize = dp_buf_config(pclkfreq, (linkfreq * 1000000), lane_count, panel_bpp); - printk(BIOS_SPEW, "JZ, after dp_buf_config, tusize: 0x%08x\n", tusize); - linkctl = ((0xF >> (4 - lane_count)) << 16) | (enhanced_framing << 14) | (tusize << 2) | @@ -804,7 +704,7 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, SOR_WRITE(SOR_NV_PDISP_SOR_DP_SPARE0_0, ((panel_edp << 1) | 0x05)); SOR_WRITE(SOR_NV_PDISP_SOR_PWR_0, 0x80000001); - printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_PWR_0.DONE\n"); + printk(BIOS_DEBUG, "Polling SOR_NV_PDISP_SOR_PWR_0.DONE\n"); dp_poll_register((void *)0x54540054, 0x00000000, 0x80000000, 1000); //SOR_NV_PDISP_SOR_PWR_0 //sor_update @@ -815,7 +715,7 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE1_0, 0x0000000e); //sor_super_update SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE0_0, 0x00000000); - printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_TEST_0.ATTACHED\n"); + printk(BIOS_DEBUG, "Polling SOR_NV_PDISP_SOR_TEST_0.ATTACHED\n"); dp_poll_register((void *)0x54540058, 0x00000400, 0x00000400, 1000); //SOR_NV_PDISP_SOR_TEST_0 @@ -823,21 +723,16 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x0000009f); DCA_WRITE(DC_CMD_DISPLAY_POWER_CONTROL_0, 0x00050155); - printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_TEST_0.AWAKE\n"); + printk(BIOS_DEBUG, "Polling SOR_NV_PDISP_SOR_TEST_0.AWAKE\n"); dp_poll_register((void *)0x54540058, 0x00000200, 0x00000300, 1000); //SOR_NV_PDISP_SOR_TEST_0 // DCA_WRITE (DC_CMD_STATE_ACCESS_0 ,0); DCA_WRITE(DC_CMD_STATE_ACCESS_0, 4); DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x0000ffff); - /* enable win_b */ - - DCA_READ_M_WRITE(DC_B_WIN_BD_WIN_OPTIONS_0, - DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD, - (DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE << - DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT)); - - printk(BIOS_SPEW, "JZ: %s: f_ret @ line %d\n", __func__, __LINE__); + DCA_READ_M_WRITE(DC_WIN_A_WIN_OPTIONS_0, + DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD, + (DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE << + DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT)); } - diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 3205699..6b0f4c8 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -39,33 +39,36 @@ static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) } static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, - u32 reg, u32 val) + u32 reg, u32 val) { void *addr = dp->aux_base + (u32) (reg << 2); WRITEL(val, addr); } static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp, - u32 reg, u32 mask, u32 exp_val, - u32 poll_interval_us, - u32 timeout_ms) + u32 reg, u32 mask, u32 exp_val, + u32 poll_interval_us, + u32 timeout_us) { u32 reg_val = 0; + u32 temp = timeout_us; - printk(BIOS_SPEW, "JZ: %s: enter, poll_reg: %#x: timeout: 0x%x\n", - __func__, reg * 4, timeout_ms); do { - udelay(1); + udelay(poll_interval_us); reg_val = tegra_dpaux_readl(dp, reg); - } while (((reg_val & mask) != exp_val) && (--timeout_ms > 0)); + if (timeout_us > poll_interval_us) + timeout_us -= poll_interval_us; + else + break; + } while ((reg_val & mask) != exp_val); if ((reg_val & mask) == exp_val) return 0; /* success */ - printk(BIOS_SPEW, + printk(BIOS_ERR, "dpaux_poll_register 0x%x: timeout: " "(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", reg, reg_val, mask, exp_val); - return timeout_ms; + return temp; } static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp) @@ -73,18 +76,18 @@ static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp) /* According to DP spec, each aux transaction needs to finish within 40ms. */ if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL, - DPAUX_DP_AUXCTL_TRANSACTREQ_MASK, - DPAUX_DP_AUXCTL_TRANSACTREQ_DONE, - 100, DP_AUX_TIMEOUT_MS * 1000) != 0) { - printk(BIOS_SPEW, "dp: DPAUX transaction timeout\n"); + DPAUX_DP_AUXCTL_TRANSACTREQ_MASK, + DPAUX_DP_AUXCTL_TRANSACTREQ_DONE, + 100, DP_AUX_TIMEOUT_MS * 1000) != 0) { + printk(BIOS_INFO, "dp: DPAUX transaction timeout\n"); return -1; } return 0; } static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, - u32 addr, u8 * data, u32 * size, - u32 * aux_stat) + u32 addr, u8 *data, u32 *size, + u32 *aux_stat) { int i; u32 reg_val; @@ -102,21 +105,11 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, case DPAUX_DP_AUXCTL_CMD_AUXWR: break; default: - printk(BIOS_SPEW, "dp: aux write cmd 0x%x is invalid\n", cmd); + printk(BIOS_ERR, "dp: aux write cmd 0x%x is invalid\n", + cmd); return -1; } -#if 0 -/* interesting. */ - if (tegra_platform_is_silicon()) { - *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { - printk(BIOS_SPEW, "dp: HPD is not detected\n"); - return -EFAULT; - } - } -#endif - tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) { memcpy(&temp_data, data, 4); @@ -139,7 +132,7 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); if (tegra_dpaux_wait_transaction(dp)) - printk(BIOS_SPEW, "dp: aux write transaction timeout\n"); + printk(BIOS_ERR, "dp: aux write transaction timeout\n"); *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); @@ -148,13 +141,13 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { if (timeout_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux write retry (0x%x) -- %d\n", + printk(BIOS_INFO, "dp: aux write retry (0x%x) -- %d\n", *aux_stat, timeout_retries); /* clear the error bits */ tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat); continue; } else { - printk(BIOS_SPEW, "dp: aux write got error (0x%x)\n", + printk(BIOS_ERR, "dp: aux write got error (0x%x)\n", *aux_stat); return -1; } @@ -163,13 +156,13 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { if (defer_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux write defer (0x%x) -- %d\n", + printk(BIOS_INFO, "dp: aux write defer (0x%x) -- %d\n", *aux_stat, defer_retries); /* clear the error bits */ tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat); continue; } else { - printk(BIOS_SPEW, "dp: aux write defer exceeds max retries " + printk(BIOS_ERR, "dp: aux write defer exceeds max retries " "(0x%x)\n", *aux_stat); return -1; } @@ -180,7 +173,8 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); return 0; } else { - printk(BIOS_SPEW, "dp: aux write failed (0x%x)\n", *aux_stat); + printk(BIOS_ERR, "dp: aux write failed (0x%x)\n", + *aux_stat); return -1; } } @@ -189,7 +183,7 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, } static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, - u8 * data, u32 * size, u32 * aux_stat) + u8 *data, u32 *size, u32 *aux_stat) { u32 cur_size = 0; u32 finished = 0; @@ -202,7 +196,7 @@ static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, cur_size = DP_AUX_MAX_BYTES; cur_left = cur_size; ret = tegra_dc_dpaux_write_chunk(dp, cmd, addr, - data, &cur_left, aux_stat); + data, &cur_left, aux_stat); cur_size -= cur_left; finished += cur_size; @@ -218,8 +212,8 @@ static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, } static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, - u32 addr, u8 * data, u32 * size, - u32 * aux_stat) + u32 addr, u8 *data, u32 *size, + u32 *aux_stat) { u32 reg_val; u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; @@ -236,7 +230,8 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, case DPAUX_DP_AUXCTL_CMD_AUXRD: break; default: - printk(BIOS_SPEW, "dp: aux read cmd 0x%x is invalid\n", cmd); + printk(BIOS_ERR, "dp: aux read cmd 0x%x is invalid\n", + cmd); return -1; } @@ -253,37 +248,38 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; reg_val |= cmd; - printk(BIOS_SPEW, "cmd = %08x\n", reg_val); reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); - printk(BIOS_SPEW, "cmd = %08x\n", reg_val); while ((timeout_retries > 0) && (defer_retries > 0)) { if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || (defer_retries != DP_AUX_DEFER_MAX_TRIES)) udelay(DP_DPCP_RETRY_SLEEP_NS * 2); reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; - printk(BIOS_SPEW, "cmd = %08x\n", reg_val); tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); if (tegra_dpaux_wait_transaction(dp)) - printk(BIOS_SPEW, "dp: aux read transaction timeout\n"); + printk(BIOS_INFO, "dp: aux read transaction timeout\n"); *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - printk(BIOS_SPEW, "dp: %s: aux stat: 0x%08x\n", __func__, *aux_stat); + printk(BIOS_DEBUG, "dp: %s: aux stat: 0x%08x\n", __func__, + *aux_stat); if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { if (timeout_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux read retry (0x%x) -- %d\n", - *aux_stat, timeout_retries); + printk(BIOS_INFO, "dp: aux read retry (0x%x)" + " -- %d\n", *aux_stat, + timeout_retries); /* clear the error bits */ - tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat); + tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, + *aux_stat); continue; /* retry */ } else { - printk(BIOS_SPEW, "dp: aux read got error (0x%x)\n", *aux_stat); + printk(BIOS_ERR, "dp: aux read got error" + " (0x%x)\n", *aux_stat); return -1; } } @@ -291,13 +287,13 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { if (defer_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux read defer (0x%x) -- %d\n", + printk(BIOS_INFO, "dp: aux read defer (0x%x) -- %d\n", *aux_stat, defer_retries); /* clear the error bits */ tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat); continue; } else { - printk(BIOS_SPEW, "dp: aux read defer exceeds max retries " + printk(BIOS_INFO, "dp: aux read defer exceeds max retries " "(0x%x)\n", *aux_stat); return -1; } @@ -310,20 +306,22 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) temp_data[i] = tegra_dpaux_readl(dp, - DPAUX_DP_AUXDATA_READ_W(i)); + DPAUX_DP_AUXDATA_READ_W(i)); *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); - printk(BIOS_SPEW, "dp: aux read data %d bytes\n", *size); + printk(BIOS_INFO, "dp: aux read data %d bytes\n", + *size); memcpy(data, temp_data, *size); return 0; } else { - printk(BIOS_SPEW, "dp: aux read failed (0x%x\n", *aux_stat); + printk(BIOS_ERR, "dp: aux read failed (0x%x\n", + *aux_stat); return -1; } } /* Should never come to here */ - printk(BIOS_SPEW, "%s: can't\n", __func__); + printk(BIOS_ERR, "%s: can't\n", __func__); return -1; } @@ -340,7 +338,7 @@ int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, cur_size = DP_AUX_MAX_BYTES; ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr, - data, &cur_size, aux_stat); + data, &cur_size, aux_stat); /* cur_size should be the real size returned */ addr += cur_size; @@ -350,12 +348,6 @@ int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, if (ret) break; -#if 0 - if (cur_size == 0) { - printk(BIOS_SPEW, "JZ: no data found, ret\n"); - break; - } -#endif } while (*size > finished); *size = finished; @@ -372,7 +364,7 @@ static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, cmd, data_ptr, &size, &status); if (ret) - printk(BIOS_SPEW, + printk(BIOS_ERR, "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n", cmd, status); @@ -380,7 +372,7 @@ static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, } static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp, - struct tegra_dc_dp_link_config *cfg) + struct tegra_dc_dp_link_config *cfg) { u8 dpcd_data; int ret; @@ -390,27 +382,26 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp, return ret; cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK; - printk(BIOS_SPEW, "JZ: %s: max_lane_count: %d\n", __func__, + printk(BIOS_INFO, "%s: max_lane_count: %d\n", __func__, cfg->max_lane_count); cfg->support_enhanced_framing = (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? 1 : 0; - printk(BIOS_SPEW, "JZ: %s: enh-framing: %d\n", __func__, + printk(BIOS_INFO, "%s: enh-framing: %d\n", __func__, cfg->support_enhanced_framing); ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD, &dpcd_data); if (ret) return ret; cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ? 1 : 0; - printk(BIOS_SPEW, "JZ: %s: downspread: %d\n", __func__, cfg->downspread); + printk(BIOS_INFO, "%s: downspread: %d\n", __func__, cfg->downspread); ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH, &cfg->max_link_bw); if (ret) return ret; - printk(BIOS_SPEW, "JZ: %s: max_link_bw: %d\n", __func__, cfg->max_link_bw); + printk(BIOS_INFO, "%s: max_link_bw: %d\n", __func__, cfg->max_link_bw); - // jz, changed // cfg->bits_per_pixel = dp->dc->pdata->default_out->depth; cfg->bits_per_pixel = 18; @@ -427,7 +418,7 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp, (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ? 1 : 0; cfg->only_enhanced_framing = (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ? 1 : 0; - printk(BIOS_SPEW, "JZ: %s: alt_reset_cap: %d, only_enh_framing: %d\n", + printk(BIOS_DEBUG, "%s: alt_reset_cap: %d, only_enh_framing: %d\n", __func__, cfg->alt_scramber_reset_cap, cfg->only_enhanced_framing); cfg->lane_count = cfg->max_lane_count; @@ -448,13 +439,13 @@ static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp, u8 * rev) ret = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, NV_DPCD_REV, rev, &size, &status); if (ret) { - printk(BIOS_SPEW, "dp: Failed to read NV_DPCD_REV\n"); + printk(BIOS_WARNING, "dp: Failed to read NV_DPCD_REV\n"); return ret; } return 0; } -u32 dp_setup_timing(u32 panel_id, u32 width, u32 height); +u32 dp_setup_timing(u32 width, u32 height); void dp_bringup(u32 winb_addr) { struct tegra_dc_dp_data *dp = &dp_data; @@ -465,40 +456,40 @@ void dp_bringup(u32 winb_addr) u32 xres = 1366; /* norrin display */ u32 yres = 768; - printk(BIOS_SPEW, "JZ: %s: entry\n", __func__); - dp->sor.base = (void *)TEGRA_ARM_SOR; dp->sor.portnum = 0; dp->aux_base = (void *)TEGRA_ARM_DPAUX; /* read panel info */ - if (!tegra_dc_dpcd_read_rev(dp, (u8 *) & dpcd_rev)) { - printk(BIOS_SPEW, "PANEL info: \n"); - printk(BIOS_SPEW, "--DPCP version(%#x): %d.%d\n", - dpcd_rev, (dpcd_rev >> 4) & 0x0f, (dpcd_rev & 0x0f)); + if (!tegra_dc_dpcd_read_rev(dp, (u8 *)&dpcd_rev)) { + printk(BIOS_INFO, "PANEL info:\n"); + printk(BIOS_INFO, "--DPCP version(%#x): %d.%d\n", + dpcd_rev, (dpcd_rev >> 4) & 0x0f, + (dpcd_rev & 0x0f)); } if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg)) - printk(BIOS_SPEW, "dp: failed to init link configuration\n"); + printk(BIOS_ERR, "dp: failed to init link configuration\n"); dp_link_training((u32) (dp->link_cfg.lane_count), (u32) (dp->link_cfg.link_bw)); - pclk_freq = dp_setup_timing(5, xres, yres); - printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n", __func__, pclk_freq); + pclk_freq = dp_setup_timing(xres, yres); + printk(BIOS_DEBUG, "%s: pclk_freq: %d\n", __func__, pclk_freq); - void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, - u32 lane_count, u32 enhanced_framing, u32 panel_edp, - u32 pclkfreq, u32 linkfreq); - dp_misc_setting(dp->link_cfg.bits_per_pixel, - xres, yres, winb_addr, - (u32) dp->link_cfg.lane_count, - (u32) dp->link_cfg.enhanced_framing, - (u32) dp->link_cfg.alt_scramber_reset_cap, - pclk_freq, dp->link_cfg.link_bw * 27); + void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, + u32 winb_addr, u32 lane_count, + u32 enhanced_framing, u32 panel_edp, + u32 pclkfreq, u32 linkfreq); + dp_misc_setting(dp->link_cfg.bits_per_pixel, + xres, yres, winb_addr, + (u32) dp->link_cfg.lane_count, + (u32) dp->link_cfg.enhanced_framing, + (u32) dp->link_cfg.alt_scramber_reset_cap, + pclk_freq, dp->link_cfg.link_bw * 27); } void debug_dpaux_print(u32 addr, u32 size) @@ -509,21 +500,22 @@ void debug_dpaux_print(u32 addr, u32 size) int i; if ((size == 0) || (size > 16)) { - printk(BIOS_SPEW, "dp: %s: invalid size %d\n", __func__, size); + printk(BIOS_ERR, "dp: %s: invalid size %d\n", __func__, size); return; } if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - addr, buf, &size, &status)) { - printk(BIOS_SPEW, "******AuxRead Error: 0x%04x: status 0x%08x\n", addr, - status); + addr, buf, &size, &status)) { + printk(BIOS_ERR, "******AuxRead Error: 0x%04x: status 0x%08x\n", + addr, status); return; } - printk(BIOS_SPEW, "%s: addr: 0x%04x, size: %d\n", __func__, addr, size); + printk(BIOS_DEBUG, "%s: addr: 0x%04x, size: %d\n", __func__, + addr, size); for (i = 0; i < size; ++i) - printk(BIOS_SPEW, " %02x", buf[i]); + printk(BIOS_DEBUG, " %02x", buf[i]); - printk(BIOS_SPEW, "\n"); + printk(BIOS_DEBUG, "\n"); } int dpaux_read(u32 addr, u32 size, u8 * data) @@ -533,14 +525,14 @@ int dpaux_read(u32 addr, u32 size, u8 * data) u32 status = 0; if ((size == 0) || (size > 16)) { - printk(BIOS_SPEW, "dp: %s: invalid size %d\n", __func__, size); + printk(BIOS_ERR, "dp: %s: invalid size %d\n", __func__, size); return -1; } if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - addr, data, &size, &status)) { - printk(BIOS_SPEW, "dp: Failed to read reg %#x, status: %#x\n", addr, - status); + addr, data, &size, &status)) { + printk(BIOS_ERR, "dp: Failed to read reg %#x, status: %#x\n", + addr, status); return -1; } @@ -553,13 +545,10 @@ int dpaux_write(u32 addr, u32 size, u32 data) u32 status = 0; int ret; - printk(BIOS_SPEW, "JZ: %s: entry, addr: 0x%08x, size: 0x%08x, data: %#x\n", - __func__, addr, size, data); - ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXWR, addr, (u8 *) & data, &size, &status); if (ret) - printk(BIOS_SPEW, "dp: Failed to write to reg %#x, status: 0x%x\n", + printk(BIOS_ERR, "dp: Failed to write to reg %#x, status: 0x%x\n", addr, status); return ret; } diff --git a/src/soc/nvidia/tegra124/emc.h b/src/soc/nvidia/tegra124/emc.h new file mode 100644 index 0000000..f9d415b --- /dev/null +++ b/src/soc/nvidia/tegra124/emc.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA124_EMC_H__ +#define __SOC_NVIDIA_TEGRA124_EMC_H__ + +#include <stddef.h> +#include <stdint.h> + +enum { + EMC_PIN_RESET_MASK = 1 << 8, + EMC_PIN_RESET_ACTIVE = 0 << 8, + EMC_PIN_RESET_INACTIVE = 1 << 8, + EMC_PIN_DQM_MASK = 1 << 4, + EMC_PIN_DQM_NORMAL = 0 << 4, + EMC_PIN_DQM_INACTIVE = 1 << 4, + EMC_PIN_CKE_MASK = 1 << 0, + EMC_PIN_CKE_POWERDOWN = 0 << 0, + EMC_PIN_CKE_NORMAL = 1 << 0, + + EMC_REF_CMD_MASK = 1 << 0, + EMC_REF_CMD_REFRESH = 1 << 0, + EMC_REF_NORMAL_MASK = 1 << 1, + EMC_REF_NORMAL_INIT = 0 << 1, + EMC_REF_NORMAL_ENABLED = 1 << 1, + EMC_REF_NUM_SHIFT = 8, + EMC_REF_NUM_MASK = 0xFF << EMC_REF_NUM_SHIFT, + EMC_REF_DEV_SELECTN_SHIFT = 30, + EMC_REF_DEV_SELECTN_MASK = 3 << EMC_REF_DEV_SELECTN_SHIFT, + + EMC_REFCTRL_REF_VALID_MASK = 1 << 31, + EMC_REFCTRL_REF_VALID_DISABLED = 0 << 31, + EMC_REFCTRL_REF_VALID_ENABLED = 1 << 31, + + EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK = 1 << 1, + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK = 1 << 2, + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK = 1 << 3, + + EMC_NOP_NOP_CMD_SHIFT = 0, + EMC_NOP_NOP_CMD_MASK = 1 << EMC_NOP_NOP_CMD_SHIFT, + EMC_NOP_NOP_DEV_SELECTN_SHIFT = 30, + EMC_NOP_NOP_DEV_SELECTN_MASK = 3 << EMC_NOP_NOP_DEV_SELECTN_SHIFT, + + EMC_TIMING_CONTROL_TIMING_UPDATE = 1, +}; + +struct tegra_emc_regs { + uint32_t intstatus; /* 0x0 */ + uint32_t intmask; /* 0x4 */ + uint32_t dbg; /* 0x8 */ + uint32_t cfg; /* 0xc */ + uint32_t adr_cfg; /* 0x10 */ + uint32_t rsvd_0x14[3]; /* 0x14 */ + + uint32_t refctrl; /* 0x20 */ + uint32_t pin; /* 0x24 */ + uint32_t timing_control; /* 0x28 */ + uint32_t rc; /* 0x2c */ + uint32_t rfc; /* 0x30 */ + uint32_t ras; /* 0x34 */ + uint32_t rp; /* 0x38 */ + uint32_t r2w; /* 0x3c */ + uint32_t w2r; /* 0x40 */ + uint32_t r2p; /* 0x44 */ + uint32_t w2p; /* 0x48 */ + uint32_t rd_rcd; /* 0x4c */ + uint32_t wr_rcd; /* 0x50 */ + uint32_t rrd; /* 0x54 */ + uint32_t rext; /* 0x58 */ + uint32_t wdv; /* 0x5c */ + uint32_t quse; /* 0x60 */ + uint32_t qrst; /* 0x64 */ + uint32_t qsafe; /* 0x68 */ + uint32_t rdv; /* 0x6c */ + uint32_t refresh; /* 0x70 */ + uint32_t burst_refresh_num; /* 0x74 */ + uint32_t pdex2wr; /* 0x78 */ + uint32_t pdex2rd; /* 0x7c */ + uint32_t pchg2pden; /* 0x80 */ + uint32_t act2pden; /* 0x84 */ + uint32_t ar2pden; /* 0x88 */ + uint32_t rw2pden; /* 0x8c */ + uint32_t txsr; /* 0x90 */ + uint32_t tcke; /* 0x94 */ + uint32_t tfaw; /* 0x98 */ + uint32_t trpab; /* 0x9c */ + uint32_t tclkstable; /* 0xa0 */ + uint32_t tclkstop; /* 0xa4 */ + uint32_t trefbw; /* 0xa8 */ + uint32_t rsvd_0xac[1]; /* 0xac */ + uint32_t odt_write; /* 0xb0 */ + uint32_t odt_read; /* 0xb4 */ + uint32_t wext; /* 0xb8 */ + uint32_t ctt; /* 0xbc */ + uint32_t rfc_slr; /* 0xc0 */ + uint32_t mrs_wait_cnt2; /* 0xc4 */ + uint32_t mrs_wait_cnt; /* 0xc8 */ + uint32_t mrs; /* 0xcc */ + uint32_t emrs; /* 0xd0 */ + uint32_t ref; /* 0xd4 */ + uint32_t pre; /* 0xd8 */ + uint32_t nop; /* 0xdc */ + uint32_t self_ref; /* 0xe0 */ + uint32_t dpd; /* 0xe4 */ + uint32_t mrw; /* 0xe8 */ + uint32_t mrr; /* 0xec */ + uint32_t cmdq; /* 0xf0 */ + uint32_t mc2emcq; /* 0xf4 */ + uint32_t xm2dqspadctrl3; /* 0xf8 */ + uint32_t rsvd_0xfc[1]; /* 0xfc */ + uint32_t fbio_spare; /* 0x100 */ + uint32_t fbio_cfg5; /* 0x104 */ + uint32_t fbio_wrptr_eq_2; /* 0x108 */ + uint32_t rsvd_0x10c[2]; /* 0x10c */ + + uint32_t fbio_cfg6; /* 0x114 */ + uint32_t rsvd_0x118[2]; /* 0x118 */ + + uint32_t cfg_rsv; /* 0x120 */ + uint32_t acpd_control; /* 0x124 */ + uint32_t rsvd_0x128[1]; /* 0x128 */ + uint32_t emrs2; /* 0x12c */ + uint32_t emrs3; /* 0x130 */ + uint32_t mrw2; /* 0x134 */ + uint32_t mrw3; /* 0x138 */ + uint32_t mrw4; /* 0x13c */ + uint32_t clken_override; /* 0x140 */ + uint32_t r2r; /* 0x144 */ + uint32_t w2w; /* 0x148 */ + uint32_t einput; /* 0x14c */ + uint32_t einput_duration; /* 0x150 */ + uint32_t puterm_extra; /* 0x154 */ + uint32_t tckesr; /* 0x158 */ + uint32_t tpd; /* 0x15c */ + uint32_t rsvd_0x160[81]; /* 0x160 */ + + uint32_t auto_cal_config; /* 0x2a4 */ + uint32_t auto_cal_interval; /* 0x2a8 */ + uint32_t auto_cal_status; /* 0x2ac */ + uint32_t req_ctrl; /* 0x2b0 */ + uint32_t status; /* 0x2b4 */ + uint32_t cfg_2; /* 0x2b8 */ + uint32_t cfg_dig_dll; /* 0x2bc */ + uint32_t cfg_dig_dll_period; /* 0x2c0 */ + uint32_t rsvd_0x2c4[1]; /* 0x2c4 */ + uint32_t dig_dll_status; /* 0x2c8 */ + uint32_t rdv_mask; /* 0x2cc */ + uint32_t wdv_mask; /* 0x2d0 */ + uint32_t rsvd_0x2d4[1]; /* 0x2d4 */ + uint32_t ctt_duration; /* 0x2d8 */ + uint32_t ctt_term_ctrl; /* 0x2dc */ + uint32_t zcal_interval; /* 0x2e0 */ + uint32_t zcal_wait_cnt; /* 0x2e4 */ + uint32_t zcal_mrw_cmd; /* 0x2e8 */ + uint32_t zq_cal; /* 0x2ec */ + uint32_t xm2cmdpadctrl; /* 0x2f0 */ + uint32_t xm2cmdpadctrl2; /* 0x2f4 */ + uint32_t xm2dqspadctrl; /* 0x2f8 */ + uint32_t xm2dqspadctrl2; /* 0x2fc */ + uint32_t xm2dqpadctrl; /* 0x300 */ + uint32_t xm2dqpadctrl2; /* 0x304 */ + uint32_t xm2clkpadctrl; /* 0x308 */ + uint32_t xm2comppadctrl; /* 0x30c */ + uint32_t xm2vttgenpadctrl; /* 0x310 */ + uint32_t xm2vttgenpadctrl2; /* 0x314 */ + uint32_t xm2vttgenpadctrl3; /* 0x318 */ + uint32_t emcpaden; /* 0x31c */ + uint32_t xm2dqspadctrl4; /* 0x320 */ + uint32_t scratch0; /* 0x324 */ + uint32_t dll_xform_dqs0; /* 0x328 */ + uint32_t dll_xform_dqs1; /* 0x32c */ + uint32_t dll_xform_dqs2; /* 0x330 */ + uint32_t dll_xform_dqs3; /* 0x334 */ + uint32_t dll_xform_dqs4; /* 0x338 */ + uint32_t dll_xform_dqs5; /* 0x33c */ + uint32_t dll_xform_dqs6; /* 0x340 */ + uint32_t dll_xform_dqs7; /* 0x344 */ + uint32_t dll_xform_quse0; /* 0x348 */ + uint32_t dll_xform_quse1; /* 0x34c */ + uint32_t dll_xform_quse2; /* 0x350 */ + uint32_t dll_xform_quse3; /* 0x354 */ + uint32_t dll_xform_quse4; /* 0x358 */ + uint32_t dll_xform_quse5; /* 0x35c */ + uint32_t dll_xform_quse6; /* 0x360 */ + uint32_t dll_xform_quse7; /* 0x364 */ + uint32_t dll_xform_dq0; /* 0x368 */ + uint32_t dll_xform_dq1; /* 0x36c */ + uint32_t dll_xform_dq2; /* 0x370 */ + uint32_t dll_xform_dq3; /* 0x374 */ + uint32_t dli_rx_trim0; /* 0x378 */ + uint32_t dli_rx_trim1; /* 0x37c */ + uint32_t dli_rx_trim2; /* 0x380 */ + uint32_t dli_rx_trim3; /* 0x384 */ + uint32_t dli_rx_trim4; /* 0x388 */ + uint32_t dli_rx_trim5; /* 0x38c */ + uint32_t dli_rx_trim6; /* 0x390 */ + uint32_t dli_rx_trim7; /* 0x394 */ + uint32_t dli_tx_trim0; /* 0x398 */ + uint32_t dli_tx_trim1; /* 0x39c */ + uint32_t dli_tx_trim2; /* 0x3a0 */ + uint32_t dli_tx_trim3; /* 0x3a4 */ + uint32_t dli_trim_txdqs0; /* 0x3a8 */ + uint32_t dli_trim_txdqs1; /* 0x3ac */ + uint32_t dli_trim_txdqs2; /* 0x3b0 */ + uint32_t dli_trim_txdqs3; /* 0x3b4 */ + uint32_t dli_trim_txdqs4; /* 0x3b8 */ + uint32_t dli_trim_txdqs5; /* 0x3bc */ + uint32_t dli_trim_txdqs6; /* 0x3c0 */ + uint32_t dli_trim_txdqs7; /* 0x3c4 */ + uint32_t rsvd_0x3c8[1]; /* 0x3c8 */ + uint32_t stall_then_exe_after_clkchange; /* 0x3cc */ + uint32_t rsvd_0x3d0[1]; /* 0x3d0 */ + uint32_t auto_cal_clk_status; /* 0x3d4 */ + uint32_t sel_dpd_ctrl; /* 0x3d8 */ + uint32_t pre_refresh_req_cnt; /* 0x3dc */ + uint32_t dyn_self_ref_control; /* 0x3e0 */ + uint32_t txsrdll; /* 0x3e4 */ + uint32_t ccfifo_addr; /* 0x3e8 */ + uint32_t ccfifo_data; /* 0x3ec */ + uint32_t ccfifo_status; /* 0x3f0 */ + uint32_t cdb_cntl_1; /* 0x3f4 */ + uint32_t cdb_cntl_2; /* 0x3f8 */ + uint32_t xm2clkpadctrl2; /* 0x3fc */ + uint32_t swizzle_rank0_byte_cfg; /* 0x400 */ + uint32_t swizzle_rank0_byte0; /* 0x404 */ + uint32_t swizzle_rank0_byte1; /* 0x408 */ + uint32_t swizzle_rank0_byte2; /* 0x40c */ + uint32_t swizzle_rank0_byte3; /* 0x410 */ + uint32_t swizzle_rank1_byte_cfg; /* 0x414 */ + uint32_t swizzle_rank1_byte0; /* 0x418 */ + uint32_t swizzle_rank1_byte1; /* 0x41c */ + uint32_t swizzle_rank1_byte2; /* 0x420 */ + uint32_t swizzle_rank1_byte3; /* 0x424 */ + uint32_t ca_training_start; /* 0x428 */ + uint32_t ca_training_busy; /* 0x42c */ + uint32_t ca_training_cfg; /* 0x430 */ + uint32_t ca_training_timing_cntl1; /* 0x434 */ + uint32_t ca_training_timing_cntl2; /* 0x438 */ + uint32_t ca_training_ca_lead_in; /* 0x43c */ + uint32_t ca_training_ca; /* 0x440 */ + uint32_t ca_training_ca_lead_out; /* 0x444 */ + uint32_t ca_training_result1; /* 0x448 */ + uint32_t ca_training_result2; /* 0x44c */ + uint32_t ca_training_result3; /* 0x450 */ + uint32_t ca_training_result4; /* 0x454 */ + uint32_t auto_cal_config2; /* 0x458 */ + uint32_t auto_cal_config3; /* 0x45c */ + uint32_t auto_cal_status2; /* 0x460 */ + uint32_t xm2cmdpadctrl3; /* 0x464 */ + uint32_t ibdly; /* 0x468 */ + uint32_t dll_xform_addr0; /* 0x46c */ + uint32_t dll_xform_addr1; /* 0x470 */ + uint32_t dll_xform_addr2; /* 0x474 */ + uint32_t dli_addr_trim; /* 0x478 */ + uint32_t dsr_vttgen_drv; /* 0x47c */ + uint32_t txdsrvttgen; /* 0x480 */ + uint32_t xm2cmdpadctrl4; /* 0x484 */ + uint32_t xm2cmdpadctrl5; /* 0x488 */ + uint32_t rsvd_0x48c[5]; /* 0x48c */ + + uint32_t dll_xform_dqs8; /* 0x4a0 */ + uint32_t dll_xform_dqs9; /* 0x4a4 */ + uint32_t dll_xform_dqs10; /* 0x4a8 */ + uint32_t dll_xform_dqs11; /* 0x4ac */ + uint32_t dll_xform_dqs12; /* 0x4b0 */ + uint32_t dll_xform_dqs13; /* 0x4b4 */ + uint32_t dll_xform_dqs14; /* 0x4b8 */ + uint32_t dll_xform_dqs15; /* 0x4bc */ + uint32_t dll_xform_quse8; /* 0x4c0 */ + uint32_t dll_xform_quse9; /* 0x4c4 */ + uint32_t dll_xform_quse10; /* 0x4c8 */ + uint32_t dll_xform_quse11; /* 0x4cc */ + uint32_t dll_xform_quse12; /* 0x4d0 */ + uint32_t dll_xform_quse13; /* 0x4d4 */ + uint32_t dll_xform_quse14; /* 0x4d8 */ + uint32_t dll_xform_quse15; /* 0x4dc */ + uint32_t dll_xform_dq4; /* 0x4e0 */ + uint32_t dll_xform_dq5; /* 0x4e4 */ + uint32_t dll_xform_dq6; /* 0x4e8 */ + uint32_t dll_xform_dq7; /* 0x4ec */ + uint32_t rsvd_0x4f0[12]; /* 0x4f0 */ + + uint32_t dli_trim_txdqs8; /* 0x520 */ + uint32_t dli_trim_txdqs9; /* 0x524 */ + uint32_t dli_trim_txdqs10; /* 0x528 */ + uint32_t dli_trim_txdqs11; /* 0x52c */ + uint32_t dli_trim_txdqs12; /* 0x530 */ + uint32_t dli_trim_txdqs13; /* 0x534 */ + uint32_t dli_trim_txdqs14; /* 0x538 */ + uint32_t dli_trim_txdqs15; /* 0x53c */ + uint32_t cdb_cntl_3; /* 0x540 */ + uint32_t xm2dqspadctrl5; /* 0x544 */ + uint32_t xm2dqspadctrl6; /* 0x548 */ + uint32_t xm2dqpadctrl3; /* 0x54c */ + uint32_t dll_xform_addr3; /* 0x550 */ + uint32_t dll_xform_addr4; /* 0x554 */ + uint32_t dll_xform_addr5; /* 0x558 */ + uint32_t rsvd_0x55c[1]; /* 0x55c */ + uint32_t cfg_pipe; /* 0x560 */ + uint32_t qpop; /* 0x564 */ + uint32_t quse_width; /* 0x568 */ + uint32_t puterm_width; /* 0x56c */ + uint32_t bgbias_ctl0; /* 0x570 */ + uint32_t puterm_adj; /* 0x574 */ +} __attribute__((packed)); + +check_member(tegra_emc_regs, puterm_adj, 0x574); + +#endif /* __SOC_NVIDIA_TEGRA124_EMC_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index b3c0b29..5e55ee5 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -66,9 +66,9 @@ enum { TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, TEGRA_DVC_BASE = TEGRA_APB_MISC_BASE + 0xD000, TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, - TEGRA_EMC_BASE = TEGRA_APB_MISC_BASE + 0xF400, TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, TEGRA_MC_BASE = 0x70019000, + TEGRA_EMC_BASE = 0x7001B000, TEGRA_CSITE_BASE = 0x70040000, TEGRA_SYSCTR0_BASE = 0x700F0000, TEGRA_USBD_BASE = 0x7D000000, diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 3ec3608..89be88b 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -247,6 +247,9 @@ enum clock_source { /* Careful: Not true for all sources, always check TRM! */ int clock_get_osc_khz(void); void clock_early_uart(void); void clock_external_output(int clk_id); +void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, + u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, + u32 same_freq); void clock_cpu0_config_and_reset(void * entry); void clock_halt_avp(void); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h index 27935d9..b764671 100644 --- a/src/soc/nvidia/tegra124/include/soc/display.h +++ b/src/soc/nvidia/tegra124/include/soc/display.h @@ -44,6 +44,9 @@ /* ardisplay_a.h */ #define DC_WIN_A_WIN_OPTIONS_0 0x700 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT 30 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD (0x1 << DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE (1) #define DC_WIN_A_BYTE_SWAP_0 0x701 #define DC_WIN_A_BUFFER_CONTROL_0 0x702 #define DC_WIN_A_COLOR_DEPTH_0 0x703 @@ -59,6 +62,7 @@ #define DC_WIN_A_BLEND_MATCH_SELECT_0 0x717 #define DC_WIN_A_BLEND_NOMATCH_SELECT_0 0x718 #define DC_WIN_A_BLEND_ALPHA_1BIT_0 0x719 +#define DC_WINBUF_A_START_ADDR_LO_0 0x800 #define DC_WINBUF_A_START_ADDR_HI_0 0x80d #define DC_WINBUF_A_ADDR_H_OFFSET_0 0x806 #define DC_WINBUF_A_ADDR_V_OFFSET_0 0x808 @@ -177,9 +181,18 @@ /* ardpaux.h */ #define DPAUX_DP_AUXDATA_READ_W0 0x19 +#define DP_LVDS_SHIFT 25 +#define DP_LVDS (1 << DP_LVDS_SHIFT) + +#define SRC_BPP 16 +#define COLORDEPTH 0x6 +#define COLOR_WHITE 0xFFFFFF + void setup_display(struct soc_nvidia_tegra124_config *config); void init_dca_regs(void); -void init_dpaux_regs(void); -void init_sor_regs(void); void dp_io_powerup(void); +u32 dp_setup_timing(u32 width, u32 height); +void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, + u32 lane_count, u32 enhanced_framing, u32 panel_edp, + u32 pclkfreq, u32 linkfreq); #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra124/lp0/Makefile b/src/soc/nvidia/tegra124/lp0/Makefile new file mode 100644 index 0000000..57680c5 --- /dev/null +++ b/src/soc/nvidia/tegra124/lp0/Makefile @@ -0,0 +1,58 @@ +################################################################################ +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +################################################################################ + +CC = $(GCC_PREFIX)gcc +NM = $(GCC_PREFIX)nm +OBJCOPY = $(GCC_PREFIX)objcopy + +OPENSSL = openssl +DD = dd +CP = cp +MV = mv +RM = rm + +SIGKEY = 00000000000000000000000000000000 + +.PHONY: all +all: tegra_lp0_resume.fw + +tegra_lp0_resume.elf: tegra_lp0_resume.ld tegra_lp0_resume.c + $(CC) -marm -march=armv4t -mno-unaligned-access -nostdlib -static \ + -Os -fpie -Wl,--build-id=none -ggdb3 -T tegra_lp0_resume.ld \ + -o $@ $(filter %.c,$+) + +tegra_lp0_resume.fw: tegra_lp0_resume.elf + @# Get rid of any files we're about to create. + $(RM) -f $@.nosig $@.sig $@.tosig + @# Convert the ELF image into a binary image. + $(OBJCOPY) -O binary $< $@.nosig + @# Extract the part of the binary which needs to be signed. + $(DD) bs=1 skip=544 if=$@.nosig of=$@.tosig + @# Calculate a signature for that part. + $(OPENSSL) dgst -mac cmac -macopt cipher:aes-128-cbc \ + -macopt hexkey:$(SIGKEY) -md5 -binary \ + $@.tosig > $@.sig + @# Inject the signature into the binary image's header. + $(DD) conv=notrunc bs=1 seek=272 count=16 if=$@.sig of=$@.nosig + @# Copy the signed binary to the target file name. + $(MV) $@.nosig $@ + +clean: + $(RM) -f tegra_lp0_resume.fw tegra_lp0_resume.fw.sig + $(RM) -f tegra_lp0_resume.fw.tosig tegra_lp0_resume.elf diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c new file mode 100644 index 0000000..72506c8 --- /dev/null +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -0,0 +1,627 @@ +/* + * Copyright 2014 Google Inc. + * Copyright 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <stdint.h> + +/* Function unit addresses. */ +enum { + UP_TAG_BASE = 0X60000000, + TIMER_BASE = 0X60005000, + CLK_RST_BASE = 0X60006000, + FLOW_CTLR_BASE = 0X60007000, + TEGRA_EVP_BASE = 0x6000f000, + PMC_CTLR_BASE = 0X7000e400, + MC_CTLR_BASE = 0X70019000, + SYSCTR_CTLR_BASE = 0X700f0000 +}; + + + +/* UP tag registers. */ +static uint32_t *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0); +enum { + UP_TAG_AVP = 0xaaaaaaaa +}; + + + +/* Timer registers. */ +static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); + + + +/* Clock and reset controller registers. */ +static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); +enum { + SWR_TRIG_SYS_RST = 0x1 << 2 +}; + +static uint32_t *clk_rst_cclk_burst_policy_ptr = (void *)(CLK_RST_BASE + 0x20); +enum { + CCLK_PLLP_BURST_POLICY = 0x20004444 +}; + +static uint32_t *clk_rst_super_cclk_div_ptr = (void *)(CLK_RST_BASE + 0x24); +enum { + SUPER_CDIV_ENB = 0x1 << 31 +}; + +static uint32_t *clk_rst_osc_ctrl_ptr = (void *)(CLK_RST_BASE + 0x50); +enum { + OSC_XOE = 0x1 << 0, + OSC_XOFS_SHIFT = 4, + OSC_XOFS_MASK = 0x3f << OSC_XOFS_SHIFT, + OSC_FREQ_SHIFT = 28, + OSC_FREQ_MASK = 0xf << OSC_FREQ_SHIFT +}; +enum { + OSC_FREQ_13 = 0, + OSC_FREQ_16P8 = 1, + OSC_FREQ_19P2 = 4, + OSC_FREQ_38P4 = 5, + OSC_FREQ_12 = 8, + OSC_FREQ_48 = 9, + OSC_FREQ_26 = 12 +}; + +static uint32_t *clk_rst_pllu_base_ptr = (void *)(CLK_RST_BASE + 0xc0); +enum { + PLLU_DIVM_SHIFT = 0, + PLLU_DIVN_SHIFT = 8, + PLLU_OVERRIDE = 0x1 << 24, + PLLU_ENABLE = 0x1 << 30, + PLLU_BYPASS = 0x1 << 31 +}; + +static uint32_t *clk_rst_pllu_misc_ptr = (void *)(CLK_RST_BASE + 0xcc); +enum { + PLLU_LFCON_SHIFT = 4, + PLLU_CPCON_SHIFT = 8, + PLLU_LOCK_ENABLE = 22 +}; + +static uint32_t *clk_rst_pllx_base_ptr = (void *)(CLK_RST_BASE + 0xe0); +enum { + PLLX_ENABLE = 0x1 << 30 +}; + +static uint32_t *clk_rst_rst_dev_u_clr_ptr = (void *)(CLK_RST_BASE + 0x314); +enum { + SWR_CSITE_RST = 0x1 << 9 +}; + +static uint32_t *clk_rst_clk_enb_l_set_ptr = (void *)(CLK_RST_BASE + 0x320); +enum { + CLK_ENB_CPU = 0x1 << 0 +}; + +static uint32_t *clk_rst_clk_out_enb_u_set_ptr = + (void *)(CLK_RST_BASE + 0x330); +enum { + CLK_ENB_CSITE = 0x1 << 9 +}; + +static uint32_t *clk_rst_cpu_softrst_ctrl2_ptr = + (void *)(CLK_RST_BASE + 0x388); +enum { + CAR2PMC_CPU_ACK_WIDTH_SHIFT = 0, + CAR2PMC_CPU_ACK_WIDTH_MASK = 0xfff << CAR2PMC_CPU_ACK_WIDTH_SHIFT +}; + +static uint32_t *clk_rst_clk_src_mselect_ptr = + (void *)(CLK_RST_BASE + 0x3b4); +enum { + MSELECT_CLK_DIV_SHIFT = 0, + MSELECT_CLK_SRC_SHIFT = 29, + MSELECT_CLK_SRC_PLLP_OUT0 = 0x0 << MSELECT_CLK_SRC_SHIFT, + MSELECT_CLK_SRC_PLLC2_OUT0 = 0x1 << MSELECT_CLK_SRC_SHIFT, + MSELECT_CLK_SRC_PLLC_OUT0 = 0x2 << MSELECT_CLK_SRC_SHIFT, + MSELECT_CLK_SRC_PLLC3_OUT0 = 0x3 << MSELECT_CLK_SRC_SHIFT +}; + +static uint32_t *clk_rst_rst_dev_v_clr_ptr = (void *)(CLK_RST_BASE + 0x434); +enum { + SWR_MSELECT_RST = 0x1 << 3 +}; + +static uint32_t *clk_rst_clk_enb_v_set_ptr = (void *)(CLK_RST_BASE + 0x440); +enum { + CLK_ENB_CPUG = 0x1 << 0, + CLK_ENB_CPULP = 0x1 << 1, + CLK_ENB_MSELECT = 0x1 << 3 +}; + +static uint32_t *clk_rst_rst_cpulp_cmplx_clr_ptr = + (void *)(CLK_RST_BASE + 0x45c); +static uint32_t *clk_rst_rst_cpug_cmplx_clr_ptr = + (void *)(CLK_RST_BASE + 0x454); +enum { + CLR_CPURESET0 = 0x1 << 0, + CLR_CPURESET1 = 0x1 << 1, + CLR_CPURESET2 = 0x1 << 2, + CLR_CPURESET3 = 0x1 << 3, + CLR_DBGRESET0 = 0x1 << 12, + CLR_DBGRESET1 = 0x1 << 13, + CLR_DBGRESET2 = 0x1 << 14, + CLR_DBGRESET3 = 0x1 << 15, + CLR_CORERESET0 = 0x1 << 16, + CLR_CORERESET1 = 0x1 << 17, + CLR_CORERESET2 = 0x1 << 18, + CLR_CORERESET3 = 0x1 << 19, + CLR_CXRESET0 = 0x1 << 20, + CLR_CXRESET1 = 0x1 << 21, + CLR_CXRESET2 = 0x1 << 22, + CLR_CXRESET3 = 0x1 << 23, + CLR_NONCPURESET = 0x1 << 29 +}; + + + +/* Reset vector. */ + +static uint32_t *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100); + + + +/* Flow controller registers. */ +static uint32_t *flow_ctlr_halt_cop_events_ptr = + (void *)(FLOW_CTLR_BASE + 0x4); +enum { + EVENT_MSEC = 0x1 << 24, + EVENT_JTAG = 0x1 << 28, + FLOW_MODE_SHIFT = 29, + FLOW_MODE_STOP = 2 << FLOW_MODE_SHIFT, +}; + +static uint32_t *flow_ctlr_cluster_control_ptr = + (void *)(FLOW_CTLR_BASE + 0x2c); +enum { + FLOW_CLUSTER_ACTIVE_LP = 0x1 << 0 +}; + + + +/* Power management controller registers. */ +enum { + PARTID_CRAIL = 0, + PARTID_CELP = 12, + PARTID_CE0 = 14, + PARTID_C0NC = 15, + PARTID_C1NC = 16 +}; + +static uint32_t *pmc_ctlr_clamp_status_ptr = (void *)(PMC_CTLR_BASE + 0x2c); + +static uint32_t *pmc_ctlr_pwrgate_toggle_ptr = (void *)(PMC_CTLR_BASE + 0x30); +enum { + PWRGATE_TOGGLE_START = 0x1 << 8 +}; + +static uint32_t *pmc_ctlr_pwrgate_status_ptr = (void *)(PMC_CTLR_BASE + 0x38); + +static uint32_t *pmc_ctlr_scratch4_ptr = (void *)(PMC_CTLR_BASE + 0x60); +enum { + PMC_SCRATCH4_LP = 0x1 << 31 +}; + +static uint32_t *pmc_ctlr_cpupwrgood_timer_ptr = + (void *)(PMC_CTLR_BASE + 0xc8); + +static uint32_t *pmc_ctlr_scratch41_ptr = (void *)(PMC_CTLR_BASE + 0x140); + +static uint32_t *pmc_ctlr_osc_edpd_over_ptr = (void *)(PMC_CTLR_BASE + 0x1a4); +enum { + PMC_XOFS_SHIFT = 1, + PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT +}; + + + +/* Memory controller registers. */ +static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c); + +static uint32_t *mc_video_protect_reg_ctrl_ptr = + (void *)(MC_CTLR_BASE + 0x650); +enum { + VIDEO_PROTECT_WRITE_ACCESS_DISABLE = 0x1 << 0, + VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS = 0x1 << 1 +}; + + + +/* System counter registers. */ +static uint32_t *sysctr_cntcr_ptr = (void *)(SYSCTR_CTLR_BASE + 0x0); +enum { + TSC_CNTCR_ENABLE = 0x1 << 0, + TSC_CNTCR_HDBG = 0x1 << 1 +}; + +static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20); + + + +/* Utility functions. */ + +static inline void __attribute__((always_inline)) + __attribute__((noreturn)) halt(void) +{ + for (;;); +} + +inline static uint32_t read32(const void *addr) +{ + return *(volatile uint32_t *)addr; +} + +inline static void write32(uint32_t val, void *addr) +{ + *(volatile uint32_t *)addr = val; +} + +inline static void setbits32(uint32_t bits, void *addr) +{ + write32(read32(addr) | bits, addr); +} + +inline static void clrbits32(uint32_t bits, void *addr) +{ + write32(read32(addr) & ~bits, addr); +} + +static void __attribute__((noreturn)) reset(void) +{ + write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr); + halt(); +} + +static void udelay(unsigned usecs) +{ + uint32_t start = read32(timer_us_ptr); + while (read32(timer_us_ptr) - start < usecs) + ; +} + + + +/* Accessors. */ + +static int wakeup_on_lp(void) +{ + return !!(read32(pmc_ctlr_scratch4_ptr) & PMC_SCRATCH4_LP); +} + +static uint32_t get_wakeup_vector(void) +{ + return read32(pmc_ctlr_scratch41_ptr); +} + +static unsigned get_osc_freq(void) +{ + return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; +} + + + +/* Clock configuration. */ + +static void config_oscillator(void) +{ + // Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy + // to OSC_CTRL.XOFS and set XOE. + uint32_t xofs = (read32(pmc_ctlr_osc_edpd_over_ptr) & + PMC_XOFS_MASK) >> PMC_XOFS_SHIFT; + + uint32_t osc_ctrl = read32(clk_rst_osc_ctrl_ptr); + osc_ctrl &= OSC_XOFS_MASK; + osc_ctrl |= (xofs << OSC_XOFS_SHIFT); + osc_ctrl |= OSC_XOE; + write32(osc_ctrl, clk_rst_osc_ctrl_ptr); +} + +static void config_pllu(void) +{ + // Figure out what parameters to use for PLLU. + uint32_t divm, divn, cpcon, lfcon; + switch (get_osc_freq()) { + case OSC_FREQ_12: + case OSC_FREQ_48: + divm = 0x0c; + divn = 0x3c0; + cpcon = 0x0c; + lfcon = 0x02; + break; + case OSC_FREQ_16P8: + divm = 0x07; + divn = 0x190; + cpcon = 0x05; + lfcon = 0x02; + break; + case OSC_FREQ_19P2: + case OSC_FREQ_38P4: + divm = 0x04; + divn = 0xc8; + cpcon = 0x03; + lfcon = 0x02; + break; + case OSC_FREQ_26: + divm = 0x1a; + divn = 0x3c0; + cpcon = 0x0c; + lfcon = 0x02; + break; + default: + // Map anything that's not recognized to 13MHz. + divm = 0x0d; + divn = 0x3c0; + cpcon = 0x0c; + lfcon = 0x02; + } + + // Configure PLLU. + uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE | + (divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT); + write32(base, clk_rst_pllu_base_ptr); + uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) | + (lfcon << PLLU_LFCON_SHIFT); + write32(misc, clk_rst_pllu_misc_ptr); + + // Enable PLLU. + base &= ~PLLU_BYPASS; + base |= PLLU_ENABLE; + write32(base, clk_rst_pllu_base_ptr); + misc |= PLLU_LOCK_ENABLE; + write32(misc, clk_rst_pllu_misc_ptr); +} + +static void config_tsc(void) +{ + // Tell the TSC the oscillator frequency. + switch (get_osc_freq()) { + case OSC_FREQ_12: + write32(12000000, sysctr_cntfid0_ptr); + break; + case OSC_FREQ_48: + write32(48000000, sysctr_cntfid0_ptr); + break; + case OSC_FREQ_16P8: + write32(16800000, sysctr_cntfid0_ptr); + break; + case OSC_FREQ_19P2: + write32(19200000, sysctr_cntfid0_ptr); + break; + case OSC_FREQ_38P4: + write32(38400000, sysctr_cntfid0_ptr); + break; + case OSC_FREQ_26: + write32(26000000, sysctr_cntfid0_ptr); + break; + default: + // Default to 13MHz. + write32(13000000, sysctr_cntfid0_ptr); + break; + } + + // Enable the TSC. + setbits32(TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG, sysctr_cntcr_ptr); +} + + + +/* Function unit configuration. */ + +static void config_core_sight(void) +{ + // Enable the CoreSight clock. + write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr); + + /* + * De-assert CoreSight reset. + * NOTE: We're leaving the CoreSight clock on the oscillator for + * now. It will be restored to its original clock source + * when the CPU-side restoration code runs. + */ + write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr); +} + +static void config_mselect(void) +{ + // Set MSELECT clock source to PLLP with 1:4 divider. + write32((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0, + clk_rst_clk_src_mselect_ptr); + + // Enable clock to MSELECT. + write32(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr); + + udelay(2); + + // Bring MSELECT out of reset. + write32(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr); +} + + + +/* Resets. */ + +static void clear_cpu_resets(void) +{ + // Take the non-cpu of the G and LP clusters out of reset. + write32(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr); + write32(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr); + + // Clear software controlled reset of the slow cluster. + write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0, + clk_rst_rst_cpulp_cmplx_clr_ptr); + + // Clear software controlled reset of the fast cluster. + write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | + CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | + CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | + CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3, + clk_rst_rst_cpug_cmplx_clr_ptr); +} + + + +/* Power. */ + +static void power_on_partition(unsigned id) +{ + uint32_t bit = 0x1 << id; + if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { + // Partition is not on. Turn it on. + write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr); + + // Wait until the partition is powerd on. + while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) + ; + + // Wait until clamp is off. + while (read32(pmc_ctlr_clamp_status_ptr) & bit) + ; + } +} + +static void power_on_main_cpu(void) +{ + /* + * Reprogram PMC_CPUPWRGOOD_TIMER register: + * + * XXX This is a fragile assumption. XXX + * The kernel prepares PMC_CPUPWRGOOD_TIMER based on a 32768Hz clock. + * Note that PMC_CPUPWRGOOD_TIMER is running at pclk. + * + * We need to reprogram PMC_CPUPWRGOOD_TIMER based on the current pclk + * which is at 408Mhz (pclk = sclk = pllp_out0) after reset. Multiply + * PMC_CPUPWRGOOD_TIMER by 408M / 32K. + * + * Save the original PMC_CPUPWRGOOD_TIMER register which we need to + * restore after the CPU is powered up. + */ + uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); + + write32(orig_timer * (408000000 / 32768), + pmc_ctlr_cpupwrgood_timer_ptr); + + if (wakeup_on_lp()) { + power_on_partition(PARTID_C1NC); + power_on_partition(PARTID_CELP); + } else { + power_on_partition(PARTID_CRAIL); + power_on_partition(PARTID_C0NC); + power_on_partition(PARTID_CE0); + } + + // Give I/O signals time to stablize. + write32(20 | EVENT_MSEC | FLOW_MODE_STOP, + flow_ctlr_halt_cop_events_ptr); + + // Restore the original PMC_CPUPWRGOOD_TIMER. + write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); +} + + + +/* Entry point. */ + +void lp0_resume(void) +{ + // If not on the AVP, reset. + if (read32(up_tag_ptr) != UP_TAG_AVP) + reset(); + + config_oscillator(); + + // Tell the flow controller which cluster to wake up. The default is + // the fast cluster. + if (wakeup_on_lp()) + setbits32(FLOW_CLUSTER_ACTIVE_LP, + flow_ctlr_cluster_control_ptr); + + // Program SUPER_CCLK_DIVIDER. + write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr); + + config_core_sight(); + + config_pllu(); + + // Set the CPU reset vector. + write32(get_wakeup_vector(), evp_cpu_reset_ptr); + + // Select CPU complex clock source. + write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr); + + config_mselect(); + + // Disable PLLX since it isn't used as CPU clock source. + clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr); + + // Set CAR2PMC_CPU_ACK_WIDTH to 408. + uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); + ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; + ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; + write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); + + // Enable the CPU complex clock. + write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); + write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); + + clear_cpu_resets(); + + config_tsc(); + + power_on_main_cpu(); + + // Disable VPR. + write32(0, mc_video_protect_size_mb_ptr); + write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, + mc_video_protect_reg_ctrl_ptr); + + // Halt the AVP. + while (1) + write32(FLOW_MODE_STOP | EVENT_JTAG, + flow_ctlr_halt_cop_events_ptr); +} + + + +/* Header. */ + +extern uint8_t blob_data; +extern uint8_t blob_data_size; +extern uint8_t blob_total_size; + +struct lp0_header { + uint32_t length_insecure; // Insecure total length. + uint32_t reserved[3]; + uint8_t rsa_modulus[256]; // RSA key modulus. + uint8_t aes_signature[16]; // AES signature. + uint8_t rsa_signature[256]; // RSA-PSS signature. + uint8_t random_aes_block[16]; // Random data, may be zero. + uint32_t length_secure; // Secure total length. + uint32_t destination; // Where to load the blob in iRAM. + uint32_t entry_point; // Entry point for the blob. + uint32_t code_length; // Length of just the data. +} __attribute__((packed)); + +struct lp0_header header __attribute__((section(".header"))) = +{ + .length_insecure = (uintptr_t)&blob_total_size, + .length_secure = (uintptr_t)&blob_total_size, + .destination = (uintptr_t)&blob_data, + .entry_point = (uintptr_t)&lp0_resume, + .code_length = (uintptr_t)&blob_data_size +}; diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld new file mode 100644 index 0000000..c4c508f --- /dev/null +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld @@ -0,0 +1,73 @@ +/* + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +PHDRS +{ + to_load PT_LOAD; +} + +ENTRY(lp0_resume) +SECTIONS +{ + . = 0x40020000 - 0x240; + + /* + * The lp0 blob header is built as a static data structure and put + * in the .header section. + */ + .header_start = .; + .header . : { + *(.header); + } : to_load = 0xff + .header_end = .; + + . = 0x40020000; + + /* The actual lp0 blob code. */ + .data_start = .; + .data . : { + *(.text); + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.data); + *(.data.*); + *(.bss); + *(.bss.*); + *(.sbss); + *(.sbss.*); + . = ALIGN(16); + } + .data_end = .; + + /* Some values we need in the header. */ + blob_data = .data_start; + blob_data_size = .data_end - .data_start; + blob_total_size = .data_end - .header_start; + + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.ARM.*) + } +} diff --git a/src/soc/nvidia/tegra124/mc.h b/src/soc/nvidia/tegra124/mc.h index 92a38ed..0fc3738 100644 --- a/src/soc/nvidia/tegra124/mc.h +++ b/src/soc/nvidia/tegra124/mc.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,34 +15,114 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef _TEGRA124_MC_H_ -#define _TEGRA124_MC_H_ +#ifndef __SOC_NVIDIA_TEGRA124_MC_H__ +#define __SOC_NVIDIA_TEGRA124_MC_H__ +#include <stddef.h> #include <stdint.h> // Memory Controller registers we need/care about struct tegra_mc_regs { - u32 reserved0[4]; - u32 mc_smmu_config; - u32 mc_smmu_tlb_config; - u32 mc_smmu_ptc_config; - u32 mc_smmu_ptb_asid; - u32 mc_smmu_ptb_data; - u32 reserved1[3]; - u32 mc_smmu_tlb_flush; - u32 mc_smmu_ptc_flush; - u32 reserved2[6]; - u32 mc_emem_cfg; - u32 mc_emem_adr_cfg; - u32 mc_emem_adr_cfg_dev0; - u32 mc_emem_adr_cfg_dev1; - u32 reserved3[12]; - u32 mc_emem_arb_reserved[28]; - u32 reserved4[338]; - u32 mc_vpr_bom; - u32 mc_vpr_size; - u32 mc_vpr_ctrl; + uint32_t rsvd_0x0[4]; /* 0x00 */ + uint32_t smmu_config; /* 0x10 */ + uint32_t smmu_tlb_config; /* 0x14 */ + uint32_t smmu_ptc_config; /* 0x18 */ + uint32_t smmu_ptb_asid; /* 0x1c */ + uint32_t smmu_ptb_data; /* 0x20 */ + uint32_t rsvd_0x24[3]; /* 0x24 */ + uint32_t smmu_tlb_flush; /* 0x30 */ + uint32_t smmu_ptc_flush; /* 0x34 */ + uint32_t rsvd_0x38[6]; /* 0x38 */ + uint32_t emem_cfg; /* 0x50 */ + uint32_t emem_adr_cfg; /* 0x54 */ + uint32_t emem_adr_cfg_dev0; /* 0x58 */ + uint32_t emem_adr_cfg_dev1; /* 0x5c */ + uint32_t rsvd_0x60[1]; /* 0x60 */ + uint32_t emem_adr_cfg_bank_mask_0; /* 0x64 */ + uint32_t emem_adr_cfg_bank_mask_1; /* 0x68 */ + uint32_t emem_adr_cfg_bank_mask_2; /* 0x6c */ + uint32_t rsvd_0x70[8]; /* 0x70 */ + uint32_t emem_arb_cfg; /* 0x90 */ + uint32_t emem_arb_outstanding_req; /* 0x94 */ + uint32_t emem_arb_timing_rcd; /* 0x98 */ + uint32_t emem_arb_timing_rp; /* 0x9c */ + uint32_t emem_arb_timing_rc; /* 0xa0 */ + uint32_t emem_arb_timing_ras; /* 0xa4 */ + uint32_t emem_arb_timing_faw; /* 0xa8 */ + uint32_t emem_arb_timing_rrd; /* 0xac */ + uint32_t emem_arb_timing_rap2pre; /* 0xb0 */ + uint32_t emem_arb_timing_wap2pre; /* 0xb4 */ + uint32_t emem_arb_timing_r2r; /* 0xb8 */ + uint32_t emem_arb_timing_w2w; /* 0xbc */ + uint32_t emem_arb_timing_r2w; /* 0xc0 */ + uint32_t emem_arb_timing_w2r; /* 0xc4 */ + uint32_t rsvd_0xc8[2]; /* 0xc8 */ + uint32_t emem_arb_da_turns; /* 0xd0 */ + uint32_t emem_arb_da_covers; /* 0xd4 */ + uint32_t emem_arb_misc0; /* 0xd8 */ + uint32_t emem_arb_misc1; /* 0xdc */ + uint32_t emem_arb_ring1_throttle; /* 0xe0 */ + uint32_t emem_arb_ring3_throttle; /* 0xe4 */ + uint32_t emem_arb_override; /* 0xe8 */ + uint32_t emem_arb_rsv; /* 0xec */ + uint32_t rsvd_0xf0[1]; /* 0xf0 */ + uint32_t clken_override; /* 0xf4 */ + uint32_t timing_control_dbg; /* 0xf8 */ + uint32_t timing_control; /* 0xfc */ + uint32_t stat_control; /* 0x100 */ + uint32_t rsvd_0x104[65]; /* 0x104 */ + uint32_t emem_arb_isochronous_0; /* 0x208 */ + uint32_t emem_arb_isochronous_1; /* 0x20c */ + uint32_t emem_arb_isochronous_2; /* 0x210 */ + uint32_t rsvd_0x214[38]; /* 0x214 */ + uint32_t dis_extra_snap_levels; /* 0x2ac */ + uint32_t rsvd_0x2b0[90]; /* 0x2b0 */ + uint32_t video_protect_vpr_override; /* 0x418 */ + uint32_t rsvd_0x41c[93]; /* 0x41c */ + uint32_t video_protect_vpr_override1; /* 0x590 */ + uint32_t rsvd_0x594[29]; /* 0x594 */ + uint32_t display_snap_ring; /* 0x608 */ + uint32_t rsvd_0x60c[15]; /* 0x60c */ + uint32_t video_protect_bom; /* 0x648 */ + uint32_t video_protect_size_mb; /* 0x64c */ + uint32_t video_protect_reg_ctrl; /* 0x650 */ + uint32_t rsvd_0x654[4]; /* 0x654 */ + uint32_t emem_cfg_access_ctrl; /* 0x664 */ + uint32_t rsvd_0x668[2]; /* 0x668 */ + uint32_t sec_carveout_bom; /* 0x670 */ + uint32_t sec_carveout_size_mb; /* 0x674 */ + uint32_t sec_carveout_reg_ctrl; /* 0x678 */ + uint32_t rsvd_0x67c[187]; /* 0x67c */ + uint32_t emem_arb_override_1; /* 0x968 */ + uint32_t rsvd_0x96c[3]; /* 0x96c */ + uint32_t video_protect_bom_adr_hi; /* 0x978 */ + uint32_t rsvd_0x97c[2]; /* 0x97c */ + uint32_t video_protect_gpu_override_0; /* 0x984 */ + uint32_t video_protect_gpu_override_1; /* 0x988 */ + uint32_t rsvd_0x98c[5]; /* 0x98c */ + uint32_t mts_carveout_bom; /* 0x9a0 */ + uint32_t mts_carveout_size_mb; /* 0x9a4 */ + uint32_t mts_carveout_adr_hi; /* 0x9a8 */ + uint32_t mts_carveout_reg_ctrl; /* 0x9ac */ + uint32_t rsvd_0x9b0[4]; /* 0x9b0 */ + uint32_t emem_bank_swizzle_cfg0; /* 0x9c0 */ + uint32_t emem_bank_swizzle_cfg1; /* 0x9c4 */ + uint32_t emem_bank_swizzle_cfg2; /* 0x9c8 */ + uint32_t emem_bank_swizzle_cfg3; /* 0x9cc */ + uint32_t rsvd_0x9d0[1]; /* 0x9d0 */ + uint32_t sec_carveout_adr_hi; /* 0x9d4 */ }; -#endif /* _TEGRA124_MC_H_ */ +enum { + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27, + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27, + + MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1, + + MC_TIMING_CONTROL_TIMING_UPDATE = 1, +}; + +check_member(tegra_mc_regs, sec_carveout_adr_hi, 0x9d4); + +#endif /* __SOC_NVIDIA_TEGRA124_MC_H__ */ diff --git a/src/soc/nvidia/tegra124/pmc.h b/src/soc/nvidia/tegra124/pmc.h index f88e253..2dfdaad 100644 --- a/src/soc/nvidia/tegra124/pmc.h +++ b/src/soc/nvidia/tegra124/pmc.h @@ -62,10 +62,36 @@ struct tegra_pmc_regs { u32 no_iopower; u32 pwr_det; u32 pwr_det_latch; - u32 scratch[20]; + u32 scratch0; + u32 scratch1; + u32 scratch2; + u32 scratch3; + u32 scratch4; + u32 scratch5; + u32 scratch6; + u32 scratch7; + u32 scratch8; + u32 scratch9; + u32 scratch10; + u32 scratch11; + u32 scratch12; + u32 scratch13; + u32 scratch14; + u32 scratch15; + u32 scratch16; + u32 scratch17; + u32 scratch18; + u32 scratch19; u32 odmdata; - u32 scratch21[24 - 21]; - u32 secure_scratch[6]; + u32 scratch21; + u32 scratch22; + u32 scratch23; + u32 secure_scratch0; + u32 secure_scratch1; + u32 secure_scratch2; + u32 secure_scratch3; + u32 secure_scratch4; + u32 secure_scratch5; u32 cpupwrgood_timer; u32 cpupwroff_timer; u32 pg_mask; @@ -79,7 +105,25 @@ struct tegra_pmc_regs { u32 usb_a0; u32 crypto_op; u32 pllp_wb0_override; - u32 scratch24[43 - 24]; + u32 scratch24; + u32 scratch25; + u32 scratch26; + u32 scratch27; + u32 scratch28; + u32 scratch29; + u32 scratch30; + u32 scratch31; + u32 scratch32; + u32 scratch33; + u32 scratch34; + u32 scratch35; + u32 scratch36; + u32 scratch37; + u32 scratch38; + u32 scratch39; + u32 scratch40; + u32 scratch41; + u32 scratch42; u32 bondout_mirror[3]; u32 sys_33v_en; u32 bondout_mirror_access; @@ -124,9 +168,24 @@ struct tegra_pmc_regs { u32 utmip_uhsic_status; u32 utmip_uhsic_fake; u32 bondout_mirror3[5 - 3]; - u32 secure_scratch6[8 - 6]; - u32 scratch43[56 - 43]; - u32 scratch_eco[3]; + u32 secure_scratch6; + u32 secure_scratch7; + u32 scratch43; + u32 scratch44; + u32 scratch45; + u32 scratch46; + u32 scratch47; + u32 scratch48; + u32 scratch49; + u32 scratch50; + u32 scratch51; + u32 scratch52; + u32 scratch53; + u32 scratch54; + u32 scratch55; + u32 scratch0_eco; + u32 por_dpd_ctrl; + u32 scratch2_eco; u32 utmip_uhsic_line_wakeup; u32 utmip_bias_master_cntrl; u32 utmip_master_config; @@ -153,10 +212,108 @@ struct tegra_pmc_regs { u32 reg_short; u32 pg_mask_andor; u8 _rsv1[0x2c]; - u32 secure_scratch8[24 - 8]; - u32 scratch56[120 - 56]; + u32 secure_scratch8; + u32 secure_scratch9; + u32 secure_scratch10; + u32 secure_scratch11; + u32 secure_scratch12; + u32 secure_scratch13; + u32 secure_scratch14; + u32 secure_scratch15; + u32 secure_scratch16; + u32 secure_scratch17; + u32 secure_scratch18; + u32 secure_scratch19; + u32 secure_scratch20; + u32 secure_scratch21; + u32 secure_scratch22; + u32 secure_scratch23; + u32 secure_scratch24; + u32 secure_scratch25; + u32 secure_scratch26; + u32 secure_scratch27; + u32 secure_scratch28; + u32 secure_scratch29; + u32 secure_scratch30; + u32 secure_scratch31; + u32 secure_scratch32; + u32 secure_scratch33; + u32 secure_scratch34; + u32 secure_scratch35; + u8 _rsv2[0xd0]; + u32 cntrl2; + u8 _rsv3[0x18]; + u32 io_dpd3_req; + u32 io_dqd3_status; + u32 strapping_opt_a; + u8 _rsv4[0x198]; + u32 scratch56; + u32 scratch57; + u32 scratch58; + u32 scratch59; + u32 scratch60; + u32 scratch61; + u32 scratch62; + u32 scratch63; + u32 scratch64; + u32 scratch65; + u32 scratch66; + u32 scratch67; + u32 scratch68; + u32 scratch69; + u32 scratch70; + u32 scratch71; + u32 scratch72; + u32 scratch73; + u32 scratch74; + u32 scratch75; + u32 scratch76; + u32 scratch77; + u32 scratch78; + u32 scratch79; + u32 scratch80; + u32 scratch81; + u32 scratch82; + u32 scratch83; + u32 scratch84; + u32 scratch85; + u32 scratch86; + u32 scratch87; + u32 scratch88; + u32 scratch89; + u32 scratch90; + u32 scratch91; + u32 scratch92; + u32 scratch93; + u32 scratch94; + u32 scratch95; + u32 scratch96; + u32 scratch97; + u32 scratch98; + u32 scratch99; + u32 scratch100; + u32 scratch101; + u32 scratch102; + u32 scratch103; + u32 scratch104; + u32 scratch105; + u32 scratch106; + u32 scratch107; + u32 scratch108; + u32 scratch109; + u32 scratch110; + u32 scratch111; + u32 scratch112; + u32 scratch113; + u32 scratch114; + u32 scratch115; + u32 scratch116; + u32 scratch117; + u32 scratch118; + u32 scratch119; }; -check_member(tegra_pmc_regs, scratch56, 0x340); + +check_member(tegra_pmc_regs, scratch119, 0x6fc); enum { PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f, @@ -191,6 +348,29 @@ enum { }; enum { + PMC_DDR_PWR_EMMC_MASK = 1 << 1, + PMC_DDR_PWR_VAL_MASK = 1 << 0, +}; + +enum { + PMC_DDR_CFG_PKG_MASK = 1 << 0, + PMC_DDR_CFG_IF_MASK = 1 << 1, + PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12, + PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13, +}; + +enum { + PMC_NO_IOPOWER_MEM_MASK = 1 << 7, + PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16, +}; + +enum { + PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0, + PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1, + PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31, +}; + +enum { PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12 }; @@ -200,4 +380,10 @@ enum { 0x3f << PMC_OSC_EDPD_OVER_XOFS_SHIFT }; +enum { + PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT = 4, + PMC_STRAPPING_OPT_A_RAM_CODE_MASK = + 0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT, +}; + #endif /* _TEGRA124_PMC_H_ */ diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c new file mode 100644 index 0000000..283cbf4 --- /dev/null +++ b/src/soc/nvidia/tegra124/sdram.c @@ -0,0 +1,611 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/clock.h> + +#include "emc.h" +#include "mc.h" +#include "pmc.h" +#include "sdram.h" + +static void sdram_patch(uintptr_t addr, uint32_t value) +{ + if (addr) + writel(value, (uint32_t*)addr); +} + +static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) +{ + clrsetbits_le32(addr, mask, (value & mask)); +} + +/* PMC must be configured before clock-enable and de-reset of MC/EMC. */ +static void sdram_configure_pmc(const struct sdram_params *param, + struct tegra_pmc_regs *regs) +{ + /* VDDP Select */ + writel(param->PmcVddpSel, &regs->vddp_sel); + udelay(param->PmcVddpSelWait); + + /* Set DDR pad voltage */ + writebits(param->PmcDdrPwr, &regs->ddr_pwr, PMC_DDR_PWR_VAL_MASK); + + /* Set package and DPD pad control */ + writebits(param->PmcDdrCfg, &regs->ddr_cfg, + (PMC_DDR_CFG_PKG_MASK | PMC_DDR_CFG_IF_MASK | + PMC_DDR_CFG_XM0_RESET_TRI_MASK | + PMC_DDR_CFG_XM0_RESET_DPDIO_MASK)); + + /* Turn on MEM IO Power */ + writebits(param->PmcNoIoPower, &regs->no_iopower, + (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK)); + + writel(param->PmcRegShort, &regs->reg_short); +} + +static void sdram_start_clocks(const struct sdram_params *param) +{ + u32 is_same_freq = (param->McEmemArbMisc0 & + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK) ? 1 : 0; + + clock_sdram(param->PllMInputDivider, param->PllMFeedbackDivider, + param->PllMSelectDiv2, param->PllMSetupControl, + param->PllMPDLshiftPh45, param->PllMPDLshiftPh90, + param->PllMPDLshiftPh135, param->PllMKVCO, + param->PllMKCP, param->PllMStableTime, + param->EmcClockSource, is_same_freq); +} + +static void sdram_deassert_clock_enable_signal(const struct sdram_params *param, + struct tegra_pmc_regs *regs) +{ + clrbits_le32(&regs->por_dpd_ctrl, + PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK); + udelay(param->PmcPorDpdCtrlWait); +} + +static void sdram_deassert_sel_dpd(const struct sdram_params *param, + struct tegra_pmc_regs *regs) +{ + clrbits_le32(&regs->por_dpd_ctrl, + (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK | + PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK)); + /* + * Note NVIDIA recommended to always do 10us delay here and ignore + * BCT.PmcPorDpdCtrlWait. + * */ + udelay(10); +} + +static void sdram_set_swizzle(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + writel(param->EmcSwizzleRank0ByteCfg, &regs->swizzle_rank0_byte_cfg); + writel(param->EmcSwizzleRank0Byte0, &regs->swizzle_rank0_byte0); + writel(param->EmcSwizzleRank0Byte1, &regs->swizzle_rank0_byte1); + writel(param->EmcSwizzleRank0Byte2, &regs->swizzle_rank0_byte2); + writel(param->EmcSwizzleRank0Byte3, &regs->swizzle_rank0_byte3); + writel(param->EmcSwizzleRank1ByteCfg, &regs->swizzle_rank1_byte_cfg); + writel(param->EmcSwizzleRank1Byte0, &regs->swizzle_rank1_byte0); + writel(param->EmcSwizzleRank1Byte1, &regs->swizzle_rank1_byte1); + writel(param->EmcSwizzleRank1Byte2, &regs->swizzle_rank1_byte2); + writel(param->EmcSwizzleRank1Byte3, &regs->swizzle_rank1_byte3); +} + +static void sdram_set_pad_controls(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Program the pad controls */ + writel(param->EmcXm2CmdPadCtrl, &regs->xm2cmdpadctrl); + writel(param->EmcXm2CmdPadCtrl2, &regs->xm2cmdpadctrl2); + writel(param->EmcXm2CmdPadCtrl3, &regs->xm2cmdpadctrl3); + writel(param->EmcXm2CmdPadCtrl4, &regs->xm2cmdpadctrl4); + writel(param->EmcXm2CmdPadCtrl5, &regs->xm2cmdpadctrl5); + + writel(param->EmcXm2DqsPadCtrl, &regs->xm2dqspadctrl); + writel(param->EmcXm2DqsPadCtrl2, &regs->xm2dqspadctrl2); + writel(param->EmcXm2DqsPadCtrl3, &regs->xm2dqspadctrl3); + writel(param->EmcXm2DqsPadCtrl4, &regs->xm2dqspadctrl4); + writel(param->EmcXm2DqsPadCtrl5, &regs->xm2dqspadctrl5); + writel(param->EmcXm2DqsPadCtrl6, &regs->xm2dqspadctrl6); + + writel(param->EmcXm2DqPadCtrl, &regs->xm2dqpadctrl); + writel(param->EmcXm2DqPadCtrl2, &regs->xm2dqpadctrl2); + writel(param->EmcXm2DqPadCtrl3, &regs->xm2dqpadctrl3); + + writel(param->EmcXm2ClkPadCtrl, &regs->xm2clkpadctrl); + writel(param->EmcXm2ClkPadCtrl2, &regs->xm2clkpadctrl2); + + writel(param->EmcXm2CompPadCtrl, &regs->xm2comppadctrl); + + writel(param->EmcXm2VttGenPadCtrl, &regs->xm2vttgenpadctrl); + writel(param->EmcXm2VttGenPadCtrl2, &regs->xm2vttgenpadctrl2); + writel(param->EmcXm2VttGenPadCtrl3, &regs->xm2vttgenpadctrl3); + + writel(param->EmcCttTermCtrl, &regs->ctt_term_ctrl); +} + +static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) +{ + writel(EMC_TIMING_CONTROL_TIMING_UPDATE, &regs->timing_control); +} + +static void sdram_init_mc(const struct sdram_params *param, + struct tegra_mc_regs *regs) +{ + /* Initialize MC VPR settings */ + writel(param->McDisplaySnapRing, &regs->display_snap_ring); + writel(param->McVideoProtectBom, &regs->video_protect_bom); + writel(param->McVideoProtectBomAdrHi, &regs->video_protect_bom_adr_hi); + writel(param->McVideoProtectSizeMb, &regs->video_protect_size_mb); + writel(param->McVideoProtectVprOverride, + &regs->video_protect_vpr_override); + writel(param->McVideoProtectVprOverride1, + &regs->video_protect_vpr_override1); + writel(param->McVideoProtectGpuOverride0, + &regs->video_protect_gpu_override_0); + writel(param->McVideoProtectGpuOverride1, + &regs->video_protect_gpu_override_1); + + /* Program SDRAM geometry paarameters */ + writel(param->McEmemAdrCfg, &regs->emem_adr_cfg); + writel(param->McEmemAdrCfgDev0, &regs->emem_adr_cfg_dev0); + writel(param->McEmemAdrCfgDev1, &regs->emem_adr_cfg_dev1); + + /* Program bank swizzling */ + writel(param->McEmemAdrCfgBankMask0, &regs->emem_bank_swizzle_cfg0); + writel(param->McEmemAdrCfgBankMask1, &regs->emem_bank_swizzle_cfg1); + writel(param->McEmemAdrCfgBankMask2, &regs->emem_bank_swizzle_cfg2); + writel(param->McEmemAdrCfgBankSwizzle3, &regs->emem_bank_swizzle_cfg3); + + /* Program external memory aperature (base and size) */ + writel(param->McEmemCfg, &regs->emem_cfg); + + /* Program SEC carveout (base and size) */ + writel(param->McSecCarveoutBom, &regs->sec_carveout_bom); + writel(param->McSecCarveoutAdrHi, &regs->sec_carveout_adr_hi); + writel(param->McSecCarveoutSizeMb, &regs->sec_carveout_size_mb); + + /* Program MTS carveout (base and size) */ + writel(param->McMtsCarveoutBom, &regs->mts_carveout_bom); + writel(param->McMtsCarveoutAdrHi, &regs->mts_carveout_adr_hi); + writel(param->McMtsCarveoutSizeMb, &regs->mts_carveout_size_mb); + + /* Program the memory arbiter */ + writel(param->McEmemArbCfg, &regs->emem_arb_cfg); + writel(param->McEmemArbOutstandingReq, &regs->emem_arb_outstanding_req); + writel(param->McEmemArbTimingRcd, &regs->emem_arb_timing_rcd); + writel(param->McEmemArbTimingRp, &regs->emem_arb_timing_rp); + writel(param->McEmemArbTimingRc, &regs->emem_arb_timing_rc); + writel(param->McEmemArbTimingRas, &regs->emem_arb_timing_ras); + writel(param->McEmemArbTimingFaw, &regs->emem_arb_timing_faw); + writel(param->McEmemArbTimingRrd, &regs->emem_arb_timing_rrd); + writel(param->McEmemArbTimingRap2Pre, &regs->emem_arb_timing_rap2pre); + writel(param->McEmemArbTimingWap2Pre, &regs->emem_arb_timing_wap2pre); + writel(param->McEmemArbTimingR2R, &regs->emem_arb_timing_r2r); + writel(param->McEmemArbTimingW2W, &regs->emem_arb_timing_w2w); + writel(param->McEmemArbTimingR2W, &regs->emem_arb_timing_r2w); + writel(param->McEmemArbTimingW2R, &regs->emem_arb_timing_w2r); + writel(param->McEmemArbDaTurns, &regs->emem_arb_da_turns); + writel(param->McEmemArbDaCovers, &regs->emem_arb_da_covers); + writel(param->McEmemArbMisc0, &regs->emem_arb_misc0); + writel(param->McEmemArbMisc1, &regs->emem_arb_misc1); + writel(param->McEmemArbRing1Throttle, &regs->emem_arb_ring1_throttle); + writel(param->McEmemArbOverride, &regs->emem_arb_override); + writel(param->McEmemArbOverride1, &regs->emem_arb_override_1); + writel(param->McEmemArbRsv, &regs->emem_arb_rsv); + + /* Program extra snap levels for display client */ + writel(param->McDisExtraSnapLevels, &regs->dis_extra_snap_levels); + + /* Trigger MC timing update */ + writel(MC_TIMING_CONTROL_TIMING_UPDATE, &regs->timing_control); + + /* Program second-level clock enable overrides */ + writel(param->McClkenOverride, &regs->clken_override); + + /* Program statistics gathering */ + writel(param->McStatControl, &regs->stat_control); +} + +static void sdram_init_emc(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Program SDRAM geometry parameters */ + writel(param->EmcAdrCfg, &regs->adr_cfg); + + /* Program second-level clock enable overrides */ + writel(param->EmcClkenOverride, &regs->clken_override); + + /* Program EMC pad auto calibration */ + writel(param->EmcAutoCalInterval, &regs->auto_cal_interval); + writel(param->EmcAutoCalConfig2, &regs->auto_cal_config2); + writel(param->EmcAutoCalConfig3, &regs->auto_cal_config3); + writel(param->EmcAutoCalConfig, &regs->auto_cal_config); + udelay(param->EmcAutoCalWait); +} + +static void sdram_set_emc_timing(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Program EMC timing configuration */ + writel(param->EmcCfg2, &regs->cfg_2); + writel(param->EmcCfgPipe, &regs->cfg_pipe); + writel(param->EmcDbg, &regs->dbg); + writel(param->EmcCmdQ, &regs->cmdq); + writel(param->EmcMc2EmcQ, &regs->mc2emcq); + writel(param->EmcMrsWaitCnt, &regs->mrs_wait_cnt); + writel(param->EmcMrsWaitCnt2, &regs->mrs_wait_cnt2); + writel(param->EmcFbioCfg5, &regs->fbio_cfg5); + writel(param->EmcRc, &regs->rc); + writel(param->EmcRfc, &regs->rfc); + writel(param->EmcRfcSlr, &regs->rfc_slr); + writel(param->EmcRas, &regs->ras); + writel(param->EmcRp, &regs->rp); + writel(param->EmcR2r, &regs->r2r); + writel(param->EmcW2w, &regs->w2w); + writel(param->EmcR2w, &regs->r2w); + writel(param->EmcW2r, &regs->w2r); + writel(param->EmcR2p, &regs->r2p); + writel(param->EmcW2p, &regs->w2p); + writel(param->EmcRdRcd, &regs->rd_rcd); + writel(param->EmcWrRcd, &regs->wr_rcd); + writel(param->EmcRrd, &regs->rrd); + writel(param->EmcRext, &regs->rext); + writel(param->EmcWext, &regs->wext); + writel(param->EmcWdv, &regs->wdv); + writel(param->EmcWdvMask, &regs->wdv_mask); + writel(param->EmcQUse, &regs->quse); + writel(param->EmcQuseWidth, &regs->quse_width); + writel(param->EmcIbdly, &regs->ibdly); + writel(param->EmcEInput, &regs->einput); + writel(param->EmcEInputDuration, &regs->einput_duration); + writel(param->EmcPutermExtra, &regs->puterm_extra); + writel(param->EmcPutermWidth, &regs->puterm_width); + writel(param->EmcPutermAdj, &regs->puterm_adj); + writel(param->EmcCdbCntl1, &regs->cdb_cntl_1); + writel(param->EmcCdbCntl2, &regs->cdb_cntl_2); + writel(param->EmcCdbCntl3, &regs->cdb_cntl_3); + writel(param->EmcQRst, &regs->qrst); + writel(param->EmcQSafe, &regs->qsafe); + writel(param->EmcRdv, &regs->rdv); + writel(param->EmcRdvMask, &regs->rdv_mask); + writel(param->EmcQpop, &regs->qpop); + writel(param->EmcCtt, &regs->ctt); + writel(param->EmcCttDuration, &regs->ctt_duration); + writel(param->EmcRefresh, &regs->refresh); + writel(param->EmcBurstRefreshNum, &regs->burst_refresh_num); + writel(param->EmcPreRefreshReqCnt, &regs->pre_refresh_req_cnt); + writel(param->EmcPdEx2Wr, &regs->pdex2wr); + writel(param->EmcPdEx2Rd, &regs->pdex2rd); + writel(param->EmcPChg2Pden, &regs->pchg2pden); + writel(param->EmcAct2Pden, &regs->act2pden); + writel(param->EmcAr2Pden, &regs->ar2pden); + writel(param->EmcRw2Pden, &regs->rw2pden); + writel(param->EmcTxsr, &regs->txsr); + writel(param->EmcTxsrDll, &regs->txsrdll); + writel(param->EmcTcke, &regs->tcke); + writel(param->EmcTckesr, &regs->tckesr); + writel(param->EmcTpd, &regs->tpd); + writel(param->EmcTfaw, &regs->tfaw); + writel(param->EmcTrpab, &regs->trpab); + writel(param->EmcTClkStable, &regs->tclkstable); + writel(param->EmcTClkStop, &regs->tclkstop); + writel(param->EmcTRefBw, &regs->trefbw); + writel(param->EmcOdtWrite, &regs->odt_write); + writel(param->EmcOdtRead, &regs->odt_read); + writel(param->EmcFbioCfg6, &regs->fbio_cfg6); + writel(param->EmcCfgDigDll, &regs->cfg_dig_dll); + writel(param->EmcCfgDigDllPeriod, &regs->cfg_dig_dll_period); + + /* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */ + writel(param->EmcFbioSpare & 0xfffffffd, &regs->fbio_spare); + + writel(param->EmcCfgRsv, &regs->cfg_rsv); + writel(param->EmcDllXformDqs0, &regs->dll_xform_dqs0); + writel(param->EmcDllXformDqs1, &regs->dll_xform_dqs1); + writel(param->EmcDllXformDqs2, &regs->dll_xform_dqs2); + writel(param->EmcDllXformDqs3, &regs->dll_xform_dqs3); + writel(param->EmcDllXformDqs4, &regs->dll_xform_dqs4); + writel(param->EmcDllXformDqs5, &regs->dll_xform_dqs5); + writel(param->EmcDllXformDqs6, &regs->dll_xform_dqs6); + writel(param->EmcDllXformDqs7, &regs->dll_xform_dqs7); + writel(param->EmcDllXformDqs8, &regs->dll_xform_dqs8); + writel(param->EmcDllXformDqs9, &regs->dll_xform_dqs9); + writel(param->EmcDllXformDqs10, &regs->dll_xform_dqs10); + writel(param->EmcDllXformDqs11, &regs->dll_xform_dqs11); + writel(param->EmcDllXformDqs12, &regs->dll_xform_dqs12); + writel(param->EmcDllXformDqs13, &regs->dll_xform_dqs13); + writel(param->EmcDllXformDqs14, &regs->dll_xform_dqs14); + writel(param->EmcDllXformDqs15, &regs->dll_xform_dqs15); + writel(param->EmcDllXformQUse0, &regs->dll_xform_quse0); + writel(param->EmcDllXformQUse1, &regs->dll_xform_quse1); + writel(param->EmcDllXformQUse2, &regs->dll_xform_quse2); + writel(param->EmcDllXformQUse3, &regs->dll_xform_quse3); + writel(param->EmcDllXformQUse4, &regs->dll_xform_quse4); + writel(param->EmcDllXformQUse5, &regs->dll_xform_quse5); + writel(param->EmcDllXformQUse6, &regs->dll_xform_quse6); + writel(param->EmcDllXformQUse7, &regs->dll_xform_quse7); + writel(param->EmcDllXformQUse8, &regs->dll_xform_quse8); + writel(param->EmcDllXformQUse9, &regs->dll_xform_quse9); + writel(param->EmcDllXformQUse10, &regs->dll_xform_quse10); + writel(param->EmcDllXformQUse11, &regs->dll_xform_quse11); + writel(param->EmcDllXformQUse12, &regs->dll_xform_quse12); + writel(param->EmcDllXformQUse13, &regs->dll_xform_quse13); + writel(param->EmcDllXformQUse14, &regs->dll_xform_quse14); + writel(param->EmcDllXformQUse15, &regs->dll_xform_quse15); + writel(param->EmcDllXformDq0, &regs->dll_xform_dq0); + writel(param->EmcDllXformDq1, &regs->dll_xform_dq1); + writel(param->EmcDllXformDq2, &regs->dll_xform_dq2); + writel(param->EmcDllXformDq3, &regs->dll_xform_dq3); + writel(param->EmcDllXformDq4, &regs->dll_xform_dq4); + writel(param->EmcDllXformDq5, &regs->dll_xform_dq5); + writel(param->EmcDllXformDq6, &regs->dll_xform_dq6); + writel(param->EmcDllXformDq7, &regs->dll_xform_dq7); + writel(param->EmcDllXformAddr0, &regs->dll_xform_addr0); + writel(param->EmcDllXformAddr1, &regs->dll_xform_addr1); + writel(param->EmcDllXformAddr2, &regs->dll_xform_addr2); + writel(param->EmcDllXformAddr3, &regs->dll_xform_addr3); + writel(param->EmcDllXformAddr4, &regs->dll_xform_addr4); + writel(param->EmcDllXformAddr5, &regs->dll_xform_addr5); + writel(param->EmcAcpdControl, &regs->acpd_control); + writel(param->EmcDsrVttgenDrv, &regs->dsr_vttgen_drv); + writel(param->EmcTxdsrvttgen, &regs->txdsrvttgen); + writel(param->EmcBgbiasCtl0, &regs->bgbias_ctl0); + + /* + * Set pipe bypass enable bits before sending any DRAM commands. + * Note other bits in EMC_CFG must be set AFTER REFCTRL is configured. + */ + writebits(param->EmcCfg, &regs->cfg, + (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK | + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK | + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK)); +} + +static void sdram_patch_bootrom(const struct sdram_params *param, + struct tegra_mc_regs *regs) +{ + if (param->BootRomPatchControl & BOOT_ROM_PATCH_CONTROL_ENABLE_MASK) { + uintptr_t addr = ((param->BootRomPatchControl & + BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >> + BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT); + addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2); + writel(param->BootRomPatchData, (uint32_t *)addr); + writel(1, &regs->timing_control); + } +} + +static void sdram_set_dpd3(const struct sdram_params *param, + struct tegra_pmc_regs *regs) +{ + /* Program DPD request */ + writel(param->PmcIoDpd3Req, &regs->io_dpd3_req); + udelay(param->PmcIoDpd3ReqWait); +} + +static void sdram_set_dli_trims(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Program DLI trims */ + writel(param->EmcDliTrimTxDqs0, &regs->dli_trim_txdqs0); + writel(param->EmcDliTrimTxDqs1, &regs->dli_trim_txdqs1); + writel(param->EmcDliTrimTxDqs2, &regs->dli_trim_txdqs2); + writel(param->EmcDliTrimTxDqs3, &regs->dli_trim_txdqs3); + writel(param->EmcDliTrimTxDqs4, &regs->dli_trim_txdqs4); + writel(param->EmcDliTrimTxDqs5, &regs->dli_trim_txdqs5); + writel(param->EmcDliTrimTxDqs6, &regs->dli_trim_txdqs6); + writel(param->EmcDliTrimTxDqs7, &regs->dli_trim_txdqs7); + writel(param->EmcDliTrimTxDqs8, &regs->dli_trim_txdqs8); + writel(param->EmcDliTrimTxDqs9, &regs->dli_trim_txdqs9); + writel(param->EmcDliTrimTxDqs10, &regs->dli_trim_txdqs10); + writel(param->EmcDliTrimTxDqs11, &regs->dli_trim_txdqs11); + writel(param->EmcDliTrimTxDqs12, &regs->dli_trim_txdqs12); + writel(param->EmcDliTrimTxDqs13, &regs->dli_trim_txdqs13); + writel(param->EmcDliTrimTxDqs14, &regs->dli_trim_txdqs14); + writel(param->EmcDliTrimTxDqs15, &regs->dli_trim_txdqs15); + + writel(param->EmcCaTrainingTimingCntl1, + &regs->ca_training_timing_cntl1); + writel(param->EmcCaTrainingTimingCntl2, + &regs->ca_training_timing_cntl2); + + sdram_trigger_emc_timing_update(regs); + udelay(param->EmcTimingControlWait); +} + +static void sdram_set_clock_enable_signal(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + volatile uint32_t dummy = 0; + clrbits_le32(&regs->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | + EMC_PIN_CKE_MASK)); + /* + * Assert dummy read of PIN register to ensure above write to PIN + * register went through. 200 is the recommended value by NVIDIA. + */ + dummy |= readl(&regs->pin); + udelay(200 + param->EmcPinExtraWait); + + /* Deassert reset */ + setbits_le32(&regs->pin, EMC_PIN_RESET_INACTIVE); + /* + * Assert dummy read of PIN register to ensure above write to PIN + * register went through. 200 is the recommended value by NVIDIA. + */ + dummy |= readl(&regs->pin); + udelay(500 + param->EmcPinExtraWait); + + /* Enable clock enable signal */ + setbits_le32(&regs->pin, EMC_PIN_CKE_NORMAL); + /* + * Assert dummy read of PIN register to ensure above write to PIN + * register went through. 200 is the recommended value by NVIDIA. + */ + dummy |= readl(&regs->pin); + udelay(param->EmcPinProgramWait); + + if (!dummy) { + die("Failed to program EMC pin."); + } + + /* Send NOP (trigger) */ + writebits(((1 << EMC_NOP_NOP_CMD_SHIFT) | + (param->EmcDevSelect << EMC_NOP_NOP_DEV_SELECTN_SHIFT)), + &regs->nop, + EMC_NOP_NOP_CMD_MASK | EMC_NOP_NOP_DEV_SELECTN_MASK); + + /* Write mode registers */ + writel(param->EmcEmrs2, &regs->emrs2); + writel(param->EmcEmrs3, &regs->emrs3); + writel(param->EmcEmrs, &regs->emrs); + writel(param->EmcMrs, &regs->mrs); + + if (param->EmcExtraModeRegWriteEnable) { + writel(param->EmcMrwExtra, &regs->mrs); + } +} + +static void sdram_init_zq_calibration(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + if ((param->EmcZcalWarmColdBootEnables & + EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK) == 1) { + /* Need to initialize ZCAL on coldboot. */ + writel(param->EmcZcalInitDev0, &regs->zq_cal); + udelay(param->EmcZcalInitWait); + + if ((param->EmcDevSelect & 2) == 0) { + writel(param->EmcZcalInitDev1, &regs->zq_cal); + udelay(param->EmcZcalInitWait); + } + } else { + udelay(param->EmcZcalInitWait); + } +} + +static void sdram_set_zq_calibration(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Start periodic ZQ calibration */ + writel(param->EmcZcalInterval, &regs->zcal_interval); + writel(param->EmcZcalWaitCnt, &regs->zcal_wait_cnt); + writel(param->EmcZcalMrwCmd, &regs->zcal_mrw_cmd); +} + +static void sdram_set_refresh(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Insert burst refresh */ + if (param->EmcExtraRefreshNum > 0) { + uint32_t refresh_num = (1 << param->EmcExtraRefreshNum) - 1; + writebits((EMC_REF_CMD_REFRESH | EMC_REF_NORMAL_ENABLED | + (refresh_num << EMC_REF_NUM_SHIFT) | + (param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT)), + &regs->ref, (EMC_REF_CMD_MASK | EMC_REF_NORMAL_MASK | + EMC_REF_NUM_MASK | + EMC_REF_DEV_SELECTN_MASK)); + } + + /* Enable refresh */ + writel((param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED), + &regs->refctrl); + + writel(param->EmcDynSelfRefControl, &regs->dyn_self_ref_control); + writel(param->EmcCfg, &regs->cfg); + writel(param->EmcSelDpdCtrl, &regs->sel_dpd_ctrl); + + /* Write addr swizzle lock bit */ + writel(param->EmcFbioSpare, &regs->fbio_spare); + + /* Re-trigger timing to latch power saving functions */ + sdram_trigger_emc_timing_update(regs); +} + +static void sdram_enable_arbiter(const struct sdram_params *param) +{ + /* TODO(hungte) Move values here to standalone header file. */ + uint32_t *AHB_ARBITRATION_XBAR_CTRL = (uint32_t*)(0x6000c000 + 0xe0); + setbits_le32(AHB_ARBITRATION_XBAR_CTRL, + param->AhbArbitrationXbarCtrlMemInitDone << 16); +} + +static void sdram_lock_carveouts(const struct sdram_params *param, + struct tegra_mc_regs *regs) +{ + /* Lock carveouts, and emem_cfg registers */ + writel(param->McVideoProtectWriteAccess, &regs->video_protect_reg_ctrl); + writel(MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED, + &regs->emem_cfg_access_ctrl); + writel(param->McSecCarveoutProtectWriteAccess, + &regs->sec_carveout_reg_ctrl); + writel(param->McMtsCarveoutRegCtrl, &regs->mts_carveout_reg_ctrl); +} + +void sdram_init(const struct sdram_params *param) +{ + struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; + struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE; + struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE; + + sdram_configure_pmc(param, pmc); + sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1); + + sdram_start_clocks(param); + sdram_patch(param->EmcBctSpare2, param->EmcBctSpare3); + + sdram_deassert_sel_dpd(param, pmc); + sdram_set_swizzle(param, emc); + sdram_set_pad_controls(param, emc); + sdram_patch(param->EmcBctSpare4, param->EmcBctSpare5); + + sdram_trigger_emc_timing_update(emc); + sdram_init_mc(param, mc); + sdram_init_emc(param, emc); + sdram_patch(param->EmcBctSpare6, param->EmcBctSpare7); + + sdram_set_emc_timing(param, emc); + sdram_patch_bootrom(param, mc); + sdram_set_dpd3(param, pmc); + sdram_set_dli_trims(param, emc); + sdram_deassert_clock_enable_signal(param, pmc); + sdram_set_clock_enable_signal(param, emc); + sdram_init_zq_calibration(param, emc); + sdram_patch(param->EmcBctSpare8, param->EmcBctSpare9); + + sdram_set_zq_calibration(param, emc); + sdram_patch(param->EmcBctSpare10, param->EmcBctSpare11); + + sdram_trigger_emc_timing_update(emc); + sdram_set_refresh(param, emc); + sdram_enable_arbiter(param); + sdram_lock_carveouts(param, mc); +} + +uint32_t sdram_get_ram_code(void) +{ + struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; + return ((readl(&pmc->strapping_opt_a) & + PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> + PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); +} diff --git a/src/soc/nvidia/tegra124/sdram.h b/src/soc/nvidia/tegra124/sdram.h new file mode 100644 index 0000000..cf5761c --- /dev/null +++ b/src/soc/nvidia/tegra124/sdram.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_SDRAM_H__ +#define __SOC_NVIDIA_TEGRA124_SDRAM_H__ + +#include "sdram_param.h" + +uint32_t sdram_get_ram_code(void); +void sdram_init(const struct sdram_params *param); + +#endif /* __SOC_NVIDIA_TEGRA124_SDRAM_H__ */ diff --git a/src/soc/nvidia/tegra124/sdram_param.h b/src/soc/nvidia/tegra124/sdram_param.h new file mode 100644 index 0000000..1f05566 --- /dev/null +++ b/src/soc/nvidia/tegra124/sdram_param.h @@ -0,0 +1,816 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. The field names are in camel case to ease + * directly converting BCT config files (*.cfg) into C structure. + */ + +#ifndef __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ +#define __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ + +#include <stddef.h> +#include <stdint.h> + +enum { + /* Specifies the memory type to be undefined */ + MEMORY_TYPE_NONE = 0, + + /* Specifies the memory type to be DDR SDRAM */ + MEMORY_TYPE_DDR = 0, + + /* Specifies the memory type to be LPDDR SDRAM */ + MEMORY_TYPE_LPDDR = 0, + + /* Specifies the memory type to be DDR2 SDRAM */ + MEMORY_TYPE_DDR2 = 0, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + MEMORY_TYPE_LPDDR2, + + /* Specifies the memory type to be DDR3 SDRAM */ + MEMORY_TYPE_DDR3, + + MEMORY_TYPE_NUM, + MEMORY_TYPE_FORCE32 = 0X7FFFFFF +}; + +enum { + BOOT_ROM_PATCH_CONTROL_ENABLE_MASK = 0x1 << 31, + BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT = 0, + BOOT_ROM_PATCH_CONTROL_OFFSET_MASK = 0x7FFFFFFF << 0, + BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS = 0x70000000, + + EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK = 1 << 0, +}; + +/** + * Defines the SDRAM parameter structure + */ +struct sdram_params { + + /* Specifies the type of memory device */ + uint32_t memory_type; + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + uint32_t PllMInputDivider; + /* Specifies the N value for PllM */ + uint32_t PllMFeedbackDivider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t PllMStableTime; + /* Specifies misc. control bits */ + uint32_t PllMSetupControl; + /* Enables the Div by 2 */ + uint32_t PllMSelectDiv2; + /* Powers down VCO output Level shifter */ + uint32_t PllMPDLshiftPh45; + /* Powers down VCO output Level shifter */ + uint32_t PllMPDLshiftPh90; + /* Powers down VCO output Level shifter */ + uint32_t PllMPDLshiftPh135; + /* Specifies value for Charge Pump Gain Control */ + uint32_t PllMKCP; + /* Specifies VCO gain */ + uint32_t PllMKVCO; + /* Spare BCT param */ + uint32_t EmcBctSpare0; + /* Spare BCT param */ + uint32_t EmcBctSpare1; + /* Spare BCT param */ + uint32_t EmcBctSpare2; + /* Spare BCT param */ + uint32_t EmcBctSpare3; + /* Spare BCT param */ + uint32_t EmcBctSpare4; + /* Spare BCT param */ + uint32_t EmcBctSpare5; + /* Spare BCT param */ + uint32_t EmcBctSpare6; + /* Spare BCT param */ + uint32_t EmcBctSpare7; + /* Spare BCT param */ + uint32_t EmcBctSpare8; + /* Spare BCT param */ + uint32_t EmcBctSpare9; + /* Spare BCT param */ + uint32_t EmcBctSpare10; + /* Spare BCT param */ + uint32_t EmcBctSpare11; + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + uint32_t EmcClockSource; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t EmcAutoCalInterval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t EmcAutoCalConfig; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t EmcAutoCalConfig2; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t EmcAutoCalConfig3; + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t EmcAutoCalWait; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t EmcAdrCfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t EmcPinProgramWait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t EmcPinExtraWait; + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t EmcTimingControlWait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t EmcRc; + /* Specifies the value for EMC_RFC */ + uint32_t EmcRfc; + /* Specifies the value for EMC_RFC_SLR */ + uint32_t EmcRfcSlr; + /* Specifies the value for EMC_RAS */ + uint32_t EmcRas; + /* Specifies the value for EMC_RP */ + uint32_t EmcRp; + /* Specifies the value for EMC_R2R */ + uint32_t EmcR2r; + /* Specifies the value for EMC_W2W */ + uint32_t EmcW2w; + /* Specifies the value for EMC_R2W */ + uint32_t EmcR2w; + /* Specifies the value for EMC_W2R */ + uint32_t EmcW2r; + /* Specifies the value for EMC_R2P */ + uint32_t EmcR2p; + /* Specifies the value for EMC_W2P */ + uint32_t EmcW2p; + /* Specifies the value for EMC_RD_RCD */ + uint32_t EmcRdRcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t EmcWrRcd; + /* Specifies the value for EMC_RRD */ + uint32_t EmcRrd; + /* Specifies the value for EMC_REXT */ + uint32_t EmcRext; + /* Specifies the value for EMC_WEXT */ + uint32_t EmcWext; + /* Specifies the value for EMC_WDV */ + uint32_t EmcWdv; + /* Specifies the value for EMC_WDV_MASK */ + uint32_t EmcWdvMask; + /* Specifies the value for EMC_QUSE */ + uint32_t EmcQUse; + /* Specifies the value for EMC_QUSE_WIDTH */ + uint32_t EmcQuseWidth; + /* Specifies the value for EMC_IBDLY */ + uint32_t EmcIbdly; + /* Specifies the value for EMC_EINPUT */ + uint32_t EmcEInput; + /* Specifies the value for EMC_EINPUT_DURATION */ + uint32_t EmcEInputDuration; + /* Specifies the value for EMC_PUTERM_EXTRA */ + uint32_t EmcPutermExtra; + /* Specifies the value for EMC_PUTERM_WIDTH */ + uint32_t EmcPutermWidth; + /* Specifies the value for EMC_PUTERM_ADJ */ + uint32_t EmcPutermAdj; + /* Specifies the value for EMC_CDB_CNTL_1 */ + uint32_t EmcCdbCntl1; + /* Specifies the value for EMC_CDB_CNTL_2 */ + uint32_t EmcCdbCntl2; + /* Specifies the value for EMC_CDB_CNTL_3 */ + uint32_t EmcCdbCntl3; + /* Specifies the value for EMC_QRST */ + uint32_t EmcQRst; + /* Specifies the value for EMC_QSAFE */ + uint32_t EmcQSafe; + /* Specifies the value for EMC_RDV */ + uint32_t EmcRdv; + /* Specifies the value for EMC_RDV_MASK */ + uint32_t EmcRdvMask; + /* Specifies the value for EMC_QPOP */ + uint32_t EmcQpop; + /* Specifies the value for EMC_CTT */ + uint32_t EmcCtt; + /* Specifies the value for EMC_CTT_DURATION */ + uint32_t EmcCttDuration; + /* Specifies the value for EMC_REFRESH */ + uint32_t EmcRefresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t EmcBurstRefreshNum; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t EmcPreRefreshReqCnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t EmcPdEx2Wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t EmcPdEx2Rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t EmcPChg2Pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t EmcAct2Pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t EmcAr2Pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t EmcRw2Pden; + /* Specifies the value for EMC_TXSR */ + uint32_t EmcTxsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t EmcTxsrDll; + /* Specifies the value for EMC_TCKE */ + uint32_t EmcTcke; + /* Specifies the value for EMC_TCKESR */ + uint32_t EmcTckesr; + /* Specifies the value for EMC_TPD */ + uint32_t EmcTpd; + /* Specifies the value for EMC_TFAW */ + uint32_t EmcTfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t EmcTrpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t EmcTClkStable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t EmcTClkStop; + /* Specifies the value for EMC_TREFBW */ + uint32_t EmcTRefBw; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t EmcFbioCfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + uint32_t EmcFbioCfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t EmcFbioSpare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t EmcCfgRsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t EmcMrs; + /* Specifies the MP0 command to initialize mode registers */ + uint32_t EmcEmrs; + /* Specifies the MP2 command to initialize mode registers */ + uint32_t EmcEmrs2; + /* Specifies the MP3 command to initialize mode registers */ + uint32_t EmcEmrs3; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t EmcMrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t EmcMrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t EmcMrw3; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t EmcMrw4; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t EmcMrwExtra; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t EmcWarmBootMrwExtra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t EmcWarmBootExtraModeRegWriteEnable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t EmcExtraModeRegWriteEnable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t EmcMrwResetCommand; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t EmcMrwResetNInitWait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t EmcMrsWaitCnt; + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + uint32_t EmcMrsWaitCnt2; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t EmcCfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t EmcCfg2; + /* Specifies the pipe bypass controls */ + uint32_t EmcCfgPipe; + /* Specifies the value for EMC_DBG */ + uint32_t EmcDbg; + /* Specifies the value for EMC_CMDQ */ + uint32_t EmcCmdQ; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t EmcMc2EmcQ; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t EmcDynSelfRefControl; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t AhbArbitrationXbarCtrlMemInitDone; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t EmcCfgDigDll; + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t EmcCfgDigDllPeriod; + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + uint32_t EmcDevSelect; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t EmcSelDpdCtrl; + + /* Pads trimmer delays */ + + /* Specifies the value for EMC_DLL_XFORM_DQS0 */ + uint32_t EmcDllXformDqs0; + /* Specifies the value for EMC_DLL_XFORM_DQS1 */ + uint32_t EmcDllXformDqs1; + /* Specifies the value for EMC_DLL_XFORM_DQS2 */ + uint32_t EmcDllXformDqs2; + /* Specifies the value for EMC_DLL_XFORM_DQS3 */ + uint32_t EmcDllXformDqs3; + /* Specifies the value for EMC_DLL_XFORM_DQS4 */ + uint32_t EmcDllXformDqs4; + /* Specifies the value for EMC_DLL_XFORM_DQS5 */ + uint32_t EmcDllXformDqs5; + /* Specifies the value for EMC_DLL_XFORM_DQS6 */ + uint32_t EmcDllXformDqs6; + /* Specifies the value for EMC_DLL_XFORM_DQS7 */ + uint32_t EmcDllXformDqs7; + /* Specifies the value for EMC_DLL_XFORM_DQS8 */ + uint32_t EmcDllXformDqs8; + /* Specifies the value for EMC_DLL_XFORM_DQS9 */ + uint32_t EmcDllXformDqs9; + /* Specifies the value for EMC_DLL_XFORM_DQS10 */ + uint32_t EmcDllXformDqs10; + /* Specifies the value for EMC_DLL_XFORM_DQS11 */ + uint32_t EmcDllXformDqs11; + /* Specifies the value for EMC_DLL_XFORM_DQS12 */ + uint32_t EmcDllXformDqs12; + /* Specifies the value for EMC_DLL_XFORM_DQS13 */ + uint32_t EmcDllXformDqs13; + /* Specifies the value for EMC_DLL_XFORM_DQS14 */ + uint32_t EmcDllXformDqs14; + /* Specifies the value for EMC_DLL_XFORM_DQS15 */ + uint32_t EmcDllXformDqs15; + /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ + uint32_t EmcDllXformQUse0; + /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ + uint32_t EmcDllXformQUse1; + /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ + uint32_t EmcDllXformQUse2; + /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ + uint32_t EmcDllXformQUse3; + /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ + uint32_t EmcDllXformQUse4; + /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ + uint32_t EmcDllXformQUse5; + /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ + uint32_t EmcDllXformQUse6; + /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ + uint32_t EmcDllXformQUse7; + /* Specifies the value for EMC_DLL_XFORM_ADDR0 */ + uint32_t EmcDllXformAddr0; + /* Specifies the value for EMC_DLL_XFORM_ADDR1 */ + uint32_t EmcDllXformAddr1; + /* Specifies the value for EMC_DLL_XFORM_ADDR2 */ + uint32_t EmcDllXformAddr2; + /* Specifies the value for EMC_DLL_XFORM_ADDR3 */ + uint32_t EmcDllXformAddr3; + /* Specifies the value for EMC_DLL_XFORM_ADDR4 */ + uint32_t EmcDllXformAddr4; + /* Specifies the value for EMC_DLL_XFORM_ADDR5 */ + uint32_t EmcDllXformAddr5; + /* Specifies the value for EMC_DLL_XFORM_QUSE8 */ + uint32_t EmcDllXformQUse8; + /* Specifies the value for EMC_DLL_XFORM_QUSE9 */ + uint32_t EmcDllXformQUse9; + /* Specifies the value for EMC_DLL_XFORM_QUSE10 */ + uint32_t EmcDllXformQUse10; + /* Specifies the value for EMC_DLL_XFORM_QUSE11 */ + uint32_t EmcDllXformQUse11; + /* Specifies the value for EMC_DLL_XFORM_QUSE12 */ + uint32_t EmcDllXformQUse12; + /* Specifies the value for EMC_DLL_XFORM_QUSE13 */ + uint32_t EmcDllXformQUse13; + /* Specifies the value for EMC_DLL_XFORM_QUSE14 */ + uint32_t EmcDllXformQUse14; + /* Specifies the value for EMC_DLL_XFORM_QUSE15 */ + uint32_t EmcDllXformQUse15; + /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ + uint32_t EmcDliTrimTxDqs0; + /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ + uint32_t EmcDliTrimTxDqs1; + /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ + uint32_t EmcDliTrimTxDqs2; + /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ + uint32_t EmcDliTrimTxDqs3; + /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ + uint32_t EmcDliTrimTxDqs4; + /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ + uint32_t EmcDliTrimTxDqs5; + /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ + uint32_t EmcDliTrimTxDqs6; + /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ + uint32_t EmcDliTrimTxDqs7; + /* Specifies the value for EMC_DLI_TRIM_TXDQS8 */ + uint32_t EmcDliTrimTxDqs8; + /* Specifies the value for EMC_DLI_TRIM_TXDQS9 */ + uint32_t EmcDliTrimTxDqs9; + /* Specifies the value for EMC_DLI_TRIM_TXDQS10 */ + uint32_t EmcDliTrimTxDqs10; + /* Specifies the value for EMC_DLI_TRIM_TXDQS11 */ + uint32_t EmcDliTrimTxDqs11; + /* Specifies the value for EMC_DLI_TRIM_TXDQS12 */ + uint32_t EmcDliTrimTxDqs12; + /* Specifies the value for EMC_DLI_TRIM_TXDQS13 */ + uint32_t EmcDliTrimTxDqs13; + /* Specifies the value for EMC_DLI_TRIM_TXDQS14 */ + uint32_t EmcDliTrimTxDqs14; + /* Specifies the value for EMC_DLI_TRIM_TXDQS15 */ + uint32_t EmcDliTrimTxDqs15; + /* Specifies the value for EMC_DLL_XFORM_DQ0 */ + uint32_t EmcDllXformDq0; + /* Specifies the value for EMC_DLL_XFORM_DQ1 */ + uint32_t EmcDllXformDq1; + /* Specifies the value for EMC_DLL_XFORM_DQ2 */ + uint32_t EmcDllXformDq2; + /* Specifies the value for EMC_DLL_XFORM_DQ3 */ + uint32_t EmcDllXformDq3; + /* Specifies the value for EMC_DLL_XFORM_DQ4 */ + uint32_t EmcDllXformDq4; + /* Specifies the value for EMC_DLL_XFORM_DQ5 */ + uint32_t EmcDllXformDq5; + /* Specifies the value for EMC_DLL_XFORM_DQ6 */ + uint32_t EmcDllXformDq6; + /* Specifies the value for EMC_DLL_XFORM_DQ7 */ + uint32_t EmcDllXformDq7; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t WarmBootWait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + uint32_t EmcCttTermCtrl; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t EmcOdtWrite; + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t EmcOdtRead; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t EmcZcalInterval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t EmcZcalWaitCnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t EmcZcalMrwCmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t EmcMrsResetDll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t EmcZcalInitDev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t EmcZcalInitDev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t EmcZcalInitWait; + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + uint32_t EmcZcalWarmColdBootEnables; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + uint32_t EmcMrwLpddr2ZcalWarmBoot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t EmcZqCalDdr3WarmBoot; + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t EmcZcalWarmBootWait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t EmcMrsWarmBootEnable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t EmcMrsResetDllWait; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t EmcMrsExtra; + /* Specifies the extra MRS command at warm boot */ + uint32_t EmcWarmBootMrsExtra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t EmcEmrsDdr2DllEnable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t EmcMrsDdr2DllReset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t EmcEmrsDdr2OcdCalib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t EmcDdr2Wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t EmcClkenOverride; + /* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */ + uint32_t McDisExtraSnapLevels; + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t EmcExtraRefreshNum; + /* Specifies the master override for all EMC clocks */ + uint32_t EmcClkenOverrideAllWarmBoot; + /* Specifies the master override for all MC clocks */ + uint32_t McClkenOverrideAllWarmBoot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t EmcCfgDigDllPeriodWarmBoot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t PmcVddpSel; + /* Specifies the wait time after programming PMC_VDDP_SEL */ + uint32_t PmcVddpSelWait; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t PmcDdrPwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t PmcDdrCfg; + /* Specifies the value for PMC_IO_DPD3_REQ */ + uint32_t PmcIoDpd3Req; + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + uint32_t PmcIoDpd3ReqWait; + /* Specifies the value for PMC_REG_SHORT */ + uint32_t PmcRegShort; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t PmcNoIoPower; + /* Specifies the wait time after programming PMC_POR_DPD_CTRL */ + uint32_t PmcPorDpdCtrlWait; + /* Specifies the value for EMC_XM2CMDPADCTRL */ + uint32_t EmcXm2CmdPadCtrl; + /* Specifies the value for EMC_XM2CMDPADCTRL2 */ + uint32_t EmcXm2CmdPadCtrl2; + /* Specifies the value for EMC_XM2CMDPADCTRL3 */ + uint32_t EmcXm2CmdPadCtrl3; + /* Specifies the value for EMC_XM2CMDPADCTRL4 */ + uint32_t EmcXm2CmdPadCtrl4; + /* Specifies the value for EMC_XM2CMDPADCTRL5 */ + uint32_t EmcXm2CmdPadCtrl5; + /* Specifies the value for EMC_XM2DQSPADCTRL */ + uint32_t EmcXm2DqsPadCtrl; + /* Specifies the value for EMC_XM2DQSPADCTRL2 */ + uint32_t EmcXm2DqsPadCtrl2; + /* Specifies the value for EMC_XM2DQSPADCTRL3 */ + uint32_t EmcXm2DqsPadCtrl3; + /* Specifies the value for EMC_XM2DQSPADCTRL4 */ + uint32_t EmcXm2DqsPadCtrl4; + /* Specifies the value for EMC_XM2DQSPADCTRL5 */ + uint32_t EmcXm2DqsPadCtrl5; + /* Specifies the value for EMC_XM2DQSPADCTRL6 */ + uint32_t EmcXm2DqsPadCtrl6; + /* Specifies the value for EMC_XM2DQPADCTRL */ + uint32_t EmcXm2DqPadCtrl; + /* Specifies the value for EMC_XM2DQPADCTRL2 */ + uint32_t EmcXm2DqPadCtrl2; + /* Specifies the value for EMC_XM2DQPADCTRL3 */ + uint32_t EmcXm2DqPadCtrl3; + /* Specifies the value for EMC_XM2CLKPADCTRL */ + uint32_t EmcXm2ClkPadCtrl; + /* Specifies the value for EMC_XM2CLKPADCTRL2 */ + uint32_t EmcXm2ClkPadCtrl2; + /* Specifies the value for EMC_XM2COMPPADCTRL */ + uint32_t EmcXm2CompPadCtrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL */ + uint32_t EmcXm2VttGenPadCtrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ + uint32_t EmcXm2VttGenPadCtrl2; + /* Specifies the value for EMC_XM2VTTGENPADCTRL3 */ + uint32_t EmcXm2VttGenPadCtrl3; + /* Specifies the value for EMC_ACPD_CONTROL */ + uint32_t EmcAcpdControl; + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ + uint32_t EmcSwizzleRank0ByteCfg; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t EmcSwizzleRank0Byte0; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t EmcSwizzleRank0Byte1; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t EmcSwizzleRank0Byte2; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t EmcSwizzleRank0Byte3; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ + uint32_t EmcSwizzleRank1ByteCfg; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t EmcSwizzleRank1Byte0; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t EmcSwizzleRank1Byte1; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t EmcSwizzleRank1Byte2; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t EmcSwizzleRank1Byte3; + + /* Specifies the value for EMC_DSR_VTTGEN_DRV */ + uint32_t EmcDsrVttgenDrv; + + /* Specifies the value for EMC_TXDSRVTTGEN */ + uint32_t EmcTxdsrvttgen; + /* Specifies the value for EMC_BGBIAS_CTL */ + uint32_t EmcBgbiasCtl0; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t McEmemAdrCfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t McEmemAdrCfgDev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t McEmemAdrCfgDev1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ + uint32_t McEmemAdrCfgBankMask0; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + uint32_t McEmemAdrCfgBankMask1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + uint32_t McEmemAdrCfgBankMask2; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */ + uint32_t McEmemAdrCfgBankSwizzle3; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t McEmemCfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t McEmemArbCfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t McEmemArbOutstandingReq; + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t McEmemArbTimingRcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t McEmemArbTimingRp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t McEmemArbTimingRc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t McEmemArbTimingRas; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t McEmemArbTimingFaw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t McEmemArbTimingRrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t McEmemArbTimingRap2Pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t McEmemArbTimingWap2Pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t McEmemArbTimingR2R; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t McEmemArbTimingW2W; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t McEmemArbTimingR2W; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t McEmemArbTimingW2R; + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t McEmemArbDaTurns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t McEmemArbDaCovers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t McEmemArbMisc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t McEmemArbMisc1; + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t McEmemArbRing1Throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t McEmemArbOverride; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + uint32_t McEmemArbOverride1; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t McEmemArbRsv; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t McClkenOverride; + + /* Specifies the value for MC_STAT_CONTROL */ + uint32_t McStatControl; + /* Specifies the value for MC_DISPLAY_SNAP_RING */ + uint32_t McDisplaySnapRing; + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + uint32_t McVideoProtectBom; + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + uint32_t McVideoProtectBomAdrHi; + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + uint32_t McVideoProtectSizeMb; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + uint32_t McVideoProtectVprOverride; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + uint32_t McVideoProtectVprOverride1; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + uint32_t McVideoProtectGpuOverride0; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + uint32_t McVideoProtectGpuOverride1; + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + uint32_t McSecCarveoutBom; + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + uint32_t McSecCarveoutAdrHi; + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + uint32_t McSecCarveoutSizeMb; + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ + uint32_t McVideoProtectWriteAccess; + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ + uint32_t McSecCarveoutProtectWriteAccess; + + /* Specifies enable for CA training */ + uint32_t EmcCaTrainingEnable; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */ + uint32_t EmcCaTrainingTimingCntl1; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */ + uint32_t EmcCaTrainingTimingCntl2; + /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ + uint32_t SwizzleRankByteEncode; + /* Specifies enable and offset for patched boot rom write */ + uint32_t BootRomPatchControl; + /* Specifies data for patched boot rom write */ + uint32_t BootRomPatchData; + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + uint32_t McMtsCarveoutBom; + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + uint32_t McMtsCarveoutAdrHi; + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + uint32_t McMtsCarveoutSizeMb; + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + uint32_t McMtsCarveoutRegCtrl; + + /* End of generated code by warmboot_code_gen */ +}; + +check_member(sdram_params, McMtsCarveoutRegCtrl, 0x4d0); + +#endif /* __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ */

1 0

New patch to review for coreboot: 275abef tegra124/nyan: memory and display updates
by Isaac Christensen 15 Sep '14

15 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6914 -gerrit commit 275abef6e54e98cad4fa65d2972c2db4043e6316 Author: Andrew Bresticker <abrestic(a)chromium.org> Date: Wed Dec 18 22:41:34 2013 -0800 tegra124/nyan: memory and display updates tegra124: take LP cluster out of reset Reviewed-on: https://chromium-review.googlesource.com/180866 (cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3) tegra124: norrin: display code clean up Reviewed-on: https://chromium-review.googlesource.com/181003 (cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17) tegra124: Change the display hack to use window A Reviewed-on: https://chromium-review.googlesource.com/182001 (cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a) tegra124: norrin: Initialize frame buffer Reviewed-on: https://chromium-review.googlesource.com/182090 (cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167) nyan: do not enable pull-ups on SPI1 (EC) data pins Reviewed-on: https://chromium-review.googlesource.com/181063 (cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c) tegra124: Add source for the LP0 resume blob. Reviewed-on: https://chromium-review.googlesource.com/183152 (cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b) tegra124: Revise Memory Controller registers structure definition. Reviewed-on: https://chromium-review.googlesource.com/182992 (cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1) tegra124: Add more PMC register details. Reviewed-on: https://chromium-review.googlesource.com/183231 (cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829) tegra124: Add SDRAM configuration header file from cbootimage. Reviewed-on: https://chromium-review.googlesource.com/182613 (cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4) tegra124: Revise sdram_param.h for Coreboot. Reviewed-on: https://chromium-review.googlesource.com/182614 (cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8) tegra124: Fix EMC base address. Reviewed-on: https://chromium-review.googlesource.com/183602 (cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e) tegra124: Add EMC registers definition. Reviewed-on: https://chromium-review.googlesource.com/183622 (cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a) tegra124: Never touch MEM(MC)/EMC clocks in ramstage. Reviewed-on: https://chromium-review.googlesource.com/183623 (cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023) tegra124: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/183833 (cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d) tegra124: Allow setting PLLM (clock for SDRAM). Reviewed-on: https://chromium-review.googlesource.com/183621 (cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683) tegra124: SDRAM Initialization. Reviewed-on: https://chromium-review.googlesource.com/182615 (cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce) tegra124: Get RAM_CODE for SDRAM initialization. Reviewed-on: https://chromium-review.googlesource.com/183781 (cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8) Squashed 17 nyan/tegra commits for memory and display. Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/nyan/bct/spi.cfg | 17 + src/mainboard/google/nyan/mainboard.c | 17 +- src/soc/nvidia/tegra124/Makefile.inc | 2 + src/soc/nvidia/tegra124/clk_rst.h | 25 +- src/soc/nvidia/tegra124/clock.c | 67 ++ src/soc/nvidia/tegra124/display.c | 15 +- src/soc/nvidia/tegra124/displayhack.c | 303 +++------ src/soc/nvidia/tegra124/dp.c | 197 +++--- src/soc/nvidia/tegra124/emc.h | 323 +++++++++ src/soc/nvidia/tegra124/include/soc/addressmap.h | 2 +- src/soc/nvidia/tegra124/include/soc/clock.h | 3 + src/soc/nvidia/tegra124/include/soc/display.h | 17 +- src/soc/nvidia/tegra124/lp0/Makefile | 58 ++ src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 627 +++++++++++++++++ src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld | 73 ++ src/soc/nvidia/tegra124/mc.h | 127 +++- src/soc/nvidia/tegra124/pmc.h | 206 +++++- src/soc/nvidia/tegra124/sdram.c | 611 +++++++++++++++++ src/soc/nvidia/tegra124/sdram.h | 28 + src/soc/nvidia/tegra124/sdram_param.h | 816 +++++++++++++++++++++++ 20 files changed, 3170 insertions(+), 364 deletions(-) diff --git a/src/mainboard/google/nyan/bct/spi.cfg b/src/mainboard/google/nyan/bct/spi.cfg index b348ed8..7d05363 100644 --- a/src/mainboard/google/nyan/bct/spi.cfg +++ b/src/mainboard/google/nyan/bct/spi.cfg @@ -14,3 +14,20 @@ DeviceParam[0].SpiFlashParams.ClockDivider = 0x16; DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0; +DevType[1] = NvBootDevType_Spi; +DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[1].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0; + +DevType[2] = NvBootDevType_Spi; +DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[2].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0; + +DevType[3] = NvBootDevType_Spi; +DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[3].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0; diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 1229e74..6fa8a95 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -89,11 +89,11 @@ static void setup_pinmux(void) // SPI1 MOSI pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | - PINMUX_PULL_UP | + PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE); // SPI1 MISO pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | - PINMUX_PULL_UP | + PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE); // SPI1 SCLK pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | @@ -216,9 +216,9 @@ static void setup_kernel_info(void) // Not strictly info, but kernel graphics driver needs this region locked down struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE; - writel(0, &mc->mc_vpr_bom); - writel(0, &mc->mc_vpr_size); - writel(1, &mc->mc_vpr_ctrl); + writel(0, &mc->video_protect_bom); + writel(0, &mc->video_protect_size_mb); + writel(1, &mc->video_protect_reg_ctrl); } static void setup_ec_spi(void) @@ -243,14 +243,17 @@ static void mainboard_init(device_t dev) * conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out * of reset and clock-enabled, otherwise reading AHUB devices (In our * case, I2S/APBIF/AUDIO<XBAR>) will hang. + * + * Note that CLK_H_MEM (MC) and CLK_H_EMC should be already either + * initialized by BootROM, or in romstage SDRAM initialization. */ clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 | CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 | CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 | CLK_L_HOST1X, - CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 | - CLK_H_PMC | CLK_H_MEM | CLK_H_USB3, + CLK_H_I2C2 | CLK_H_SBC1 | CLK_H_PMC | + CLK_H_USB3, CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3, diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index b743570..7a6bced 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -20,10 +20,12 @@ endif romstage-y += cbfs.c romstage-y += cbmem.c +romstage-y += clock.c romstage-y += early_display.c romstage-y += dma.c romstage-y += i2c.c romstage-y += monotonic_timer.c +romstage-y += sdram.c romstage-y += spi.c romstage-y += ../tegra/gpio.c romstage-y += ../tegra/i2c.c diff --git a/src/soc/nvidia/tegra124/clk_rst.h b/src/soc/nvidia/tegra124/clk_rst.h index 156e9a6..efceec5 100644 --- a/src/soc/nvidia/tegra124/clk_rst.h +++ b/src/soc/nvidia/tegra124/clk_rst.h @@ -352,10 +352,20 @@ check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644); #define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT) /* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */ -#define PLLCMX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) +#define PLLCX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) +#define PLLM_BASE_DIVP_MASK (0x1U << PLL_BASE_DIVP_SHIFT) #define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT) #define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT) +/* PLLM specific registers */ +#define PLLM_MISC1_SETUP_SHIFT 0 +#define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT 28 +#define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT 29 +#define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT 30 +#define PLLM_MISC2_KCP_SHIFT 1 +#define PLLM_MISC2_KVCO_SHIFT 0 +#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) + /* Generic, indiscriminate divisor mask. May catch some innocent bystander bits * on the side that we don't particularly care about. */ #define PLL_BASE_DIV_MASK (0xffffff) @@ -414,6 +424,8 @@ check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644); #define CLK_SOURCE_SHIFT 29 #define CLK_SOURCE_MASK (0x7 << CLK_SOURCE_SHIFT) +#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16) + #define CLK_UART_DIV_OVERRIDE (1 << 24) /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ @@ -525,4 +537,15 @@ enum { CRC_RST_CPUG_CLR_PDBG = 0x1 << 30, }; +// RST_CPULP_CMPLX_CLR +enum { + CRC_RST_CPULP_CLR_CPU0 = 0x1 << 0, + CRC_RST_CPULP_CLR_DBG0 = 0x1 << 12, + CRC_RST_CPULP_CLR_CORE0 = 0x1 << 16, + CRC_RST_CPULP_CLR_CX0 = 0x1 << 20, + CRC_RST_CPULP_CLR_L2 = 0x1 << 24, + CRC_RST_CPULP_CLR_NONCPU = 0x1 << 29, + CRC_RST_CPULP_CLR_PDBG = 0x1 << 30, +}; + #endif /* _TEGRA124_CLK_RST_H_ */ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index d98da29..de947f6 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -327,6 +327,63 @@ void clock_external_output(int clk_id) } } +/* Start PLLM for SDRAM. */ +void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, + u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, + u32 same_freq) +{ + u32 misc1 = ((setup << PLLM_MISC1_SETUP_SHIFT) | + (ph45 << PLLM_MISC1_PD_LSHIFT_PH45_SHIFT) | + (ph90 << PLLM_MISC1_PD_LSHIFT_PH90_SHIFT) | + (ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)), + misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) | + (kcp << PLLM_MISC2_KCP_SHIFT)), + base; + + if (same_freq) + emc_source |= CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; + else + emc_source &= ~CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; + + /* + * Note PLLM_BASE.PLLM_OUT1_RSTN must be in RESET_ENABLE mode, and + * PLLM_BASE.ENABLE must be in DISABLE state (both are the default + * values after coldboot reset). + */ + + writel(misc1, &clk_rst->pllm_misc1); + writel(misc2, &clk_rst->pllm_misc2); + + /* PLLM.BASE needs BYPASS=0, different from general init_pll */ + base = readl(&clk_rst->pllm_base); + base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK | + PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS); + base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | + (p << PLL_BASE_DIVP_SHIFT)); + writel(base, &clk_rst->pllm_base); + + setbits_le32(&clk_rst->pllm_base, PLL_BASE_ENABLE); + /* stable_time is required, before we can start to check lock. */ + udelay(stable_time); + + while (!(readl(&clk_rst->pllm_base) & PLL_BASE_LOCK)) { + udelay(1); + } + /* + * After PLLM reports being locked, we have to delay 10us before + * enabling PLLM_OUT. + */ + udelay(10); + + /* Put OUT1 out of reset state (start to output). */ + setbits_le32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE); + + /* Enable and start MEM(MC) and EMC. */ + clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); + writel(emc_source, &clk_rst->clk_src_emc); + udelay(IO_STABILIZATION_DELAY); +} + void clock_cpu0_config_and_reset(void *entry) { void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; @@ -357,6 +414,7 @@ void clock_cpu0_config_and_reset(void *entry) // Enable other CPU related clocks. setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); // Disable the reset on the non-CPU parts of the fast cluster. write32(CRC_RST_CPUG_CLR_NONCPU, @@ -372,6 +430,15 @@ void clock_cpu0_config_and_reset(void *entry) CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, &clk_rst->rst_cpug_cmplx_clr); + + // Disable the reset on the non-CPU parts of the slow cluster. + write32(CRC_RST_CPULP_CLR_NONCPU, + &clk_rst->rst_cpulp_cmplx_clr); + // Disable the various resets on the LP CPU. + write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | + CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | + CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG, + &clk_rst->rst_cpulp_cmplx_clr); } void clock_halt_avp(void) diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 0572ce3..ba357fd 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -301,11 +301,6 @@ void display_startup(device_t dev) /* init dc_a */ init_dca_regs(); - /* init sor */ - init_sor_regs(); - - /* init dpaux */ - init_dpaux_regs(); /* power up perip */ dp_io_powerup(); @@ -313,13 +308,9 @@ void display_startup(device_t dev) /* bringup dp */ dp_bringup(framebuffer_base_mb*MiB); - { u16 *cp = (void *)(framebuffer_base_mb*MiB); - for(i = 0; i < 1048576*8; i++) - if (i % (1376 / 2) < 688 / 2) - cp[i] = 0x222; - else - cp[i] = 0x888; - } + /* init frame buffer */ + memset((void *)(framebuffer_base_mb*MiB), 0x00, + framebuffer_size_mb*MiB); /* tell depthcharge ... */ diff --git a/src/soc/nvidia/tegra124/displayhack.c b/src/soc/nvidia/tegra124/displayhack.c index 0f70e92..af0ac16 100644 --- a/src/soc/nvidia/tegra124/displayhack.c +++ b/src/soc/nvidia/tegra124/displayhack.c @@ -46,11 +46,6 @@ void debug_dpaux_print(u32 addr, u32 size); int dpaux_write(u32 addr, u32 size, u32 data); int dpaux_read(u32 addr, u32 size, u8 * data); -void init_dca_regs(void) -{ - printk(BIOS_SPEW, "%s: entry\n", __func__); - -#if 1 #define DCA_WRITE(reg, val) \ { \ WRITEL(val, (void *)(TEGRA_ARM_DISPLAYA + (reg<<2))); \ @@ -63,17 +58,31 @@ void init_dca_regs(void) _reg_val |= val; \ WRITEL(_reg_val, (void *)(TEGRA_ARM_DISPLAYA + (reg<<2))); \ } -#else // read back -#define DCA_WRITE(reg, val) \ + +#define SOR_WRITE(reg, val) \ + { \ + WRITEL(val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ + } + +#define SOR_READ(reg) READL((void *)(TEGRA_ARM_SOR + (reg<<2))) + +#define SOR_READ_M_WRITE(reg, mask, val) \ + { \ + u32 _reg_val; \ + _reg_val = READL((void *)(TEGRA_ARM_SOR + (reg<<2))); \ + _reg_val &= ~mask; \ + _reg_val |= val; \ + WRITEL(_reg_val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ + } + +#define DPAUX_WRITE(reg, val) \ { \ - printk(BIOS_SPEW,"DCA_WRITE: addr %#x = %#x\n", - (unsigned int) (TEGRA_ARM_DISPLAYA + (reg<<2)), val); \ - WRITEL(val, (void *)(TEGRA_ARM_DISPLAYA + (reg<<2))); \ - printk(BIOS_SPEW,"reads as %#x\n", \ - (unsigned int)READL( (void *)(TEGRA_ARM_DISPLAYA + (reg<<2)))); \ + WRITEL(val, (void *)(TEGRA_ARM_DPAUX + (reg<<2))); \ } -#endif +#define DPAUX_READ(reg) READL((void *)(TEGRA_ARM_DPAUX + (reg<<2))) +void init_dca_regs(void) +{ DCA_WRITE (DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x000000F0); DCA_WRITE (DC_WIN_A_WIN_OPTIONS_0, 0x00000000); DCA_WRITE (DC_WIN_A_BYTE_SWAP_0, 0x00000000); @@ -105,86 +114,20 @@ void init_dca_regs(void) DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE1_0, 0x00000000); DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE2_0, 0x00510104); DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE3_0, 0x00000555); - - printk(BIOS_SPEW, "initial DCA done\n"); -} - -void init_sor_regs(void) -{ - - printk(BIOS_SPEW, "JZ: %s: entry\n", __func__); - -#if 1 -#define SOR_WRITE(reg, val) \ - { \ - WRITEL(val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ - } - -#define SOR_READ(reg) READL( (void *)(TEGRA_ARM_SOR + (reg<<2))) - -#else // read back -#define SOR_WRITE(reg, val) \ - { \ - printk(BIOS_SPEW,"SOR_WRITE: addr %#x = %#x\n", - (unsigned int) (TEGRA_ARM_SOR + (reg<<2)), val); \ - WRITEL(val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ - printk(BIOS_SPEW,"= %#x\n", \ - (unsigned int)READL( (void *)(TEGRA_ARM_SOR + (reg<<2)))); \ - } -#endif -#define SOR_READ_M_WRITE(reg, mask, val) \ - { \ - u32 _reg_val; \ - _reg_val = READL( (void *)(TEGRA_ARM_SOR + (reg<<2))); \ - _reg_val &= ~mask; \ - _reg_val |= val; \ - WRITEL(_reg_val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ - } - - printk(BIOS_SPEW, "initial SOR done\n"); -} - -void init_dpaux_regs(void) -{ - - printk(BIOS_SPEW, "%s: entry\n", __func__); - -#if 1 -#define DPAUX_WRITE(reg, val) \ - { \ - WRITEL(val, (void *)(TEGRA_ARM_DPAUX + (reg<<2))); \ - } -#define DPAUX_READ(reg) READL( (void *)(TEGRA_ARM_DPAUX + (reg<<2))) - -#else // read back -#define DPAUX_WRITE(reg, val) \ - { \ - printk(BIOS_SPEW,"DPAUX_WRITE: addr %#x = %#x\n", (unsigned int) - (TEGRA_ARM_DPAUX + (reg<<2)), val); \ - WRITEL(val, (void *)(TEGRA_ARM_DPAUX + (reg<<2))); \ - printk(BIOS_SPEW,"= %#x\n", \ - (unsigned int)READL( (void *)(TEGRA_ARM_DPAUX + (reg<<2)))); \ - } -#endif - - printk(BIOS_SPEW, "initial DPAUX done\n"); } static int dp_poll_register(void *addr, u32 exp_val, u32 mask, u32 timeout_ms) { - u32 reg_val = 0; - printk(BIOS_SPEW, "JZ: %s: enter, addr %#x: exp_val: %#x, mask: %#x\n", - __func__, (unsigned int)addr, exp_val, mask); do { - udelay(1); + udelay(1000); reg_val = READL(addr); } while (((reg_val & mask) != exp_val) && (--timeout_ms > 0)); if ((reg_val & mask) == exp_val) return 0; /* success */ - printk(BIOS_SPEW, "poll_register %p: timeout\n", addr); + printk(BIOS_WARNING, "poll_register %p: timeout\n", addr); return timeout_ms; } @@ -196,15 +139,10 @@ static void dp_io_set_dpd(u32 power_down) * 1: into deep power down */ u32 val_reg; -#define DP_LVDS_SHIFT 25 -#define DP_LVDS (1 << DP_LVDS_SHIFT) val_reg = READL((void *)(0x7000e400 + 0x1c4)); /* APBDEV_PMC_IO_DPD2_STATUS_0 */ - printk(BIOS_SPEW, "JZ: %s: enter, into dpd %d, cur_status: %#x\n", - __func__, power_down, val_reg); - if ((((val_reg & DP_LVDS) >> DP_LVDS_SHIFT) & 1) == power_down) { - printk(BIOS_SPEW, "PAD already POWER=%d\n", 1 - power_down); + printk(BIOS_DEBUG, "PAD already POWER=%d\n", 1 - power_down); return; } @@ -212,14 +150,11 @@ static void dp_io_set_dpd(u32 power_down) WRITEL((DP_LVDS | ((1 + power_down) << 30)), (void *)(0x7000e400 + 0x1c0)); dp_poll_register((void *)(0x7000e400 + 0x1C4), 0, DP_LVDS, 1000); - //APBDEV_PMC_IO_DPD2_STATUS_0 + /* APBDEV_PMC_IO_DPD2_STATUS_0 */ } void dp_io_powerup(void) { - - printk(BIOS_SPEW, "%s: entry\n", __func__); - SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, (6 << 2) | 2);//select PLLDP, lowest speed(6x) SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, 0x00800000); //set PDCAL SOR_WRITE(SOR_NV_PDISP_SOR_PLL0_0, 0x050003D5); //set PWR,VCOPD @@ -227,14 +162,21 @@ void dp_io_powerup(void) SOR_WRITE(SOR_NV_PDISP_SOR_PLL2_0, 0x01C20000); //set AUX1,6,7,8; clr AUX2 SOR_WRITE(SOR_NV_PDISP_SOR_PLL3_0, 0x38002220); + /* Deassert E_DPD to enable core logic circuits, and wait for > 5us */ dp_io_set_dpd(0); - udelay(1); //Deassert E_DPD to enable core logic circuits, and wait for > 5us + udelay(10); + /* Deassert PDBG to enable bandgap, and wait for > 20us. */ SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL2_0, SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD, (0 << SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT)); - udelay(20); //Deassert PDBG to enable bandgap, and wait for > 20us. + udelay(25); + /* + * Enable the PLL/charge-pump/VCO, and wait for >200us for the PLL to + * lock. Input Clock must be running and stable before PDPLL + * de-assertion. + */ SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL0_0, SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD, (0 << SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT)); @@ -244,10 +186,8 @@ void dp_io_powerup(void) SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL2_0, SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD, (0 << SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT)); - udelay(200); - //Enable the PLL/charge-pump/VCO, and wait for >200us for the PLL to - //lock. Input Clock must be running and stable before PDPLL - //de-assertion. + udelay(210); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL2_0, SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD, (0 << SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT)); @@ -256,7 +196,6 @@ void dp_io_powerup(void) (1 << SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT)); udelay(100); - printk(BIOS_SPEW, "%s: exit\n", __func__); } static int dpaux_check(u32 bytes, u32 data, u32 mask) @@ -268,18 +207,19 @@ static int dpaux_check(u32 bytes, u32 data, u32 mask) DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W0, 0); status = dpaux_read(0x202, bytes, buf); if (status != 0) - printk(BIOS_SPEW, "******AuxRead Error:%04x: status %08x\n", 0x202, - status); + printk(BIOS_ERR, "******AuxRead Error:%04x: status %08x\n", + 0x202, status); else { temp = DPAUX_READ(DPAUX_DP_AUXDATA_READ_W0); if ((temp & mask) != (data & mask)) { - printk(BIOS_SPEW, "AuxCheck ERROR:(r_data) %08x & (mask) %08x != " - "(data) %08x & (mask) %08x\n", temp, mask, data, mask); + printk(BIOS_ERR, "AuxCheck ERROR:(r_data) %08x &" + " (mask) %08x != (data) %08x & (mask) %08x\n", + temp, mask, data, mask); return -1; } else { - printk(BIOS_SPEW, - "AuxCheck PASS:(bytes=%d,data=%08x,mask=%08x):0x%08x\n", - bytes, data, mask, temp); + printk(BIOS_DEBUG, "AuxCheck PASS:(bytes=%d, " + "data=%08x, mask=%08x):0x%08x\n", + bytes, data, mask, temp); return 0; } } @@ -304,8 +244,6 @@ static int dpaux_check(u32 bytes, u32 data, u32 mask) */ static void pattern_level(u32 current, u32 preemph, u32 postcur) { - printk(BIOS_SPEW, "set level:%d %d %d\n", current, preemph, postcur); - //calibrating required if (current == 0) SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0, 0x20202020); @@ -355,7 +293,7 @@ static int dp_training(u32 level, u32 check, u32 speed) wcfg = wcfg | 0x20; wcfg = wcfg | (wcfg << 8) | (wcfg << 16) | (wcfg << 24); dpaux_write(0x103, 4, wcfg); - udelay(50); //100us + udelay(100); DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W0, 0); if (!dpaux_check(2, check, check)) cnt = 100; @@ -366,7 +304,7 @@ static int dp_training(u32 level, u32 check, u32 speed) if (cfg == cfg_d) { ++cnt; if (cnt > 5) - printk(BIOS_SPEW, "link training FAILED\n"); + printk(BIOS_ERR, "Error: link training FAILED\n"); } else { cnt = 0; cfg_d = cfg; @@ -396,10 +334,7 @@ void dp_link_training(u32 lanes, u32 speed) u32 mask, level; u32 reg_val; - printk(BIOS_SPEW, "%s: entry, lanes: %d, speed: %d\n", __func__, lanes, - speed); - - printk(BIOS_SPEW, "\nLink training start\n"); + printk(BIOS_DEBUG, "\nLink training start\n"); switch (lanes) { case 1: @@ -412,21 +347,22 @@ void dp_link_training(u32 lanes, u32 speed) lane_on = 0x0f; break; default: - printk(BIOS_SPEW, "dp: invalid lane count: %d\n", lanes); + printk(BIOS_DEBUG, "dp: invalid lane count: %d\n", + lanes); return; } SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, (0x008000000 | lane_on)); SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, - SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD, - (6 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT)); + SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD, + (6 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT)); SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, - SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD, - (1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT)); + SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD, + (1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT)); SOR_WRITE(SOR_NV_PDISP_SOR_LVDS_0, 0); SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, ((speed << 2) | 2)); - udelay(100); + udelay(100 * 1000); sor_clock_start(); @@ -434,34 +370,34 @@ void dp_link_training(u32 lanes, u32 speed) (((0xF >> (4 - lanes)) << 16) | 1)); SOR_WRITE(SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0, 0x80100000); - printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0.DONE\n"); + printk(BIOS_DEBUG, "Polling SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0.DONE\n"); dp_poll_register((void *)0x54540084, 0x00000000, 0x80000000, 1000); debug_dpaux_print(0x202, 4); - printk(BIOS_SPEW, "set link rate and lane number: %dMHz, %d lanes\n", + printk(BIOS_DEBUG, "set link rate and lane number: %dMHz, %d lanes\n", (speed * 27), lanes); dpaux_write(0x100, 2, ((lanes << 8) | speed)); - printk(BIOS_SPEW, "precharge lane 10us\n"); + printk(BIOS_DEBUG, "precharge lane 10us\n"); reg_val = SOR_READ(SOR_NV_PDISP_SOR_DP_PADCTL0_0); SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, (0x000000f0 | reg_val)); - udelay(100); + udelay(100 * 1000); SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, reg_val); - printk(BIOS_SPEW, "link training cr start\n"); + printk(BIOS_DEBUG, "link training cr start\n"); SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x41414141); dpaux_write(0x102, 1, 0x21); mask = 0x0000ffff >> ((4 - lanes) * 4); level = 0; level = dp_training(level, 0x1111 & mask, speed); - printk(BIOS_SPEW, "level:%x\n", level); + printk(BIOS_DEBUG, "level:%x\n", level); debug_dpaux_print(0x210, 16); - printk(BIOS_SPEW, "link training eq start\n"); + printk(BIOS_DEBUG, "link training eq start\n"); if (speed == 20) { SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x43434343); dpaux_write(0x102, 1, 0x23); @@ -471,7 +407,7 @@ void dp_link_training(u32 lanes, u32 speed) } level = dp_training(level, (0x7777 & mask) | 0x10000, speed); - printk(BIOS_SPEW, "level:%x\n", level); + printk(BIOS_DEBUG, "level:%x\n", level); debug_dpaux_print(0x210, 16); @@ -482,8 +418,7 @@ void dp_link_training(u32 lanes, u32 speed) debug_dpaux_print(0x200, 16); debug_dpaux_print(0x210, 16); - printk(BIOS_SPEW, "Link training done\n\n"); - printk(BIOS_SPEW, "%s: exit\n", __func__); + printk(BIOS_DEBUG, "Link training done\n\n"); } static u32 div_f(u32 a, u32 b, u32 one) @@ -492,23 +427,10 @@ static u32 div_f(u32 a, u32 b, u32 one) return (d); } -u32 dp_setup_timing(u32 panel_id, u32 width, u32 height); -u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) +u32 dp_setup_timing(u32 width, u32 height) { u32 pclk_freq = 0; - /////////////////////////////////////////// - // set up clocks, using PLLD2 - // format: pclk , PLL , panel - //2560x1440: 241.5 , 483/2, dp VESA.red. - //1920x1080: 148.5 , 594/4, dp CEA - //1600x1200: 161.0 , 483/3, dp VESA - //1280x 720: 74.25 , 594/8, dp CEA - // 1024x768: 63.5 , 508/8, dp VESA - // 800x600: 38.25 , 459/12, dp VESA - // 720x480: 27.00 , 594/22, dp CEA - // 640x480: 23.75 , 475/20, dp VESA - u32 PLL_FREQ = (12 / 12 * 283) / 1 / 2; /* 141.5 */ u32 PLL_DIV = 2; u32 SYNC_WIDTH = (8 << 16) | 46; @@ -529,14 +451,6 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) u32 PCLK_FREQ_I, PCLK_FREQ_F; u32 FRATE_I, FRATE_F; - printk(BIOS_SPEW, "%s: entry\n", __func__); - - if (panel_id != 5) { - printk(BIOS_SPEW, "%s: Unsupported panel_id: %d, format=%dx%d\n", - __func__, panel_id, width, height); - return pclk_freq; - } - PLL_FREQ = PLL_FREQ * 1000000; pclk_freq = PLL_FREQ / PLL_DIV; PLL_FREQ_I = PLL_FREQ / 1000000; @@ -545,19 +459,19 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) PCLK_FREQ_F = div_f(PLL_FREQ, PLL_DIV * 1000000, 100); FRATE_I = PLL_FREQ / (PLL_DIV * TOTAL_PIXELS); FRATE_F = div_f(PLL_FREQ, (PLL_DIV * TOTAL_PIXELS), 100); - //bug 1021453 + /* nv_bug 1021453 */ BACK_PORCH = BACK_PORCH - 0x10000; FRONT_PORCH = FRONT_PORCH + 0x10000; - printk(BIOS_SPEW, "ACTIVE: %dx%d\n", (DISP_ACTIVE & 0xFFFF), + printk(BIOS_DEBUG, "ACTIVE: %dx%d\n", (DISP_ACTIVE & 0xFFFF), (DISP_ACTIVE >> 16)); - printk(BIOS_SPEW, "TOTAL: %dx%d\n", (DISP_TOTAL & 0xffff), + printk(BIOS_DEBUG, "TOTAL: %dx%d\n", (DISP_TOTAL & 0xffff), (DISP_TOTAL >> 16)); - printk(BIOS_SPEW, "PLL Freq: %d.%d MHz\n", PLL_FREQ_I, PLL_FREQ_F); - printk(BIOS_SPEW, "Pclk Freq: %d.%d MHz\n", PCLK_FREQ_I, + printk(BIOS_DEBUG, "PLL Freq: %d.%d MHz\n", PLL_FREQ_I, PLL_FREQ_F); + printk(BIOS_DEBUG, "Pclk Freq: %d.%d MHz\n", PCLK_FREQ_I, PCLK_FREQ_F); - printk(BIOS_SPEW, "Frame Rate: %d.%d Hz\n", FRATE_I, FRATE_F); - printk(BIOS_SPEW, "\n"); + printk(BIOS_DEBUG, "Frame Rate: %d.%d Hz\n", FRATE_I, FRATE_F); + printk(BIOS_DEBUG, "\n"); DCA_WRITE(DC_CMD_STATE_ACCESS_0, 0x00000004); DCA_WRITE(DC_DISP_DISP_CLOCK_CONTROL_0, SHIFT_CLK_DIVIDER); @@ -569,9 +483,6 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) DCA_WRITE(DC_DISP_DISP_ACTIVE_0, DISP_ACTIVE); DCA_WRITE(DC_DISP_FRONT_PORCH_0, FRONT_PORCH); - printk(BIOS_SPEW, - "JZ: sync_width: %d, back_porch: %d, disp_active: %d, front_porch: %d\n", - SYNC_WIDTH, BACK_PORCH, DISP_ACTIVE, FRONT_PORCH); //REG(DC_DISP_DISP_WIN_OPTIONS_0, SOR_ENABLE , 1) DCA_READ_M_WRITE(DC_DISP_DISP_WIN_OPTIONS_0, DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD, @@ -611,7 +522,6 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD, (SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 << SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT)); - printk(BIOS_SPEW, "%s: exit\n", __func__); return pclk_freq; } @@ -623,7 +533,9 @@ static u32 calc_config(u32 ts, u32 a, u32 b, u32 bpp) u32 act_frac; u32 err; u32 water_mark; - printk(BIOS_SPEW, "calc_config ts %d a %d b %d bpp %d\n", ts, a, b, bpp); + + printk(BIOS_DEBUG, "calc_config ts %d a %d b %d bpp %d\n", + ts, a, b, bpp); if (diff != 0) { if (diff > (b / 2)) { diff = b - diff; @@ -669,7 +581,7 @@ static u32 calc_config(u32 ts, u32 a, u32 b, u32 bpp) (water_mark << SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT)); - printk(BIOS_SPEW, + printk(BIOS_DEBUG, "SOR_DP_CONFIG0:TU,CNT,POL,FRAC,WMK,ERR=%d,%d,%d,%d,%d,%d/%d\n", ts, act_cnt, act_pol, act_frac, water_mark, err, b); } @@ -687,7 +599,8 @@ static u32 dp_buf_config(u32 pclkfreq, u32 linkfreq, u32 lanes, u32 bpp) u32 min_err = 1000000000; u32 ts = 64; u32 c_err; - printk(BIOS_SPEW, "dp buf config pclkfreq %d linkfreq %d lanes %d bpp %d\n", + + printk(BIOS_DEBUG, "dp buf config pclkfreq %d linkfreq %d lanes %d bpp %d\n", pclkfreq, linkfreq, lanes, bpp); for (i = 2; i <= 7; ++i) { while (((pf / i * i) == pf) && ((lf / i * i) == lf)) { @@ -698,9 +611,9 @@ static u32 dp_buf_config(u32 pclkfreq, u32 linkfreq, u32 lanes, u32 bpp) a = pf * bpp / 8; b = lf * lanes; - printk(BIOS_SPEW, "ratio:%d/%d\n", a, b); + printk(BIOS_DEBUG, "ratio:%d/%d\n", a, b); if (a > (b * 98 / 100)) - printk(BIOS_SPEW, "Error:link speed not enough\n"); + printk(BIOS_ERR, "Error:link speed not enough\n"); //search best tusize //min_err = 1000000000; @@ -727,10 +640,11 @@ static u32 dp_buf_config(u32 pclkfreq, u32 linkfreq, u32 lanes, u32 bpp) return (tusize); } +/* void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, u32 lane_count, u32 enhanced_framing, u32 panel_edp, u32 pclkfreq, u32 linkfreq); - +*/ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, u32 lane_count, u32 enhanced_framing, u32 panel_edp, u32 pclkfreq, u32 linkfreq) @@ -738,8 +652,8 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, u32 tusize; u32 linkctl; - printk(BIOS_SPEW, "%s: entry, winb: 0x%08x ", __func__, winb_addr); - printk(BIOS_SPEW, " panel_bpp %d\n", panel_bpp); + printk(BIOS_DEBUG, "%s: winb: 0x%08x, panel_bpp %d ", + __func__, winb_addr, panel_bpp); if (panel_bpp == 18) { //0x54540010 @@ -755,37 +669,25 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT)); } -#define SRC_BPP 16 -#define COLORDEPTH 0x6 - -#define BLUE 0xFF0000 -#define GREEN 0x00FF00 -#define RED 0x0000FF -#define YELLOW 0x00FFFF -#define BLACK 0x000000 -#define WHITE 0xFFFFFF -#define GREY 0x55aa00 - - DCA_WRITE(DC_B_WIN_BD_SIZE_0, ((height << 16) | width)); - DCA_WRITE(DC_B_WIN_BD_PRESCALED_SIZE_0, + DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000010); + DCA_WRITE(DC_WIN_A_SIZE_0, ((height << 16) | width)); + DCA_WRITE(DC_WIN_A_PRESCALED_SIZE_0, ((height << 16) | (width * SRC_BPP / 8))); - DCA_WRITE(DC_B_WIN_BD_LINE_STRIDE_0, + DCA_WRITE(DC_WIN_A_LINE_STRIDE_0, ((width * SRC_BPP / 8 + 31) / 32 * 32)); - DCA_WRITE(DC_B_WIN_BD_COLOR_DEPTH_0, COLORDEPTH); - DCA_WRITE(DC_B_WINBUF_BD_START_ADDR_0, winb_addr); - DCA_WRITE(DC_B_WIN_BD_DDA_INCREMENT_0, 0x10001000); + DCA_WRITE(DC_WIN_A_COLOR_DEPTH_0, COLORDEPTH); + DCA_WRITE(DC_WINBUF_A_START_ADDR_LO_0, winb_addr); + DCA_WRITE(DC_WIN_A_DDA_INCREMENT_0, 0x10001000); SOR_WRITE(SOR_NV_PDISP_SOR_CRC_CNTRL_0, 0x00000001); DCA_WRITE(DC_COM_CRC_CONTROL_0, 0x00000009); //CRC_ALWAYS+CRC_ENABLE DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE2_0, 0x00000000); DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE3_0, 0x00000000); DCA_WRITE(DC_DISP_DISP_SIGNAL_OPTIONS0_0, 0x00000000); - // DCA_WRITE (DC_DISP_BLEND_BACKGROUND_COLOR_0 ,WHITE ); - DCA_WRITE(DC_DISP_BLEND_BACKGROUND_COLOR_0, YELLOW); + DCA_WRITE(DC_DISP_BLEND_BACKGROUND_COLOR_0, COLOR_WHITE); DCA_WRITE(DC_CMD_DISPLAY_COMMAND_0, 0x00000020); SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0, 0x00000e48); - dpaux_write(0x101, 1, (enhanced_framing << 7) | lane_count); if (panel_edp) dpaux_write(0x10A, 1, 1); @@ -793,8 +695,6 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, tusize = dp_buf_config(pclkfreq, (linkfreq * 1000000), lane_count, panel_bpp); - printk(BIOS_SPEW, "JZ, after dp_buf_config, tusize: 0x%08x\n", tusize); - linkctl = ((0xF >> (4 - lane_count)) << 16) | (enhanced_framing << 14) | (tusize << 2) | @@ -804,7 +704,7 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, SOR_WRITE(SOR_NV_PDISP_SOR_DP_SPARE0_0, ((panel_edp << 1) | 0x05)); SOR_WRITE(SOR_NV_PDISP_SOR_PWR_0, 0x80000001); - printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_PWR_0.DONE\n"); + printk(BIOS_DEBUG, "Polling SOR_NV_PDISP_SOR_PWR_0.DONE\n"); dp_poll_register((void *)0x54540054, 0x00000000, 0x80000000, 1000); //SOR_NV_PDISP_SOR_PWR_0 //sor_update @@ -815,7 +715,7 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE1_0, 0x0000000e); //sor_super_update SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE0_0, 0x00000000); - printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_TEST_0.ATTACHED\n"); + printk(BIOS_DEBUG, "Polling SOR_NV_PDISP_SOR_TEST_0.ATTACHED\n"); dp_poll_register((void *)0x54540058, 0x00000400, 0x00000400, 1000); //SOR_NV_PDISP_SOR_TEST_0 @@ -823,21 +723,16 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x0000009f); DCA_WRITE(DC_CMD_DISPLAY_POWER_CONTROL_0, 0x00050155); - printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_TEST_0.AWAKE\n"); + printk(BIOS_DEBUG, "Polling SOR_NV_PDISP_SOR_TEST_0.AWAKE\n"); dp_poll_register((void *)0x54540058, 0x00000200, 0x00000300, 1000); //SOR_NV_PDISP_SOR_TEST_0 // DCA_WRITE (DC_CMD_STATE_ACCESS_0 ,0); DCA_WRITE(DC_CMD_STATE_ACCESS_0, 4); DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x0000ffff); - /* enable win_b */ - - DCA_READ_M_WRITE(DC_B_WIN_BD_WIN_OPTIONS_0, - DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD, - (DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE << - DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT)); - - printk(BIOS_SPEW, "JZ: %s: f_ret @ line %d\n", __func__, __LINE__); + DCA_READ_M_WRITE(DC_WIN_A_WIN_OPTIONS_0, + DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD, + (DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE << + DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT)); } - diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 3205699..6b0f4c8 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -39,33 +39,36 @@ static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) } static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, - u32 reg, u32 val) + u32 reg, u32 val) { void *addr = dp->aux_base + (u32) (reg << 2); WRITEL(val, addr); } static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp, - u32 reg, u32 mask, u32 exp_val, - u32 poll_interval_us, - u32 timeout_ms) + u32 reg, u32 mask, u32 exp_val, + u32 poll_interval_us, + u32 timeout_us) { u32 reg_val = 0; + u32 temp = timeout_us; - printk(BIOS_SPEW, "JZ: %s: enter, poll_reg: %#x: timeout: 0x%x\n", - __func__, reg * 4, timeout_ms); do { - udelay(1); + udelay(poll_interval_us); reg_val = tegra_dpaux_readl(dp, reg); - } while (((reg_val & mask) != exp_val) && (--timeout_ms > 0)); + if (timeout_us > poll_interval_us) + timeout_us -= poll_interval_us; + else + break; + } while ((reg_val & mask) != exp_val); if ((reg_val & mask) == exp_val) return 0; /* success */ - printk(BIOS_SPEW, + printk(BIOS_ERR, "dpaux_poll_register 0x%x: timeout: " "(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", reg, reg_val, mask, exp_val); - return timeout_ms; + return temp; } static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp) @@ -73,18 +76,18 @@ static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp) /* According to DP spec, each aux transaction needs to finish within 40ms. */ if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL, - DPAUX_DP_AUXCTL_TRANSACTREQ_MASK, - DPAUX_DP_AUXCTL_TRANSACTREQ_DONE, - 100, DP_AUX_TIMEOUT_MS * 1000) != 0) { - printk(BIOS_SPEW, "dp: DPAUX transaction timeout\n"); + DPAUX_DP_AUXCTL_TRANSACTREQ_MASK, + DPAUX_DP_AUXCTL_TRANSACTREQ_DONE, + 100, DP_AUX_TIMEOUT_MS * 1000) != 0) { + printk(BIOS_INFO, "dp: DPAUX transaction timeout\n"); return -1; } return 0; } static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, - u32 addr, u8 * data, u32 * size, - u32 * aux_stat) + u32 addr, u8 *data, u32 *size, + u32 *aux_stat) { int i; u32 reg_val; @@ -102,21 +105,11 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, case DPAUX_DP_AUXCTL_CMD_AUXWR: break; default: - printk(BIOS_SPEW, "dp: aux write cmd 0x%x is invalid\n", cmd); + printk(BIOS_ERR, "dp: aux write cmd 0x%x is invalid\n", + cmd); return -1; } -#if 0 -/* interesting. */ - if (tegra_platform_is_silicon()) { - *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { - printk(BIOS_SPEW, "dp: HPD is not detected\n"); - return -EFAULT; - } - } -#endif - tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) { memcpy(&temp_data, data, 4); @@ -139,7 +132,7 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); if (tegra_dpaux_wait_transaction(dp)) - printk(BIOS_SPEW, "dp: aux write transaction timeout\n"); + printk(BIOS_ERR, "dp: aux write transaction timeout\n"); *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); @@ -148,13 +141,13 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { if (timeout_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux write retry (0x%x) -- %d\n", + printk(BIOS_INFO, "dp: aux write retry (0x%x) -- %d\n", *aux_stat, timeout_retries); /* clear the error bits */ tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat); continue; } else { - printk(BIOS_SPEW, "dp: aux write got error (0x%x)\n", + printk(BIOS_ERR, "dp: aux write got error (0x%x)\n", *aux_stat); return -1; } @@ -163,13 +156,13 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { if (defer_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux write defer (0x%x) -- %d\n", + printk(BIOS_INFO, "dp: aux write defer (0x%x) -- %d\n", *aux_stat, defer_retries); /* clear the error bits */ tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat); continue; } else { - printk(BIOS_SPEW, "dp: aux write defer exceeds max retries " + printk(BIOS_ERR, "dp: aux write defer exceeds max retries " "(0x%x)\n", *aux_stat); return -1; } @@ -180,7 +173,8 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); return 0; } else { - printk(BIOS_SPEW, "dp: aux write failed (0x%x)\n", *aux_stat); + printk(BIOS_ERR, "dp: aux write failed (0x%x)\n", + *aux_stat); return -1; } } @@ -189,7 +183,7 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, } static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, - u8 * data, u32 * size, u32 * aux_stat) + u8 *data, u32 *size, u32 *aux_stat) { u32 cur_size = 0; u32 finished = 0; @@ -202,7 +196,7 @@ static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, cur_size = DP_AUX_MAX_BYTES; cur_left = cur_size; ret = tegra_dc_dpaux_write_chunk(dp, cmd, addr, - data, &cur_left, aux_stat); + data, &cur_left, aux_stat); cur_size -= cur_left; finished += cur_size; @@ -218,8 +212,8 @@ static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, } static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, - u32 addr, u8 * data, u32 * size, - u32 * aux_stat) + u32 addr, u8 *data, u32 *size, + u32 *aux_stat) { u32 reg_val; u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; @@ -236,7 +230,8 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, case DPAUX_DP_AUXCTL_CMD_AUXRD: break; default: - printk(BIOS_SPEW, "dp: aux read cmd 0x%x is invalid\n", cmd); + printk(BIOS_ERR, "dp: aux read cmd 0x%x is invalid\n", + cmd); return -1; } @@ -253,37 +248,38 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; reg_val |= cmd; - printk(BIOS_SPEW, "cmd = %08x\n", reg_val); reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); - printk(BIOS_SPEW, "cmd = %08x\n", reg_val); while ((timeout_retries > 0) && (defer_retries > 0)) { if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || (defer_retries != DP_AUX_DEFER_MAX_TRIES)) udelay(DP_DPCP_RETRY_SLEEP_NS * 2); reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; - printk(BIOS_SPEW, "cmd = %08x\n", reg_val); tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); if (tegra_dpaux_wait_transaction(dp)) - printk(BIOS_SPEW, "dp: aux read transaction timeout\n"); + printk(BIOS_INFO, "dp: aux read transaction timeout\n"); *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - printk(BIOS_SPEW, "dp: %s: aux stat: 0x%08x\n", __func__, *aux_stat); + printk(BIOS_DEBUG, "dp: %s: aux stat: 0x%08x\n", __func__, + *aux_stat); if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { if (timeout_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux read retry (0x%x) -- %d\n", - *aux_stat, timeout_retries); + printk(BIOS_INFO, "dp: aux read retry (0x%x)" + " -- %d\n", *aux_stat, + timeout_retries); /* clear the error bits */ - tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat); + tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, + *aux_stat); continue; /* retry */ } else { - printk(BIOS_SPEW, "dp: aux read got error (0x%x)\n", *aux_stat); + printk(BIOS_ERR, "dp: aux read got error" + " (0x%x)\n", *aux_stat); return -1; } } @@ -291,13 +287,13 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { if (defer_retries-- > 0) { - printk(BIOS_SPEW, "dp: aux read defer (0x%x) -- %d\n", + printk(BIOS_INFO, "dp: aux read defer (0x%x) -- %d\n", *aux_stat, defer_retries); /* clear the error bits */ tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat); continue; } else { - printk(BIOS_SPEW, "dp: aux read defer exceeds max retries " + printk(BIOS_INFO, "dp: aux read defer exceeds max retries " "(0x%x)\n", *aux_stat); return -1; } @@ -310,20 +306,22 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) temp_data[i] = tegra_dpaux_readl(dp, - DPAUX_DP_AUXDATA_READ_W(i)); + DPAUX_DP_AUXDATA_READ_W(i)); *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); - printk(BIOS_SPEW, "dp: aux read data %d bytes\n", *size); + printk(BIOS_INFO, "dp: aux read data %d bytes\n", + *size); memcpy(data, temp_data, *size); return 0; } else { - printk(BIOS_SPEW, "dp: aux read failed (0x%x\n", *aux_stat); + printk(BIOS_ERR, "dp: aux read failed (0x%x\n", + *aux_stat); return -1; } } /* Should never come to here */ - printk(BIOS_SPEW, "%s: can't\n", __func__); + printk(BIOS_ERR, "%s: can't\n", __func__); return -1; } @@ -340,7 +338,7 @@ int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, cur_size = DP_AUX_MAX_BYTES; ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr, - data, &cur_size, aux_stat); + data, &cur_size, aux_stat); /* cur_size should be the real size returned */ addr += cur_size; @@ -350,12 +348,6 @@ int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, if (ret) break; -#if 0 - if (cur_size == 0) { - printk(BIOS_SPEW, "JZ: no data found, ret\n"); - break; - } -#endif } while (*size > finished); *size = finished; @@ -372,7 +364,7 @@ static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, cmd, data_ptr, &size, &status); if (ret) - printk(BIOS_SPEW, + printk(BIOS_ERR, "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n", cmd, status); @@ -380,7 +372,7 @@ static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, } static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp, - struct tegra_dc_dp_link_config *cfg) + struct tegra_dc_dp_link_config *cfg) { u8 dpcd_data; int ret; @@ -390,27 +382,26 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp, return ret; cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK; - printk(BIOS_SPEW, "JZ: %s: max_lane_count: %d\n", __func__, + printk(BIOS_INFO, "%s: max_lane_count: %d\n", __func__, cfg->max_lane_count); cfg->support_enhanced_framing = (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? 1 : 0; - printk(BIOS_SPEW, "JZ: %s: enh-framing: %d\n", __func__, + printk(BIOS_INFO, "%s: enh-framing: %d\n", __func__, cfg->support_enhanced_framing); ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD, &dpcd_data); if (ret) return ret; cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ? 1 : 0; - printk(BIOS_SPEW, "JZ: %s: downspread: %d\n", __func__, cfg->downspread); + printk(BIOS_INFO, "%s: downspread: %d\n", __func__, cfg->downspread); ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH, &cfg->max_link_bw); if (ret) return ret; - printk(BIOS_SPEW, "JZ: %s: max_link_bw: %d\n", __func__, cfg->max_link_bw); + printk(BIOS_INFO, "%s: max_link_bw: %d\n", __func__, cfg->max_link_bw); - // jz, changed // cfg->bits_per_pixel = dp->dc->pdata->default_out->depth; cfg->bits_per_pixel = 18; @@ -427,7 +418,7 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp, (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ? 1 : 0; cfg->only_enhanced_framing = (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ? 1 : 0; - printk(BIOS_SPEW, "JZ: %s: alt_reset_cap: %d, only_enh_framing: %d\n", + printk(BIOS_DEBUG, "%s: alt_reset_cap: %d, only_enh_framing: %d\n", __func__, cfg->alt_scramber_reset_cap, cfg->only_enhanced_framing); cfg->lane_count = cfg->max_lane_count; @@ -448,13 +439,13 @@ static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp, u8 * rev) ret = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, NV_DPCD_REV, rev, &size, &status); if (ret) { - printk(BIOS_SPEW, "dp: Failed to read NV_DPCD_REV\n"); + printk(BIOS_WARNING, "dp: Failed to read NV_DPCD_REV\n"); return ret; } return 0; } -u32 dp_setup_timing(u32 panel_id, u32 width, u32 height); +u32 dp_setup_timing(u32 width, u32 height); void dp_bringup(u32 winb_addr) { struct tegra_dc_dp_data *dp = &dp_data; @@ -465,40 +456,40 @@ void dp_bringup(u32 winb_addr) u32 xres = 1366; /* norrin display */ u32 yres = 768; - printk(BIOS_SPEW, "JZ: %s: entry\n", __func__); - dp->sor.base = (void *)TEGRA_ARM_SOR; dp->sor.portnum = 0; dp->aux_base = (void *)TEGRA_ARM_DPAUX; /* read panel info */ - if (!tegra_dc_dpcd_read_rev(dp, (u8 *) & dpcd_rev)) { - printk(BIOS_SPEW, "PANEL info: \n"); - printk(BIOS_SPEW, "--DPCP version(%#x): %d.%d\n", - dpcd_rev, (dpcd_rev >> 4) & 0x0f, (dpcd_rev & 0x0f)); + if (!tegra_dc_dpcd_read_rev(dp, (u8 *)&dpcd_rev)) { + printk(BIOS_INFO, "PANEL info:\n"); + printk(BIOS_INFO, "--DPCP version(%#x): %d.%d\n", + dpcd_rev, (dpcd_rev >> 4) & 0x0f, + (dpcd_rev & 0x0f)); } if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg)) - printk(BIOS_SPEW, "dp: failed to init link configuration\n"); + printk(BIOS_ERR, "dp: failed to init link configuration\n"); dp_link_training((u32) (dp->link_cfg.lane_count), (u32) (dp->link_cfg.link_bw)); - pclk_freq = dp_setup_timing(5, xres, yres); - printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n", __func__, pclk_freq); + pclk_freq = dp_setup_timing(xres, yres); + printk(BIOS_DEBUG, "%s: pclk_freq: %d\n", __func__, pclk_freq); - void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, - u32 lane_count, u32 enhanced_framing, u32 panel_edp, - u32 pclkfreq, u32 linkfreq); - dp_misc_setting(dp->link_cfg.bits_per_pixel, - xres, yres, winb_addr, - (u32) dp->link_cfg.lane_count, - (u32) dp->link_cfg.enhanced_framing, - (u32) dp->link_cfg.alt_scramber_reset_cap, - pclk_freq, dp->link_cfg.link_bw * 27); + void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, + u32 winb_addr, u32 lane_count, + u32 enhanced_framing, u32 panel_edp, + u32 pclkfreq, u32 linkfreq); + dp_misc_setting(dp->link_cfg.bits_per_pixel, + xres, yres, winb_addr, + (u32) dp->link_cfg.lane_count, + (u32) dp->link_cfg.enhanced_framing, + (u32) dp->link_cfg.alt_scramber_reset_cap, + pclk_freq, dp->link_cfg.link_bw * 27); } void debug_dpaux_print(u32 addr, u32 size) @@ -509,21 +500,22 @@ void debug_dpaux_print(u32 addr, u32 size) int i; if ((size == 0) || (size > 16)) { - printk(BIOS_SPEW, "dp: %s: invalid size %d\n", __func__, size); + printk(BIOS_ERR, "dp: %s: invalid size %d\n", __func__, size); return; } if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - addr, buf, &size, &status)) { - printk(BIOS_SPEW, "******AuxRead Error: 0x%04x: status 0x%08x\n", addr, - status); + addr, buf, &size, &status)) { + printk(BIOS_ERR, "******AuxRead Error: 0x%04x: status 0x%08x\n", + addr, status); return; } - printk(BIOS_SPEW, "%s: addr: 0x%04x, size: %d\n", __func__, addr, size); + printk(BIOS_DEBUG, "%s: addr: 0x%04x, size: %d\n", __func__, + addr, size); for (i = 0; i < size; ++i) - printk(BIOS_SPEW, " %02x", buf[i]); + printk(BIOS_DEBUG, " %02x", buf[i]); - printk(BIOS_SPEW, "\n"); + printk(BIOS_DEBUG, "\n"); } int dpaux_read(u32 addr, u32 size, u8 * data) @@ -533,14 +525,14 @@ int dpaux_read(u32 addr, u32 size, u8 * data) u32 status = 0; if ((size == 0) || (size > 16)) { - printk(BIOS_SPEW, "dp: %s: invalid size %d\n", __func__, size); + printk(BIOS_ERR, "dp: %s: invalid size %d\n", __func__, size); return -1; } if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - addr, data, &size, &status)) { - printk(BIOS_SPEW, "dp: Failed to read reg %#x, status: %#x\n", addr, - status); + addr, data, &size, &status)) { + printk(BIOS_ERR, "dp: Failed to read reg %#x, status: %#x\n", + addr, status); return -1; } @@ -553,13 +545,10 @@ int dpaux_write(u32 addr, u32 size, u32 data) u32 status = 0; int ret; - printk(BIOS_SPEW, "JZ: %s: entry, addr: 0x%08x, size: 0x%08x, data: %#x\n", - __func__, addr, size, data); - ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXWR, addr, (u8 *) & data, &size, &status); if (ret) - printk(BIOS_SPEW, "dp: Failed to write to reg %#x, status: 0x%x\n", + printk(BIOS_ERR, "dp: Failed to write to reg %#x, status: 0x%x\n", addr, status); return ret; } diff --git a/src/soc/nvidia/tegra124/emc.h b/src/soc/nvidia/tegra124/emc.h new file mode 100644 index 0000000..f9d415b --- /dev/null +++ b/src/soc/nvidia/tegra124/emc.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA124_EMC_H__ +#define __SOC_NVIDIA_TEGRA124_EMC_H__ + +#include <stddef.h> +#include <stdint.h> + +enum { + EMC_PIN_RESET_MASK = 1 << 8, + EMC_PIN_RESET_ACTIVE = 0 << 8, + EMC_PIN_RESET_INACTIVE = 1 << 8, + EMC_PIN_DQM_MASK = 1 << 4, + EMC_PIN_DQM_NORMAL = 0 << 4, + EMC_PIN_DQM_INACTIVE = 1 << 4, + EMC_PIN_CKE_MASK = 1 << 0, + EMC_PIN_CKE_POWERDOWN = 0 << 0, + EMC_PIN_CKE_NORMAL = 1 << 0, + + EMC_REF_CMD_MASK = 1 << 0, + EMC_REF_CMD_REFRESH = 1 << 0, + EMC_REF_NORMAL_MASK = 1 << 1, + EMC_REF_NORMAL_INIT = 0 << 1, + EMC_REF_NORMAL_ENABLED = 1 << 1, + EMC_REF_NUM_SHIFT = 8, + EMC_REF_NUM_MASK = 0xFF << EMC_REF_NUM_SHIFT, + EMC_REF_DEV_SELECTN_SHIFT = 30, + EMC_REF_DEV_SELECTN_MASK = 3 << EMC_REF_DEV_SELECTN_SHIFT, + + EMC_REFCTRL_REF_VALID_MASK = 1 << 31, + EMC_REFCTRL_REF_VALID_DISABLED = 0 << 31, + EMC_REFCTRL_REF_VALID_ENABLED = 1 << 31, + + EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK = 1 << 1, + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK = 1 << 2, + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK = 1 << 3, + + EMC_NOP_NOP_CMD_SHIFT = 0, + EMC_NOP_NOP_CMD_MASK = 1 << EMC_NOP_NOP_CMD_SHIFT, + EMC_NOP_NOP_DEV_SELECTN_SHIFT = 30, + EMC_NOP_NOP_DEV_SELECTN_MASK = 3 << EMC_NOP_NOP_DEV_SELECTN_SHIFT, + + EMC_TIMING_CONTROL_TIMING_UPDATE = 1, +}; + +struct tegra_emc_regs { + uint32_t intstatus; /* 0x0 */ + uint32_t intmask; /* 0x4 */ + uint32_t dbg; /* 0x8 */ + uint32_t cfg; /* 0xc */ + uint32_t adr_cfg; /* 0x10 */ + uint32_t rsvd_0x14[3]; /* 0x14 */ + + uint32_t refctrl; /* 0x20 */ + uint32_t pin; /* 0x24 */ + uint32_t timing_control; /* 0x28 */ + uint32_t rc; /* 0x2c */ + uint32_t rfc; /* 0x30 */ + uint32_t ras; /* 0x34 */ + uint32_t rp; /* 0x38 */ + uint32_t r2w; /* 0x3c */ + uint32_t w2r; /* 0x40 */ + uint32_t r2p; /* 0x44 */ + uint32_t w2p; /* 0x48 */ + uint32_t rd_rcd; /* 0x4c */ + uint32_t wr_rcd; /* 0x50 */ + uint32_t rrd; /* 0x54 */ + uint32_t rext; /* 0x58 */ + uint32_t wdv; /* 0x5c */ + uint32_t quse; /* 0x60 */ + uint32_t qrst; /* 0x64 */ + uint32_t qsafe; /* 0x68 */ + uint32_t rdv; /* 0x6c */ + uint32_t refresh; /* 0x70 */ + uint32_t burst_refresh_num; /* 0x74 */ + uint32_t pdex2wr; /* 0x78 */ + uint32_t pdex2rd; /* 0x7c */ + uint32_t pchg2pden; /* 0x80 */ + uint32_t act2pden; /* 0x84 */ + uint32_t ar2pden; /* 0x88 */ + uint32_t rw2pden; /* 0x8c */ + uint32_t txsr; /* 0x90 */ + uint32_t tcke; /* 0x94 */ + uint32_t tfaw; /* 0x98 */ + uint32_t trpab; /* 0x9c */ + uint32_t tclkstable; /* 0xa0 */ + uint32_t tclkstop; /* 0xa4 */ + uint32_t trefbw; /* 0xa8 */ + uint32_t rsvd_0xac[1]; /* 0xac */ + uint32_t odt_write; /* 0xb0 */ + uint32_t odt_read; /* 0xb4 */ + uint32_t wext; /* 0xb8 */ + uint32_t ctt; /* 0xbc */ + uint32_t rfc_slr; /* 0xc0 */ + uint32_t mrs_wait_cnt2; /* 0xc4 */ + uint32_t mrs_wait_cnt; /* 0xc8 */ + uint32_t mrs; /* 0xcc */ + uint32_t emrs; /* 0xd0 */ + uint32_t ref; /* 0xd4 */ + uint32_t pre; /* 0xd8 */ + uint32_t nop; /* 0xdc */ + uint32_t self_ref; /* 0xe0 */ + uint32_t dpd; /* 0xe4 */ + uint32_t mrw; /* 0xe8 */ + uint32_t mrr; /* 0xec */ + uint32_t cmdq; /* 0xf0 */ + uint32_t mc2emcq; /* 0xf4 */ + uint32_t xm2dqspadctrl3; /* 0xf8 */ + uint32_t rsvd_0xfc[1]; /* 0xfc */ + uint32_t fbio_spare; /* 0x100 */ + uint32_t fbio_cfg5; /* 0x104 */ + uint32_t fbio_wrptr_eq_2; /* 0x108 */ + uint32_t rsvd_0x10c[2]; /* 0x10c */ + + uint32_t fbio_cfg6; /* 0x114 */ + uint32_t rsvd_0x118[2]; /* 0x118 */ + + uint32_t cfg_rsv; /* 0x120 */ + uint32_t acpd_control; /* 0x124 */ + uint32_t rsvd_0x128[1]; /* 0x128 */ + uint32_t emrs2; /* 0x12c */ + uint32_t emrs3; /* 0x130 */ + uint32_t mrw2; /* 0x134 */ + uint32_t mrw3; /* 0x138 */ + uint32_t mrw4; /* 0x13c */ + uint32_t clken_override; /* 0x140 */ + uint32_t r2r; /* 0x144 */ + uint32_t w2w; /* 0x148 */ + uint32_t einput; /* 0x14c */ + uint32_t einput_duration; /* 0x150 */ + uint32_t puterm_extra; /* 0x154 */ + uint32_t tckesr; /* 0x158 */ + uint32_t tpd; /* 0x15c */ + uint32_t rsvd_0x160[81]; /* 0x160 */ + + uint32_t auto_cal_config; /* 0x2a4 */ + uint32_t auto_cal_interval; /* 0x2a8 */ + uint32_t auto_cal_status; /* 0x2ac */ + uint32_t req_ctrl; /* 0x2b0 */ + uint32_t status; /* 0x2b4 */ + uint32_t cfg_2; /* 0x2b8 */ + uint32_t cfg_dig_dll; /* 0x2bc */ + uint32_t cfg_dig_dll_period; /* 0x2c0 */ + uint32_t rsvd_0x2c4[1]; /* 0x2c4 */ + uint32_t dig_dll_status; /* 0x2c8 */ + uint32_t rdv_mask; /* 0x2cc */ + uint32_t wdv_mask; /* 0x2d0 */ + uint32_t rsvd_0x2d4[1]; /* 0x2d4 */ + uint32_t ctt_duration; /* 0x2d8 */ + uint32_t ctt_term_ctrl; /* 0x2dc */ + uint32_t zcal_interval; /* 0x2e0 */ + uint32_t zcal_wait_cnt; /* 0x2e4 */ + uint32_t zcal_mrw_cmd; /* 0x2e8 */ + uint32_t zq_cal; /* 0x2ec */ + uint32_t xm2cmdpadctrl; /* 0x2f0 */ + uint32_t xm2cmdpadctrl2; /* 0x2f4 */ + uint32_t xm2dqspadctrl; /* 0x2f8 */ + uint32_t xm2dqspadctrl2; /* 0x2fc */ + uint32_t xm2dqpadctrl; /* 0x300 */ + uint32_t xm2dqpadctrl2; /* 0x304 */ + uint32_t xm2clkpadctrl; /* 0x308 */ + uint32_t xm2comppadctrl; /* 0x30c */ + uint32_t xm2vttgenpadctrl; /* 0x310 */ + uint32_t xm2vttgenpadctrl2; /* 0x314 */ + uint32_t xm2vttgenpadctrl3; /* 0x318 */ + uint32_t emcpaden; /* 0x31c */ + uint32_t xm2dqspadctrl4; /* 0x320 */ + uint32_t scratch0; /* 0x324 */ + uint32_t dll_xform_dqs0; /* 0x328 */ + uint32_t dll_xform_dqs1; /* 0x32c */ + uint32_t dll_xform_dqs2; /* 0x330 */ + uint32_t dll_xform_dqs3; /* 0x334 */ + uint32_t dll_xform_dqs4; /* 0x338 */ + uint32_t dll_xform_dqs5; /* 0x33c */ + uint32_t dll_xform_dqs6; /* 0x340 */ + uint32_t dll_xform_dqs7; /* 0x344 */ + uint32_t dll_xform_quse0; /* 0x348 */ + uint32_t dll_xform_quse1; /* 0x34c */ + uint32_t dll_xform_quse2; /* 0x350 */ + uint32_t dll_xform_quse3; /* 0x354 */ + uint32_t dll_xform_quse4; /* 0x358 */ + uint32_t dll_xform_quse5; /* 0x35c */ + uint32_t dll_xform_quse6; /* 0x360 */ + uint32_t dll_xform_quse7; /* 0x364 */ + uint32_t dll_xform_dq0; /* 0x368 */ + uint32_t dll_xform_dq1; /* 0x36c */ + uint32_t dll_xform_dq2; /* 0x370 */ + uint32_t dll_xform_dq3; /* 0x374 */ + uint32_t dli_rx_trim0; /* 0x378 */ + uint32_t dli_rx_trim1; /* 0x37c */ + uint32_t dli_rx_trim2; /* 0x380 */ + uint32_t dli_rx_trim3; /* 0x384 */ + uint32_t dli_rx_trim4; /* 0x388 */ + uint32_t dli_rx_trim5; /* 0x38c */ + uint32_t dli_rx_trim6; /* 0x390 */ + uint32_t dli_rx_trim7; /* 0x394 */ + uint32_t dli_tx_trim0; /* 0x398 */ + uint32_t dli_tx_trim1; /* 0x39c */ + uint32_t dli_tx_trim2; /* 0x3a0 */ + uint32_t dli_tx_trim3; /* 0x3a4 */ + uint32_t dli_trim_txdqs0; /* 0x3a8 */ + uint32_t dli_trim_txdqs1; /* 0x3ac */ + uint32_t dli_trim_txdqs2; /* 0x3b0 */ + uint32_t dli_trim_txdqs3; /* 0x3b4 */ + uint32_t dli_trim_txdqs4; /* 0x3b8 */ + uint32_t dli_trim_txdqs5; /* 0x3bc */ + uint32_t dli_trim_txdqs6; /* 0x3c0 */ + uint32_t dli_trim_txdqs7; /* 0x3c4 */ + uint32_t rsvd_0x3c8[1]; /* 0x3c8 */ + uint32_t stall_then_exe_after_clkchange; /* 0x3cc */ + uint32_t rsvd_0x3d0[1]; /* 0x3d0 */ + uint32_t auto_cal_clk_status; /* 0x3d4 */ + uint32_t sel_dpd_ctrl; /* 0x3d8 */ + uint32_t pre_refresh_req_cnt; /* 0x3dc */ + uint32_t dyn_self_ref_control; /* 0x3e0 */ + uint32_t txsrdll; /* 0x3e4 */ + uint32_t ccfifo_addr; /* 0x3e8 */ + uint32_t ccfifo_data; /* 0x3ec */ + uint32_t ccfifo_status; /* 0x3f0 */ + uint32_t cdb_cntl_1; /* 0x3f4 */ + uint32_t cdb_cntl_2; /* 0x3f8 */ + uint32_t xm2clkpadctrl2; /* 0x3fc */ + uint32_t swizzle_rank0_byte_cfg; /* 0x400 */ + uint32_t swizzle_rank0_byte0; /* 0x404 */ + uint32_t swizzle_rank0_byte1; /* 0x408 */ + uint32_t swizzle_rank0_byte2; /* 0x40c */ + uint32_t swizzle_rank0_byte3; /* 0x410 */ + uint32_t swizzle_rank1_byte_cfg; /* 0x414 */ + uint32_t swizzle_rank1_byte0; /* 0x418 */ + uint32_t swizzle_rank1_byte1; /* 0x41c */ + uint32_t swizzle_rank1_byte2; /* 0x420 */ + uint32_t swizzle_rank1_byte3; /* 0x424 */ + uint32_t ca_training_start; /* 0x428 */ + uint32_t ca_training_busy; /* 0x42c */ + uint32_t ca_training_cfg; /* 0x430 */ + uint32_t ca_training_timing_cntl1; /* 0x434 */ + uint32_t ca_training_timing_cntl2; /* 0x438 */ + uint32_t ca_training_ca_lead_in; /* 0x43c */ + uint32_t ca_training_ca; /* 0x440 */ + uint32_t ca_training_ca_lead_out; /* 0x444 */ + uint32_t ca_training_result1; /* 0x448 */ + uint32_t ca_training_result2; /* 0x44c */ + uint32_t ca_training_result3; /* 0x450 */ + uint32_t ca_training_result4; /* 0x454 */ + uint32_t auto_cal_config2; /* 0x458 */ + uint32_t auto_cal_config3; /* 0x45c */ + uint32_t auto_cal_status2; /* 0x460 */ + uint32_t xm2cmdpadctrl3; /* 0x464 */ + uint32_t ibdly; /* 0x468 */ + uint32_t dll_xform_addr0; /* 0x46c */ + uint32_t dll_xform_addr1; /* 0x470 */ + uint32_t dll_xform_addr2; /* 0x474 */ + uint32_t dli_addr_trim; /* 0x478 */ + uint32_t dsr_vttgen_drv; /* 0x47c */ + uint32_t txdsrvttgen; /* 0x480 */ + uint32_t xm2cmdpadctrl4; /* 0x484 */ + uint32_t xm2cmdpadctrl5; /* 0x488 */ + uint32_t rsvd_0x48c[5]; /* 0x48c */ + + uint32_t dll_xform_dqs8; /* 0x4a0 */ + uint32_t dll_xform_dqs9; /* 0x4a4 */ + uint32_t dll_xform_dqs10; /* 0x4a8 */ + uint32_t dll_xform_dqs11; /* 0x4ac */ + uint32_t dll_xform_dqs12; /* 0x4b0 */ + uint32_t dll_xform_dqs13; /* 0x4b4 */ + uint32_t dll_xform_dqs14; /* 0x4b8 */ + uint32_t dll_xform_dqs15; /* 0x4bc */ + uint32_t dll_xform_quse8; /* 0x4c0 */ + uint32_t dll_xform_quse9; /* 0x4c4 */ + uint32_t dll_xform_quse10; /* 0x4c8 */ + uint32_t dll_xform_quse11; /* 0x4cc */ + uint32_t dll_xform_quse12; /* 0x4d0 */ + uint32_t dll_xform_quse13; /* 0x4d4 */ + uint32_t dll_xform_quse14; /* 0x4d8 */ + uint32_t dll_xform_quse15; /* 0x4dc */ + uint32_t dll_xform_dq4; /* 0x4e0 */ + uint32_t dll_xform_dq5; /* 0x4e4 */ + uint32_t dll_xform_dq6; /* 0x4e8 */ + uint32_t dll_xform_dq7; /* 0x4ec */ + uint32_t rsvd_0x4f0[12]; /* 0x4f0 */ + + uint32_t dli_trim_txdqs8; /* 0x520 */ + uint32_t dli_trim_txdqs9; /* 0x524 */ + uint32_t dli_trim_txdqs10; /* 0x528 */ + uint32_t dli_trim_txdqs11; /* 0x52c */ + uint32_t dli_trim_txdqs12; /* 0x530 */ + uint32_t dli_trim_txdqs13; /* 0x534 */ + uint32_t dli_trim_txdqs14; /* 0x538 */ + uint32_t dli_trim_txdqs15; /* 0x53c */ + uint32_t cdb_cntl_3; /* 0x540 */ + uint32_t xm2dqspadctrl5; /* 0x544 */ + uint32_t xm2dqspadctrl6; /* 0x548 */ + uint32_t xm2dqpadctrl3; /* 0x54c */ + uint32_t dll_xform_addr3; /* 0x550 */ + uint32_t dll_xform_addr4; /* 0x554 */ + uint32_t dll_xform_addr5; /* 0x558 */ + uint32_t rsvd_0x55c[1]; /* 0x55c */ + uint32_t cfg_pipe; /* 0x560 */ + uint32_t qpop; /* 0x564 */ + uint32_t quse_width; /* 0x568 */ + uint32_t puterm_width; /* 0x56c */ + uint32_t bgbias_ctl0; /* 0x570 */ + uint32_t puterm_adj; /* 0x574 */ +} __attribute__((packed)); + +check_member(tegra_emc_regs, puterm_adj, 0x574); + +#endif /* __SOC_NVIDIA_TEGRA124_EMC_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index b3c0b29..5e55ee5 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -66,9 +66,9 @@ enum { TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, TEGRA_DVC_BASE = TEGRA_APB_MISC_BASE + 0xD000, TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, - TEGRA_EMC_BASE = TEGRA_APB_MISC_BASE + 0xF400, TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, TEGRA_MC_BASE = 0x70019000, + TEGRA_EMC_BASE = 0x7001B000, TEGRA_CSITE_BASE = 0x70040000, TEGRA_SYSCTR0_BASE = 0x700F0000, TEGRA_USBD_BASE = 0x7D000000, diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 3ec3608..89be88b 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -247,6 +247,9 @@ enum clock_source { /* Careful: Not true for all sources, always check TRM! */ int clock_get_osc_khz(void); void clock_early_uart(void); void clock_external_output(int clk_id); +void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, + u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, + u32 same_freq); void clock_cpu0_config_and_reset(void * entry); void clock_halt_avp(void); void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h index 27935d9..b764671 100644 --- a/src/soc/nvidia/tegra124/include/soc/display.h +++ b/src/soc/nvidia/tegra124/include/soc/display.h @@ -44,6 +44,9 @@ /* ardisplay_a.h */ #define DC_WIN_A_WIN_OPTIONS_0 0x700 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT 30 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD (0x1 << DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE (1) #define DC_WIN_A_BYTE_SWAP_0 0x701 #define DC_WIN_A_BUFFER_CONTROL_0 0x702 #define DC_WIN_A_COLOR_DEPTH_0 0x703 @@ -59,6 +62,7 @@ #define DC_WIN_A_BLEND_MATCH_SELECT_0 0x717 #define DC_WIN_A_BLEND_NOMATCH_SELECT_0 0x718 #define DC_WIN_A_BLEND_ALPHA_1BIT_0 0x719 +#define DC_WINBUF_A_START_ADDR_LO_0 0x800 #define DC_WINBUF_A_START_ADDR_HI_0 0x80d #define DC_WINBUF_A_ADDR_H_OFFSET_0 0x806 #define DC_WINBUF_A_ADDR_V_OFFSET_0 0x808 @@ -177,9 +181,18 @@ /* ardpaux.h */ #define DPAUX_DP_AUXDATA_READ_W0 0x19 +#define DP_LVDS_SHIFT 25 +#define DP_LVDS (1 << DP_LVDS_SHIFT) + +#define SRC_BPP 16 +#define COLORDEPTH 0x6 +#define COLOR_WHITE 0xFFFFFF + void setup_display(struct soc_nvidia_tegra124_config *config); void init_dca_regs(void); -void init_dpaux_regs(void); -void init_sor_regs(void); void dp_io_powerup(void); +u32 dp_setup_timing(u32 width, u32 height); +void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, + u32 lane_count, u32 enhanced_framing, u32 panel_edp, + u32 pclkfreq, u32 linkfreq); #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra124/lp0/Makefile b/src/soc/nvidia/tegra124/lp0/Makefile new file mode 100644 index 0000000..57680c5 --- /dev/null +++ b/src/soc/nvidia/tegra124/lp0/Makefile @@ -0,0 +1,58 @@ +################################################################################ +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +################################################################################ + +CC = $(GCC_PREFIX)gcc +NM = $(GCC_PREFIX)nm +OBJCOPY = $(GCC_PREFIX)objcopy + +OPENSSL = openssl +DD = dd +CP = cp +MV = mv +RM = rm + +SIGKEY = 00000000000000000000000000000000 + +.PHONY: all +all: tegra_lp0_resume.fw + +tegra_lp0_resume.elf: tegra_lp0_resume.ld tegra_lp0_resume.c + $(CC) -marm -march=armv4t -mno-unaligned-access -nostdlib -static \ + -Os -fpie -Wl,--build-id=none -ggdb3 -T tegra_lp0_resume.ld \ + -o $@ $(filter %.c,$+) + +tegra_lp0_resume.fw: tegra_lp0_resume.elf + @# Get rid of any files we're about to create. + $(RM) -f $@.nosig $@.sig $@.tosig + @# Convert the ELF image into a binary image. + $(OBJCOPY) -O binary $< $@.nosig + @# Extract the part of the binary which needs to be signed. + $(DD) bs=1 skip=544 if=$@.nosig of=$@.tosig + @# Calculate a signature for that part. + $(OPENSSL) dgst -mac cmac -macopt cipher:aes-128-cbc \ + -macopt hexkey:$(SIGKEY) -md5 -binary \ + $@.tosig > $@.sig + @# Inject the signature into the binary image's header. + $(DD) conv=notrunc bs=1 seek=272 count=16 if=$@.sig of=$@.nosig + @# Copy the signed binary to the target file name. + $(MV) $@.nosig $@ + +clean: + $(RM) -f tegra_lp0_resume.fw tegra_lp0_resume.fw.sig + $(RM) -f tegra_lp0_resume.fw.tosig tegra_lp0_resume.elf diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c new file mode 100644 index 0000000..72506c8 --- /dev/null +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -0,0 +1,627 @@ +/* + * Copyright 2014 Google Inc. + * Copyright 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <stdint.h> + +/* Function unit addresses. */ +enum { + UP_TAG_BASE = 0X60000000, + TIMER_BASE = 0X60005000, + CLK_RST_BASE = 0X60006000, + FLOW_CTLR_BASE = 0X60007000, + TEGRA_EVP_BASE = 0x6000f000, + PMC_CTLR_BASE = 0X7000e400, + MC_CTLR_BASE = 0X70019000, + SYSCTR_CTLR_BASE = 0X700f0000 +}; + + + +/* UP tag registers. */ +static uint32_t *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0); +enum { + UP_TAG_AVP = 0xaaaaaaaa +}; + + + +/* Timer registers. */ +static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); + + + +/* Clock and reset controller registers. */ +static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); +enum { + SWR_TRIG_SYS_RST = 0x1 << 2 +}; + +static uint32_t *clk_rst_cclk_burst_policy_ptr = (void *)(CLK_RST_BASE + 0x20); +enum { + CCLK_PLLP_BURST_POLICY = 0x20004444 +}; + +static uint32_t *clk_rst_super_cclk_div_ptr = (void *)(CLK_RST_BASE + 0x24); +enum { + SUPER_CDIV_ENB = 0x1 << 31 +}; + +static uint32_t *clk_rst_osc_ctrl_ptr = (void *)(CLK_RST_BASE + 0x50); +enum { + OSC_XOE = 0x1 << 0, + OSC_XOFS_SHIFT = 4, + OSC_XOFS_MASK = 0x3f << OSC_XOFS_SHIFT, + OSC_FREQ_SHIFT = 28, + OSC_FREQ_MASK = 0xf << OSC_FREQ_SHIFT +}; +enum { + OSC_FREQ_13 = 0, + OSC_FREQ_16P8 = 1, + OSC_FREQ_19P2 = 4, + OSC_FREQ_38P4 = 5, + OSC_FREQ_12 = 8, + OSC_FREQ_48 = 9, + OSC_FREQ_26 = 12 +}; + +static uint32_t *clk_rst_pllu_base_ptr = (void *)(CLK_RST_BASE + 0xc0); +enum { + PLLU_DIVM_SHIFT = 0, + PLLU_DIVN_SHIFT = 8, + PLLU_OVERRIDE = 0x1 << 24, + PLLU_ENABLE = 0x1 << 30, + PLLU_BYPASS = 0x1 << 31 +}; + +static uint32_t *clk_rst_pllu_misc_ptr = (void *)(CLK_RST_BASE + 0xcc); +enum { + PLLU_LFCON_SHIFT = 4, + PLLU_CPCON_SHIFT = 8, + PLLU_LOCK_ENABLE = 22 +}; + +static uint32_t *clk_rst_pllx_base_ptr = (void *)(CLK_RST_BASE + 0xe0); +enum { + PLLX_ENABLE = 0x1 << 30 +}; + +static uint32_t *clk_rst_rst_dev_u_clr_ptr = (void *)(CLK_RST_BASE + 0x314); +enum { + SWR_CSITE_RST = 0x1 << 9 +}; + +static uint32_t *clk_rst_clk_enb_l_set_ptr = (void *)(CLK_RST_BASE + 0x320); +enum { + CLK_ENB_CPU = 0x1 << 0 +}; + +static uint32_t *clk_rst_clk_out_enb_u_set_ptr = + (void *)(CLK_RST_BASE + 0x330); +enum { + CLK_ENB_CSITE = 0x1 << 9 +}; + +static uint32_t *clk_rst_cpu_softrst_ctrl2_ptr = + (void *)(CLK_RST_BASE + 0x388); +enum { + CAR2PMC_CPU_ACK_WIDTH_SHIFT = 0, + CAR2PMC_CPU_ACK_WIDTH_MASK = 0xfff << CAR2PMC_CPU_ACK_WIDTH_SHIFT +}; + +static uint32_t *clk_rst_clk_src_mselect_ptr = + (void *)(CLK_RST_BASE + 0x3b4); +enum { + MSELECT_CLK_DIV_SHIFT = 0, + MSELECT_CLK_SRC_SHIFT = 29, + MSELECT_CLK_SRC_PLLP_OUT0 = 0x0 << MSELECT_CLK_SRC_SHIFT, + MSELECT_CLK_SRC_PLLC2_OUT0 = 0x1 << MSELECT_CLK_SRC_SHIFT, + MSELECT_CLK_SRC_PLLC_OUT0 = 0x2 << MSELECT_CLK_SRC_SHIFT, + MSELECT_CLK_SRC_PLLC3_OUT0 = 0x3 << MSELECT_CLK_SRC_SHIFT +}; + +static uint32_t *clk_rst_rst_dev_v_clr_ptr = (void *)(CLK_RST_BASE + 0x434); +enum { + SWR_MSELECT_RST = 0x1 << 3 +}; + +static uint32_t *clk_rst_clk_enb_v_set_ptr = (void *)(CLK_RST_BASE + 0x440); +enum { + CLK_ENB_CPUG = 0x1 << 0, + CLK_ENB_CPULP = 0x1 << 1, + CLK_ENB_MSELECT = 0x1 << 3 +}; + +static uint32_t *clk_rst_rst_cpulp_cmplx_clr_ptr = + (void *)(CLK_RST_BASE + 0x45c); +static uint32_t *clk_rst_rst_cpug_cmplx_clr_ptr = + (void *)(CLK_RST_BASE + 0x454); +enum { + CLR_CPURESET0 = 0x1 << 0, + CLR_CPURESET1 = 0x1 << 1, + CLR_CPURESET2 = 0x1 << 2, + CLR_CPURESET3 = 0x1 << 3, + CLR_DBGRESET0 = 0x1 << 12, + CLR_DBGRESET1 = 0x1 << 13, + CLR_DBGRESET2 = 0x1 << 14, + CLR_DBGRESET3 = 0x1 << 15, + CLR_CORERESET0 = 0x1 << 16, + CLR_CORERESET1 = 0x1 << 17, + CLR_CORERESET2 = 0x1 << 18, + CLR_CORERESET3 = 0x1 << 19, + CLR_CXRESET0 = 0x1 << 20, + CLR_CXRESET1 = 0x1 << 21, + CLR_CXRESET2 = 0x1 << 22, + CLR_CXRESET3 = 0x1 << 23, + CLR_NONCPURESET = 0x1 << 29 +}; + + + +/* Reset vector. */ + +static uint32_t *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100); + + + +/* Flow controller registers. */ +static uint32_t *flow_ctlr_halt_cop_events_ptr = + (void *)(FLOW_CTLR_BASE + 0x4); +enum { + EVENT_MSEC = 0x1 << 24, + EVENT_JTAG = 0x1 << 28, + FLOW_MODE_SHIFT = 29, + FLOW_MODE_STOP = 2 << FLOW_MODE_SHIFT, +}; + +static uint32_t *flow_ctlr_cluster_control_ptr = + (void *)(FLOW_CTLR_BASE + 0x2c); +enum { + FLOW_CLUSTER_ACTIVE_LP = 0x1 << 0 +}; + + + +/* Power management controller registers. */ +enum { + PARTID_CRAIL = 0, + PARTID_CELP = 12, + PARTID_CE0 = 14, + PARTID_C0NC = 15, + PARTID_C1NC = 16 +}; + +static uint32_t *pmc_ctlr_clamp_status_ptr = (void *)(PMC_CTLR_BASE + 0x2c); + +static uint32_t *pmc_ctlr_pwrgate_toggle_ptr = (void *)(PMC_CTLR_BASE + 0x30); +enum { + PWRGATE_TOGGLE_START = 0x1 << 8 +}; + +static uint32_t *pmc_ctlr_pwrgate_status_ptr = (void *)(PMC_CTLR_BASE + 0x38); + +static uint32_t *pmc_ctlr_scratch4_ptr = (void *)(PMC_CTLR_BASE + 0x60); +enum { + PMC_SCRATCH4_LP = 0x1 << 31 +}; + +static uint32_t *pmc_ctlr_cpupwrgood_timer_ptr = + (void *)(PMC_CTLR_BASE + 0xc8); + +static uint32_t *pmc_ctlr_scratch41_ptr = (void *)(PMC_CTLR_BASE + 0x140); + +static uint32_t *pmc_ctlr_osc_edpd_over_ptr = (void *)(PMC_CTLR_BASE + 0x1a4); +enum { + PMC_XOFS_SHIFT = 1, + PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT +}; + + + +/* Memory controller registers. */ +static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c); + +static uint32_t *mc_video_protect_reg_ctrl_ptr = + (void *)(MC_CTLR_BASE + 0x650); +enum { + VIDEO_PROTECT_WRITE_ACCESS_DISABLE = 0x1 << 0, + VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS = 0x1 << 1 +}; + + + +/* System counter registers. */ +static uint32_t *sysctr_cntcr_ptr = (void *)(SYSCTR_CTLR_BASE + 0x0); +enum { + TSC_CNTCR_ENABLE = 0x1 << 0, + TSC_CNTCR_HDBG = 0x1 << 1 +}; + +static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20); + + + +/* Utility functions. */ + +static inline void __attribute__((always_inline)) + __attribute__((noreturn)) halt(void) +{ + for (;;); +} + +inline static uint32_t read32(const void *addr) +{ + return *(volatile uint32_t *)addr; +} + +inline static void write32(uint32_t val, void *addr) +{ + *(volatile uint32_t *)addr = val; +} + +inline static void setbits32(uint32_t bits, void *addr) +{ + write32(read32(addr) | bits, addr); +} + +inline static void clrbits32(uint32_t bits, void *addr) +{ + write32(read32(addr) & ~bits, addr); +} + +static void __attribute__((noreturn)) reset(void) +{ + write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr); + halt(); +} + +static void udelay(unsigned usecs) +{ + uint32_t start = read32(timer_us_ptr); + while (read32(timer_us_ptr) - start < usecs) + ; +} + + + +/* Accessors. */ + +static int wakeup_on_lp(void) +{ + return !!(read32(pmc_ctlr_scratch4_ptr) & PMC_SCRATCH4_LP); +} + +static uint32_t get_wakeup_vector(void) +{ + return read32(pmc_ctlr_scratch41_ptr); +} + +static unsigned get_osc_freq(void) +{ + return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; +} + + + +/* Clock configuration. */ + +static void config_oscillator(void) +{ + // Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy + // to OSC_CTRL.XOFS and set XOE. + uint32_t xofs = (read32(pmc_ctlr_osc_edpd_over_ptr) & + PMC_XOFS_MASK) >> PMC_XOFS_SHIFT; + + uint32_t osc_ctrl = read32(clk_rst_osc_ctrl_ptr); + osc_ctrl &= OSC_XOFS_MASK; + osc_ctrl |= (xofs << OSC_XOFS_SHIFT); + osc_ctrl |= OSC_XOE; + write32(osc_ctrl, clk_rst_osc_ctrl_ptr); +} + +static void config_pllu(void) +{ + // Figure out what parameters to use for PLLU. + uint32_t divm, divn, cpcon, lfcon; + switch (get_osc_freq()) { + case OSC_FREQ_12: + case OSC_FREQ_48: + divm = 0x0c; + divn = 0x3c0; + cpcon = 0x0c; + lfcon = 0x02; + break; + case OSC_FREQ_16P8: + divm = 0x07; + divn = 0x190; + cpcon = 0x05; + lfcon = 0x02; + break; + case OSC_FREQ_19P2: + case OSC_FREQ_38P4: + divm = 0x04; + divn = 0xc8; + cpcon = 0x03; + lfcon = 0x02; + break; + case OSC_FREQ_26: + divm = 0x1a; + divn = 0x3c0; + cpcon = 0x0c; + lfcon = 0x02; + break; + default: + // Map anything that's not recognized to 13MHz. + divm = 0x0d; + divn = 0x3c0; + cpcon = 0x0c; + lfcon = 0x02; + } + + // Configure PLLU. + uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE | + (divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT); + write32(base, clk_rst_pllu_base_ptr); + uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) | + (lfcon << PLLU_LFCON_SHIFT); + write32(misc, clk_rst_pllu_misc_ptr); + + // Enable PLLU. + base &= ~PLLU_BYPASS; + base |= PLLU_ENABLE; + write32(base, clk_rst_pllu_base_ptr); + misc |= PLLU_LOCK_ENABLE; + write32(misc, clk_rst_pllu_misc_ptr); +} + +static void config_tsc(void) +{ + // Tell the TSC the oscillator frequency. + switch (get_osc_freq()) { + case OSC_FREQ_12: + write32(12000000, sysctr_cntfid0_ptr); + break; + case OSC_FREQ_48: + write32(48000000, sysctr_cntfid0_ptr); + break; + case OSC_FREQ_16P8: + write32(16800000, sysctr_cntfid0_ptr); + break; + case OSC_FREQ_19P2: + write32(19200000, sysctr_cntfid0_ptr); + break; + case OSC_FREQ_38P4: + write32(38400000, sysctr_cntfid0_ptr); + break; + case OSC_FREQ_26: + write32(26000000, sysctr_cntfid0_ptr); + break; + default: + // Default to 13MHz. + write32(13000000, sysctr_cntfid0_ptr); + break; + } + + // Enable the TSC. + setbits32(TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG, sysctr_cntcr_ptr); +} + + + +/* Function unit configuration. */ + +static void config_core_sight(void) +{ + // Enable the CoreSight clock. + write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr); + + /* + * De-assert CoreSight reset. + * NOTE: We're leaving the CoreSight clock on the oscillator for + * now. It will be restored to its original clock source + * when the CPU-side restoration code runs. + */ + write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr); +} + +static void config_mselect(void) +{ + // Set MSELECT clock source to PLLP with 1:4 divider. + write32((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0, + clk_rst_clk_src_mselect_ptr); + + // Enable clock to MSELECT. + write32(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr); + + udelay(2); + + // Bring MSELECT out of reset. + write32(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr); +} + + + +/* Resets. */ + +static void clear_cpu_resets(void) +{ + // Take the non-cpu of the G and LP clusters out of reset. + write32(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr); + write32(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr); + + // Clear software controlled reset of the slow cluster. + write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0, + clk_rst_rst_cpulp_cmplx_clr_ptr); + + // Clear software controlled reset of the fast cluster. + write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | + CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | + CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | + CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3, + clk_rst_rst_cpug_cmplx_clr_ptr); +} + + + +/* Power. */ + +static void power_on_partition(unsigned id) +{ + uint32_t bit = 0x1 << id; + if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { + // Partition is not on. Turn it on. + write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr); + + // Wait until the partition is powerd on. + while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) + ; + + // Wait until clamp is off. + while (read32(pmc_ctlr_clamp_status_ptr) & bit) + ; + } +} + +static void power_on_main_cpu(void) +{ + /* + * Reprogram PMC_CPUPWRGOOD_TIMER register: + * + * XXX This is a fragile assumption. XXX + * The kernel prepares PMC_CPUPWRGOOD_TIMER based on a 32768Hz clock. + * Note that PMC_CPUPWRGOOD_TIMER is running at pclk. + * + * We need to reprogram PMC_CPUPWRGOOD_TIMER based on the current pclk + * which is at 408Mhz (pclk = sclk = pllp_out0) after reset. Multiply + * PMC_CPUPWRGOOD_TIMER by 408M / 32K. + * + * Save the original PMC_CPUPWRGOOD_TIMER register which we need to + * restore after the CPU is powered up. + */ + uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); + + write32(orig_timer * (408000000 / 32768), + pmc_ctlr_cpupwrgood_timer_ptr); + + if (wakeup_on_lp()) { + power_on_partition(PARTID_C1NC); + power_on_partition(PARTID_CELP); + } else { + power_on_partition(PARTID_CRAIL); + power_on_partition(PARTID_C0NC); + power_on_partition(PARTID_CE0); + } + + // Give I/O signals time to stablize. + write32(20 | EVENT_MSEC | FLOW_MODE_STOP, + flow_ctlr_halt_cop_events_ptr); + + // Restore the original PMC_CPUPWRGOOD_TIMER. + write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); +} + + + +/* Entry point. */ + +void lp0_resume(void) +{ + // If not on the AVP, reset. + if (read32(up_tag_ptr) != UP_TAG_AVP) + reset(); + + config_oscillator(); + + // Tell the flow controller which cluster to wake up. The default is + // the fast cluster. + if (wakeup_on_lp()) + setbits32(FLOW_CLUSTER_ACTIVE_LP, + flow_ctlr_cluster_control_ptr); + + // Program SUPER_CCLK_DIVIDER. + write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr); + + config_core_sight(); + + config_pllu(); + + // Set the CPU reset vector. + write32(get_wakeup_vector(), evp_cpu_reset_ptr); + + // Select CPU complex clock source. + write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr); + + config_mselect(); + + // Disable PLLX since it isn't used as CPU clock source. + clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr); + + // Set CAR2PMC_CPU_ACK_WIDTH to 408. + uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); + ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; + ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; + write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); + + // Enable the CPU complex clock. + write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); + write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); + + clear_cpu_resets(); + + config_tsc(); + + power_on_main_cpu(); + + // Disable VPR. + write32(0, mc_video_protect_size_mb_ptr); + write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, + mc_video_protect_reg_ctrl_ptr); + + // Halt the AVP. + while (1) + write32(FLOW_MODE_STOP | EVENT_JTAG, + flow_ctlr_halt_cop_events_ptr); +} + + + +/* Header. */ + +extern uint8_t blob_data; +extern uint8_t blob_data_size; +extern uint8_t blob_total_size; + +struct lp0_header { + uint32_t length_insecure; // Insecure total length. + uint32_t reserved[3]; + uint8_t rsa_modulus[256]; // RSA key modulus. + uint8_t aes_signature[16]; // AES signature. + uint8_t rsa_signature[256]; // RSA-PSS signature. + uint8_t random_aes_block[16]; // Random data, may be zero. + uint32_t length_secure; // Secure total length. + uint32_t destination; // Where to load the blob in iRAM. + uint32_t entry_point; // Entry point for the blob. + uint32_t code_length; // Length of just the data. +} __attribute__((packed)); + +struct lp0_header header __attribute__((section(".header"))) = +{ + .length_insecure = (uintptr_t)&blob_total_size, + .length_secure = (uintptr_t)&blob_total_size, + .destination = (uintptr_t)&blob_data, + .entry_point = (uintptr_t)&lp0_resume, + .code_length = (uintptr_t)&blob_data_size +}; diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld new file mode 100644 index 0000000..c4c508f --- /dev/null +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld @@ -0,0 +1,73 @@ +/* + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +PHDRS +{ + to_load PT_LOAD; +} + +ENTRY(lp0_resume) +SECTIONS +{ + . = 0x40020000 - 0x240; + + /* + * The lp0 blob header is built as a static data structure and put + * in the .header section. + */ + .header_start = .; + .header . : { + *(.header); + } : to_load = 0xff + .header_end = .; + + . = 0x40020000; + + /* The actual lp0 blob code. */ + .data_start = .; + .data . : { + *(.text); + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.data); + *(.data.*); + *(.bss); + *(.bss.*); + *(.sbss); + *(.sbss.*); + . = ALIGN(16); + } + .data_end = .; + + /* Some values we need in the header. */ + blob_data = .data_start; + blob_data_size = .data_end - .data_start; + blob_total_size = .data_end - .header_start; + + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.ARM.*) + } +} diff --git a/src/soc/nvidia/tegra124/mc.h b/src/soc/nvidia/tegra124/mc.h index 92a38ed..0fc3738 100644 --- a/src/soc/nvidia/tegra124/mc.h +++ b/src/soc/nvidia/tegra124/mc.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,34 +15,114 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef _TEGRA124_MC_H_ -#define _TEGRA124_MC_H_ +#ifndef __SOC_NVIDIA_TEGRA124_MC_H__ +#define __SOC_NVIDIA_TEGRA124_MC_H__ +#include <stddef.h> #include <stdint.h> // Memory Controller registers we need/care about struct tegra_mc_regs { - u32 reserved0[4]; - u32 mc_smmu_config; - u32 mc_smmu_tlb_config; - u32 mc_smmu_ptc_config; - u32 mc_smmu_ptb_asid; - u32 mc_smmu_ptb_data; - u32 reserved1[3]; - u32 mc_smmu_tlb_flush; - u32 mc_smmu_ptc_flush; - u32 reserved2[6]; - u32 mc_emem_cfg; - u32 mc_emem_adr_cfg; - u32 mc_emem_adr_cfg_dev0; - u32 mc_emem_adr_cfg_dev1; - u32 reserved3[12]; - u32 mc_emem_arb_reserved[28]; - u32 reserved4[338]; - u32 mc_vpr_bom; - u32 mc_vpr_size; - u32 mc_vpr_ctrl; + uint32_t rsvd_0x0[4]; /* 0x00 */ + uint32_t smmu_config; /* 0x10 */ + uint32_t smmu_tlb_config; /* 0x14 */ + uint32_t smmu_ptc_config; /* 0x18 */ + uint32_t smmu_ptb_asid; /* 0x1c */ + uint32_t smmu_ptb_data; /* 0x20 */ + uint32_t rsvd_0x24[3]; /* 0x24 */ + uint32_t smmu_tlb_flush; /* 0x30 */ + uint32_t smmu_ptc_flush; /* 0x34 */ + uint32_t rsvd_0x38[6]; /* 0x38 */ + uint32_t emem_cfg; /* 0x50 */ + uint32_t emem_adr_cfg; /* 0x54 */ + uint32_t emem_adr_cfg_dev0; /* 0x58 */ + uint32_t emem_adr_cfg_dev1; /* 0x5c */ + uint32_t rsvd_0x60[1]; /* 0x60 */ + uint32_t emem_adr_cfg_bank_mask_0; /* 0x64 */ + uint32_t emem_adr_cfg_bank_mask_1; /* 0x68 */ + uint32_t emem_adr_cfg_bank_mask_2; /* 0x6c */ + uint32_t rsvd_0x70[8]; /* 0x70 */ + uint32_t emem_arb_cfg; /* 0x90 */ + uint32_t emem_arb_outstanding_req; /* 0x94 */ + uint32_t emem_arb_timing_rcd; /* 0x98 */ + uint32_t emem_arb_timing_rp; /* 0x9c */ + uint32_t emem_arb_timing_rc; /* 0xa0 */ + uint32_t emem_arb_timing_ras; /* 0xa4 */ + uint32_t emem_arb_timing_faw; /* 0xa8 */ + uint32_t emem_arb_timing_rrd; /* 0xac */ + uint32_t emem_arb_timing_rap2pre; /* 0xb0 */ + uint32_t emem_arb_timing_wap2pre; /* 0xb4 */ + uint32_t emem_arb_timing_r2r; /* 0xb8 */ + uint32_t emem_arb_timing_w2w; /* 0xbc */ + uint32_t emem_arb_timing_r2w; /* 0xc0 */ + uint32_t emem_arb_timing_w2r; /* 0xc4 */ + uint32_t rsvd_0xc8[2]; /* 0xc8 */ + uint32_t emem_arb_da_turns; /* 0xd0 */ + uint32_t emem_arb_da_covers; /* 0xd4 */ + uint32_t emem_arb_misc0; /* 0xd8 */ + uint32_t emem_arb_misc1; /* 0xdc */ + uint32_t emem_arb_ring1_throttle; /* 0xe0 */ + uint32_t emem_arb_ring3_throttle; /* 0xe4 */ + uint32_t emem_arb_override; /* 0xe8 */ + uint32_t emem_arb_rsv; /* 0xec */ + uint32_t rsvd_0xf0[1]; /* 0xf0 */ + uint32_t clken_override; /* 0xf4 */ + uint32_t timing_control_dbg; /* 0xf8 */ + uint32_t timing_control; /* 0xfc */ + uint32_t stat_control; /* 0x100 */ + uint32_t rsvd_0x104[65]; /* 0x104 */ + uint32_t emem_arb_isochronous_0; /* 0x208 */ + uint32_t emem_arb_isochronous_1; /* 0x20c */ + uint32_t emem_arb_isochronous_2; /* 0x210 */ + uint32_t rsvd_0x214[38]; /* 0x214 */ + uint32_t dis_extra_snap_levels; /* 0x2ac */ + uint32_t rsvd_0x2b0[90]; /* 0x2b0 */ + uint32_t video_protect_vpr_override; /* 0x418 */ + uint32_t rsvd_0x41c[93]; /* 0x41c */ + uint32_t video_protect_vpr_override1; /* 0x590 */ + uint32_t rsvd_0x594[29]; /* 0x594 */ + uint32_t display_snap_ring; /* 0x608 */ + uint32_t rsvd_0x60c[15]; /* 0x60c */ + uint32_t video_protect_bom; /* 0x648 */ + uint32_t video_protect_size_mb; /* 0x64c */ + uint32_t video_protect_reg_ctrl; /* 0x650 */ + uint32_t rsvd_0x654[4]; /* 0x654 */ + uint32_t emem_cfg_access_ctrl; /* 0x664 */ + uint32_t rsvd_0x668[2]; /* 0x668 */ + uint32_t sec_carveout_bom; /* 0x670 */ + uint32_t sec_carveout_size_mb; /* 0x674 */ + uint32_t sec_carveout_reg_ctrl; /* 0x678 */ + uint32_t rsvd_0x67c[187]; /* 0x67c */ + uint32_t emem_arb_override_1; /* 0x968 */ + uint32_t rsvd_0x96c[3]; /* 0x96c */ + uint32_t video_protect_bom_adr_hi; /* 0x978 */ + uint32_t rsvd_0x97c[2]; /* 0x97c */ + uint32_t video_protect_gpu_override_0; /* 0x984 */ + uint32_t video_protect_gpu_override_1; /* 0x988 */ + uint32_t rsvd_0x98c[5]; /* 0x98c */ + uint32_t mts_carveout_bom; /* 0x9a0 */ + uint32_t mts_carveout_size_mb; /* 0x9a4 */ + uint32_t mts_carveout_adr_hi; /* 0x9a8 */ + uint32_t mts_carveout_reg_ctrl; /* 0x9ac */ + uint32_t rsvd_0x9b0[4]; /* 0x9b0 */ + uint32_t emem_bank_swizzle_cfg0; /* 0x9c0 */ + uint32_t emem_bank_swizzle_cfg1; /* 0x9c4 */ + uint32_t emem_bank_swizzle_cfg2; /* 0x9c8 */ + uint32_t emem_bank_swizzle_cfg3; /* 0x9cc */ + uint32_t rsvd_0x9d0[1]; /* 0x9d0 */ + uint32_t sec_carveout_adr_hi; /* 0x9d4 */ }; -#endif /* _TEGRA124_MC_H_ */ +enum { + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27, + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27, + + MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1, + + MC_TIMING_CONTROL_TIMING_UPDATE = 1, +}; + +check_member(tegra_mc_regs, sec_carveout_adr_hi, 0x9d4); + +#endif /* __SOC_NVIDIA_TEGRA124_MC_H__ */ diff --git a/src/soc/nvidia/tegra124/pmc.h b/src/soc/nvidia/tegra124/pmc.h index f88e253..2dfdaad 100644 --- a/src/soc/nvidia/tegra124/pmc.h +++ b/src/soc/nvidia/tegra124/pmc.h @@ -62,10 +62,36 @@ struct tegra_pmc_regs { u32 no_iopower; u32 pwr_det; u32 pwr_det_latch; - u32 scratch[20]; + u32 scratch0; + u32 scratch1; + u32 scratch2; + u32 scratch3; + u32 scratch4; + u32 scratch5; + u32 scratch6; + u32 scratch7; + u32 scratch8; + u32 scratch9; + u32 scratch10; + u32 scratch11; + u32 scratch12; + u32 scratch13; + u32 scratch14; + u32 scratch15; + u32 scratch16; + u32 scratch17; + u32 scratch18; + u32 scratch19; u32 odmdata; - u32 scratch21[24 - 21]; - u32 secure_scratch[6]; + u32 scratch21; + u32 scratch22; + u32 scratch23; + u32 secure_scratch0; + u32 secure_scratch1; + u32 secure_scratch2; + u32 secure_scratch3; + u32 secure_scratch4; + u32 secure_scratch5; u32 cpupwrgood_timer; u32 cpupwroff_timer; u32 pg_mask; @@ -79,7 +105,25 @@ struct tegra_pmc_regs { u32 usb_a0; u32 crypto_op; u32 pllp_wb0_override; - u32 scratch24[43 - 24]; + u32 scratch24; + u32 scratch25; + u32 scratch26; + u32 scratch27; + u32 scratch28; + u32 scratch29; + u32 scratch30; + u32 scratch31; + u32 scratch32; + u32 scratch33; + u32 scratch34; + u32 scratch35; + u32 scratch36; + u32 scratch37; + u32 scratch38; + u32 scratch39; + u32 scratch40; + u32 scratch41; + u32 scratch42; u32 bondout_mirror[3]; u32 sys_33v_en; u32 bondout_mirror_access; @@ -124,9 +168,24 @@ struct tegra_pmc_regs { u32 utmip_uhsic_status; u32 utmip_uhsic_fake; u32 bondout_mirror3[5 - 3]; - u32 secure_scratch6[8 - 6]; - u32 scratch43[56 - 43]; - u32 scratch_eco[3]; + u32 secure_scratch6; + u32 secure_scratch7; + u32 scratch43; + u32 scratch44; + u32 scratch45; + u32 scratch46; + u32 scratch47; + u32 scratch48; + u32 scratch49; + u32 scratch50; + u32 scratch51; + u32 scratch52; + u32 scratch53; + u32 scratch54; + u32 scratch55; + u32 scratch0_eco; + u32 por_dpd_ctrl; + u32 scratch2_eco; u32 utmip_uhsic_line_wakeup; u32 utmip_bias_master_cntrl; u32 utmip_master_config; @@ -153,10 +212,108 @@ struct tegra_pmc_regs { u32 reg_short; u32 pg_mask_andor; u8 _rsv1[0x2c]; - u32 secure_scratch8[24 - 8]; - u32 scratch56[120 - 56]; + u32 secure_scratch8; + u32 secure_scratch9; + u32 secure_scratch10; + u32 secure_scratch11; + u32 secure_scratch12; + u32 secure_scratch13; + u32 secure_scratch14; + u32 secure_scratch15; + u32 secure_scratch16; + u32 secure_scratch17; + u32 secure_scratch18; + u32 secure_scratch19; + u32 secure_scratch20; + u32 secure_scratch21; + u32 secure_scratch22; + u32 secure_scratch23; + u32 secure_scratch24; + u32 secure_scratch25; + u32 secure_scratch26; + u32 secure_scratch27; + u32 secure_scratch28; + u32 secure_scratch29; + u32 secure_scratch30; + u32 secure_scratch31; + u32 secure_scratch32; + u32 secure_scratch33; + u32 secure_scratch34; + u32 secure_scratch35; + u8 _rsv2[0xd0]; + u32 cntrl2; + u8 _rsv3[0x18]; + u32 io_dpd3_req; + u32 io_dqd3_status; + u32 strapping_opt_a; + u8 _rsv4[0x198]; + u32 scratch56; + u32 scratch57; + u32 scratch58; + u32 scratch59; + u32 scratch60; + u32 scratch61; + u32 scratch62; + u32 scratch63; + u32 scratch64; + u32 scratch65; + u32 scratch66; + u32 scratch67; + u32 scratch68; + u32 scratch69; + u32 scratch70; + u32 scratch71; + u32 scratch72; + u32 scratch73; + u32 scratch74; + u32 scratch75; + u32 scratch76; + u32 scratch77; + u32 scratch78; + u32 scratch79; + u32 scratch80; + u32 scratch81; + u32 scratch82; + u32 scratch83; + u32 scratch84; + u32 scratch85; + u32 scratch86; + u32 scratch87; + u32 scratch88; + u32 scratch89; + u32 scratch90; + u32 scratch91; + u32 scratch92; + u32 scratch93; + u32 scratch94; + u32 scratch95; + u32 scratch96; + u32 scratch97; + u32 scratch98; + u32 scratch99; + u32 scratch100; + u32 scratch101; + u32 scratch102; + u32 scratch103; + u32 scratch104; + u32 scratch105; + u32 scratch106; + u32 scratch107; + u32 scratch108; + u32 scratch109; + u32 scratch110; + u32 scratch111; + u32 scratch112; + u32 scratch113; + u32 scratch114; + u32 scratch115; + u32 scratch116; + u32 scratch117; + u32 scratch118; + u32 scratch119; }; -check_member(tegra_pmc_regs, scratch56, 0x340); + +check_member(tegra_pmc_regs, scratch119, 0x6fc); enum { PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f, @@ -191,6 +348,29 @@ enum { }; enum { + PMC_DDR_PWR_EMMC_MASK = 1 << 1, + PMC_DDR_PWR_VAL_MASK = 1 << 0, +}; + +enum { + PMC_DDR_CFG_PKG_MASK = 1 << 0, + PMC_DDR_CFG_IF_MASK = 1 << 1, + PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12, + PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13, +}; + +enum { + PMC_NO_IOPOWER_MEM_MASK = 1 << 7, + PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16, +}; + +enum { + PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0, + PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1, + PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31, +}; + +enum { PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12 }; @@ -200,4 +380,10 @@ enum { 0x3f << PMC_OSC_EDPD_OVER_XOFS_SHIFT }; +enum { + PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT = 4, + PMC_STRAPPING_OPT_A_RAM_CODE_MASK = + 0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT, +}; + #endif /* _TEGRA124_PMC_H_ */ diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c new file mode 100644 index 0000000..283cbf4 --- /dev/null +++ b/src/soc/nvidia/tegra124/sdram.c @@ -0,0 +1,611 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/clock.h> + +#include "emc.h" +#include "mc.h" +#include "pmc.h" +#include "sdram.h" + +static void sdram_patch(uintptr_t addr, uint32_t value) +{ + if (addr) + writel(value, (uint32_t*)addr); +} + +static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) +{ + clrsetbits_le32(addr, mask, (value & mask)); +} + +/* PMC must be configured before clock-enable and de-reset of MC/EMC. */ +static void sdram_configure_pmc(const struct sdram_params *param, + struct tegra_pmc_regs *regs) +{ + /* VDDP Select */ + writel(param->PmcVddpSel, &regs->vddp_sel); + udelay(param->PmcVddpSelWait); + + /* Set DDR pad voltage */ + writebits(param->PmcDdrPwr, &regs->ddr_pwr, PMC_DDR_PWR_VAL_MASK); + + /* Set package and DPD pad control */ + writebits(param->PmcDdrCfg, &regs->ddr_cfg, + (PMC_DDR_CFG_PKG_MASK | PMC_DDR_CFG_IF_MASK | + PMC_DDR_CFG_XM0_RESET_TRI_MASK | + PMC_DDR_CFG_XM0_RESET_DPDIO_MASK)); + + /* Turn on MEM IO Power */ + writebits(param->PmcNoIoPower, &regs->no_iopower, + (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK)); + + writel(param->PmcRegShort, &regs->reg_short); +} + +static void sdram_start_clocks(const struct sdram_params *param) +{ + u32 is_same_freq = (param->McEmemArbMisc0 & + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK) ? 1 : 0; + + clock_sdram(param->PllMInputDivider, param->PllMFeedbackDivider, + param->PllMSelectDiv2, param->PllMSetupControl, + param->PllMPDLshiftPh45, param->PllMPDLshiftPh90, + param->PllMPDLshiftPh135, param->PllMKVCO, + param->PllMKCP, param->PllMStableTime, + param->EmcClockSource, is_same_freq); +} + +static void sdram_deassert_clock_enable_signal(const struct sdram_params *param, + struct tegra_pmc_regs *regs) +{ + clrbits_le32(&regs->por_dpd_ctrl, + PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK); + udelay(param->PmcPorDpdCtrlWait); +} + +static void sdram_deassert_sel_dpd(const struct sdram_params *param, + struct tegra_pmc_regs *regs) +{ + clrbits_le32(&regs->por_dpd_ctrl, + (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK | + PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK)); + /* + * Note NVIDIA recommended to always do 10us delay here and ignore + * BCT.PmcPorDpdCtrlWait. + * */ + udelay(10); +} + +static void sdram_set_swizzle(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + writel(param->EmcSwizzleRank0ByteCfg, &regs->swizzle_rank0_byte_cfg); + writel(param->EmcSwizzleRank0Byte0, &regs->swizzle_rank0_byte0); + writel(param->EmcSwizzleRank0Byte1, &regs->swizzle_rank0_byte1); + writel(param->EmcSwizzleRank0Byte2, &regs->swizzle_rank0_byte2); + writel(param->EmcSwizzleRank0Byte3, &regs->swizzle_rank0_byte3); + writel(param->EmcSwizzleRank1ByteCfg, &regs->swizzle_rank1_byte_cfg); + writel(param->EmcSwizzleRank1Byte0, &regs->swizzle_rank1_byte0); + writel(param->EmcSwizzleRank1Byte1, &regs->swizzle_rank1_byte1); + writel(param->EmcSwizzleRank1Byte2, &regs->swizzle_rank1_byte2); + writel(param->EmcSwizzleRank1Byte3, &regs->swizzle_rank1_byte3); +} + +static void sdram_set_pad_controls(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Program the pad controls */ + writel(param->EmcXm2CmdPadCtrl, &regs->xm2cmdpadctrl); + writel(param->EmcXm2CmdPadCtrl2, &regs->xm2cmdpadctrl2); + writel(param->EmcXm2CmdPadCtrl3, &regs->xm2cmdpadctrl3); + writel(param->EmcXm2CmdPadCtrl4, &regs->xm2cmdpadctrl4); + writel(param->EmcXm2CmdPadCtrl5, &regs->xm2cmdpadctrl5); + + writel(param->EmcXm2DqsPadCtrl, &regs->xm2dqspadctrl); + writel(param->EmcXm2DqsPadCtrl2, &regs->xm2dqspadctrl2); + writel(param->EmcXm2DqsPadCtrl3, &regs->xm2dqspadctrl3); + writel(param->EmcXm2DqsPadCtrl4, &regs->xm2dqspadctrl4); + writel(param->EmcXm2DqsPadCtrl5, &regs->xm2dqspadctrl5); + writel(param->EmcXm2DqsPadCtrl6, &regs->xm2dqspadctrl6); + + writel(param->EmcXm2DqPadCtrl, &regs->xm2dqpadctrl); + writel(param->EmcXm2DqPadCtrl2, &regs->xm2dqpadctrl2); + writel(param->EmcXm2DqPadCtrl3, &regs->xm2dqpadctrl3); + + writel(param->EmcXm2ClkPadCtrl, &regs->xm2clkpadctrl); + writel(param->EmcXm2ClkPadCtrl2, &regs->xm2clkpadctrl2); + + writel(param->EmcXm2CompPadCtrl, &regs->xm2comppadctrl); + + writel(param->EmcXm2VttGenPadCtrl, &regs->xm2vttgenpadctrl); + writel(param->EmcXm2VttGenPadCtrl2, &regs->xm2vttgenpadctrl2); + writel(param->EmcXm2VttGenPadCtrl3, &regs->xm2vttgenpadctrl3); + + writel(param->EmcCttTermCtrl, &regs->ctt_term_ctrl); +} + +static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) +{ + writel(EMC_TIMING_CONTROL_TIMING_UPDATE, &regs->timing_control); +} + +static void sdram_init_mc(const struct sdram_params *param, + struct tegra_mc_regs *regs) +{ + /* Initialize MC VPR settings */ + writel(param->McDisplaySnapRing, &regs->display_snap_ring); + writel(param->McVideoProtectBom, &regs->video_protect_bom); + writel(param->McVideoProtectBomAdrHi, &regs->video_protect_bom_adr_hi); + writel(param->McVideoProtectSizeMb, &regs->video_protect_size_mb); + writel(param->McVideoProtectVprOverride, + &regs->video_protect_vpr_override); + writel(param->McVideoProtectVprOverride1, + &regs->video_protect_vpr_override1); + writel(param->McVideoProtectGpuOverride0, + &regs->video_protect_gpu_override_0); + writel(param->McVideoProtectGpuOverride1, + &regs->video_protect_gpu_override_1); + + /* Program SDRAM geometry paarameters */ + writel(param->McEmemAdrCfg, &regs->emem_adr_cfg); + writel(param->McEmemAdrCfgDev0, &regs->emem_adr_cfg_dev0); + writel(param->McEmemAdrCfgDev1, &regs->emem_adr_cfg_dev1); + + /* Program bank swizzling */ + writel(param->McEmemAdrCfgBankMask0, &regs->emem_bank_swizzle_cfg0); + writel(param->McEmemAdrCfgBankMask1, &regs->emem_bank_swizzle_cfg1); + writel(param->McEmemAdrCfgBankMask2, &regs->emem_bank_swizzle_cfg2); + writel(param->McEmemAdrCfgBankSwizzle3, &regs->emem_bank_swizzle_cfg3); + + /* Program external memory aperature (base and size) */ + writel(param->McEmemCfg, &regs->emem_cfg); + + /* Program SEC carveout (base and size) */ + writel(param->McSecCarveoutBom, &regs->sec_carveout_bom); + writel(param->McSecCarveoutAdrHi, &regs->sec_carveout_adr_hi); + writel(param->McSecCarveoutSizeMb, &regs->sec_carveout_size_mb); + + /* Program MTS carveout (base and size) */ + writel(param->McMtsCarveoutBom, &regs->mts_carveout_bom); + writel(param->McMtsCarveoutAdrHi, &regs->mts_carveout_adr_hi); + writel(param->McMtsCarveoutSizeMb, &regs->mts_carveout_size_mb); + + /* Program the memory arbiter */ + writel(param->McEmemArbCfg, &regs->emem_arb_cfg); + writel(param->McEmemArbOutstandingReq, &regs->emem_arb_outstanding_req); + writel(param->McEmemArbTimingRcd, &regs->emem_arb_timing_rcd); + writel(param->McEmemArbTimingRp, &regs->emem_arb_timing_rp); + writel(param->McEmemArbTimingRc, &regs->emem_arb_timing_rc); + writel(param->McEmemArbTimingRas, &regs->emem_arb_timing_ras); + writel(param->McEmemArbTimingFaw, &regs->emem_arb_timing_faw); + writel(param->McEmemArbTimingRrd, &regs->emem_arb_timing_rrd); + writel(param->McEmemArbTimingRap2Pre, &regs->emem_arb_timing_rap2pre); + writel(param->McEmemArbTimingWap2Pre, &regs->emem_arb_timing_wap2pre); + writel(param->McEmemArbTimingR2R, &regs->emem_arb_timing_r2r); + writel(param->McEmemArbTimingW2W, &regs->emem_arb_timing_w2w); + writel(param->McEmemArbTimingR2W, &regs->emem_arb_timing_r2w); + writel(param->McEmemArbTimingW2R, &regs->emem_arb_timing_w2r); + writel(param->McEmemArbDaTurns, &regs->emem_arb_da_turns); + writel(param->McEmemArbDaCovers, &regs->emem_arb_da_covers); + writel(param->McEmemArbMisc0, &regs->emem_arb_misc0); + writel(param->McEmemArbMisc1, &regs->emem_arb_misc1); + writel(param->McEmemArbRing1Throttle, &regs->emem_arb_ring1_throttle); + writel(param->McEmemArbOverride, &regs->emem_arb_override); + writel(param->McEmemArbOverride1, &regs->emem_arb_override_1); + writel(param->McEmemArbRsv, &regs->emem_arb_rsv); + + /* Program extra snap levels for display client */ + writel(param->McDisExtraSnapLevels, &regs->dis_extra_snap_levels); + + /* Trigger MC timing update */ + writel(MC_TIMING_CONTROL_TIMING_UPDATE, &regs->timing_control); + + /* Program second-level clock enable overrides */ + writel(param->McClkenOverride, &regs->clken_override); + + /* Program statistics gathering */ + writel(param->McStatControl, &regs->stat_control); +} + +static void sdram_init_emc(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Program SDRAM geometry parameters */ + writel(param->EmcAdrCfg, &regs->adr_cfg); + + /* Program second-level clock enable overrides */ + writel(param->EmcClkenOverride, &regs->clken_override); + + /* Program EMC pad auto calibration */ + writel(param->EmcAutoCalInterval, &regs->auto_cal_interval); + writel(param->EmcAutoCalConfig2, &regs->auto_cal_config2); + writel(param->EmcAutoCalConfig3, &regs->auto_cal_config3); + writel(param->EmcAutoCalConfig, &regs->auto_cal_config); + udelay(param->EmcAutoCalWait); +} + +static void sdram_set_emc_timing(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Program EMC timing configuration */ + writel(param->EmcCfg2, &regs->cfg_2); + writel(param->EmcCfgPipe, &regs->cfg_pipe); + writel(param->EmcDbg, &regs->dbg); + writel(param->EmcCmdQ, &regs->cmdq); + writel(param->EmcMc2EmcQ, &regs->mc2emcq); + writel(param->EmcMrsWaitCnt, &regs->mrs_wait_cnt); + writel(param->EmcMrsWaitCnt2, &regs->mrs_wait_cnt2); + writel(param->EmcFbioCfg5, &regs->fbio_cfg5); + writel(param->EmcRc, &regs->rc); + writel(param->EmcRfc, &regs->rfc); + writel(param->EmcRfcSlr, &regs->rfc_slr); + writel(param->EmcRas, &regs->ras); + writel(param->EmcRp, &regs->rp); + writel(param->EmcR2r, &regs->r2r); + writel(param->EmcW2w, &regs->w2w); + writel(param->EmcR2w, &regs->r2w); + writel(param->EmcW2r, &regs->w2r); + writel(param->EmcR2p, &regs->r2p); + writel(param->EmcW2p, &regs->w2p); + writel(param->EmcRdRcd, &regs->rd_rcd); + writel(param->EmcWrRcd, &regs->wr_rcd); + writel(param->EmcRrd, &regs->rrd); + writel(param->EmcRext, &regs->rext); + writel(param->EmcWext, &regs->wext); + writel(param->EmcWdv, &regs->wdv); + writel(param->EmcWdvMask, &regs->wdv_mask); + writel(param->EmcQUse, &regs->quse); + writel(param->EmcQuseWidth, &regs->quse_width); + writel(param->EmcIbdly, &regs->ibdly); + writel(param->EmcEInput, &regs->einput); + writel(param->EmcEInputDuration, &regs->einput_duration); + writel(param->EmcPutermExtra, &regs->puterm_extra); + writel(param->EmcPutermWidth, &regs->puterm_width); + writel(param->EmcPutermAdj, &regs->puterm_adj); + writel(param->EmcCdbCntl1, &regs->cdb_cntl_1); + writel(param->EmcCdbCntl2, &regs->cdb_cntl_2); + writel(param->EmcCdbCntl3, &regs->cdb_cntl_3); + writel(param->EmcQRst, &regs->qrst); + writel(param->EmcQSafe, &regs->qsafe); + writel(param->EmcRdv, &regs->rdv); + writel(param->EmcRdvMask, &regs->rdv_mask); + writel(param->EmcQpop, &regs->qpop); + writel(param->EmcCtt, &regs->ctt); + writel(param->EmcCttDuration, &regs->ctt_duration); + writel(param->EmcRefresh, &regs->refresh); + writel(param->EmcBurstRefreshNum, &regs->burst_refresh_num); + writel(param->EmcPreRefreshReqCnt, &regs->pre_refresh_req_cnt); + writel(param->EmcPdEx2Wr, &regs->pdex2wr); + writel(param->EmcPdEx2Rd, &regs->pdex2rd); + writel(param->EmcPChg2Pden, &regs->pchg2pden); + writel(param->EmcAct2Pden, &regs->act2pden); + writel(param->EmcAr2Pden, &regs->ar2pden); + writel(param->EmcRw2Pden, &regs->rw2pden); + writel(param->EmcTxsr, &regs->txsr); + writel(param->EmcTxsrDll, &regs->txsrdll); + writel(param->EmcTcke, &regs->tcke); + writel(param->EmcTckesr, &regs->tckesr); + writel(param->EmcTpd, &regs->tpd); + writel(param->EmcTfaw, &regs->tfaw); + writel(param->EmcTrpab, &regs->trpab); + writel(param->EmcTClkStable, &regs->tclkstable); + writel(param->EmcTClkStop, &regs->tclkstop); + writel(param->EmcTRefBw, &regs->trefbw); + writel(param->EmcOdtWrite, &regs->odt_write); + writel(param->EmcOdtRead, &regs->odt_read); + writel(param->EmcFbioCfg6, &regs->fbio_cfg6); + writel(param->EmcCfgDigDll, &regs->cfg_dig_dll); + writel(param->EmcCfgDigDllPeriod, &regs->cfg_dig_dll_period); + + /* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */ + writel(param->EmcFbioSpare & 0xfffffffd, &regs->fbio_spare); + + writel(param->EmcCfgRsv, &regs->cfg_rsv); + writel(param->EmcDllXformDqs0, &regs->dll_xform_dqs0); + writel(param->EmcDllXformDqs1, &regs->dll_xform_dqs1); + writel(param->EmcDllXformDqs2, &regs->dll_xform_dqs2); + writel(param->EmcDllXformDqs3, &regs->dll_xform_dqs3); + writel(param->EmcDllXformDqs4, &regs->dll_xform_dqs4); + writel(param->EmcDllXformDqs5, &regs->dll_xform_dqs5); + writel(param->EmcDllXformDqs6, &regs->dll_xform_dqs6); + writel(param->EmcDllXformDqs7, &regs->dll_xform_dqs7); + writel(param->EmcDllXformDqs8, &regs->dll_xform_dqs8); + writel(param->EmcDllXformDqs9, &regs->dll_xform_dqs9); + writel(param->EmcDllXformDqs10, &regs->dll_xform_dqs10); + writel(param->EmcDllXformDqs11, &regs->dll_xform_dqs11); + writel(param->EmcDllXformDqs12, &regs->dll_xform_dqs12); + writel(param->EmcDllXformDqs13, &regs->dll_xform_dqs13); + writel(param->EmcDllXformDqs14, &regs->dll_xform_dqs14); + writel(param->EmcDllXformDqs15, &regs->dll_xform_dqs15); + writel(param->EmcDllXformQUse0, &regs->dll_xform_quse0); + writel(param->EmcDllXformQUse1, &regs->dll_xform_quse1); + writel(param->EmcDllXformQUse2, &regs->dll_xform_quse2); + writel(param->EmcDllXformQUse3, &regs->dll_xform_quse3); + writel(param->EmcDllXformQUse4, &regs->dll_xform_quse4); + writel(param->EmcDllXformQUse5, &regs->dll_xform_quse5); + writel(param->EmcDllXformQUse6, &regs->dll_xform_quse6); + writel(param->EmcDllXformQUse7, &regs->dll_xform_quse7); + writel(param->EmcDllXformQUse8, &regs->dll_xform_quse8); + writel(param->EmcDllXformQUse9, &regs->dll_xform_quse9); + writel(param->EmcDllXformQUse10, &regs->dll_xform_quse10); + writel(param->EmcDllXformQUse11, &regs->dll_xform_quse11); + writel(param->EmcDllXformQUse12, &regs->dll_xform_quse12); + writel(param->EmcDllXformQUse13, &regs->dll_xform_quse13); + writel(param->EmcDllXformQUse14, &regs->dll_xform_quse14); + writel(param->EmcDllXformQUse15, &regs->dll_xform_quse15); + writel(param->EmcDllXformDq0, &regs->dll_xform_dq0); + writel(param->EmcDllXformDq1, &regs->dll_xform_dq1); + writel(param->EmcDllXformDq2, &regs->dll_xform_dq2); + writel(param->EmcDllXformDq3, &regs->dll_xform_dq3); + writel(param->EmcDllXformDq4, &regs->dll_xform_dq4); + writel(param->EmcDllXformDq5, &regs->dll_xform_dq5); + writel(param->EmcDllXformDq6, &regs->dll_xform_dq6); + writel(param->EmcDllXformDq7, &regs->dll_xform_dq7); + writel(param->EmcDllXformAddr0, &regs->dll_xform_addr0); + writel(param->EmcDllXformAddr1, &regs->dll_xform_addr1); + writel(param->EmcDllXformAddr2, &regs->dll_xform_addr2); + writel(param->EmcDllXformAddr3, &regs->dll_xform_addr3); + writel(param->EmcDllXformAddr4, &regs->dll_xform_addr4); + writel(param->EmcDllXformAddr5, &regs->dll_xform_addr5); + writel(param->EmcAcpdControl, &regs->acpd_control); + writel(param->EmcDsrVttgenDrv, &regs->dsr_vttgen_drv); + writel(param->EmcTxdsrvttgen, &regs->txdsrvttgen); + writel(param->EmcBgbiasCtl0, &regs->bgbias_ctl0); + + /* + * Set pipe bypass enable bits before sending any DRAM commands. + * Note other bits in EMC_CFG must be set AFTER REFCTRL is configured. + */ + writebits(param->EmcCfg, &regs->cfg, + (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK | + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK | + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK)); +} + +static void sdram_patch_bootrom(const struct sdram_params *param, + struct tegra_mc_regs *regs) +{ + if (param->BootRomPatchControl & BOOT_ROM_PATCH_CONTROL_ENABLE_MASK) { + uintptr_t addr = ((param->BootRomPatchControl & + BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >> + BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT); + addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2); + writel(param->BootRomPatchData, (uint32_t *)addr); + writel(1, &regs->timing_control); + } +} + +static void sdram_set_dpd3(const struct sdram_params *param, + struct tegra_pmc_regs *regs) +{ + /* Program DPD request */ + writel(param->PmcIoDpd3Req, &regs->io_dpd3_req); + udelay(param->PmcIoDpd3ReqWait); +} + +static void sdram_set_dli_trims(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Program DLI trims */ + writel(param->EmcDliTrimTxDqs0, &regs->dli_trim_txdqs0); + writel(param->EmcDliTrimTxDqs1, &regs->dli_trim_txdqs1); + writel(param->EmcDliTrimTxDqs2, &regs->dli_trim_txdqs2); + writel(param->EmcDliTrimTxDqs3, &regs->dli_trim_txdqs3); + writel(param->EmcDliTrimTxDqs4, &regs->dli_trim_txdqs4); + writel(param->EmcDliTrimTxDqs5, &regs->dli_trim_txdqs5); + writel(param->EmcDliTrimTxDqs6, &regs->dli_trim_txdqs6); + writel(param->EmcDliTrimTxDqs7, &regs->dli_trim_txdqs7); + writel(param->EmcDliTrimTxDqs8, &regs->dli_trim_txdqs8); + writel(param->EmcDliTrimTxDqs9, &regs->dli_trim_txdqs9); + writel(param->EmcDliTrimTxDqs10, &regs->dli_trim_txdqs10); + writel(param->EmcDliTrimTxDqs11, &regs->dli_trim_txdqs11); + writel(param->EmcDliTrimTxDqs12, &regs->dli_trim_txdqs12); + writel(param->EmcDliTrimTxDqs13, &regs->dli_trim_txdqs13); + writel(param->EmcDliTrimTxDqs14, &regs->dli_trim_txdqs14); + writel(param->EmcDliTrimTxDqs15, &regs->dli_trim_txdqs15); + + writel(param->EmcCaTrainingTimingCntl1, + &regs->ca_training_timing_cntl1); + writel(param->EmcCaTrainingTimingCntl2, + &regs->ca_training_timing_cntl2); + + sdram_trigger_emc_timing_update(regs); + udelay(param->EmcTimingControlWait); +} + +static void sdram_set_clock_enable_signal(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + volatile uint32_t dummy = 0; + clrbits_le32(&regs->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | + EMC_PIN_CKE_MASK)); + /* + * Assert dummy read of PIN register to ensure above write to PIN + * register went through. 200 is the recommended value by NVIDIA. + */ + dummy |= readl(&regs->pin); + udelay(200 + param->EmcPinExtraWait); + + /* Deassert reset */ + setbits_le32(&regs->pin, EMC_PIN_RESET_INACTIVE); + /* + * Assert dummy read of PIN register to ensure above write to PIN + * register went through. 200 is the recommended value by NVIDIA. + */ + dummy |= readl(&regs->pin); + udelay(500 + param->EmcPinExtraWait); + + /* Enable clock enable signal */ + setbits_le32(&regs->pin, EMC_PIN_CKE_NORMAL); + /* + * Assert dummy read of PIN register to ensure above write to PIN + * register went through. 200 is the recommended value by NVIDIA. + */ + dummy |= readl(&regs->pin); + udelay(param->EmcPinProgramWait); + + if (!dummy) { + die("Failed to program EMC pin."); + } + + /* Send NOP (trigger) */ + writebits(((1 << EMC_NOP_NOP_CMD_SHIFT) | + (param->EmcDevSelect << EMC_NOP_NOP_DEV_SELECTN_SHIFT)), + &regs->nop, + EMC_NOP_NOP_CMD_MASK | EMC_NOP_NOP_DEV_SELECTN_MASK); + + /* Write mode registers */ + writel(param->EmcEmrs2, &regs->emrs2); + writel(param->EmcEmrs3, &regs->emrs3); + writel(param->EmcEmrs, &regs->emrs); + writel(param->EmcMrs, &regs->mrs); + + if (param->EmcExtraModeRegWriteEnable) { + writel(param->EmcMrwExtra, &regs->mrs); + } +} + +static void sdram_init_zq_calibration(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + if ((param->EmcZcalWarmColdBootEnables & + EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK) == 1) { + /* Need to initialize ZCAL on coldboot. */ + writel(param->EmcZcalInitDev0, &regs->zq_cal); + udelay(param->EmcZcalInitWait); + + if ((param->EmcDevSelect & 2) == 0) { + writel(param->EmcZcalInitDev1, &regs->zq_cal); + udelay(param->EmcZcalInitWait); + } + } else { + udelay(param->EmcZcalInitWait); + } +} + +static void sdram_set_zq_calibration(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Start periodic ZQ calibration */ + writel(param->EmcZcalInterval, &regs->zcal_interval); + writel(param->EmcZcalWaitCnt, &regs->zcal_wait_cnt); + writel(param->EmcZcalMrwCmd, &regs->zcal_mrw_cmd); +} + +static void sdram_set_refresh(const struct sdram_params *param, + struct tegra_emc_regs *regs) +{ + /* Insert burst refresh */ + if (param->EmcExtraRefreshNum > 0) { + uint32_t refresh_num = (1 << param->EmcExtraRefreshNum) - 1; + writebits((EMC_REF_CMD_REFRESH | EMC_REF_NORMAL_ENABLED | + (refresh_num << EMC_REF_NUM_SHIFT) | + (param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT)), + &regs->ref, (EMC_REF_CMD_MASK | EMC_REF_NORMAL_MASK | + EMC_REF_NUM_MASK | + EMC_REF_DEV_SELECTN_MASK)); + } + + /* Enable refresh */ + writel((param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED), + &regs->refctrl); + + writel(param->EmcDynSelfRefControl, &regs->dyn_self_ref_control); + writel(param->EmcCfg, &regs->cfg); + writel(param->EmcSelDpdCtrl, &regs->sel_dpd_ctrl); + + /* Write addr swizzle lock bit */ + writel(param->EmcFbioSpare, &regs->fbio_spare); + + /* Re-trigger timing to latch power saving functions */ + sdram_trigger_emc_timing_update(regs); +} + +static void sdram_enable_arbiter(const struct sdram_params *param) +{ + /* TODO(hungte) Move values here to standalone header file. */ + uint32_t *AHB_ARBITRATION_XBAR_CTRL = (uint32_t*)(0x6000c000 + 0xe0); + setbits_le32(AHB_ARBITRATION_XBAR_CTRL, + param->AhbArbitrationXbarCtrlMemInitDone << 16); +} + +static void sdram_lock_carveouts(const struct sdram_params *param, + struct tegra_mc_regs *regs) +{ + /* Lock carveouts, and emem_cfg registers */ + writel(param->McVideoProtectWriteAccess, &regs->video_protect_reg_ctrl); + writel(MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED, + &regs->emem_cfg_access_ctrl); + writel(param->McSecCarveoutProtectWriteAccess, + &regs->sec_carveout_reg_ctrl); + writel(param->McMtsCarveoutRegCtrl, &regs->mts_carveout_reg_ctrl); +} + +void sdram_init(const struct sdram_params *param) +{ + struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; + struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE; + struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE; + + sdram_configure_pmc(param, pmc); + sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1); + + sdram_start_clocks(param); + sdram_patch(param->EmcBctSpare2, param->EmcBctSpare3); + + sdram_deassert_sel_dpd(param, pmc); + sdram_set_swizzle(param, emc); + sdram_set_pad_controls(param, emc); + sdram_patch(param->EmcBctSpare4, param->EmcBctSpare5); + + sdram_trigger_emc_timing_update(emc); + sdram_init_mc(param, mc); + sdram_init_emc(param, emc); + sdram_patch(param->EmcBctSpare6, param->EmcBctSpare7); + + sdram_set_emc_timing(param, emc); + sdram_patch_bootrom(param, mc); + sdram_set_dpd3(param, pmc); + sdram_set_dli_trims(param, emc); + sdram_deassert_clock_enable_signal(param, pmc); + sdram_set_clock_enable_signal(param, emc); + sdram_init_zq_calibration(param, emc); + sdram_patch(param->EmcBctSpare8, param->EmcBctSpare9); + + sdram_set_zq_calibration(param, emc); + sdram_patch(param->EmcBctSpare10, param->EmcBctSpare11); + + sdram_trigger_emc_timing_update(emc); + sdram_set_refresh(param, emc); + sdram_enable_arbiter(param); + sdram_lock_carveouts(param, mc); +} + +uint32_t sdram_get_ram_code(void) +{ + struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; + return ((readl(&pmc->strapping_opt_a) & + PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> + PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); +} diff --git a/src/soc/nvidia/tegra124/sdram.h b/src/soc/nvidia/tegra124/sdram.h new file mode 100644 index 0000000..cf5761c --- /dev/null +++ b/src/soc/nvidia/tegra124/sdram.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_SDRAM_H__ +#define __SOC_NVIDIA_TEGRA124_SDRAM_H__ + +#include "sdram_param.h" + +uint32_t sdram_get_ram_code(void); +void sdram_init(const struct sdram_params *param); + +#endif /* __SOC_NVIDIA_TEGRA124_SDRAM_H__ */ diff --git a/src/soc/nvidia/tegra124/sdram_param.h b/src/soc/nvidia/tegra124/sdram_param.h new file mode 100644 index 0000000..1f05566 --- /dev/null +++ b/src/soc/nvidia/tegra124/sdram_param.h @@ -0,0 +1,816 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. The field names are in camel case to ease + * directly converting BCT config files (*.cfg) into C structure. + */ + +#ifndef __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ +#define __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ + +#include <stddef.h> +#include <stdint.h> + +enum { + /* Specifies the memory type to be undefined */ + MEMORY_TYPE_NONE = 0, + + /* Specifies the memory type to be DDR SDRAM */ + MEMORY_TYPE_DDR = 0, + + /* Specifies the memory type to be LPDDR SDRAM */ + MEMORY_TYPE_LPDDR = 0, + + /* Specifies the memory type to be DDR2 SDRAM */ + MEMORY_TYPE_DDR2 = 0, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + MEMORY_TYPE_LPDDR2, + + /* Specifies the memory type to be DDR3 SDRAM */ + MEMORY_TYPE_DDR3, + + MEMORY_TYPE_NUM, + MEMORY_TYPE_FORCE32 = 0X7FFFFFF +}; + +enum { + BOOT_ROM_PATCH_CONTROL_ENABLE_MASK = 0x1 << 31, + BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT = 0, + BOOT_ROM_PATCH_CONTROL_OFFSET_MASK = 0x7FFFFFFF << 0, + BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS = 0x70000000, + + EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK = 1 << 0, +}; + +/** + * Defines the SDRAM parameter structure + */ +struct sdram_params { + + /* Specifies the type of memory device */ + uint32_t memory_type; + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + uint32_t PllMInputDivider; + /* Specifies the N value for PllM */ + uint32_t PllMFeedbackDivider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t PllMStableTime; + /* Specifies misc. control bits */ + uint32_t PllMSetupControl; + /* Enables the Div by 2 */ + uint32_t PllMSelectDiv2; + /* Powers down VCO output Level shifter */ + uint32_t PllMPDLshiftPh45; + /* Powers down VCO output Level shifter */ + uint32_t PllMPDLshiftPh90; + /* Powers down VCO output Level shifter */ + uint32_t PllMPDLshiftPh135; + /* Specifies value for Charge Pump Gain Control */ + uint32_t PllMKCP; + /* Specifies VCO gain */ + uint32_t PllMKVCO; + /* Spare BCT param */ + uint32_t EmcBctSpare0; + /* Spare BCT param */ + uint32_t EmcBctSpare1; + /* Spare BCT param */ + uint32_t EmcBctSpare2; + /* Spare BCT param */ + uint32_t EmcBctSpare3; + /* Spare BCT param */ + uint32_t EmcBctSpare4; + /* Spare BCT param */ + uint32_t EmcBctSpare5; + /* Spare BCT param */ + uint32_t EmcBctSpare6; + /* Spare BCT param */ + uint32_t EmcBctSpare7; + /* Spare BCT param */ + uint32_t EmcBctSpare8; + /* Spare BCT param */ + uint32_t EmcBctSpare9; + /* Spare BCT param */ + uint32_t EmcBctSpare10; + /* Spare BCT param */ + uint32_t EmcBctSpare11; + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + uint32_t EmcClockSource; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t EmcAutoCalInterval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t EmcAutoCalConfig; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t EmcAutoCalConfig2; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t EmcAutoCalConfig3; + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t EmcAutoCalWait; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t EmcAdrCfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t EmcPinProgramWait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t EmcPinExtraWait; + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t EmcTimingControlWait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t EmcRc; + /* Specifies the value for EMC_RFC */ + uint32_t EmcRfc; + /* Specifies the value for EMC_RFC_SLR */ + uint32_t EmcRfcSlr; + /* Specifies the value for EMC_RAS */ + uint32_t EmcRas; + /* Specifies the value for EMC_RP */ + uint32_t EmcRp; + /* Specifies the value for EMC_R2R */ + uint32_t EmcR2r; + /* Specifies the value for EMC_W2W */ + uint32_t EmcW2w; + /* Specifies the value for EMC_R2W */ + uint32_t EmcR2w; + /* Specifies the value for EMC_W2R */ + uint32_t EmcW2r; + /* Specifies the value for EMC_R2P */ + uint32_t EmcR2p; + /* Specifies the value for EMC_W2P */ + uint32_t EmcW2p; + /* Specifies the value for EMC_RD_RCD */ + uint32_t EmcRdRcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t EmcWrRcd; + /* Specifies the value for EMC_RRD */ + uint32_t EmcRrd; + /* Specifies the value for EMC_REXT */ + uint32_t EmcRext; + /* Specifies the value for EMC_WEXT */ + uint32_t EmcWext; + /* Specifies the value for EMC_WDV */ + uint32_t EmcWdv; + /* Specifies the value for EMC_WDV_MASK */ + uint32_t EmcWdvMask; + /* Specifies the value for EMC_QUSE */ + uint32_t EmcQUse; + /* Specifies the value for EMC_QUSE_WIDTH */ + uint32_t EmcQuseWidth; + /* Specifies the value for EMC_IBDLY */ + uint32_t EmcIbdly; + /* Specifies the value for EMC_EINPUT */ + uint32_t EmcEInput; + /* Specifies the value for EMC_EINPUT_DURATION */ + uint32_t EmcEInputDuration; + /* Specifies the value for EMC_PUTERM_EXTRA */ + uint32_t EmcPutermExtra; + /* Specifies the value for EMC_PUTERM_WIDTH */ + uint32_t EmcPutermWidth; + /* Specifies the value for EMC_PUTERM_ADJ */ + uint32_t EmcPutermAdj; + /* Specifies the value for EMC_CDB_CNTL_1 */ + uint32_t EmcCdbCntl1; + /* Specifies the value for EMC_CDB_CNTL_2 */ + uint32_t EmcCdbCntl2; + /* Specifies the value for EMC_CDB_CNTL_3 */ + uint32_t EmcCdbCntl3; + /* Specifies the value for EMC_QRST */ + uint32_t EmcQRst; + /* Specifies the value for EMC_QSAFE */ + uint32_t EmcQSafe; + /* Specifies the value for EMC_RDV */ + uint32_t EmcRdv; + /* Specifies the value for EMC_RDV_MASK */ + uint32_t EmcRdvMask; + /* Specifies the value for EMC_QPOP */ + uint32_t EmcQpop; + /* Specifies the value for EMC_CTT */ + uint32_t EmcCtt; + /* Specifies the value for EMC_CTT_DURATION */ + uint32_t EmcCttDuration; + /* Specifies the value for EMC_REFRESH */ + uint32_t EmcRefresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t EmcBurstRefreshNum; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t EmcPreRefreshReqCnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t EmcPdEx2Wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t EmcPdEx2Rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t EmcPChg2Pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t EmcAct2Pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t EmcAr2Pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t EmcRw2Pden; + /* Specifies the value for EMC_TXSR */ + uint32_t EmcTxsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t EmcTxsrDll; + /* Specifies the value for EMC_TCKE */ + uint32_t EmcTcke; + /* Specifies the value for EMC_TCKESR */ + uint32_t EmcTckesr; + /* Specifies the value for EMC_TPD */ + uint32_t EmcTpd; + /* Specifies the value for EMC_TFAW */ + uint32_t EmcTfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t EmcTrpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t EmcTClkStable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t EmcTClkStop; + /* Specifies the value for EMC_TREFBW */ + uint32_t EmcTRefBw; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t EmcFbioCfg5; + /* Specifies the value for EMC_FBIO_CFG6 */ + uint32_t EmcFbioCfg6; + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t EmcFbioSpare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t EmcCfgRsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t EmcMrs; + /* Specifies the MP0 command to initialize mode registers */ + uint32_t EmcEmrs; + /* Specifies the MP2 command to initialize mode registers */ + uint32_t EmcEmrs2; + /* Specifies the MP3 command to initialize mode registers */ + uint32_t EmcEmrs3; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t EmcMrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t EmcMrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t EmcMrw3; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t EmcMrw4; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t EmcMrwExtra; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t EmcWarmBootMrwExtra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t EmcWarmBootExtraModeRegWriteEnable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t EmcExtraModeRegWriteEnable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t EmcMrwResetCommand; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t EmcMrwResetNInitWait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t EmcMrsWaitCnt; + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + uint32_t EmcMrsWaitCnt2; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t EmcCfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t EmcCfg2; + /* Specifies the pipe bypass controls */ + uint32_t EmcCfgPipe; + /* Specifies the value for EMC_DBG */ + uint32_t EmcDbg; + /* Specifies the value for EMC_CMDQ */ + uint32_t EmcCmdQ; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t EmcMc2EmcQ; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t EmcDynSelfRefControl; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t AhbArbitrationXbarCtrlMemInitDone; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t EmcCfgDigDll; + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t EmcCfgDigDllPeriod; + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + uint32_t EmcDevSelect; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t EmcSelDpdCtrl; + + /* Pads trimmer delays */ + + /* Specifies the value for EMC_DLL_XFORM_DQS0 */ + uint32_t EmcDllXformDqs0; + /* Specifies the value for EMC_DLL_XFORM_DQS1 */ + uint32_t EmcDllXformDqs1; + /* Specifies the value for EMC_DLL_XFORM_DQS2 */ + uint32_t EmcDllXformDqs2; + /* Specifies the value for EMC_DLL_XFORM_DQS3 */ + uint32_t EmcDllXformDqs3; + /* Specifies the value for EMC_DLL_XFORM_DQS4 */ + uint32_t EmcDllXformDqs4; + /* Specifies the value for EMC_DLL_XFORM_DQS5 */ + uint32_t EmcDllXformDqs5; + /* Specifies the value for EMC_DLL_XFORM_DQS6 */ + uint32_t EmcDllXformDqs6; + /* Specifies the value for EMC_DLL_XFORM_DQS7 */ + uint32_t EmcDllXformDqs7; + /* Specifies the value for EMC_DLL_XFORM_DQS8 */ + uint32_t EmcDllXformDqs8; + /* Specifies the value for EMC_DLL_XFORM_DQS9 */ + uint32_t EmcDllXformDqs9; + /* Specifies the value for EMC_DLL_XFORM_DQS10 */ + uint32_t EmcDllXformDqs10; + /* Specifies the value for EMC_DLL_XFORM_DQS11 */ + uint32_t EmcDllXformDqs11; + /* Specifies the value for EMC_DLL_XFORM_DQS12 */ + uint32_t EmcDllXformDqs12; + /* Specifies the value for EMC_DLL_XFORM_DQS13 */ + uint32_t EmcDllXformDqs13; + /* Specifies the value for EMC_DLL_XFORM_DQS14 */ + uint32_t EmcDllXformDqs14; + /* Specifies the value for EMC_DLL_XFORM_DQS15 */ + uint32_t EmcDllXformDqs15; + /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ + uint32_t EmcDllXformQUse0; + /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ + uint32_t EmcDllXformQUse1; + /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ + uint32_t EmcDllXformQUse2; + /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ + uint32_t EmcDllXformQUse3; + /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ + uint32_t EmcDllXformQUse4; + /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ + uint32_t EmcDllXformQUse5; + /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ + uint32_t EmcDllXformQUse6; + /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ + uint32_t EmcDllXformQUse7; + /* Specifies the value for EMC_DLL_XFORM_ADDR0 */ + uint32_t EmcDllXformAddr0; + /* Specifies the value for EMC_DLL_XFORM_ADDR1 */ + uint32_t EmcDllXformAddr1; + /* Specifies the value for EMC_DLL_XFORM_ADDR2 */ + uint32_t EmcDllXformAddr2; + /* Specifies the value for EMC_DLL_XFORM_ADDR3 */ + uint32_t EmcDllXformAddr3; + /* Specifies the value for EMC_DLL_XFORM_ADDR4 */ + uint32_t EmcDllXformAddr4; + /* Specifies the value for EMC_DLL_XFORM_ADDR5 */ + uint32_t EmcDllXformAddr5; + /* Specifies the value for EMC_DLL_XFORM_QUSE8 */ + uint32_t EmcDllXformQUse8; + /* Specifies the value for EMC_DLL_XFORM_QUSE9 */ + uint32_t EmcDllXformQUse9; + /* Specifies the value for EMC_DLL_XFORM_QUSE10 */ + uint32_t EmcDllXformQUse10; + /* Specifies the value for EMC_DLL_XFORM_QUSE11 */ + uint32_t EmcDllXformQUse11; + /* Specifies the value for EMC_DLL_XFORM_QUSE12 */ + uint32_t EmcDllXformQUse12; + /* Specifies the value for EMC_DLL_XFORM_QUSE13 */ + uint32_t EmcDllXformQUse13; + /* Specifies the value for EMC_DLL_XFORM_QUSE14 */ + uint32_t EmcDllXformQUse14; + /* Specifies the value for EMC_DLL_XFORM_QUSE15 */ + uint32_t EmcDllXformQUse15; + /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ + uint32_t EmcDliTrimTxDqs0; + /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ + uint32_t EmcDliTrimTxDqs1; + /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ + uint32_t EmcDliTrimTxDqs2; + /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ + uint32_t EmcDliTrimTxDqs3; + /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ + uint32_t EmcDliTrimTxDqs4; + /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ + uint32_t EmcDliTrimTxDqs5; + /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ + uint32_t EmcDliTrimTxDqs6; + /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ + uint32_t EmcDliTrimTxDqs7; + /* Specifies the value for EMC_DLI_TRIM_TXDQS8 */ + uint32_t EmcDliTrimTxDqs8; + /* Specifies the value for EMC_DLI_TRIM_TXDQS9 */ + uint32_t EmcDliTrimTxDqs9; + /* Specifies the value for EMC_DLI_TRIM_TXDQS10 */ + uint32_t EmcDliTrimTxDqs10; + /* Specifies the value for EMC_DLI_TRIM_TXDQS11 */ + uint32_t EmcDliTrimTxDqs11; + /* Specifies the value for EMC_DLI_TRIM_TXDQS12 */ + uint32_t EmcDliTrimTxDqs12; + /* Specifies the value for EMC_DLI_TRIM_TXDQS13 */ + uint32_t EmcDliTrimTxDqs13; + /* Specifies the value for EMC_DLI_TRIM_TXDQS14 */ + uint32_t EmcDliTrimTxDqs14; + /* Specifies the value for EMC_DLI_TRIM_TXDQS15 */ + uint32_t EmcDliTrimTxDqs15; + /* Specifies the value for EMC_DLL_XFORM_DQ0 */ + uint32_t EmcDllXformDq0; + /* Specifies the value for EMC_DLL_XFORM_DQ1 */ + uint32_t EmcDllXformDq1; + /* Specifies the value for EMC_DLL_XFORM_DQ2 */ + uint32_t EmcDllXformDq2; + /* Specifies the value for EMC_DLL_XFORM_DQ3 */ + uint32_t EmcDllXformDq3; + /* Specifies the value for EMC_DLL_XFORM_DQ4 */ + uint32_t EmcDllXformDq4; + /* Specifies the value for EMC_DLL_XFORM_DQ5 */ + uint32_t EmcDllXformDq5; + /* Specifies the value for EMC_DLL_XFORM_DQ6 */ + uint32_t EmcDllXformDq6; + /* Specifies the value for EMC_DLL_XFORM_DQ7 */ + uint32_t EmcDllXformDq7; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t WarmBootWait; + + /* Specifies the value for EMC_CTT_TERM_CTRL */ + uint32_t EmcCttTermCtrl; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t EmcOdtWrite; + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t EmcOdtRead; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t EmcZcalInterval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t EmcZcalWaitCnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t EmcZcalMrwCmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t EmcMrsResetDll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t EmcZcalInitDev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t EmcZcalInitDev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t EmcZcalInitWait; + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + uint32_t EmcZcalWarmColdBootEnables; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + uint32_t EmcMrwLpddr2ZcalWarmBoot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t EmcZqCalDdr3WarmBoot; + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t EmcZcalWarmBootWait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t EmcMrsWarmBootEnable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t EmcMrsResetDllWait; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t EmcMrsExtra; + /* Specifies the extra MRS command at warm boot */ + uint32_t EmcWarmBootMrsExtra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t EmcEmrsDdr2DllEnable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t EmcMrsDdr2DllReset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t EmcEmrsDdr2OcdCalib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t EmcDdr2Wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t EmcClkenOverride; + /* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */ + uint32_t McDisExtraSnapLevels; + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t EmcExtraRefreshNum; + /* Specifies the master override for all EMC clocks */ + uint32_t EmcClkenOverrideAllWarmBoot; + /* Specifies the master override for all MC clocks */ + uint32_t McClkenOverrideAllWarmBoot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t EmcCfgDigDllPeriodWarmBoot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t PmcVddpSel; + /* Specifies the wait time after programming PMC_VDDP_SEL */ + uint32_t PmcVddpSelWait; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t PmcDdrPwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t PmcDdrCfg; + /* Specifies the value for PMC_IO_DPD3_REQ */ + uint32_t PmcIoDpd3Req; + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + uint32_t PmcIoDpd3ReqWait; + /* Specifies the value for PMC_REG_SHORT */ + uint32_t PmcRegShort; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t PmcNoIoPower; + /* Specifies the wait time after programming PMC_POR_DPD_CTRL */ + uint32_t PmcPorDpdCtrlWait; + /* Specifies the value for EMC_XM2CMDPADCTRL */ + uint32_t EmcXm2CmdPadCtrl; + /* Specifies the value for EMC_XM2CMDPADCTRL2 */ + uint32_t EmcXm2CmdPadCtrl2; + /* Specifies the value for EMC_XM2CMDPADCTRL3 */ + uint32_t EmcXm2CmdPadCtrl3; + /* Specifies the value for EMC_XM2CMDPADCTRL4 */ + uint32_t EmcXm2CmdPadCtrl4; + /* Specifies the value for EMC_XM2CMDPADCTRL5 */ + uint32_t EmcXm2CmdPadCtrl5; + /* Specifies the value for EMC_XM2DQSPADCTRL */ + uint32_t EmcXm2DqsPadCtrl; + /* Specifies the value for EMC_XM2DQSPADCTRL2 */ + uint32_t EmcXm2DqsPadCtrl2; + /* Specifies the value for EMC_XM2DQSPADCTRL3 */ + uint32_t EmcXm2DqsPadCtrl3; + /* Specifies the value for EMC_XM2DQSPADCTRL4 */ + uint32_t EmcXm2DqsPadCtrl4; + /* Specifies the value for EMC_XM2DQSPADCTRL5 */ + uint32_t EmcXm2DqsPadCtrl5; + /* Specifies the value for EMC_XM2DQSPADCTRL6 */ + uint32_t EmcXm2DqsPadCtrl6; + /* Specifies the value for EMC_XM2DQPADCTRL */ + uint32_t EmcXm2DqPadCtrl; + /* Specifies the value for EMC_XM2DQPADCTRL2 */ + uint32_t EmcXm2DqPadCtrl2; + /* Specifies the value for EMC_XM2DQPADCTRL3 */ + uint32_t EmcXm2DqPadCtrl3; + /* Specifies the value for EMC_XM2CLKPADCTRL */ + uint32_t EmcXm2ClkPadCtrl; + /* Specifies the value for EMC_XM2CLKPADCTRL2 */ + uint32_t EmcXm2ClkPadCtrl2; + /* Specifies the value for EMC_XM2COMPPADCTRL */ + uint32_t EmcXm2CompPadCtrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL */ + uint32_t EmcXm2VttGenPadCtrl; + /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ + uint32_t EmcXm2VttGenPadCtrl2; + /* Specifies the value for EMC_XM2VTTGENPADCTRL3 */ + uint32_t EmcXm2VttGenPadCtrl3; + /* Specifies the value for EMC_ACPD_CONTROL */ + uint32_t EmcAcpdControl; + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ + uint32_t EmcSwizzleRank0ByteCfg; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t EmcSwizzleRank0Byte0; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t EmcSwizzleRank0Byte1; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t EmcSwizzleRank0Byte2; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t EmcSwizzleRank0Byte3; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ + uint32_t EmcSwizzleRank1ByteCfg; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t EmcSwizzleRank1Byte0; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t EmcSwizzleRank1Byte1; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t EmcSwizzleRank1Byte2; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t EmcSwizzleRank1Byte3; + + /* Specifies the value for EMC_DSR_VTTGEN_DRV */ + uint32_t EmcDsrVttgenDrv; + + /* Specifies the value for EMC_TXDSRVTTGEN */ + uint32_t EmcTxdsrvttgen; + /* Specifies the value for EMC_BGBIAS_CTL */ + uint32_t EmcBgbiasCtl0; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t McEmemAdrCfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t McEmemAdrCfgDev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t McEmemAdrCfgDev1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ + uint32_t McEmemAdrCfgBankMask0; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + uint32_t McEmemAdrCfgBankMask1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + uint32_t McEmemAdrCfgBankMask2; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */ + uint32_t McEmemAdrCfgBankSwizzle3; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t McEmemCfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t McEmemArbCfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t McEmemArbOutstandingReq; + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t McEmemArbTimingRcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t McEmemArbTimingRp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t McEmemArbTimingRc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t McEmemArbTimingRas; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t McEmemArbTimingFaw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t McEmemArbTimingRrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t McEmemArbTimingRap2Pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t McEmemArbTimingWap2Pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t McEmemArbTimingR2R; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t McEmemArbTimingW2W; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t McEmemArbTimingR2W; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t McEmemArbTimingW2R; + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t McEmemArbDaTurns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t McEmemArbDaCovers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t McEmemArbMisc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t McEmemArbMisc1; + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t McEmemArbRing1Throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t McEmemArbOverride; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + uint32_t McEmemArbOverride1; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t McEmemArbRsv; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t McClkenOverride; + + /* Specifies the value for MC_STAT_CONTROL */ + uint32_t McStatControl; + /* Specifies the value for MC_DISPLAY_SNAP_RING */ + uint32_t McDisplaySnapRing; + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + uint32_t McVideoProtectBom; + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + uint32_t McVideoProtectBomAdrHi; + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + uint32_t McVideoProtectSizeMb; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + uint32_t McVideoProtectVprOverride; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + uint32_t McVideoProtectVprOverride1; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + uint32_t McVideoProtectGpuOverride0; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + uint32_t McVideoProtectGpuOverride1; + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + uint32_t McSecCarveoutBom; + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + uint32_t McSecCarveoutAdrHi; + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + uint32_t McSecCarveoutSizeMb; + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ + uint32_t McVideoProtectWriteAccess; + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ + uint32_t McSecCarveoutProtectWriteAccess; + + /* Specifies enable for CA training */ + uint32_t EmcCaTrainingEnable; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */ + uint32_t EmcCaTrainingTimingCntl1; + /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */ + uint32_t EmcCaTrainingTimingCntl2; + /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ + uint32_t SwizzleRankByteEncode; + /* Specifies enable and offset for patched boot rom write */ + uint32_t BootRomPatchControl; + /* Specifies data for patched boot rom write */ + uint32_t BootRomPatchData; + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + uint32_t McMtsCarveoutBom; + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + uint32_t McMtsCarveoutAdrHi; + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + uint32_t McMtsCarveoutSizeMb; + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + uint32_t McMtsCarveoutRegCtrl; + + /* End of generated code by warmboot_code_gen */ +}; + +check_member(sdram_params, McMtsCarveoutRegCtrl, 0x4d0); + +#endif /* __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ */

1 0

New patch to review for coreboot: 2753d65 slippy: remove FUI support
by Isaac Christensen 15 Sep '14

15 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6913 -gerrit commit 2753d65ea749d8be45f3ad17652cad6e85845d18 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Tue Dec 17 15:24:24 2013 -0800 slippy: remove FUI support There's no reason to keep maintaining support on this mainboard, since nobody has one. Change-Id: I5c7c8ea4640170ba231fec82a94a54ee1876b845 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/180503 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Commit-Queue: Ronald Minnich <rminnich(a)chromium.org> Tested-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit e291d82acbc8bf0d1372e11ac100a7dd340a0040) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/slippy/Makefile.inc | 1 - src/mainboard/google/slippy/gma.c | 388 ------------------------------- src/mainboard/google/slippy/i915io.c | 135 ----------- 3 files changed, 524 deletions(-) diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 9e3c310..37378b1 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -21,7 +21,6 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-y += chromeos.c ramstage-y += chromeos.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c deleted file mode 100644 index bbb4e72..0000000 --- a/src/mainboard/google/slippy/gma.c +++ /dev/null @@ -1,388 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <string.h> -#include <stdlib.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <delay.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <smbios.h> -#include <device/pci.h> -#include <ec/google/chromeec/ec.h> -#include <cbfs_core.h> - -#include <cpu/x86/tsc.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <edid.h> -#include <drivers/intel/gma/i915.h> -#include "mainboard.h" - -/* - * Here is the rough outline of how we bring up the display: - * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD - * 2. Source determines video mode by reading DPCD receiver capability field - * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD - * 0000Dh). - * 3. Sink replies DPCD receiver capability field. - * 4. Source starts EDID read thru I2C-over-AUX. - * 5. Sink replies EDID thru I2C-over-AUX. - * 6. Source determines link configuration, such as MAX_LINK_RATE and - * MAX_LANE_COUNT. Source also determines which type of eDP Authentication - * method to use and writes DPCD link configuration field (DPCD 00100h to - * 0010Ah) including eDP configuration set (DPCD 0010Ah). - * 7. Source starts link training. Sink does clock recovery and equalization. - * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). - * 9. Sink replies DPCD link status field. If main link is not stable, Source - * repeats Step 7. - * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video - * parameters and recovers stream clock. - * 11. Source sends video data. - */ - -/* how many bytes do we need for the framebuffer? - * Well, this gets messy. To get an exact answer, we have - * to ask the panel, but we'd rather zero the memory - * and set up the gtt while the panel powers up. So, - * we take a reasonable guess, secure in the knowledge that the - * MRC has to overestimate the number of bytes used. - * 8 MiB is a very safe guess. There may be a better way later, but - * fact is, the initial framebuffer is only very temporary. And taking - * a little long is ok; this is done much faster than the AUX - * channel is ready for IO. - */ -#define FRAME_BUFFER_BYTES (8*MiB) -/* how many 4096-byte pages do we need for the framebuffer? - * There are hard ways to get this, and easy ways: - * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096 - * on this chip (and in fact every Intel graphics chip we've seen). - */ -#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096)) - -static unsigned int *mmio; -static unsigned int graphics; -static unsigned int physbase; - -void ug1(int); -void ug2(int); -void ug22(int); -void ug3(int); - -/* GTT is the Global Translation Table for the graphics pipeline. - * It is used to translate graphics addresses to physical - * memory addresses. As in the CPU, GTTs map 4K pages. - * The setgtt function adds a further bit of flexibility: - * it allows you to set a range (the first two parameters) to point - * to a physical address (third parameter);the physical address is - * incremented by a count (fourth parameter) for each GTT in the - * range. - * Why do it this way? For ultrafast startup, - * we can point all the GTT entries to point to one page, - * and set that page to 0s: - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * this takes about 2 ms, and is a win because zeroing - * the page takes a up to 200 ms. - * This call sets the GTT to point to a linear range of pages - * starting at physbase. - */ - -#define GTT_PTE_BASE (2 << 20) - -static void -setgtt(int start, int end, unsigned long base, int inc) -{ - int i; - - for(i = start; i < end; i++){ - u32 word = base + i*inc; - /* note: we've confirmed by checking - * the values that mrc does no - * useful setup before we run this. - */ - gtt_write(GTT_PTE_BASE + i * 4, word|1); - gtt_read(GTT_PTE_BASE + i * 4); - } -} - -static int i915_init_done = 0; - -/* fill the palette. */ -static void palette(void) -{ - int i; - unsigned long color = 0; - - for(i = 0; i < 256; i++, color += 0x010101){ - gtt_write(_LGC_PALETTE_A + (i<<2),color); - } -} - -void dp_init_dim_regs(struct intel_dp *dp); -void dp_init_dim_regs(struct intel_dp *dp) -{ - struct edid *edid = &(dp->edid); - - dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8; - - dp->stride = edid->bytes_per_line; - - dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16); - - dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16); - - dp->hsync = (edid->ha + edid->hso - 1) | - ((edid->ha + edid->hso + edid->hspw - 1) << 16); - - dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16); - - dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16); - - dp->vsync = (edid->va + edid->vso - 1) | - ((edid->va + edid->vso + edid->vspw - 1) << 16); - - /* PIPEASRC is wid-1 x ht-1 */ - dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1); - - dp->pfa_pos = 0; - - dp->pfa_ctl = 0x80800000; - - dp->pfa_sz = (edid->ha << 16) | (edid->va); - - dp->flags = intel_ddi_calc_transcoder_flags(3 * 6, /* bits per color is 6 */ - dp->port, - dp->pipe, - dp->type, - dp->lane_count, - dp->pfa_sz, - dp->edid.phsync == '+'?1:0, - dp->edid.pvsync == '+'?1:0); - - dp->transcoder = intel_ddi_get_transcoder(dp->port, - dp->pipe); - - intel_dp_compute_m_n(dp->pipe_bits_per_pixel, - dp->lane_count, - dp->edid.pixel_clock, - dp->edid.link_clock, - &dp->m_n); - - printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride); - printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal); - printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank); - printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync); - printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal); - printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank); - printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync); - printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc); - printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos); - printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl); - printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz); - printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m); - printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n); - printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m); - printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m); - printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n); - printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags); -} - -void mainboard_train_link(struct intel_dp *intel_dp) -{ - u8 read_val; - u8 link_status[DP_LINK_STATUS_SIZE]; - - gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); - gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011); - - intel_dp_get_training_pattern(intel_dp, &read_val); - intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); - intel_dp_get_lane_count(intel_dp, &read_val); - intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0); - intel_dp_get_link_status(intel_dp, link_status); - - gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2); - - intel_dp_get_training_pattern(intel_dp, &read_val); - intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); - intel_dp_get_link_status(intel_dp, link_status); - intel_dp_get_lane_align_status(intel_dp, &read_val); - intel_dp_get_training_pattern(intel_dp, &read_val); - intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); -} - -#define TEST_GFX 0 - -#if TEST_GFX -static void test_gfx(struct intel_dp *dp) -{ - int i; - - /* This is a sanity test code which fills the screen with two bands -- - green and blue. It is very useful to ensure all the initializations - are made right. Thus, to be used only for testing, not otherwise - */ - for (i = 0; i < (dp->edid.va - 4); i++) { - u32 *l; - int j; - u32 tcolor = 0x0ff; - for (j = 0; j < (dp->edid.ha-4); j++) { - if (j == (dp->edid.ha/2)) { - tcolor = 0xff00; - } - l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor)); - memcpy(l,&tcolor,sizeof(tcolor)); - } - } -} -#else -static void test_gfx(struct intel_dp *dp) {} -#endif - - -void mainboard_set_port_clk_dp(struct intel_dp *intel_dp) -{ - u32 ddi_pll_sel = 0; - - switch (intel_dp->link_bw) { - case DP_LINK_BW_1_62: - ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; - break; - case DP_LINK_BW_2_7: - ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; - break; - case DP_LINK_BW_5_4: - ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; - break; - default: - printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw); - return; - } - - gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel); -} - -int i915lightup(unsigned int pphysbase, unsigned int pmmio, - unsigned int pgfx, unsigned int init_fb) -{ - int must_cycle_power = 0; - struct intel_dp adp, *dp = &adp; - int i; - int edid_ok; - int pixels = FRAME_BUFFER_BYTES/64; - - mmio = (void *)pmmio; - physbase = pphysbase; - graphics = pgfx; - printk(BIOS_SPEW, - "i915lightup: graphics %p mmio %p" - "physbase %08x\n", - (void *)graphics, mmio, physbase); - - void runio(struct intel_dp *dp); - void runlinux(struct intel_dp *dp); - dp->gen = 8; // This is gen 8 which we believe is Haswell - dp->is_haswell = 1; - dp->DP = 0x2; - /* These values are used for training the link */ - dp->lane_count = 2; - dp->link_bw = DP_LINK_BW_2_7; - dp->panel_power_down_delay = 600; - dp->panel_power_up_delay = 200; - dp->panel_power_cycle_delay = 600; - dp->pipe = PIPE_A; - dp->port = PORT_A; - dp->plane = PLANE_A; - dp->clock = 160000; - dp->pipe_bits_per_pixel = 32; - dp->type = INTEL_OUTPUT_EDP; - dp->output_reg = DP_A; - /* observed from YABEL. */ - dp->aux_clock_divider = 0xe1; - dp->precharge = 3; - - /* 1. Normal mode: Set the first page to zero and make - all GTT entries point to the same page - 2. Developer/Recovery mode: We do not zero out all - the pages pointed to by GTT in order to avoid wasting time */ - if (init_fb) - setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); - else { - setgtt(0, FRAME_BUFFER_PAGES, physbase, 0); - memset((void*)graphics, 0, 4096); - } - - dp->address = 0x50; - - if ( !intel_dp_get_dpcd(dp) ) - goto fail; - - intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL); - for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){ - if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ, - 0x50, &dp->rawedid[i]) < 0) - break; - dp->edidlen++; - } - - edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid); - printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); - - dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw); - - printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",dp->edid.pixel_clock, dp->edid.link_clock); - - dp_init_dim_regs(dp); - - intel_ddi_set_pipe_settings(dp); - - runio(dp); - - palette(); - - pixels = dp->edid.ha * (dp->edid.va-4) * 4; - printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va); - - test_gfx(dp); - - set_vbe_mode_info_valid(&dp->edid, graphics); - i915_init_done = 1; - return i915_init_done; - -fail: - printk(BIOS_SPEW, "Graphics could not be started;"); - if (0 && must_cycle_power){ - printk(BIOS_SPEW, "Turn off power and wait ..."); - gtt_write(PCH_PP_CONTROL,0xabcd0000); - udelay(600000); - gtt_write(PCH_PP_CONTROL,0xabcd000f); - } - printk(BIOS_SPEW, "Returning.\n"); - return 0; -} diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c deleted file mode 100644 index aae7f29..0000000 --- a/src/mainboard/google/slippy/i915io.c +++ /dev/null @@ -1,135 +0,0 @@ -/* -* This file is part of the coreboot project. -* -* Copyright 2013 Google Inc. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; version 2 of the License. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -/* This code was originally generated using an i915tool program. It has been - * improved by hand. - */ - -#include <stdint.h> -#include <console/console.h> -#include <delay.h> -#include <drivers/intel/gma/i915.h> -#include <arch/io.h> -#include "mainboard.h" - -/* these variables will be removed when the proper support is finished in src/drivers/intel/gma/intel_dp.c */ -int index; -u32 auxout; -u8 auxin[20]; -u8 msg[32]; - -/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */ -void runio(struct intel_dp *dp); - -void runio(struct intel_dp *dp) -{ - u8 read_val; - - intel_dp_wait_panel_power_control(0xabcd0008); - - /* vbios spins at this point. Some haswell weirdness? */ - intel_dp_wait_panel_power_control(0xabcd0008); - - /* This should be a function like intel_panel_enable_backlight - However, we are not sure how the value 0x3a9 comes up. - It has to do something with PWM frequency */ - gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE); - - gtt_write(DEIIR,0x00008000); - intel_dp_wait_reg(DEIIR, 0x00000000); - - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - - intel_dp_sink_dpms(dp, 0); - - intel_dp_get_max_downspread(dp, &read_val); - - intel_dp_set_m_n_regs(dp); - - intel_dp_set_resolution(dp); - - gtt_write(PIPESRC(dp->pipe),dp->pipesrc); - gtt_write(PIPECONF(dp->transcoder),0x00000000); - gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000); - - mainboard_set_port_clk_dp(dp); - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888); - gtt_write(DEIIR,0x00000080); - - gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags); - gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN); - - intel_dp_wait_panel_power_control(0xabcd000a); - - /* what is this doing? Not sure yet. */ - intel_dp_i2c_write(dp, 0x0); - intel_dp_i2c_read(dp, &read_val); - intel_dp_i2c_write(dp, 0x04); - intel_dp_i2c_read(dp, &read_val); - intel_dp_i2c_write(dp, 0x7e); - intel_dp_i2c_read(dp, &read_val); - - /* this needs to be a call to a function */ - gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091); - gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); - gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091); - - /* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */ - gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a); - gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a); - - intel_dp_set_bw(dp); - intel_dp_set_lane_count(dp); - - mainboard_train_link(dp); - - /* need a function: intel_ddi_set_tp or similar */ - gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE); - gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL); - - gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL1,0x80000000); - - /* some of this is not needed. */ - gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE ); - - gtt_write(SDEIIR,0x00000000); - gtt_write(DEIIR,0x00000000); - gtt_write(DEIIR,0x00008000); - intel_dp_wait_reg(DEIIR, 0x00000000); - - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - gtt_write(PIPESRC(dp->pipe),dp->pipesrc); - - gtt_write(DEIIR,0x00000080); - intel_dp_wait_reg(DEIIR, 0x00000000); - - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888); - - gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON); - - gtt_write(SDEIIR,0x00000000); - gtt_write(SDEIIR,0x00000000); - gtt_write(DEIIR,0x00000000); -}

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New patch to review for coreboot: 1cb3ef6 Peppy/Falco: always use native graphics
by Isaac Christensen 15 Sep '14

15 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6912 -gerrit commit 1cb3ef6d7bd56a86475a8b0f748bf153f961ab0b Author: Ronald G. Minnich <rminnich(a)google.com> Date: Mon Dec 30 09:09:31 2013 -0800 Peppy/Falco: always use native graphics The products having shipped, and living in their own branch, we might as well enable native graphics since: 1. it works 2. it removes a blob and the only good blob is a dead blob 3. it's faster 4. when we have problems, we can diagnose them more easily 5. when we get to newer kernels the boot time will magically get faster as the driver realizes graphics is running. Where else do you get a 3-4 second speedup for free? Change-Id: Iad937320e7f46b1de7ab00dace04115a7f182ed1 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/181225 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Ronald Minnich <rminnich(a)chromium.org> Tested-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 7b567d87a9fcf6736e90e730bd052e4465d57bdf) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/falco/gma.c | 1 - src/mainboard/google/peppy/Kconfig | 1 + src/mainboard/google/peppy/gma.c | 1 - 4 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 3323fc2..ba39c7d 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EXTERNAL_MRC_BLOB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_INT15 config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/gma.c b/src/mainboard/google/falco/gma.c index 38ea162..6e3afdb 100644 --- a/src/mainboard/google/falco/gma.c +++ b/src/mainboard/google/falco/gma.c @@ -31,7 +31,6 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> -#include "hda_verb.h" #include <smbios.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 2343b8d..f991903 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EXTERNAL_MRC_BLOB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_DP select INTEL_DDI select INTEL_INT15 diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c index 972dd76..953dad9 100644 --- a/src/mainboard/google/peppy/gma.c +++ b/src/mainboard/google/peppy/gma.c @@ -31,7 +31,6 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> -#include "hda_verb.h" #include <smbios.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h>

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New patch to review for coreboot: eb5907e peppy and falco: set panel power timings in northbridge, using devicetree, not mainboards
by Isaac Christensen 15 Sep '14

15 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6911 -gerrit commit eb5907ed9692309bc8bd55b7dea54f54afe1bb00 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Tue Dec 17 15:21:54 2013 -0800 peppy and falco: set panel power timings in northbridge, using devicetree, not mainboards Historically we had set panel timing in the mainboard gma code. This goes back to the replay-attack video startup. We can let the haswell gma code set these values from the device tree settings. Change-Id: If32150d2857241ca2d2c88880086f49d25815d76 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/180521 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Ronald Minnich <rminnich(a)chromium.org> Tested-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 406eab3ca6a9bc59382866817786bf96bbb19d56) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/falco/gma.c | 3 --- src/mainboard/google/peppy/gma.c | 5 ----- src/northbridge/intel/haswell/gma.c | 1 - 3 files changed, 9 deletions(-) diff --git a/src/mainboard/google/falco/gma.c b/src/mainboard/google/falco/gma.c index 4e32b28..38ea162 100644 --- a/src/mainboard/google/falco/gma.c +++ b/src/mainboard/google/falco/gma.c @@ -189,9 +189,6 @@ int panel_lightup(struct intel_dp *dp, unsigned int init_fb) /* These values are used for training the link */ dp->lane_count = 2; dp->link_bw = DP_LINK_BW_2_7; - dp->panel_power_down_delay = 600; - dp->panel_power_up_delay = 200; - dp->panel_power_cycle_delay = 600; dp->pipe = PIPE_A; dp->port = PORT_A; dp->plane = PLANE_A; diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c index 9b8a32b..972dd76 100644 --- a/src/mainboard/google/peppy/gma.c +++ b/src/mainboard/google/peppy/gma.c @@ -215,11 +215,6 @@ int panel_lightup(struct intel_dp *dp, unsigned int init_fb) dp->aux_clock_divider = 0xe1; dp->precharge = 3; - /* CRAP -- needs to be done elsewhere from the device tree. */ - dp->panel_power_down_delay = 600; - dp->panel_power_up_delay = 200; - dp->panel_power_cycle_delay = 600; - /* 1. Normal mode: Set the first page to zero and make all GTT entries point to the same page 2. Developer/Recovery mode: Set up a tasteful color diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 015eabe..373f429 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -460,7 +460,6 @@ static void gma_func0_init(struct device *dev) dp.panel_power_up_delay = conf->gpu_panel_power_up_delay; dp.panel_power_cycle_delay = conf->gpu_panel_power_cycle_delay; - dp.physbase = pci_read_config32(dev, 0x5c) & ~0xf; #ifdef CONFIG_CHROMEOS init_fb = developer_mode_enabled() || recovery_mode_enabled(); #endif

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New patch to review for coreboot: 0de1b5c pnp: Allow setting of misc register 0xf4 in device tree
by Isaac Christensen 15 Sep '14

15 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6910 -gerrit commit 0de1b5ceb3b2064f35693bb8ce787c458132488a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Dec 11 11:06:08 2013 -0800 pnp: Allow setting of misc register 0xf4 in device tree Change-Id: I602f970e0ee2fd634a74fd4c25358c2e78ca58f9 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/179536 Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit 02b0583e632f1ba53557f8cfe4293ad4ed29ff4d) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/device/pnp_device.c | 5 +++++ src/include/device/pnp.h | 3 ++- src/include/device/pnp_def.h | 1 + src/superio/ite/it8772f/superio.c | 3 ++- 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 0aaadaa..e4aa4d3 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -300,6 +300,11 @@ static void get_resources(device_t dev, struct pnp_info *info) resource->size = 1; resource->flags |= IORESOURCE_IRQ; } + if (info->flags & PNP_MSC4) { + resource = new_resource(dev, PNP_IDX_MSC4); + resource->size = 1; + resource->flags |= IORESOURCE_IRQ; + } if (info->flags & PNP_MSC10) { resource = new_resource(dev, PNP_IDX_MSC10); resource->size = 1; diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index aed0439..d0d6fa3 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -48,7 +48,8 @@ struct pnp_info { #define PNP_EN 0x100 #define PNP_MSC0 0x200 #define PNP_MSC1 0x400 -#define PNP_MSC10 0x800 +#define PNP_MSC4 0x800 +#define PNP_MSC10 0x1000 struct io_info io0, io1, io2, io3; }; struct resource *pnp_get_resource(device_t dev, unsigned index); diff --git a/src/include/device/pnp_def.h b/src/include/device/pnp_def.h index 3258354..bbc39fd 100644 --- a/src/include/device/pnp_def.h +++ b/src/include/device/pnp_def.h @@ -12,6 +12,7 @@ #define PNP_IDX_DRQ1 0x75 #define PNP_IDX_MSC0 0xf0 #define PNP_IDX_MSC1 0xf1 +#define PNP_IDX_MSC4 0xf4 #define PNP_IDX_MSC10 0xfa #endif /* DEVICE_PNP_DEF_H */ diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 44bf33d..38f31c0 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -207,7 +207,8 @@ static struct pnp_info pnp_dev_info[] = { /* Serial Port 1 */ { &ops, IT8772F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, /* Environmental Controller */ - { &ops, IT8772F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC10, + { &ops, IT8772F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | + PNP_MSC4 | PNP_MSC10, {0x0ff8, 0}, {0x0ffc, 4}, }, /* KBC Keyboard */ { &ops, IT8772F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0,

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New patch to review for coreboot: 804809a spi: add Kconfig variable for dual-output read enable
by Isaac Christensen 15 Sep '14

15 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6909 -gerrit commit 804809a6de0954455ecb128a929f71aaf602fd4d Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Nov 22 18:41:38 2013 -0800 spi: add Kconfig variable for dual-output read enable Add a Kconfig variable so that driver code knows whether or not to use dual-output reads. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I31d23bfedd91521d719378ec573e33b381ebd2c5 Reviewed-on: https://chromium-review.googlesource.com/177834 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit de6869a3350041c6823427787971efc9fcf469b8) tegra124: implement x2 mode for SPI transfers on CBFS media This implements x2 mode when reading CBFS media over SPI. In theory this effectively doubles our throughput, though the initial results were almost negligibly better. Using a logic analyzer we see a pattern of 12 clocks, ~70ns delay, 4 clocks, ~310ns delay. So if we want to see further gains here then we'll probably need to tune AHB arbitration and utilization to eliminate bubbles/stalls when copying from APB DMA. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I33d6ae30923fc42b4dc7103d029085985472cf3e Reviewed-on: https://chromium-review.googlesource.com/177835 Reviewed-by: Tom Warren <twarren(a)nvidia.com> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 29289223362b12e84da5cbb130f285c6b9d314cc) nyan: turn on dual-output reads for SPI flash Nyan's SPI chip is capable of dual-output reads, so let's use it. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I51a97c05aa25442d8ddcc4e3e35a2507d91a64df Reviewed-on: https://chromium-review.googlesource.com/177836 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 62de0889a9cfc5686800645d05e21e272e4beb5c) Squashed three commits to enable dual output spi reads for nyan. Also fixed the spi_xfer interface that has been updated to use bytes instead of bits. Change-Id: I750a177576175b297f61e1b10eac6db15e75aa6e Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/drivers/spi/Kconfig | 9 +++++++ src/mainboard/google/nyan/Kconfig | 2 ++ src/soc/nvidia/tegra124/spi.c | 53 ++++++++++++++++++++++++++++++--------- src/soc/nvidia/tegra124/spi.h | 1 + 4 files changed, 53 insertions(+), 12 deletions(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 6b31053..d832e0c 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -103,4 +103,13 @@ config SPI_FLASH_WINBOND Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond. +config SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B + bool + default n + depends on SPI_FLASH + help + Select this option if your SPI flash supports the fast read dual- + output command (opcode 0x3b) where the opcode and address are sent + to the chip on MOSI and data is received on both MOSI and MISO. + endif # SPI_FLASH diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 1a7b260..320039f 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -28,6 +28,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_BOOTBLOCK_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_1024 + select SPI_FLASH + select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config MAINBOARD_DIR string diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index c13f2c3..ae8a9a7 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -710,18 +710,20 @@ static int xfer_finish(struct tegra_spi_channel *spi) return ret; } +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return buf_len; +} + int spi_xfer(struct spi_slave *slave, const void *dout, - unsigned int bitsout, void *din, unsigned int bitsin) + unsigned int out_bytes, void *din, unsigned int in_bytes) { - unsigned int out_bytes = bitsout / 8, in_bytes = bitsin / 8; struct tegra_spi_channel *spi = to_tegra_spi(slave->bus); u8 *out_buf = (u8 *)dout; u8 *in_buf = (u8 *)din; unsigned int todo; int ret = 0, frame_started = 1; - ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0); - /* tegra bus numbers start at 1 */ ASSERT(slave->bus >= 1 && slave->bus <= ARRAY_SIZE(tegra_spi_channels)); @@ -842,19 +844,37 @@ static int tegra_spi_cbfs_close(struct cbfs_media *media) return 0; } -#define JEDEC_READ 0x03 -#define JEDEC_READ_OUTSIZE 0x04 -/* JEDEC_READ_INSIZE : any length */ +#define JEDEC_READ 0x03 +#define JEDEC_READ_OUTSIZE 0x04 +#define JEDEC_FAST_READ_DUAL 0x3b +#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05 static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest, size_t offset, size_t count) { struct tegra_spi_media *spi = (struct tegra_spi_media *)media->context; - u8 spi_read_cmd[JEDEC_READ_OUTSIZE]; + u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE]; + unsigned int read_cmd_bytes; int ret = count; + struct tegra_spi_channel *channel; + + channel = to_tegra_spi(spi->slave->bus); - /* TODO: Dual mode (BOTH_EN_BIT) and packed mode */ - spi_read_cmd[0] = JEDEC_READ; + if (channel->dual_mode) { + /* + * Command 0x3b will interleave data only, command 0xbb will + * interleave the address as well. It's nice to see the address + * plainly when debugging, and we're mostly concerned with + * large transfers so the optimization of using 0xbb isn't + * really worthwhile. + */ + spi_read_cmd[0] = JEDEC_FAST_READ_DUAL; + spi_read_cmd[4] = 0x00; /* dummy byte */ + read_cmd_bytes = JEDEC_FAST_READ_DUAL_OUTSIZE; + } else { + spi_read_cmd[0] = JEDEC_READ; + read_cmd_bytes = JEDEC_READ_OUTSIZE; + } spi_read_cmd[1] = (offset >> 16) & 0xff; spi_read_cmd[2] = (offset >> 8) & 0xff; spi_read_cmd[3] = offset & 0xff; @@ -863,18 +883,23 @@ static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest, spi_cs_activate(spi->slave); if (spi_xfer(spi->slave, spi_read_cmd, - sizeof(spi_read_cmd) * 8, NULL, 0) < 0) { + read_cmd_bytes, NULL, 0) < 0) { ret = -1; printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", __func__, sizeof(spi_read_cmd)); goto tegra_spi_cbfs_read_exit; } - if (spi_xfer(spi->slave, NULL, 0, dest, count * 8)) { + if (channel->dual_mode) { + setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT); + } + if (spi_xfer(spi->slave, NULL, 0, dest, count)) { ret = -1; printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", __func__, count); } + if (channel->dual_mode) + clrbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT); tegra_spi_cbfs_read_exit: /* de-assert /CS */ @@ -924,6 +949,10 @@ int initialize_tegra_spi_cbfs_media(struct cbfs_media *media, media->map = tegra_spi_cbfs_map; media->unmap = tegra_spi_cbfs_unmap; +#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1 + channel->dual_mode = 1; +#endif + return 0; } diff --git a/src/soc/nvidia/tegra124/spi.h b/src/soc/nvidia/tegra124/spi.h index b722240..fa238f2 100644 --- a/src/soc/nvidia/tegra124/spi.h +++ b/src/soc/nvidia/tegra124/spi.h @@ -56,6 +56,7 @@ struct tegra_spi_channel { /* stuff that is specific to the attached device */ int rx_frame_header_enable; u8 frame_header; + int dual_mode; /* for x2 transfers with bit interleaving */ /* context (used internally) */ u8 *in_buf, *out_buf;

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