coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 0b054eb arch/x86/Makefile.inc: trivial: fix indent of informative output about bootblock
by Daniele Forsi 02 Aug '14

02 Aug '14

Daniele Forsi (dforsi(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6466 -gerrit commit 0b054ebc5ad84f36a613ee95108069fdefa34bd4 Author: Daniele Forsi <dforsi(a)gmail.com> Date: Sat Aug 2 13:45:17 2014 +0200 arch/x86/Makefile.inc: trivial: fix indent of informative output about bootblock Fixes the 4th line of this sequence: ROMCC generated/bootblock.inc GEN generated/bootblock_inc.S CC generated/bootblock.s CC generated/bootblock.o GEN generated/bootblock.ld Change-Id: Ic0704b83ec9c4191e26a94e0d69cbf4c0486ceed Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> --- src/arch/x86/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2e92d89..90a697c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -114,7 +114,7 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) $(CFLAGS_x86_32) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h

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Patch set updated for coreboot: 5e65951 lenovo/t530/mainboard.c: Add EC info to SMBIOS
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6399 -gerrit commit 5e65951141db5ca0ed6192c02892f4e5fa882e7d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 20:52:17 2014 +1000 lenovo/t530/mainboard.c: Add EC info to SMBIOS As is in: 91175bb lenovo/x201 & x230: Add EC info to SMBIOS This is needed for the Linux driver for the Lenovo's to properly attach. Change-Id: Ib910b25f392d9d3d6362b6909ce9fd4eeae9a096 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/mainboard.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 325f90f..4d6e623 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -173,12 +173,28 @@ static void mainboard_init(device_t dev) 0x42, 0x142); } +static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *current) +{ + int len; + char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; + const char *oem_strings[] = { + tpec, + }; + + h8_build_id_and_function_spec_version(tpec + 35, 17); + len = smbios_write_type11(current, (*handle)++, oem_strings, ARRAY_SIZE(oem_strings)); + + return len; +} + // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = mainboard_smbios_data; + #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler);

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New patch to review for coreboot: eeb8e81 superio/smsc/sio1036: Clean up RAMstage superio.c component
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6465 -gerrit commit eeb8e813fdf0d9a7cbe69ca9446c85a284e062d2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 20:45:13 2014 +1000 superio/smsc/sio1036: Clean up RAMstage superio.c component Remove spurious includes, unused variables and some wasted new lines. Re-organise things to be consistent with other superio's. Change-Id: I959bab2f7a83a1b9160d7f010a0de9638b30cf07 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/smsc/sio1036/superio.c | 37 +++++++++++-------------------------- 1 file changed, 11 insertions(+), 26 deletions(-) diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index d2bfd8d..208bc85 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -24,20 +24,16 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <console/console.h> -#include <device/smbus.h> -#include <string.h> -#include <pc80/keyboard.h> #include <stdlib.h> -#include "sio1036.h" -/* Forward declarations */ -static void enable_dev(device_t dev); -static void sio1036_init(device_t dev); +#include "sio1036.h" -struct chip_operations superio_smsc_sio1036_ops = { - CHIP_NAME("SMSC SIO1036 Super I/O") - .enable_dev = enable_dev -}; +static void sio1036_init(device_t dev) +{ + if (!dev->enabled) { + return; + } +} static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -57,19 +53,8 @@ static void enable_dev(device_t dev) pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -static void sio1036_init(device_t dev) -{ - struct resource *res0, *res1; - - - - if (!dev->enabled) { - return; - } - - switch(dev->path.pnp.device) { +struct chip_operations superio_smsc_sio1036_ops = { + CHIP_NAME("SMSC SIO1036 Super I/O") + .enable_dev = enable_dev +}; - default: - break; - } -}

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Patch set updated for coreboot: ab84518 superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6463 -gerrit commit ab845184465371a6481f12e90a3f6692c598f070 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 20:08:35 2014 +1000 superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match. Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/Kconfig | 1 + src/mainboard/amd/dinar/romstage.c | 6 ++---- src/superio/smsc/sio1036/Makefile.inc | 1 + src/superio/smsc/sio1036/sio1036.h | 5 +++++ src/superio/smsc/sio1036/sio1036_early_init.c | 15 +++++++-------- 5 files changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index e826459..b71c5a5 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY15 select NORTHBRIDGE_AMD_CIMX_RD890 select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_SMSC_SIO1036 select SUPERIO_SMSC_SCH4037 select BOARD_ROMSIZE_KB_2048 select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 842b4f0..1700166 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -33,13 +33,11 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" -#include "superio/smsc/sio1036/sio1036_early_init.c" +#include <superio/smsc/sio1036/sio1036.h> #include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -53,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { /* Found SMSC SIO1036 LPC Debug Card */ - sio1036_early_init(0x4E); + sio1036_early_init(0x4E, CONFIG_TTYS0_BASE); } post_code(0x31); diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc index f09d451..c4b6138 100644 --- a/src/superio/smsc/sio1036/Makefile.inc +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index e61b600..6049d36 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -26,4 +26,9 @@ #define LPT_POWER_DOWN (1 << 2) #define IR_OUPUT_MUX (1 << 6) +#include <stdint.h> + +u8 detect_sio1036_chip(unsigned port); +void sio1036_early_init(unsigned port, u16 iobase); + #endif /* SUPERIO_SMSC_1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..ab1d282 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -20,24 +20,23 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ #include <arch/io.h> +#include <stdint.h> + #include "sio1036.h" -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3F8 -#endif static inline void sio1036_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0x55, port); } static inline void sio1036_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0xaa, port); } -static u8 detect_sio1036_chip(unsigned port) +u8 detect_sio1036_chip(unsigned port) { device_t dev; dev = PNP_DEV (port, SIO1036_SP1); @@ -55,7 +54,7 @@ static u8 detect_sio1036_chip(unsigned port) }; } -static inline void sio1036_early_init(unsigned port) +void sio1036_early_init(unsigned port, u16 iobase) { device_t dev; dev = PNP_DEV (port, SIO1036_SP1); @@ -91,7 +90,7 @@ static inline void sio1036_early_init(unsigned port) /* Enable SMSC UART 0 */ /*Set base io address */ - pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + pnp_write_config (dev, 0x25, (u8)(iobase >> 2)); /* Set UART IRQ onto 0x04 */ pnp_write_config (dev, 0x28, 0x04);

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New patch to review for coreboot: a3bb57e Fix src/northbridge 'RAMINIT_H' header guards
by HAOUAS Elyes 02 Aug '14

02 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6464 -gerrit commit a3bb57ec0eeb120649650defb28f4759d99465b9 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Aug 2 12:31:56 2014 +0200 Fix src/northbridge 'RAMINIT_H' header guards Change-Id: I46db08a575a2320f8fe00361ab7d72b95e86eed6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdfam10/raminit.h | 7 +++---- src/northbridge/amd/amdk8/raminit.h | 6 +++--- src/northbridge/amd/gx1/raminit.h | 6 +++--- src/northbridge/amd/gx2/raminit.h | 6 +++--- src/northbridge/amd/lx/raminit.h | 6 +++--- src/northbridge/intel/e7501/raminit.h | 6 +++--- src/northbridge/intel/e7505/raminit.h | 6 +++--- src/northbridge/intel/e7520/raminit.h | 6 +++--- src/northbridge/intel/e7525/raminit.h | 6 +++--- src/northbridge/intel/fsp_sandybridge/raminit.h | 6 +++--- src/northbridge/intel/haswell/raminit.h | 6 +++--- src/northbridge/intel/i440bx/raminit.h | 6 +++--- src/northbridge/intel/i440lx/raminit.h | 6 +++--- src/northbridge/intel/i945/raminit.h | 6 +++--- src/northbridge/intel/nehalem/raminit.h | 6 +++--- src/northbridge/intel/sandybridge/raminit.h | 6 +++--- src/northbridge/intel/sandybridge/raminit_native.h | 6 +++--- src/northbridge/intel/sch/raminit.h | 6 +++--- src/northbridge/via/cn400/raminit.h | 6 +++--- src/northbridge/via/cn700/raminit.h | 6 +++--- src/northbridge/via/cx700/raminit.h | 6 +++--- src/northbridge/via/vt8601/raminit.h | 6 +++--- src/northbridge/via/vt8623/raminit.h | 6 +++--- src/northbridge/via/vx800/raminit.h | 6 +++--- 24 files changed, 72 insertions(+), 73 deletions(-) diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 8ecdac3..a93e2f0 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef AMDFAM10_RAMINIT_H +#define AMDFAM10_RAMINIT_H #if 0 #if CONFIG_DIMM_SUPPORT==0x0110 @@ -69,5 +69,4 @@ struct mem_controller { //#endif - -#endif +#endif /* AMDFAM10_RAMINIT_H */ diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 9da8417..f428029 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef AMDK8_RAMINIT_H +#define AMDK8_RAMINIT_H #define NODE_NUMS 8 @@ -21,4 +21,4 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl, void * void sdram_initialize(int controllers, const struct mem_controller *ctrl); #endif -#endif /* RAMINIT_H */ +#endif /* AMDK8_RAMINIT_H */ diff --git a/src/northbridge/amd/gx1/raminit.h b/src/northbridge/amd/gx1/raminit.h index 6e40683..4e0c7fc 100644 --- a/src/northbridge/amd/gx1/raminit.h +++ b/src/northbridge/amd/gx1/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef GX1_RAMINIT_H +#define GX1_RAMINIT_H #define DIMM_SOCKETS 4 struct mem_controller { @@ -8,4 +8,4 @@ struct mem_controller { }; -#endif /* RAMINIT_H */ +#endif /* GX1_RAMINIT_H */ diff --git a/src/northbridge/amd/gx2/raminit.h b/src/northbridge/amd/gx2/raminit.h index a49bf20..4464dd7 100644 --- a/src/northbridge/amd/gx2/raminit.h +++ b/src/northbridge/amd/gx2/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef GX2_RAMINIT_H +#define GX2_RAMINIT_H #define DIMM_SOCKETS 2 @@ -9,4 +9,4 @@ struct mem_controller { void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif /* RAMINIT_H */ +#endif /* GX2_RAMINIT_H */ diff --git a/src/northbridge/amd/lx/raminit.h b/src/northbridge/amd/lx/raminit.h index 01d25e9..8bff8bc 100644 --- a/src/northbridge/amd/lx/raminit.h +++ b/src/northbridge/amd/lx/raminit.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef AMD_LX_RAMINIT_H +#define AMD_LX_RAMINIT_H #define DIMM_SOCKETS 2 @@ -36,4 +36,4 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl); /* mainboard specific */ int spd_read_byte(unsigned device, unsigned address); -#endif +#endif /* AMD_LX_RAMINIT_H */ diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h index 05c3889..b1e6ef7 100644 --- a/src/northbridge/intel/e7501/raminit.h +++ b/src/northbridge/intel/e7501/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef E7501_RAMINIT_H +#define E7501_RAMINIT_H #define MAX_DIMM_SOCKETS_PER_CHANNEL 4 #define MAX_NUM_CHANNELS 2 @@ -17,4 +17,4 @@ struct mem_controller { void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif /* RAMINIT_H */ +#endif /* E7501_RAMINIT_H */ diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index 8eb4990..c64569e 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef E7505_RAMINIT_H +#define E7505_RAMINIT_H #define MAX_DIMM_SOCKETS_PER_CHANNEL 4 #define MAX_NUM_CHANNELS 2 @@ -24,4 +24,4 @@ int e7505_mch_is_ready(void); /* Mainboard exports this. */ int spd_read_byte(unsigned device, unsigned address); -#endif /* RAMINIT_H */ +#endif /* E7505_RAMINIT_H */ diff --git a/src/northbridge/intel/e7520/raminit.h b/src/northbridge/intel/e7520/raminit.h index 9fcc380..4d8c2d0 100644 --- a/src/northbridge/intel/e7520/raminit.h +++ b/src/northbridge/intel/e7520/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef E7520_RAMINIT_H +#define E7520_RAMINIT_H #define DIMM_SOCKETS 4 struct mem_controller { @@ -9,4 +9,4 @@ struct mem_controller { u16 channel1[DIMM_SOCKETS]; }; -#endif /* RAMINIT_H */ +#endif /* E7520_RAMINIT_H */ diff --git a/src/northbridge/intel/e7525/raminit.h b/src/northbridge/intel/e7525/raminit.h index 183ace8..6077321 100644 --- a/src/northbridge/intel/e7525/raminit.h +++ b/src/northbridge/intel/e7525/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef E7525_RAMINIT_H +#define E7525_RAMINIT_H #define DIMM_SOCKETS 4 struct mem_controller { @@ -9,4 +9,4 @@ struct mem_controller { uint16_t channel1[DIMM_SOCKETS]; }; -#endif /* RAMINIT_H */ +#endif /* E7525_RAMINIT_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.h b/src/northbridge/intel/fsp_sandybridge/raminit.h index 73e563f..28e2f52 100644 --- a/src/northbridge/intel/fsp_sandybridge/raminit.h +++ b/src/northbridge/intel/fsp_sandybridge/raminit.h @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef FSP_SANDYBRIDGE_RAMINIT_H +#define FSP_SANDYBRIDGE_RAMINIT_H void report_memory_config(void); -#endif /* RAMINIT_H */ +#endif /* FSP_SANDYBRIDGE_RAMINIT_H */ diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 706c286..fe80605 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef HASWELL_RAMINIT_H +#define HASWELL_RAMINIT_H #include "pei_data.h" @@ -27,4 +27,4 @@ int fixup_haswell_errata(void); /* save_mrc_data() must be called after cbmem has been initialized. */ void save_mrc_data(struct pei_data *pei_data); -#endif /* RAMINIT_H */ +#endif /* HASWELL_RAMINIT_H */ diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index a92c892..dcbee35 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef I440BX_RAMINIT_H +#define I440BX_RAMINIT_H /* The 440BX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4 @@ -36,4 +36,4 @@ void dump_pci_device(unsigned dev); #else #define dump_spd_registers() #endif -#endif /* RAMINIT_H */ +#endif /* I440BX_RAMINIT_H */ diff --git a/src/northbridge/intel/i440lx/raminit.h b/src/northbridge/intel/i440lx/raminit.h index 3b906e9..8482a38 100644 --- a/src/northbridge/intel/i440lx/raminit.h +++ b/src/northbridge/intel/i440lx/raminit.h @@ -19,10 +19,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef I440LX_RAMINIT_H +#define I440LX_RAMINIT_H /* The 440LX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4 -#endif /* RAMINIT_H */ +#endif /* I440LX_RAMINIT_H */ diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 9eb4193..e20e2d1 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef I945_RAMINIT_H +#define I945_RAMINIT_H #define DIMM_SOCKETS 2 @@ -75,4 +75,4 @@ void udelay(u32 us); #if CONFIG_DEBUG_RAM_SETUP void sdram_dump_mchbar_registers(void); #endif -#endif /* RAMINIT_H */ +#endif /* I945_RAMINIT_H */ diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/nehalem/raminit.h index 0485694..9400a26 100644 --- a/src/northbridge/intel/nehalem/raminit.h +++ b/src/northbridge/intel/nehalem/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NEHALEM_RAMINIT_H +#define NEHALEM_RAMINIT_H #include "nehalem.h" @@ -32,4 +32,4 @@ void chipset_init(const int s3resume); */ void raminit(const int s3resume, const u8 *spd_addrmap); -#endif /* RAMINIT_H */ +#endif /* NEHALEM_RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index c3b1c2a..2785cff 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef SANDYBRIDGE_RAMINIT_H +#define SANDYBRIDGE_RAMINIT_H #include "pei_data.h" @@ -33,4 +33,4 @@ void sdram_initialize(struct pei_data *pei_data); void save_mrc_data(struct pei_data *pei_data); int fixup_sandybridge_errata(void); -#endif /* RAMINIT_H */ +#endif /* SANDYBRIDGE_RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index 7ed75ff..0cab066 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef RAMINIT_NATIVE_H +#define RAMINIT_NATIVE_H #include <device/dram/ddr3.h> @@ -26,4 +26,4 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int s3resume); void read_spd(spd_raw_data *spd, u8 addr); -#endif /* RAMINIT_H */ +#endif /* RAMINIT_NATIVE_H */ diff --git a/src/northbridge/intel/sch/raminit.h b/src/northbridge/intel/sch/raminit.h index f139490..bcddb03 100644 --- a/src/northbridge/intel/sch/raminit.h +++ b/src/northbridge/intel/sch/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef SCH_RAMINIT_H +#define SCH_RAMINIT_H /** * Bit Equates @@ -179,4 +179,4 @@ struct sys_info { void sdram_initialize(int boot_mode); -#endif /* RAMINIT_H */ +#endif /* SCH_RAMINIT_H */ diff --git a/src/northbridge/via/cn400/raminit.h b/src/northbridge/via/cn400/raminit.h index 89ea0d6..df98d60 100644 --- a/src/northbridge/via/cn400/raminit.h +++ b/src/northbridge/via/cn400/raminit.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef CN400_RAMINIT_H +#define CN400_RAMINIT_H #define DIMM_SOCKETS 1 /* Only one works, for now. */ @@ -28,4 +28,4 @@ struct mem_controller { u8 channel0[DIMM_SOCKETS]; }; -#endif +#endif /* CN400_RAMINIT_H */ diff --git a/src/northbridge/via/cn700/raminit.h b/src/northbridge/via/cn700/raminit.h index 89ea0d6..f58d7ed 100644 --- a/src/northbridge/via/cn700/raminit.h +++ b/src/northbridge/via/cn700/raminit.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef CN700_RAMINIT_H +#define CN700_RAMINIT_H #define DIMM_SOCKETS 1 /* Only one works, for now. */ @@ -28,4 +28,4 @@ struct mem_controller { u8 channel0[DIMM_SOCKETS]; }; -#endif +#endif /* CN700_RAMINIT_H */ diff --git a/src/northbridge/via/cx700/raminit.h b/src/northbridge/via/cx700/raminit.h index 98e21f0..30434ba 100644 --- a/src/northbridge/via/cx700/raminit.h +++ b/src/northbridge/via/cx700/raminit.h @@ -17,12 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef CX700_RAMINIT_H +#define CX700_RAMINIT_H #define DIMM_SOCKETS 2 struct mem_controller { u16 channel0[DIMM_SOCKETS]; }; -#endif +#endif /* CX700_RAMINIT_H */ diff --git a/src/northbridge/via/vt8601/raminit.h b/src/northbridge/via/vt8601/raminit.h index b6d2339..de94452 100644 --- a/src/northbridge/via/vt8601/raminit.h +++ b/src/northbridge/via/vt8601/raminit.h @@ -1,8 +1,8 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef VT8601_RAMINIT_H +#define VT8601_RAMINIT_H struct mem_controller { int empty; }; -#endif /* RAMINIT_H */ +#endif /* VT8601_RAMINIT_H */ diff --git a/src/northbridge/via/vt8623/raminit.h b/src/northbridge/via/vt8623/raminit.h index b6d2339..c41b4fa 100644 --- a/src/northbridge/via/vt8623/raminit.h +++ b/src/northbridge/via/vt8623/raminit.h @@ -1,8 +1,8 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef VT8623_RAMINIT_H +#define VT8623_RAMINIT_H struct mem_controller { int empty; }; -#endif /* RAMINIT_H */ +#endif /* VT8623_RAMINIT_H */ diff --git a/src/northbridge/via/vx800/raminit.h b/src/northbridge/via/vx800/raminit.h index 4c4990c..df3fa5d 100644 --- a/src/northbridge/via/vx800/raminit.h +++ b/src/northbridge/via/vx800/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef VX800_RAMINIT_H +#define VX800_RAMINIT_H #define MEMCTRL PCI_DEV(0,0,3) -#endif /* RAMINIT_H */ +#endif /* VX800_RAMINIT_H */

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Patch set updated for coreboot: f242254 superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6463 -gerrit commit f242254184e05944cd4cfff96dc1f94dcb88f725 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 20:08:35 2014 +1000 superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match. Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/Kconfig | 1 + src/mainboard/amd/dinar/romstage.c | 6 ++---- src/superio/smsc/sio1036/Makefile.inc | 1 + src/superio/smsc/sio1036/sio1036.h | 5 +++++ src/superio/smsc/sio1036/sio1036_early_init.c | 15 +++++++-------- 5 files changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index e826459..b71c5a5 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY15 select NORTHBRIDGE_AMD_CIMX_RD890 select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_SMSC_SIO1036 select SUPERIO_SMSC_SCH4037 select BOARD_ROMSIZE_KB_2048 select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 842b4f0..1700166 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -33,13 +33,11 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" -#include "superio/smsc/sio1036/sio1036_early_init.c" +#include <superio/smsc/sio1036/sio1036.h> #include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -53,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { /* Found SMSC SIO1036 LPC Debug Card */ - sio1036_early_init(0x4E); + sio1036_early_init(0x4E, CONFIG_TTYS0_BASE); } post_code(0x31); diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc index f09d451..c4b6138 100644 --- a/src/superio/smsc/sio1036/Makefile.inc +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index e61b600..6049d36 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -26,4 +26,9 @@ #define LPT_POWER_DOWN (1 << 2) #define IR_OUPUT_MUX (1 << 6) +#include <stdint.h> + +u8 detect_sio1036_chip(unsigned port); +void sio1036_early_init(unsigned port, u16 iobase); + #endif /* SUPERIO_SMSC_1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..ab1d282 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -20,24 +20,23 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ #include <arch/io.h> +#include <stdint.h> + #include "sio1036.h" -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3F8 -#endif static inline void sio1036_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0x55, port); } static inline void sio1036_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0xaa, port); } -static u8 detect_sio1036_chip(unsigned port) +u8 detect_sio1036_chip(unsigned port) { device_t dev; dev = PNP_DEV (port, SIO1036_SP1); @@ -55,7 +54,7 @@ static u8 detect_sio1036_chip(unsigned port) }; } -static inline void sio1036_early_init(unsigned port) +void sio1036_early_init(unsigned port, u16 iobase) { device_t dev; dev = PNP_DEV (port, SIO1036_SP1); @@ -91,7 +90,7 @@ static inline void sio1036_early_init(unsigned port) /* Enable SMSC UART 0 */ /*Set base io address */ - pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + pnp_write_config (dev, 0x25, (u8)(iobase >> 2)); /* Set UART IRQ onto 0x04 */ pnp_write_config (dev, 0x28, 0x04);

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Patch set updated for coreboot: d1583dc superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6463 -gerrit commit d1583dc6b3588572d287dd0dc470d0d74cb1e733 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 20:08:35 2014 +1000 superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match. Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/romstage.c | 6 ++---- src/superio/smsc/sio1036/Makefile.inc | 1 + src/superio/smsc/sio1036/sio1036.h | 5 +++++ src/superio/smsc/sio1036/sio1036_early_init.c | 15 +++++++-------- 4 files changed, 15 insertions(+), 12 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 842b4f0..1700166 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -33,13 +33,11 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" -#include "superio/smsc/sio1036/sio1036_early_init.c" +#include <superio/smsc/sio1036/sio1036.h> #include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -53,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { /* Found SMSC SIO1036 LPC Debug Card */ - sio1036_early_init(0x4E); + sio1036_early_init(0x4E, CONFIG_TTYS0_BASE); } post_code(0x31); diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc index f09d451..c4b6138 100644 --- a/src/superio/smsc/sio1036/Makefile.inc +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index e61b600..6049d36 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -26,4 +26,9 @@ #define LPT_POWER_DOWN (1 << 2) #define IR_OUPUT_MUX (1 << 6) +#include <stdint.h> + +u8 detect_sio1036_chip(unsigned port); +void sio1036_early_init(unsigned port, u16 iobase); + #endif /* SUPERIO_SMSC_1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..ab1d282 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -20,24 +20,23 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ #include <arch/io.h> +#include <stdint.h> + #include "sio1036.h" -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3F8 -#endif static inline void sio1036_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0x55, port); } static inline void sio1036_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0xaa, port); } -static u8 detect_sio1036_chip(unsigned port) +u8 detect_sio1036_chip(unsigned port) { device_t dev; dev = PNP_DEV (port, SIO1036_SP1); @@ -55,7 +54,7 @@ static u8 detect_sio1036_chip(unsigned port) }; } -static inline void sio1036_early_init(unsigned port) +void sio1036_early_init(unsigned port, u16 iobase) { device_t dev; dev = PNP_DEV (port, SIO1036_SP1); @@ -91,7 +90,7 @@ static inline void sio1036_early_init(unsigned port) /* Enable SMSC UART 0 */ /*Set base io address */ - pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + pnp_write_config (dev, 0x25, (u8)(iobase >> 2)); /* Set UART IRQ onto 0x04 */ pnp_write_config (dev, 0x28, 0x04);

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New patch to review for coreboot: ec33d6b superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6463 -gerrit commit ec33d6bf94556268ba04fb736155d77343b53e12 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 20:08:35 2014 +1000 superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match. Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/romstage.c | 4 ++-- src/superio/smsc/sio1036/Makefile.inc | 1 + src/superio/smsc/sio1036/sio1036.h | 4 ++++ src/superio/smsc/sio1036/sio1036_early_init.c | 13 ++++++------- 4 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 842b4f0..6e217f1 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -33,7 +33,7 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" -#include "superio/smsc/sio1036/sio1036_early_init.c" +#include <superio/smsc/sio1036/sio1036.h> #include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> @@ -53,7 +53,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { /* Found SMSC SIO1036 LPC Debug Card */ - sio1036_early_init(0x4E); + sio1036_early_init(0x4E, CONFIG_TTYS0_BASE); } post_code(0x31); diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc index f09d451..c4b6138 100644 --- a/src/superio/smsc/sio1036/Makefile.inc +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index e61b600..d6b7978 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -26,4 +26,8 @@ #define LPT_POWER_DOWN (1 << 2) #define IR_OUPUT_MUX (1 << 6) +#include <stdint.h> + +void sio1036_early_init(unsigned port, u16 iobase); + #endif /* SUPERIO_SMSC_1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..be91669 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -20,20 +20,19 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ #include <arch/io.h> +#include <stdint.h> + #include "sio1036.h" -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3F8 -#endif static inline void sio1036_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0x55, port); } static inline void sio1036_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0xaa, port); } @@ -55,7 +54,7 @@ static u8 detect_sio1036_chip(unsigned port) }; } -static inline void sio1036_early_init(unsigned port) +void sio1036_early_init(unsigned port, u16 iobase) { device_t dev; dev = PNP_DEV (port, SIO1036_SP1); @@ -91,7 +90,7 @@ static inline void sio1036_early_init(unsigned port) /* Enable SMSC UART 0 */ /*Set base io address */ - pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + pnp_write_config (dev, 0x25, (u8)(iobase >> 2)); /* Set UART IRQ onto 0x04 */ pnp_write_config (dev, 0x28, 0x04);

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Patch set updated for coreboot: 124ff70 intel eagleheights & xe7501devkit 'ioapic.h': Add missing header guards
by HAOUAS Elyes 02 Aug '14

02 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6449 -gerrit commit 124ff7012e5d30b6712108179c392c24b9015d65 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Aug 2 08:32:10 2014 +0200 intel eagleheights & xe7501devkit 'ioapic.h': Add missing header guards Change-Id: I010ce8e66a01367611b822bea7d1907eab166917 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/intel/eagleheights/ioapic.h | 5 +++++ src/mainboard/intel/xe7501devkit/ioapic.h | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/src/mainboard/intel/eagleheights/ioapic.h b/src/mainboard/intel/eagleheights/ioapic.h index 4ac7d62..2f0a8d3 100644 --- a/src/mainboard/intel/eagleheights/ioapic.h +++ b/src/mainboard/intel/eagleheights/ioapic.h @@ -1,2 +1,7 @@ +#ifndef EAGLEHEIGHTS_IOAPIC_H +#define EAGLEHEIGHTS_IOAPIC_H + #define IOAPIC_I3100 2 #define INTEL_IOAPIC_NUM_INTERRUPTS 24 + +#endif /* EAGLEHEIGHTS_IOAPIC_H */ diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h index 9ac2aee..6a329d5 100644 --- a/src/mainboard/intel/xe7501devkit/ioapic.h +++ b/src/mainboard/intel/xe7501devkit/ioapic.h @@ -1,5 +1,7 @@ // IOAPIC addresses determined by coreboot enumeration. // Someday add functions to get APIC IDs and versions from the chips themselves. +#ifndef XE7501DEVKIT_IOAPIC_H +#define XE7501DEVKIT_IOAPIC_H #define IOAPIC_ICH3 2 #define IOAPIC_P64H2_2_BUS_B 3 // IOAPIC 3 at 01:1c.0 MBAR = fe300000 DataAddr = fe300010 @@ -9,3 +11,5 @@ #define P64H2_IOAPIC_VERSION 0x20 #define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-3 and P64-H2 + +#endif /* XE7501DEVKIT_IOAPIC_H */

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New patch to review for coreboot: 8bc2f8b cpu/x86/smm/Makefile.inc: Correct SMM linkage under clang builds
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6462 -gerrit commit 8bc2f8b54de98a735596e875f01192c896027e1b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 14:51:30 2014 +1000 cpu/x86/smm/Makefile.inc: Correct SMM linkage under clang builds Ensure that the SMM build stage links properly using the compiler-rt runtime under a Clang build. Change-Id: Iead28c46d63f5bbb27757b7dc66fe06b4813d03c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/x86/smm/Makefile.inc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index ff4023b..ef6b80e 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -83,11 +83,20 @@ endif smm-y += smihandler.c +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) +$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBCLANG_RT_FILE_NAME_smm) + $(LD_smm) -nostdlib -r -o $@ --start-group $(smm-objs) $(LIBCLANG_RT_FILE_NAME_smm) --end-group +else $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME_smm) $(CC_smm) $(CFLAGS_smm) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME_smm) -Wl,--end-group +endif $(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD_smm) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o +else $(CC_smm) $(CFLAGS_smm) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o +endif $(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm

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coreboot-gerrit August 2014