coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 36e607a build: Allow clang build linkage to use libcompiler-rt
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6144 -gerrit commit 36e607a2afcdf6234b6f1ed74e7110c6a770f6c2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 03:02:52 2014 +1000 build: Allow clang build linkage to use libcompiler-rt NOTFORMERGE: (pending one more patch upstream) NOTE: *** Requires at least clang 3.5.0 r211866. Change-Id: I7f63284473d6067bf775409970c8dd98f5d5a8d5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 4 +++- src/arch/x86/Makefile.inc | 6 +++--- toolchain.inc | 1 + 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index a55ad67..1762323 100644 --- a/Makefile +++ b/Makefile @@ -118,7 +118,9 @@ include $(HAVE_DOTCONFIG) ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # FIXME: armv7/aarch64 won't build right now -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-elf -m32 +# NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a +# this means the triple is i386-linux-elf instead of i386-none-elf +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 CC_x86_32:=clang ifneq ($(CONFIG_MMX),y) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2e92d89..b1d0e94 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -209,7 +209,7 @@ romstage-libs ?= $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_null.ld + $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBCLANG_RT_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_null.ld else $(CC_romstage) $(CFLAGS_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif @@ -221,7 +221,7 @@ endif $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_xip.ld + $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBCLANG_RT_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_xip.ld else $(CC_romstage) $(CFLAGS_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif @@ -332,7 +332,7 @@ endif $(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_ramstage) -m elf_i386 -r -o $@ --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) --end-group + $(LD_ramstage) -m elf_i386 -r -o $@ --start-group $(ramstage-objs) $(ramstage-libs) $(LIBCLANG_RT_FILE_NAME_ramstage) --end-group else $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group endif diff --git a/toolchain.inc b/toolchain.inc index 842473b..d9d1817 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -96,6 +96,7 @@ READELF_$(1) := $(READELF_$(2)) CFLAGS_$(1) += $$(CFLAGS_common) $$(CFLAGS_$(2)) CPPFLAGS_$(1) += $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) LIBGCC_FILE_NAME_$(1) = $(wildcard $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-libgcc-file-name)) +LIBCLANG_RT_FILE_NAME_$(1) = $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-librt-file-name) endef # initialize standard toolchain (CC,AS and others) for give stage

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Patch set updated for coreboot: bd8b976 northbridge/intel/*/gma.c: Remove dead code
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6130 -gerrit commit bd8b9764a16f0bd0fca02d64df0e76d0ebffa364 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jun 26 22:33:03 2014 +1000 northbridge/intel/*/gma.c: Remove dead code Remove some dead coded spotted in Clang builds. Change-Id: Ia23e16eae76593eee249e0894ef1d704a274616f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/nehalem/gma.c | 56 --------------------------------- src/northbridge/intel/sandybridge/gma.c | 56 --------------------------------- 2 files changed, 112 deletions(-) diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index bc4c74d..2470b0f 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -144,62 +144,6 @@ static const struct gt_powermeter ivb_pm_gt1[] = { {0} }; -static const struct gt_powermeter ivb_pm_gt2[] = { - {0xa800, 0x10000000}, - {0xa804, 0x00033800}, - {0xa808, 0x00000902}, - {0xa80c, 0x0c002f00}, - {0xa810, 0x12000400}, - {0xa814, 0x00000000}, - {0xa818, 0x00d20800}, - {0xa81c, 0x00000002}, - {0xa820, 0x03004b02}, - {0xa824, 0x00000600}, - {0xa828, 0x07000773}, - {0xa82c, 0x00000000}, - {0xa830, 0x00010032}, - {0xa834, 0x1520040d}, - {0xa838, 0x00020105}, - {0xa83c, 0x00083700}, - {0xa840, 0x0000151d}, - {0xa844, 0x00000000}, - {0xa848, 0x20001b00}, - {0xa84c, 0x0a000010}, - {0xa850, 0x00000000}, - {0xa854, 0x00000008}, - {0xa858, 0x00000008}, - {0xa85c, 0x00000000}, - {0xa860, 0x00020000}, - {0xa248, 0x0000221e}, - {0xa900, 0x00000000}, - {0xa904, 0x00003500}, - {0xa908, 0x00000000}, - {0xa90c, 0x0c000000}, - {0xa910, 0x12000500}, - {0xa914, 0x00000000}, - {0xa918, 0x00b20000}, - {0xa91c, 0x00000000}, - {0xa920, 0x08004b02}, - {0xa924, 0x00000200}, - {0xa928, 0x07000820}, - {0xa92c, 0x00000000}, - {0xa930, 0x00030000}, - {0xa934, 0x050f020d}, - {0xa938, 0x00020300}, - {0xa93c, 0x00903900}, - {0xa940, 0x00000000}, - {0xa944, 0x00000000}, - {0xa948, 0x20001b00}, - {0xa94c, 0x0a000010}, - {0xa950, 0x00000000}, - {0xa954, 0x00000008}, - {0xa960, 0x00110000}, - {0xaa3c, 0x00003900}, - {0xaa54, 0x00000008}, - {0xaa60, 0x00110000}, - {0} -}; - static const struct gt_powermeter ivb_pm_gt2_17w[] = { {0xa800, 0x20000000}, {0xa804, 0x000e3800}, diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index a01fe9f..0add055 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -139,62 +139,6 @@ static const struct gt_powermeter ivb_pm_gt1[] = { { 0 } }; -static const struct gt_powermeter ivb_pm_gt2[] = { - { 0xa800, 0x10000000 }, - { 0xa804, 0x00033800 }, - { 0xa808, 0x00000902 }, - { 0xa80c, 0x0c002f00 }, - { 0xa810, 0x12000400 }, - { 0xa814, 0x00000000 }, - { 0xa818, 0x00d20800 }, - { 0xa81c, 0x00000002 }, - { 0xa820, 0x03004b02 }, - { 0xa824, 0x00000600 }, - { 0xa828, 0x07000773 }, - { 0xa82c, 0x00000000 }, - { 0xa830, 0x00010032 }, - { 0xa834, 0x1520040d }, - { 0xa838, 0x00020105 }, - { 0xa83c, 0x00083700 }, - { 0xa840, 0x0000151d }, - { 0xa844, 0x00000000 }, - { 0xa848, 0x20001b00 }, - { 0xa84c, 0x0a000010 }, - { 0xa850, 0x00000000 }, - { 0xa854, 0x00000008 }, - { 0xa858, 0x00000008 }, - { 0xa85c, 0x00000000 }, - { 0xa860, 0x00020000 }, - { 0xa248, 0x0000221e }, - { 0xa900, 0x00000000 }, - { 0xa904, 0x00003500 }, - { 0xa908, 0x00000000 }, - { 0xa90c, 0x0c000000 }, - { 0xa910, 0x12000500 }, - { 0xa914, 0x00000000 }, - { 0xa918, 0x00b20000 }, - { 0xa91c, 0x00000000 }, - { 0xa920, 0x08004b02 }, - { 0xa924, 0x00000200 }, - { 0xa928, 0x07000820 }, - { 0xa92c, 0x00000000 }, - { 0xa930, 0x00030000 }, - { 0xa934, 0x050f020d }, - { 0xa938, 0x00020300 }, - { 0xa93c, 0x00903900 }, - { 0xa940, 0x00000000 }, - { 0xa944, 0x00000000 }, - { 0xa948, 0x20001b00 }, - { 0xa94c, 0x0a000010 }, - { 0xa950, 0x00000000 }, - { 0xa954, 0x00000008 }, - { 0xa960, 0x00110000 }, - { 0xaa3c, 0x00003900 }, - { 0xaa54, 0x00000008 }, - { 0xaa60, 0x00110000 }, - { 0 } -}; - static const struct gt_powermeter ivb_pm_gt2_17w[] = { { 0xa800, 0x20000000 }, { 0xa804, 0x000e3800 },

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Patch set updated for coreboot: 36472f7 Re-factor 'to_flash_offset()' into 'spi_flash.h'
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5834 -gerrit commit 36472f77080af9c9864cd0304c762ac45c4fb409 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:09:50 2014 +1000 Re-factor 'to_flash_offset()' into 'spi_flash.h' Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by Clang complaining that the function 'to_flash_offset' is unused. Change-Id: I129cf8349e9ee2ebd4a4d0f69a6d830bdbc4ebf0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/intel/fsp/fastboot_cache.c | 13 ++----------- src/include/spi_flash.h | 15 +++++++++++++++ src/northbridge/intel/haswell/mrccache.c | 8 ++------ src/northbridge/intel/sandybridge/mrccache.c | 8 ++------ src/soc/intel/baytrail/nvm.c | 10 ++-------- src/soc/intel/fsp_baytrail/nvm.c | 13 ++----------- 6 files changed, 25 insertions(+), 42 deletions(-) diff --git a/src/drivers/intel/fsp/fastboot_cache.c b/src/drivers/intel/fsp/fastboot_cache.c index 64982d8..907e143 100644 --- a/src/drivers/intel/fsp/fastboot_cache.c +++ b/src/drivers/intel/fsp/fastboot_cache.c @@ -31,15 +31,6 @@ #include <lib.h> // hexdump #include "fsp_util.h" -#ifndef CONFIG_VIRTUAL_ROM_SIZE -#error "CONFIG_VIRTUAL_ROM_SIZE must be set." -#endif - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -205,7 +196,7 @@ void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -213,7 +204,7 @@ void update_mrc_cache(void *unused) /* 4. write mrc data with flash->write() */ printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); } diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 70ca784..94ac284 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -76,4 +76,19 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, return flash->erase(flash, offset, len); } +#ifndef CONFIG_VIRTUAL_ROM_SIZE +#error "CONFIG_VIRTUAL_ROM_SIZE must be set." +#endif + +#if !defined(__PRE_RAM__) +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { +#if defined(CONFIG_VIRTUAL_ROM_SIZE) + return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); +#else + return ((u32)p + flash->size); +#endif /* defined(CONFIG_VIRTUAL_ROM_SIZE) */ +} +#endif /* !defined(__PRE_RAM__) */ + #endif /* _SPI_FLASH_H_ */ diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index a921e04..73b4429 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -124,6 +119,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ + #if !defined(__PRE_RAM__) /* find the first empty block in the MRC cache area. * If there's none, return NULL. @@ -228,7 +224,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..2a1f353 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -123,6 +118,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ + #if !defined(__PRE_RAM__) /* find the first empty block in the MRC cache area. * If there's none, return NULL. @@ -227,7 +223,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/baytrail/nvm.c b/src/soc/intel/baytrail/nvm.c index 0cc64f5..a880984 100644 --- a/src/soc/intel/baytrail/nvm.c +++ b/src/soc/intel/baytrail/nvm.c @@ -46,12 +46,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -70,7 +64,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + flash->erase(flash, to_flash_offset(flash, start), size); return 0; } @@ -79,6 +73,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + flash->write(flash, to_flash_offset(flash, start), size, data); return 0; } diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c index 0224463..d1e5223 100644 --- a/src/soc/intel/fsp_baytrail/nvm.c +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -47,15 +47,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ -#ifndef CONFIG_ROM_SIZE -#error CONFIG_ROM_SIZE must be set. -#endif - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -74,7 +65,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + flash->erase(flash, to_flash_offset(flash, start), size); return 0; } @@ -83,6 +74,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + flash->write(flash, to_flash_offset(flash, start), size, data); return 0; }

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New patch to review for coreboot: 54a5249 lenovo/t530: Make use of gpio.h for gpio configuration
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6461 -gerrit commit 54a524999587e669f0324395efbb539fb0571346 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 12:58:29 2014 +1000 lenovo/t530: Make use of gpio.h for gpio configuration Rather than using 'outl()' calls directly, update and use gpio.h struct's with the internal southbridge resource allocator to do the write outs. Change-Id: I289e525f34ce74dba2f4d6ab55a30b155beb0e24 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/gpio.h | 143 +++++++++++++++++++++++------------ src/mainboard/lenovo/t530/romstage.c | 14 +--- 2 files changed, 97 insertions(+), 60 deletions(-) diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.h index 70e4c09..f741eb3 100644 --- a/src/mainboard/lenovo/t530/gpio.h +++ b/src/mainboard/lenovo/t530/gpio.h @@ -23,6 +23,7 @@ #include "southbridge/intel/bd82x6x/gpio.h" +/* outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); */ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, @@ -32,32 +33,33 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio5 = GPIO_MODE_GPIO, .gpio6 = GPIO_MODE_GPIO, .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_NATIVE, - .gpio10 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_NATIVE, .gpio11 = GPIO_MODE_NATIVE, - .gpio12 = GPIO_MODE_NATIVE, - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_NATIVE, - .gpio15 = GPIO_MODE_GPIO, - .gpio16 = GPIO_MODE_NATIVE, - .gpio17 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_NATIVE, .gpio18 = GPIO_MODE_NATIVE, .gpio19 = GPIO_MODE_NATIVE, - .gpio20 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, .gpio21 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio23 = GPIO_MODE_NATIVE, - .gpio24 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_NATIVE, .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, .gpio27 = GPIO_MODE_GPIO, .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, .gpio30 = GPIO_MODE_NATIVE, .gpio31 = GPIO_MODE_NATIVE, }; +/* outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); */ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, @@ -93,47 +95,86 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT }; +/* outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); */ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_HIGH, .gpio3 = GPIO_LEVEL_HIGH, .gpio4 = GPIO_LEVEL_HIGH, - .gpio5 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, .gpio6 = GPIO_LEVEL_HIGH, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, .gpio9 = GPIO_LEVEL_HIGH, .gpio10 = GPIO_LEVEL_HIGH, .gpio11 = GPIO_LEVEL_HIGH, .gpio12 = GPIO_LEVEL_HIGH, .gpio13 = GPIO_LEVEL_HIGH, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio17 = GPIO_LEVEL_HIGH, - .gpio18 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, .gpio19 = GPIO_LEVEL_HIGH, - .gpio20 = GPIO_LEVEL_HIGH, - .gpio21 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_LOW, .gpio31 = GPIO_LEVEL_LOW, }; +/* Output Control Registers */ +/* outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); */ +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +/* outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); */ const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; +/* outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); */ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, @@ -169,10 +210,11 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; +/* outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); */ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, .gpio35 = GPIO_DIR_INPUT, .gpio36 = GPIO_DIR_INPUT, .gpio37 = GPIO_DIR_INPUT, @@ -204,28 +246,29 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; +/* outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); */ const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, - .gpio33 = GPIO_LEVEL_HIGH, + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_LOW, .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_HIGH, .gpio37 = GPIO_LEVEL_LOW, .gpio38 = GPIO_LEVEL_HIGH, - .gpio39 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_HIGH, .gpio40 = GPIO_LEVEL_HIGH, .gpio41 = GPIO_LEVEL_HIGH, .gpio42 = GPIO_LEVEL_HIGH, .gpio43 = GPIO_LEVEL_HIGH, .gpio44 = GPIO_LEVEL_HIGH, .gpio45 = GPIO_LEVEL_HIGH, - .gpio46 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_LOW, .gpio47 = GPIO_LEVEL_HIGH, .gpio48 = GPIO_LEVEL_HIGH, .gpio49 = GPIO_LEVEL_HIGH, .gpio50 = GPIO_LEVEL_HIGH, .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, .gpio53 = GPIO_LEVEL_HIGH, .gpio54 = GPIO_LEVEL_HIGH, .gpio55 = GPIO_LEVEL_HIGH, @@ -236,11 +279,13 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio60 = GPIO_LEVEL_HIGH, .gpio61 = GPIO_LEVEL_HIGH, .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_LOW, }; +/* GPIO_USE_SEL3 */ +/* outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); */ const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, + .gpio64 = GPIO_MODE_GPIO, // native = 0, gpio = 1 .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, .gpio67 = GPIO_MODE_GPIO, @@ -254,8 +299,10 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; +/* GP_IO_SEL3 */ +/* outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); */ const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, + .gpio64 = GPIO_DIR_INPUT, // out = 0, in = 1 .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, .gpio67 = GPIO_DIR_INPUT, @@ -269,15 +316,17 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; +/* GP_LVL3 */ +/* outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); */ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, .gpio67 = GPIO_LEVEL_HIGH, .gpio68 = GPIO_LEVEL_LOW, - .gpio69 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, // low = 0 .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_LOW, .gpio72 = GPIO_LEVEL_HIGH, .gpio73 = GPIO_LEVEL_HIGH, .gpio74 = GPIO_LEVEL_HIGH, @@ -289,8 +338,8 @@ const struct pch_gpio_map t530_gpio_map = { .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, .invert = &pch_gpio_set1_invert, - }, .set2 = { .mode = &pch_gpio_set2_mode, diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 685572d..937e6fe 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -181,19 +181,7 @@ void main(unsigned long bist) pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); -// setup_pch_gpios(&t530_gpio_map); - /* ICH7 GPIOBASE */ - outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); - outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); - outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); - outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); - outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); - outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); - outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); - outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); - outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); - outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); - outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); + setup_pch_gpios(&t530_gpio_map); /* Initialize console device(s) */ console_init();

1 0

New patch to review for coreboot: 1e4d7d5 payloads/external/SeaBIOS: retain the built binary
by Idwer Vollering 02 Aug '14

02 Aug '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6460 -gerrit commit 1e4d7d513a464ca030b821e46f856240ed2a80e2 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sat Aug 2 03:36:09 2014 +0200 payloads/external/SeaBIOS: retain the built binary build/ is wiped during 'make clean': move SeaBIOS' build directory out of build/ Change-Id: Ia7d515cd7e349beebcd9b62c9d956137acb73c82 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 26 +++++++++++++------------- src/Kconfig | 2 +- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index a0025f5..1f280b1 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -12,40 +12,40 @@ all: seabios clone: echo " Cloning SeaBIOS from Git" - git clone http://review.coreboot.org/p/seabios.git $(OUT)/seabios + git clone http://review.coreboot.org/p/seabios.git seabios fetch: clone - cd $(OUT)/seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ + cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi checkout: fetch echo " Checking out SeaBIOS revision $(TAG-y)" - cd $(OUT)/seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) config: checkout echo " CONFIG SeaBIOS $(TAG-y)" - echo "CONFIG_COREBOOT=y" > $(OUT)/seabios/.config + echo "CONFIG_COREBOOT=y" > seabios/.config ifeq ($(CONFIG_CONSOLE_SERIAL),y) - echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config - echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> $(OUT)/seabios/.config + echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config + echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config else - echo "# CONFIG_DEBUG_SERIAL is not set" >> $(OUT)/seabios/.config + echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) - echo "# CONFIG_THREAD_OPTIONROMS is not set" >> $(OUT)/seabios/.config + echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config - $(MAKE) -C $(OUT)/seabios olddefconfig OUT=$(OUT)/seabios/out/ + #echo "# CONFIG_SMBIOS is not set" >> seabios/.config + $(MAKE) -C seabios olddefconfig OUT=out/ seabios: config echo " MAKE SeaBIOS $(TAG-y)" - $(MAKE) -C $(OUT)/seabios OUT=$(OUT)/seabios/out/ + $(MAKE) -C seabios OUT=out/ clean: - test -d $(OUT)/seabios && $(MAKE) -C $(OUT)/seabios clean OUT=$(OUT)/seabios/out/ || exit 0 + test -d seabios && $(MAKE) -C seabios clean OUT=out/ || exit 0 distclean: - rm -rf $(OUT)/seabios + rm -rf seabios .PHONY: clone fetch checkout config seabios clean distclean diff --git a/src/Kconfig b/src/Kconfig index af82353..8127315 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -671,7 +671,7 @@ config PAYLOAD_FILE config PAYLOAD_FILE depends on PAYLOAD_SEABIOS - default "$(obj)/seabios/out/bios.bin.elf" + default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" config PAYLOAD_FILE depends on PAYLOAD_FILO

1 0

Patch set updated for coreboot: 95ea1a6 payloads/external/SeaBIOS: Makefile.inc cosmetics
by Idwer Vollering 02 Aug '14

02 Aug '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6387 -gerrit commit 95ea1a64cdd9f2a0d972a1221e3e07abbaecc78c Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sat Aug 2 03:22:03 2014 +0200 payloads/external/SeaBIOS: Makefile.inc cosmetics Change-Id: I561b209798396d995984c244890e54f31671b5b1 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 21f933a..a0025f5 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -8,13 +8,13 @@ unexport KCONFIG_SPLITCONFIG unexport KCONFIG_TRISTATE unexport KCONFIG_NEGATIVES -all: build +all: seabios -$(OUT)/seabios: +clone: echo " Cloning SeaBIOS from Git" git clone http://review.coreboot.org/p/seabios.git $(OUT)/seabios -fetch: $(OUT)/seabios +fetch: clone cd $(OUT)/seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi @@ -38,7 +38,7 @@ endif #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config $(MAKE) -C $(OUT)/seabios olddefconfig OUT=$(OUT)/seabios/out/ -build: config +seabios: config echo " MAKE SeaBIOS $(TAG-y)" $(MAKE) -C $(OUT)/seabios OUT=$(OUT)/seabios/out/ @@ -48,4 +48,4 @@ clean: distclean: rm -rf $(OUT)/seabios -.PHONY: checkout config build clean distclean clone fetch +.PHONY: clone fetch checkout config seabios clean distclean

1 0

Patch set updated for coreboot: 2977287 util/inteltool: Typo in dump output for 'GP_IO_SEL3'
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6459 -gerrit commit 297728764a99a5ba844f277a8d34e7112c4748c2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 10:15:44 2014 +1000 util/inteltool: Typo in dump output for 'GP_IO_SEL3' The GPIO offset of '0x44 - GP_IO_SEL3' as specified in the pch.h header is incorrectly reported as 'GPIO_SEL3'. Change-Id: I56dcdda109d5f57ed45938d60b995807bdfb46b1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- util/inteltool/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 42e7272..49c1325 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -188,7 +188,7 @@ static const io_register_t ich10_gpio_registers[] = { { 0x38, 4, "GP_LVL2" }, { 0x3C, 4, "RESERVED" }, { 0x40, 4, "GPIO_USE_SEL3" }, - { 0x44, 4, "GPIO_SEL3" }, + { 0x44, 4, "GP_IO_SEL3" }, { 0x48, 4, "GPIO_LVL3" }, { 0x4c, 4, "RESERVED" }, { 0x50, 4, "RESERVED" }, @@ -242,7 +242,7 @@ static const io_register_t pch_gpio_registers[] = { { 0x38, 4, "GP_LVL2" }, { 0x3c, 4, "RESERVED" }, { 0x40, 4, "GPIO_USE_SEL3" }, - { 0x44, 4, "GPIO_SEL3" }, + { 0x44, 4, "GP_IO_SEL3" }, { 0x48, 4, "GPIO_LVL3" }, { 0x4c, 4, "RESERVED" }, { 0x50, 4, "RESERVED" },

1 0

Patch set updated for coreboot: be11dcf lenovo/t530: Be safe by disabling blink gpio hw with a writeout
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6436 -gerrit commit be11dcf0a0b401ad1a64dcf3a22a01ffae11ddf4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:30:21 2014 +1000 lenovo/t530: Be safe by disabling blink gpio hw with a writeout This disables the blink hardware as it seems to be in the dump. This is safer as it does not rely on 0 as the reset value when '0x00040000' is the default according to the util/inteltool. As seen: gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 2412807..685572d 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -186,6 +186,7 @@ void main(unsigned long bist) outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); + outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2);

1 0

Patch set updated for coreboot: 23496c3 lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6435 -gerrit commit 23496c3189c6193216a370255e42d89f1f7dddc6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:29:40 2014 +1000 lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header Use defines of offsets rather than hard coded values. Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index d65031a..2412807 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -182,16 +182,17 @@ void main(unsigned long bist) pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); // setup_pch_gpios(&t530_gpio_map); - outl(0x3962a5ff, DEFAULT_GPIOBASE); - outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); - outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc); - outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); - outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); - outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); - outl(0xffbeff43, DEFAULT_GPIOBASE + 0x38); - outl(0x000000ff, DEFAULT_GPIOBASE + 0x40); - outl(0x00000fff, DEFAULT_GPIOBASE + 0x44); - outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); + /* ICH7 GPIOBASE */ + outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); + outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); + outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); + outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); + outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); + outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); + outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); + outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); + outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); /* Initialize console device(s) */ console_init();

1 0

New patch to review for coreboot: 4ad59c4 util/inteltool: Typo in dump output for 'GP_IO_SEL3'
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6459 -gerrit commit 4ad59c48e57cdb182c5720d04f39af52b1057930 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 10:15:44 2014 +1000 util/inteltool: Typo in dump output for 'GP_IO_SEL3' The GPIO offset of '0x44 - GP_IO_SEL3' as specified in the pch.h header is incorrectly reported as 'GPIO_SEL3'. Change-Id: I56dcdda109d5f57ed45938d60b995807bdfb46b1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- util/inteltool/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 42e7272..49c1325 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -188,7 +188,7 @@ static const io_register_t ich10_gpio_registers[] = { { 0x38, 4, "GP_LVL2" }, { 0x3C, 4, "RESERVED" }, { 0x40, 4, "GPIO_USE_SEL3" }, - { 0x44, 4, "GPIO_SEL3" }, + { 0x44, 4, "GP_IO_SEL3" }, { 0x48, 4, "GPIO_LVL3" }, { 0x4c, 4, "RESERVED" }, { 0x50, 4, "RESERVED" }, @@ -242,7 +242,7 @@ static const io_register_t pch_gpio_registers[] = { { 0x38, 4, "GP_LVL2" }, { 0x3c, 4, "RESERVED" }, { 0x40, 4, "GPIO_USE_SEL3" }, - { 0x44, 4, "GPIO_SEL3" }, + { 0x44, 4, "GP_IO_SEL3" }, { 0x48, 4, "GPIO_LVL3" }, { 0x4c, 4, "RESERVED" }, { 0x50, 4, "RESERVED" },

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coreboot-gerrit August 2014