coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 136d4c0 Re-structuring Payload loading
by Naman Govil 01 Aug '14

01 Aug '14

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6303 -gerrit commit 136d4c048c7d60354f05898fd87114a54ac23ae4 Author: Naman Govil <namangov(a)gmail.com> Date: Fri Jul 18 16:20:38 2014 +0530 Re-structuring Payload loading Removing dependency for mapping entire segments for payload loading by segragating segments by reading metadata and then processing them. Change-Id: I87a52cca7f0270cf7575d2bf5133e17fbb6c9470 Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/include/payload_loader.h | 4 + src/lib/cbfs_core.c | 5 +- src/lib/loaders/cbfs_payload_loader.c | 15 +- src/lib/loaders/load_and_run_payload.c | 3 - src/lib/selfboot.c | 275 ++++++++++++++++++++++++++------- 5 files changed, 231 insertions(+), 71 deletions(-) diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 7a3f045..cac7d27 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,7 @@ #include <stdint.h> #include <stddef.h> +#include <cbfs_core.h> struct buffer_area { void *data; @@ -32,6 +34,8 @@ struct payload { struct buffer_area backing_store; /* Used when payload wants memory coreboot ramstage is running at. */ struct buffer_area bounce; + struct cbfs_media *media; + struct cbfs_file_handle f; void *entry; }; diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 1eee51d..d3f8efb 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -198,6 +198,9 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, struct cbfs_media default_media; void *content; + if (sz) + *sz = 0; + if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { @@ -213,8 +216,6 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, } DEBUG("Found file. Will be mapping it now!\n"); - if (sz) - *sz = 0; if (sz) *sz = f.data_len; diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c index 2c1d179..f0b5bbc 100644 --- a/src/lib/loaders/cbfs_payload_loader.c +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,21 +20,21 @@ #include <cbfs.h> #include <payload_loader.h> +#include <cbfs_core.h> static int cbfs_locate_payload(struct payload *payload) { - void *buffer; - size_t size; const int type = CBFS_TYPE_PAYLOAD; + struct cbfs_media default_media, *m; - buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name, - type, &size); + m = &default_media; + if (init_default_cbfs_media(m) != 0) + return -1; - if (buffer == NULL) + if (cbfs_find_file(m, &payload->f, payload->name, type) < 0) return -1; - payload->backing_store.data = buffer; - payload->backing_store.size = size; + payload->media = CBFS_DEFAULT_MEDIA; return 0; } diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 2204090..0dcecfb 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -58,9 +58,6 @@ struct payload *payload_load(void) ops->name); continue; } - printk(BIOS_DEBUG, "%s: located payload @ %p, %zu bytes.\n", - ops->name, payload->backing_store.data, - payload->backing_store.size); break; } diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 8e9e0de..ac092d1 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -3,7 +3,7 @@ * * Copyright (C) 2003 Eric W. Biederman <ebiederm(a)xmission.com> * Copyright (C) 2009 Ron Minnich <rminnich(a)gmail.com> - * + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -28,6 +28,7 @@ #include <lib.h> #include <bootmem.h> #include <payload_loader.h> +#include <cbfs_core.h> /* from ramstage.ld: */ extern unsigned char _ram_seg; @@ -40,9 +41,9 @@ struct segment { struct segment *next; struct segment *prev; unsigned long s_dstaddr; - unsigned long s_srcaddr; unsigned long s_memsz; unsigned long s_filesz; + unsigned long s_offset; int compression; }; @@ -66,6 +67,102 @@ struct segment { * and much simpler than the general case implemented in kexec. */ +struct sb_helper { + int (*init)(struct sb_helper *sbh, struct payload *payload); + int (*open)(struct payload *payload); + int (*close)(struct payload *payload); + size_t (*read)(struct payload *payload, void *dest, size_t offset, size_t size); + void *(*map)(struct payload *payload, size_t offset, size_t size); + void *sb_media; +}; + +static struct cbfs_media default_media; + +static int init_cbfs(struct sb_helper *sbh, struct payload *payload) +{ + /*Backing store is in use hence no loading via cbfs + */ + if (payload->backing_store.data != NULL) + return 0; + if (payload->media == CBFS_DEFAULT_MEDIA) { + sbh->sb_media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return 0; + } + } + return 1; +} + +static size_t cbfs_read(struct payload *payload, void *dest, size_t offset, size_t size) +{ + return payload->media->read(payload->media, dest, offset, size); +} + +static void *cbfs_map(struct payload *payload, size_t offset, size_t size) +{ + return payload->media->map(payload->media, offset, size); +} + +static int cbfs_open(struct payload *payload) +{ + payload->media->open(payload->media); + return 0; +} + +static int cbfs_close(struct payload *payload) +{ + payload->media->close(payload->media); + return 0; +} + +static int init_backing_store(struct sb_helper *sbh, struct payload *payload) +{ + if (payload->backing_store.data != NULL) + return 1; + else + return 0; +} + +static size_t backing_store_read(struct payload *payload, void *dest, size_t offset, size_t size) +{ + memcpy(dest, (void *)payload->backing_store.data + offset, size); + return size; +} + +static void *backing_store_map(struct payload *payload, size_t offset, size_t size) +{ + return (void *)payload->backing_store.data + offset; +} + +static int backing_store_open(struct payload *payload) +{ + return 0; +} + +static int backing_store_close(struct payload *payload) +{ + return 0; +} + +struct sb_helper cbfs_helper = { + .init = init_cbfs, + .open = cbfs_open, + .close = cbfs_close, + .read = cbfs_read, + .map = cbfs_map, + .sb_media = &default_media, +}; + +struct sb_helper backing_store_helper = { + .init = init_backing_store, + .open = backing_store_open, + .close = backing_store_close, + .read = backing_store_read, + .map = backing_store_map, + .sb_media = NULL, +}; + static unsigned long bounce_size, bounce_buffer; static void get_bounce_buffer(unsigned long req_size) @@ -140,7 +237,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->s_memsz = len; seg->s_memsz -= len; seg->s_dstaddr += len; - seg->s_srcaddr += len; + seg->s_offset += len; if (seg->s_filesz > len) { new->s_filesz = len; seg->s_filesz -= len; @@ -176,7 +273,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) seg->s_memsz = len; new->s_memsz -= len; new->s_dstaddr += len; - new->s_srcaddr += len; + new->s_offset += len; if (seg->s_filesz > len) { seg->s_filesz = len; new->s_filesz -= len; @@ -212,68 +309,95 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) } +static struct sb_helper *get_selfboot_method(struct payload *payload) +{ + struct sb_helper sbh; + if (cbfs_helper.init(&sbh, payload)) + return &cbfs_helper; + if (backing_store_helper.init(&sbh, payload)) + return &backing_store_helper; + return NULL; +} + static int build_self_segment_list( struct segment *head, struct payload *payload, uintptr_t *entry) { struct segment *new; - struct segment *ptr; - struct cbfs_payload_segment *segment, *first_segment; - struct cbfs_payload *cbfs_payload; - cbfs_payload = payload->backing_store.data; + struct cbfs_payload_segment segment; + unsigned long current_offset; + struct sb_helper *sbh; + + if (payload->media == CBFS_DEFAULT_MEDIA) { + payload->media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } + + sbh = get_selfboot_method(payload); + + if (sbh != NULL) { + memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = segment = &cbfs_payload->segments; - while(1) { - printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); - switch(segment->type) { + current_offset = payload->f.data_offset; + sbh->open(payload); + + while(sbh->read(payload, &segment, current_offset, sizeof(segment)) + == sizeof(segment)) { + + printk(BIOS_DEBUG, "Reading segment from offset 0x%lx\n", current_offset); + segment.compression = ntohl(segment.compression); + segment.offset = ntohl(segment.offset); + segment.load_addr = ntohll(segment.load_addr); + segment.mem_len = ntohl(segment.mem_len); + segment.len = ntohl(segment.len); + + switch(segment.type) { case PAYLOAD_SEGMENT_PARAMS: printk(BIOS_DEBUG, " parameter section (skipped)\n"); - segment++; + current_offset += sizeof(segment); continue; case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", - segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", - ntohl(segment->compression)); + segment.type == PAYLOAD_SEGMENT_CODE ? "code" : "data", + segment.compression); new = malloc(sizeof(*new)); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); - new->compression = ntohl(segment->compression); - - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_filesz = ntohl(segment->len); - printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; + new->compression = segment.compression; + new->s_filesz = segment.len; + new->s_offset = segment.offset; + + printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); /* Clean up the values */ if (new->s_filesz > new->s_memsz) { new->s_filesz = new->s_memsz; } - printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); break; case PAYLOAD_SEGMENT_BSS: - printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) - (intptr_t)ntohll(segment->load_addr), - ntohl(segment->mem_len)); + printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", + (void *)(intptr_t)segment.load_addr, segment.mem_len); new = malloc(sizeof(*new)); new->s_filesz = 0; - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); + new->s_offset = segment.offset; + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; break; case PAYLOAD_SEGMENT_ENTRY: printk(BIOS_DEBUG, " Entry Point 0x%p\n", - (void *)(intptr_t)ntohll(segment->load_addr)); - *entry = ntohll(segment->load_addr); + (void *)(intptr_t)segment.load_addr); + *entry = segment.load_addr; /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurrence of the * entry point as break condition for the loop. @@ -285,27 +409,26 @@ static int build_self_segment_list( /* We found something that we don't know about. Throw * hands into the sky and run away! */ - printk(BIOS_EMERG, "Bad segment type %x\n", segment->type); + printk(BIOS_EMERG, "Bad segment type %x\n", segment.type); return -1; } /* We have found another CODE, DATA or BSS segment */ - segment++; + current_offset += sizeof(segment); - /* Find place where to insert our segment */ - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (new->s_srcaddr < ntohll(segment->load_addr)) - break; - } - - /* Order by stream offset */ - new->next = ptr; - new->prev = ptr->prev; - ptr->prev->next = new; - ptr->prev = new; + /* Insert to the end of the list */ + new->next = head; + new->prev = head->prev; + head->prev->next = new; + head->prev = new; } - + sbh->close(payload); return 1; + } + else { + printk(BIOS_ERR, "Failed to build self_segments\n"); + return -1; + } } static int load_self_segments( @@ -315,6 +438,18 @@ static int load_self_segments( struct segment *ptr; const unsigned long one_meg = (1UL << 20); unsigned long bounce_high = lb_end; + struct sb_helper *sbh; + + if (payload->media == CBFS_DEFAULT_MEDIA) { + payload->media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } + + sbh = get_selfboot_method(payload); + if (sbh != NULL) { for(ptr = head->next; ptr != head; ptr = ptr->next) { if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, @@ -362,7 +497,7 @@ static int load_self_segments( payload->bounce.size = bounce_size; for(ptr = head->next; ptr != head; ptr = ptr->next) { - unsigned char *dest, *src; + unsigned char *dest; printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); @@ -378,7 +513,8 @@ static int load_self_segments( /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); - src = (unsigned char *)(ptr->s_srcaddr); + size_t v_read; + void *v_map; /* Copy data from the initial buffer */ if (ptr->s_filesz) { @@ -388,14 +524,31 @@ static int load_self_segments( switch(ptr->compression) { case CBFS_COMPRESS_LZMA: { printk(BIOS_DEBUG, "using LZMA\n"); - len = ulzma(src, dest); + printk(BIOS_DEBUG, "need to map first\n"); + sbh->open(payload); + v_map = sbh->map(payload, payload->f.data_offset + ptr->s_offset, + len); + + sbh->close(payload); + if (v_map == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + printk(BIOS_ERR, "Failed to map\n"); + return -1; + } + len = ulzma(v_map, dest); if (!len) /* Decompression Error. */ return 0; break; } case CBFS_COMPRESS_NONE: { - printk(BIOS_DEBUG, "it's not compressed!\n"); - memcpy(dest, src, len); + printk(BIOS_DEBUG, "it's not compressed! hence read directly\n"); + sbh->open(payload); + v_read = sbh->read(payload, dest, payload->f.data_offset + ptr->s_offset, + len); + sbh->close(payload); + if (v_read != len) { + printk(BIOS_ERR, "Reading of uncompressed segments not successful\n"); + return -1; + } break; } default: @@ -404,11 +557,10 @@ static int load_self_segments( } end = dest + ptr->s_memsz; middle = dest + len; - printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx) <- %08lx\n", + printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx )\n", (unsigned long)dest, (unsigned long)middle, - (unsigned long)end, - (unsigned long)src); + (unsigned long)end); /* Zero the extra bytes between middle & end */ if (middle < end) { @@ -439,6 +591,11 @@ static int load_self_segments( } } return 1; + } + else { + printk(BIOS_ERR, "Failed to load self_segments\n"); + return -1; + } } void *selfload(struct payload *payload)

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New patch to review for coreboot: 2990c02 southbridge nvs.h: Add missing header guards
by HAOUAS Elyes 01 Aug '14

01 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6437 -gerrit commit 2990c02ecb4a60946db34c8626118b116dd7796b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 12:41:48 2014 +0200 southbridge nvs.h: Add missing header guards Change-Id: I000911e98f42ec2dfb4c9cd701413aebe82c5ebe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/bd82x6x/nvs.h | 5 +++++ src/southbridge/intel/fsp_bd82x6x/nvs.h | 5 +++++ src/southbridge/intel/fsp_rangeley/nvs.h | 5 +++++ src/southbridge/intel/i82801dx/nvs.h | 5 +++++ src/southbridge/intel/i82801gx/nvs.h | 5 +++++ src/southbridge/intel/i82801ix/nvs.h | 5 +++++ src/southbridge/intel/ibexpeak/nvs.h | 5 +++++ src/southbridge/intel/lynxpoint/nvs.h | 5 +++++ src/southbridge/via/vt8237r/nvs.h | 5 +++++ 9 files changed, 45 insertions(+) diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 1038f73..cd40124 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -158,3 +161,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* NVS_H */ diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h index 8889f02..fc063c7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/nvs.h +++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -156,3 +159,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* NVS_H */ diff --git a/src/southbridge/intel/fsp_rangeley/nvs.h b/src/southbridge/intel/fsp_rangeley/nvs.h index dce23e0..f9935c4 100644 --- a/src/southbridge/intel/fsp_rangeley/nvs.h +++ b/src/southbridge/intel/fsp_rangeley/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -153,3 +156,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* NVS_H */ diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index 14f0ad3..ea4a2cb 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -135,3 +138,5 @@ typedef struct { u8 bten; u8 rsvd13[14]; } __attribute__((packed)) global_nvs_t; + +#endif /* NVS_H */ diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 14f0ad3..ea4a2cb 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -135,3 +138,5 @@ typedef struct { u8 bten; u8 rsvd13[14]; } __attribute__((packed)) global_nvs_t; + +#endif /* NVS_H */ diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 14f0ad3..ea4a2cb 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -135,3 +138,5 @@ typedef struct { u8 bten; u8 rsvd13[14]; } __attribute__((packed)) global_nvs_t; + +#endif /* NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 1038f73..cd40124 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -158,3 +161,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* NVS_H */ diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 48010ff..8fc2aaf 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -134,3 +137,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* NVS_H */ diff --git a/src/southbridge/via/vt8237r/nvs.h b/src/southbridge/via/vt8237r/nvs.h index d2aab34..967eeff 100644 --- a/src/southbridge/via/vt8237r/nvs.h +++ b/src/southbridge/via/vt8237r/nvs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -43,3 +46,5 @@ typedef struct { u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ } __attribute__((packed)) global_nvs_t; + +#endif /* NVS_H */

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New patch to review for coreboot: fd40751 lenovo/t530: Possibly missing gpio writeout
by Edward O'Callaghan 01 Aug '14

01 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6436 -gerrit commit fd4075177d1899fbd4e5bafe9b33a3c0597d68ca Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:30:21 2014 +1000 lenovo/t530: Possibly missing gpio writeout Include raw dump for the purpose of review: CPU: ID 0x306a9, Processor Type 0x0, Family 0x6, Model 0x3a, Stepping 0x9 Northbridge: 8086:0154 (3rd generation (Ivy Bridge family) Core Processor) Southbridge: 8086:1e55 (QM77) ========== GPIO DIFFS =========== GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0x3962a5ff (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x80090400 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x8ebf6aff (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0x60400400 (GP_IO_SEL) DIFF gpiobase+0x000c: 0x66917ebb (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0x646f7fbb (GP_LVL) DIFF gpiobase+0x0018: 0x00000000 (GPO_BLINK) gpiobase+0x0018: 0x00040000 (GPO_BLINK) DEFAULT gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF gpiobase+0x002c: 0x00002002 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002002 (GPI_INV) DIFF gpiobase+0x0030: 0x02ff08fe (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300fe (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x00fc0800 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x1f47f7fd (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x00100809 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xbfbeff43 (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x1b14ff44 (GP_LVL2) DIFF gpiobase+0x0040: 0x000000ff (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000030 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000cf (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000fff (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x0000000f (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000f4f (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000f8f (GPIO_LVL3) DIFF Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 36df52d..1b8f484 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -185,6 +185,7 @@ void main(unsigned long bist) outl(0x3962a5ff, DEFAULT_GPIOBASE); // GPIO_USE_SEL outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); // GP_IO_SEL outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc); // GP_LVL + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); // GPO_BLINK outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); // GPI_INV outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); // GPIO_USE_SEL2 outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); // GP_IO_SEL2

1 0

New patch to review for coreboot: a0ab902 lenovo/t530: Comment gpio writeouts for later reference
by Edward O'Callaghan 01 Aug '14

01 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6435 -gerrit commit a0ab9023da7af75560ca959a81d31ee153442c66 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:29:40 2014 +1000 lenovo/t530: Comment gpio writeouts for later reference Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index d65031a..36df52d 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -182,16 +182,16 @@ void main(unsigned long bist) pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); // setup_pch_gpios(&t530_gpio_map); - outl(0x3962a5ff, DEFAULT_GPIOBASE); - outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); - outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc); - outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); - outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); - outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); - outl(0xffbeff43, DEFAULT_GPIOBASE + 0x38); - outl(0x000000ff, DEFAULT_GPIOBASE + 0x40); - outl(0x00000fff, DEFAULT_GPIOBASE + 0x44); - outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); + outl(0x3962a5ff, DEFAULT_GPIOBASE); // GPIO_USE_SEL + outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); // GP_IO_SEL + outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc); // GP_LVL + outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); // GPI_INV + outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); // GPIO_USE_SEL2 + outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); // GP_IO_SEL2 + outl(0xffbeff43, DEFAULT_GPIOBASE + 0x38); // GP_LVL2 + outl(0x000000ff, DEFAULT_GPIOBASE + 0x40); // GPIO_USE_SEL3 + outl(0x00000fff, DEFAULT_GPIOBASE + 0x44); // GPIO_SEL3 + outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); // GPIO_LVL3 /* Initialize console device(s) */ console_init();

1 0

New patch to review for coreboot: a7425cd Format `mb_sysconf.h'
by HAOUAS Elyes 01 Aug '14

01 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6434 -gerrit commit a7425cd4dbfa1bb88449130417b54dddcc0b1f08 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 12:12:38 2014 +0200 Format `mb_sysconf.h' Change-Id: Ib26b87b980f61c8a118883477e6a4c728c0f2e5c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/mahogany_fam10/mb_sysconf.h | 3 +-- src/mainboard/amd/serengeti_cheetah/mb_sysconf.h | 3 +-- src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h | 3 +-- src/mainboard/amd/tilapia_fam10/mb_sysconf.h | 3 +-- src/mainboard/asus/m4a78-em/mb_sysconf.h | 3 +-- src/mainboard/asus/m4a785-m/mb_sysconf.h | 3 +-- src/mainboard/gigabyte/ma785gm/mb_sysconf.h | 3 +-- src/mainboard/hp/dl145_g1/mb_sysconf.h | 3 +-- src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h | 3 +-- src/mainboard/iwill/dk8_htx/mb_sysconf.h | 3 +-- src/mainboard/msi/ms9282/mb_sysconf.h | 3 +-- src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h | 3 +-- 12 files changed, 12 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/mahogany_fam10/mb_sysconf.h b/src/mainboard/amd/mahogany_fam10/mb_sysconf.h index 25d63d5..a9dce01 100644 --- a/src/mainboard/amd/mahogany_fam10/mb_sysconf.h +++ b/src/mainboard/amd/mahogany_fam10/mb_sysconf.h @@ -18,7 +18,6 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h index ef3dace..09c372c 100644 --- a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h +++ b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h @@ -1,5 +1,4 @@ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -24,4 +23,4 @@ struct mb_sysconf_t { }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h index 4fb3f18..3c96d8b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h @@ -18,7 +18,6 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -39,4 +38,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/amd/tilapia_fam10/mb_sysconf.h b/src/mainboard/amd/tilapia_fam10/mb_sysconf.h index 25d63d5..a9dce01 100644 --- a/src/mainboard/amd/tilapia_fam10/mb_sysconf.h +++ b/src/mainboard/amd/tilapia_fam10/mb_sysconf.h @@ -18,7 +18,6 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/asus/m4a78-em/mb_sysconf.h b/src/mainboard/asus/m4a78-em/mb_sysconf.h index 25d63d5..a9dce01 100644 --- a/src/mainboard/asus/m4a78-em/mb_sysconf.h +++ b/src/mainboard/asus/m4a78-em/mb_sysconf.h @@ -18,7 +18,6 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/asus/m4a785-m/mb_sysconf.h b/src/mainboard/asus/m4a785-m/mb_sysconf.h index 25d63d5..a9dce01 100644 --- a/src/mainboard/asus/m4a785-m/mb_sysconf.h +++ b/src/mainboard/asus/m4a785-m/mb_sysconf.h @@ -18,7 +18,6 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/gigabyte/ma785gm/mb_sysconf.h b/src/mainboard/gigabyte/ma785gm/mb_sysconf.h index 25d63d5..a9dce01 100644 --- a/src/mainboard/gigabyte/ma785gm/mb_sysconf.h +++ b/src/mainboard/gigabyte/ma785gm/mb_sysconf.h @@ -18,7 +18,6 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h index 3dfd5de..cc8cf29 100644 --- a/src/mainboard/hp/dl145_g1/mb_sysconf.h +++ b/src/mainboard/hp/dl145_g1/mb_sysconf.h @@ -3,7 +3,6 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -20,4 +19,4 @@ struct mb_sysconf_t { unsigned sbdn3; }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h b/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h index 25d63d5..a9dce01 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h +++ b/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h @@ -18,7 +18,6 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/iwill/dk8_htx/mb_sysconf.h b/src/mainboard/iwill/dk8_htx/mb_sysconf.h index ef3dace..09c372c 100644 --- a/src/mainboard/iwill/dk8_htx/mb_sysconf.h +++ b/src/mainboard/iwill/dk8_htx/mb_sysconf.h @@ -1,5 +1,4 @@ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -24,4 +23,4 @@ struct mb_sysconf_t { }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/msi/ms9282/mb_sysconf.h b/src/mainboard/msi/ms9282/mb_sysconf.h index 4b15168..4efe699 100644 --- a/src/mainboard/msi/ms9282/mb_sysconf.h +++ b/src/mainboard/msi/ms9282/mb_sysconf.h @@ -22,7 +22,6 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -30,4 +29,4 @@ struct mb_sysconf_t { unsigned apicid_mcp55; }; -#endif +#endif /* MB_SYSCONF_H */ diff --git a/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h index 25d63d5..a9dce01 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h @@ -18,7 +18,6 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H struct mb_sysconf_t { @@ -40,4 +39,4 @@ struct mb_sysconf_t { u32 sbdn5[31]; }; -#endif +#endif /* MB_SYSCONF_H */

1 0

Patch set updated for coreboot: a2bad55 lenovo/t530: Use native raminit over MRC blob
by Edward O'Callaghan 01 Aug '14

01 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6394 -gerrit commit a2bad55d9ecd6ba4bed40cdf25f96d05eaa5e485 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 14:09:27 2014 +1000 lenovo/t530: Use native raminit over MRC blob We now have Native raminit for both sandy/ivybridge introduced in: 7686a56 sandy/ivybridge: Native raminit. Let us make good use of this support over using the Intel MRC blob to initialise memory. USB RCBA configuration data taken between base of 0x3500 up to 0x3600 from `inteltool -r`. Included is the raw dump for the purposes of review: 0x3500: 0x20000f57 0x3504: 0x20000f57 0x3508: 0x2000055b 0x350c: 0x20000f57 0x3510: 0x20000f57 0x3514: 0x20000153 0x3518: 0x20000153 0x351c: 0x2000055b 0x3520: 0x20000153 0x3524: 0x20000f57 0x3528: 0x20000153 0x352c: 0x20000153 0x3530: 0x20000f51 0x3534: 0x20000f57 0x3560: 0x024c8001 0x3564: 0x000024a3 0x3568: 0x00040002 0x356c: 0x01000050 0x3570: 0x02000772 0x3574: 0x16000f9f 0x3578: 0x1800ff4f 0x357c: 0x0001d630 0x359c: 0x00001448 0x35a0: 0x04100201 0x35a4: 0x00000200 0x3600: 0xffffffff Remark: Note the current port is poorly tested at the moment and I am the sole maintainer, however one less blob invites more interest for better support. More to come hopefully. Change-Id: I41d0ef8303dfd369c5565b823e68a6bee09c44f5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 12 ++-- src/mainboard/lenovo/t530/romstage.c | 135 ++++++++++++++--------------------- 2 files changed, 56 insertions(+), 91 deletions(-) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 473f8b8..efeca4b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_T530 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 @@ -18,8 +18,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE config HAVE_MRC_CACHE - bool - default n + bool + default y config HAVE_IFD_BIN bool @@ -41,10 +41,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config IRQ_SLOT_COUNT int default 18 @@ -57,7 +53,7 @@ config USBDEBUG_HCD_INDEX int default 2 -config DRAM_GATE_GPIO +config DRAM_RESET_GATE_GPIO int default 10 diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index d65031a..9f6479a 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -33,7 +33,7 @@ #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" +#include "northbridge/intel/sandybridge/raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/gpio.h" #include <arch/cpu.h> @@ -109,66 +109,58 @@ static void rcba_config(void) RCBA32(BUC) = 0; } +static void +init_usb (void) +{ + const u32 rcba_dump[64] = { + /* 3500 */ 0x20000f57, 0x20000f57, 0x2000055b, 0x20000f57, + /* 3510 */ 0x20000f57, 0x20000153, 0x20000153, 0x2000055b, + /* 3520 */ 0x20000153, 0x20000f57, 0x20000153, 0x20000153, + /* 3530 */ 0x20000f51, 0x20000f57, 0x00000000, 0x00000000, + /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, + /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, + /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00001448, + /* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000, + /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + }; + int i; + /* Activate PMBAR. */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + + /* Unlock registers. */ + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + for (i = 0; i < 64; i++) + write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]); + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + /* Relock registers. */ + outw (0x0000, DEFAULT_PMBASE | 0x003c); +} + + void main(unsigned long bist) { - int boot_mode = 0; - int cbmem_was_initted; + int s3resume = 0; u32 pm1_cnt; u16 pm1_sts; + spd_raw_data spd[4]; if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); hlt (); } - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, - .dmibar = DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA2,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled usb oc pin length */ - { 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */ - { 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */ - { 1, 3, 0x0080 }, /* P2: dock, OC 3 */ - { 1, 0, 0x0040 }, /* P3: wwan, no OC */ - { 1, 0, 0x0080 }, /* P4: Wacom tablet on X230t, otherwise empty */ - { 1, 0, 0x0080 }, /* P5: Expresscard, no OC */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 1, 0, 0x0080 }, /* P7: dock, no OC */ - { 0, 0, 0x0000 }, /* P8: Empty */ - { 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */ - { 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */ - { 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */ - { 1, 0, 0x0040 }, /* P12: wlan, no OC */ - { 1, 0, 0x0080 }, /* P13: webcam, no OC */ - }, - .ddr_refresh_rate_config = 2, /* Force double refresh rate */ - }; - timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); @@ -193,6 +185,8 @@ void main(unsigned long bist) outl(0x00000fff, DEFAULT_GPIOBASE + 0x44); outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); + init_usb(); + /* Initialize console device(s) */ console_init(); @@ -214,7 +208,7 @@ void main(unsigned long bist) if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { if (acpi_s3_resume_allowed()) { printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; + s3resume = 1; /* Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. */ @@ -228,31 +222,16 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - post_code(0x39); post_code(0x3a); - pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); - /* MRC.bin has a bug and sometimes halts (instead of reboot?). - */ - if (boot_mode != 2) - { - RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */ - outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */ - } - - sdram_initialize(&pei_data); + memset (spd, 0, sizeof (spd)); + read_spd (&spd[0], 0x50); + read_spd (&spd[2], 0x51); - if (boot_mode != 2) - { - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - } + init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); @@ -260,13 +239,7 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d); - quick_ram_check(); - post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - if (boot_mode!=2) - save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so @@ -276,18 +249,14 @@ void main(unsigned long bist) *(u32 *)CBMEM_BOOT_MODE = 0; *(u32 *)CBMEM_RESUME_BACKUP = 0; - if ((boot_mode == 2) && cbmem_was_initted) { + if (s3resume) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_BOOT_MODE = 2; *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - hlt(); } else { pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); }

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Patch set updated for coreboot: cc9cb10 lenovo/t520/mainboard.c: Include header `h8.h` for prototype
by HAOUAS Elyes 01 Aug '14

01 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6424 -gerrit commit cc9cb10ce6f11f7df328fdc5b40347033879461e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 31 10:39:57 2014 +0200 lenovo/t520/mainboard.c: Include header `h8.h` for prototype Change-Id: I5ac6608ebf78f2d48bc7f68bce9eae7a2be82332 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/lenovo/t520/mainboard.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index c213791..d374e7e 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -39,6 +39,7 @@ #include <device/pci.h> #include <cbfs.h> #include <pc80/keyboard.h> +#include <ec/lenovo/h8/h8.h> void mainboard_suspend_resume(void) { @@ -182,8 +183,6 @@ static void mainboard_enable(device_t dev) verb_setup(); } -void h8_mainboard_init_dock (void); - void h8_mainboard_init_dock (void) { return;

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Patch set updated for coreboot: 994d0fc bayleybay_fsp: Add bakersport board variant
by Martin Roth 01 Aug '14

01 Aug '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5983 -gerrit commit 994d0fc2f3464152048d6d97acab83205ed79747 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jun 12 12:08:26 2014 -0600 bayleybay_fsp: Add bakersport board variant The Bakersport board is a variant of the Bayley Bay mainboard that uses one ECC DIMM instead of two non-ECC dimms. This commit uses the Bayley Bay mainboard directory and modifies the required pieces to add the Bakersport board variant. It disables the second DIMM, points to an ECC version of the FSP, and sets the board name to be Bakersport instead of Bayley Bay. All of the code is still contained in the bayleybay_fsp directory. It seems like duplicating the whole directory for the one line of code that's actually different between the two platforms. Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/intel/Kconfig | 3 + src/mainboard/intel/bakersport_fsp/Kconfig | 103 ++++++++++++++++++++++++++ src/mainboard/intel/bakersport_fsp/readme.txt | 5 ++ src/mainboard/intel/bayleybay_fsp/romstage.c | 5 ++ 4 files changed, 116 insertions(+) diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 4f1ff4c..4578dfe 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -3,6 +3,8 @@ if VENDOR_INTEL choice prompt "Mainboard model" +config BOARD_INTEL_BAKERSPORT_FSP + bool "Bakersport FSP-based CRB" config BOARD_INTEL_BAYLEYBAY_FSP bool "Bayley Bay FSP-based CRB" config BOARD_INTEL_COUGAR_CANYON2 @@ -32,6 +34,7 @@ config BOARD_INTEL_WTM2 endchoice +source "src/mainboard/intel/bakersport_fsp/Kconfig" source "src/mainboard/intel/bayleybay_fsp/Kconfig" source "src/mainboard/intel/cougar_canyon2/Kconfig" source "src/mainboard/intel/d810e2cb/Kconfig" diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig new file mode 100644 index 0000000..043e98a --- /dev/null +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -0,0 +1,103 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_INTEL_BAKERSPORT_FSP + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_FSP_BAYTRAIL + select BOARD_ROMSIZE_KB_2048 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select OVERRIDE_MRC_CACHE_LOC + select POST_IO + select INCLUDE_MICROCODE_IN_BUILD if FSP_PACKAGE_DEFAULT + select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT + select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT + select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT + select TSC_MONOTONIC_TIMER + +config MAINBOARD_DIR + string + default "intel/bayleybay_fsp" + +config INCLUDE_ME + bool + default n + +config LOCK_MANAGEMENT_ENGINE + bool + default n + +config MAINBOARD_PART_NUMBER + string + default "Bakersport CRB" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 16 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x800000 + +config FSP_FILE + string + default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP + +config MRC_CACHE_LOC_OVERRIDE + hex + default 0xfff80000 + depends on ENABLE_FSP_FAST_BOOT + +config CBFS_SIZE + hex + default 0x00200000 + +config DRIVERS_PS2_KEYBOARD + bool + default n + +config CONSOLE_POST + bool + default y + +config ENABLE_FSP_FAST_BOOT + bool + depends on HAVE_FSP_BIN + default y + +config VIRTUAL_ROM_SIZE + hex + depends on ENABLE_FSP_FAST_BOOT + default 0x800000 + +config FSP_PACKAGE_DEFAULT + bool "Configure defaults for the Intel FSP package" + default n + +config VGA_BIOS + bool + default y if FSP_PACKAGE_DEFAULT + +endif # BOARD_INTEL_BAKERSPORT_FSP diff --git a/src/mainboard/intel/bakersport_fsp/readme.txt b/src/mainboard/intel/bakersport_fsp/readme.txt new file mode 100644 index 0000000..b76592c --- /dev/null +++ b/src/mainboard/intel/bakersport_fsp/readme.txt @@ -0,0 +1,5 @@ +The code for the bakersport board is in the bayleybay_fsp directory. + +This directory is just here so so that the bakersport board gets built by +abuild and so that there is a separate entry in the wiki and board-status +tree. diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index 34199bd..ef848fa 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -173,4 +173,9 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) /* Initialize the Azalia Verb Tables to mainboard specific version */ UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; + + /* Disable 2nd DIMM on Bakersport*/ +#if IS_ENABLED(BOARD_INTEL_BAKERSPORT_FSP) + UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */ +#endif }

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Patch set updated for coreboot: 3fef456 payloads/external/SeaBIOS: Allow setting buffers below 0xC0000
by Martin Roth 01 Aug '14

01 Aug '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6364 -gerrit commit 3fef456d39bc921d5c923d3cf2f3d3b1821c71d8 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Jul 25 14:39:05 2014 -0600 payloads/external/SeaBIOS: Allow setting buffers below 0xC0000 Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is an absolute requirement on the upcoming Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB from bus-mastering into the buffers when they're set in the typical 0xE0000 area. This will be set to Y unless defaulted to N by the mainboard or chipset. Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- payloads/external/SeaBIOS/Makefile.inc | 3 +++ src/Kconfig | 13 +++++++++++++ src/arch/x86/Makefile.inc | 1 + 3 files changed, 17 insertions(+) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 21f933a..03e2b08 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -31,6 +31,9 @@ ifeq ($(CONFIG_CONSOLE_SERIAL),y) else echo "# CONFIG_DEBUG_SERIAL is not set" >> $(OUT)/seabios/.config endif +ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y) + echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> $(OUT)/seabios/.config +endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> $(OUT)/seabios/.config endif diff --git a/src/Kconfig b/src/Kconfig index af82353..842d448 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -626,6 +626,19 @@ config SEABIOS_THREAD_OPTIONROMS variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option. +config SEABIOS_MALLOC_UPPERMEMORY + bool + default y + depends on PAYLOAD_SEABIOS + help + Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal + "low memory" allocations. If this is not selected, the memory is + instead allocated from the "9-segment" (0x90000-0xa0000). + This is not typically needed, but may be required on some platforms + to allow USB and SATA buffers to be written correctly by the + hardware. In general, if this is desired, the option will be + set to 'N' by the chipset Kconfig. + choice prompt "GRUB2 version" default GRUB2_MASTER diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2e92d89..3b2517b 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -352,6 +352,7 @@ seabios: CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ + CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \ OUT=$(abspath $(obj)) IASL="$(IASL)" filo:

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New patch to review for coreboot: 5cdf93a i82801ix: Provide ramstage smbus functions.
by Vladimir Serbinenko 01 Aug '14

01 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6433 -gerrit commit 5cdf93ad9b130c4c96050285b51c554c9a713d48 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Aug 1 02:49:27 2014 +0200 i82801ix: Provide ramstage smbus functions. Change-Id: Idc62e382a4002274abe6c23d76fe0874c62846c5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/i82801ix/Makefile.inc | 1 + src/southbridge/intel/i82801ix/smbus.c | 116 ++++++++++++++++++++++++++++ src/southbridge/intel/i82801ix/smbus.h | 45 +++++++++++ 3 files changed, 162 insertions(+) diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 9176ff1..096533c 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -26,6 +26,7 @@ ramstage-y += usb_ehci.c ramstage-y += sata.c ramstage-y += hdaudio.c ramstage-y += thermal.c +ramstage-y += smbus.c ramstage-y += ../i82801gx/reset.c ramstage-y += ../i82801gx/watchdog.c diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c new file mode 100644 index 0000000..25b21fa --- /dev/null +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/smbus.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "smbus.h" + +static void pch_smbus_init(device_t dev) +{ + u16 reg16; + + /* Enable clock gating */ + reg16 = pci_read_config16(dev, 0x80); + reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); + pci_write_config16(dev, 0x80, reg16); +} + +static int lsmbus_read_byte(device_t dev, u8 address) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + + return do_smbus_read_byte(res->base, device, address); +} + +static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + + return do_smbus_write_byte(res->base, device, address, val); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, +}; + +static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations smbus_pci_ops = { + .set_subsystem = smbus_set_subsystem, +}; + +static void smbus_read_resources(device_t dev) +{ + struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); + res->base = SMBUS_IO_BASE; + res->size = 32; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Also add MMIO resource */ + res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); +} + +static struct device_operations smbus_ops = { + .read_resources = smbus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_static_bus, + .init = pch_smbus_init, + .ops_smbus_bus = &lops_smbus_bus, + .ops_pci = &smbus_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { 0x2930, 0 }; + +static const struct pci_driver pch_smbus __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/southbridge/intel/i82801ix/smbus.h b/src/southbridge/intel/i82801ix/smbus.h index f215fb4..af95c54 100644 --- a/src/southbridge/intel/i82801ix/smbus.h +++ b/src/southbridge/intel/i82801ix/smbus.h @@ -97,3 +97,48 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add } return byte; } + +#ifndef __PRE_RAM__ +static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data) +{ + unsigned char global_status_register; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(data, smbus_base + SMBHSTDAT0); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + + global_status_register = inb(smbus_base + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + if (global_status_register != (1 << 1)) + return SMBUS_ERROR; + + return 0; +} +#endif

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coreboot-gerrit August 2014