August 2014 - coreboot-gerrit - mail.coreboot.org

New patch to review for coreboot: b8101ab Add missing header guards
by HAOUAS Elyes Aug. 1, 2014

Aug. 1, 2014

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6455 -gerrit commit b8101ab7610c31c39467f407852d37f33070c66d Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 15:39:31 2014 +0200 Add missing header guards Change-Id: I065297cdb20dc0f31c1eddc03f0382d5c59ec7e7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/siemens/sitemp_g1p1/int15_func.h | 5 ++++- src/northbridge/amd/amdfam10/amdfam10.h | 2 +- src/northbridge/amd/amdfam10/nums.h | 3 +-- src/northbridge/amd/amdk8/amdk8.h | 1 - src/northbridge/amd/amdmct/amddefs.h | 5 +++++ src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 4 ++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 4 ++++ src/northbridge/intel/e7501/e7501.h | 5 +++++ src/northbridge/intel/e7505/e7505.h | 5 +++++ src/northbridge/intel/e7520/e7520.h | 5 +++++ src/northbridge/intel/e7525/e7525.h | 5 +++++ src/northbridge/intel/i82830/i82830.h | 5 +++++ src/northbridge/intel/i855/i855.h | 5 +++++ src/northbridge/via/cn400/cn400.h | 5 +++++ src/northbridge/via/cn700/cn700.h | 5 +++++ src/northbridge/via/cx700/registers.h | 5 +++++ src/southbridge/amd/amd8111/amd8111_smbus.h | 5 +++++ src/southbridge/intel/i82870/82870.h | 5 +++++ src/southbridge/nvidia/ck804/early_setup_ss.h | 5 +++++ src/southbridge/nvidia/ck804/early_smbus.h | 5 +++++ src/southbridge/nvidia/mcp55/early_setup_ss.h | 5 +++++ src/southbridge/ricoh/rl5c476/rl5c476.h | 6 +++++- src/southbridge/sis/sis966/early_setup_ss.h | 5 +++++ src/southbridge/ti/pci7420/pci7420.h | 4 ++++ src/southbridge/via/common/via_early_smbus.h | 5 +++++ src/southbridge/via/vt82c686/vt82c686.h | 5 +++++ 26 files changed, 113 insertions(+), 6 deletions(-) diff --git a/src/mainboard/siemens/sitemp_g1p1/int15_func.h b/src/mainboard/siemens/sitemp_g1p1/int15_func.h index 26f679e..32e4284 100644 --- a/src/mainboard/siemens/sitemp_g1p1/int15_func.h +++ b/src/mainboard/siemens/sitemp_g1p1/int15_func.h @@ -20,7 +20,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef INT15_FUNC_H +#define INT15_FUNC_H typedef struct { u8 func00_LCD_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID u8 func02_set_expansion; @@ -33,3 +34,5 @@ typedef struct { }INT15_function_extensions; extern void install_INT15_function_extensions(INT15_function_extensions *); + +#endif /* INT15_FUNC_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 6e71b4e..c01d182 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -18,8 +18,8 @@ */ #ifndef AMDFAM10_H - #define AMDFAM10_H + /* Definitions of various FAM10 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 diff --git a/src/northbridge/amd/amdfam10/nums.h b/src/northbridge/amd/amdfam10/nums.h index 12bac5d..c1ecf7f 100644 --- a/src/northbridge/amd/amdfam10/nums.h +++ b/src/northbridge/amd/amdfam10/nums.h @@ -18,7 +18,6 @@ */ #ifndef AMDFAM10_NUMS_H - #define AMDFAM10_NUMS_H #if CONFIG_MAX_PHYSICAL_CPUS > 8 @@ -37,4 +36,4 @@ //it could be more bigger #define HC_POSSIBLE_NUM 32 -#endif +#endif /* AMDFAM10_NUMS_H */ diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 05117f7..591244d 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -1,5 +1,4 @@ #ifndef AMDK8_H - #define AMDK8_H #if CONFIG_K8_REV_F_SUPPORT diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 9efc1db..6ac9e64 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef AMDDEFS_H +#define AMDDEFS_H + /* FIXME: this file should be moved to include/cpu/amd/amddefs.h */ /* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ @@ -148,3 +151,5 @@ #define AMD_PKGTYPE_G34 3 #define AMD_PKGTYPE_ASB2 4 #define AMD_PKGTYPE_C32 5 + +#endif /* AMDDEFS_H */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index e989ae3..72b141f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MCT_D_GCC_H +#define MCT_D_GCC_H static inline void _WRMSR(u32 addr, u32 lo, u32 hi) { @@ -376,3 +378,5 @@ static u8 oemNodePresent_D(u8 Node, u8 *ret) *ret = 0; return 0; } + +#endif /* MCT_D_GCC_H */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index abe6e7b..8024075 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MCT_D_GCC_H +#define MCT_D_GCC_H static inline void _WRMSR(u32 addr, u32 lo, u32 hi) { __asm__ volatile ( @@ -358,3 +360,5 @@ static u8 oemNodePresent_D(u8 Node, u8 *ret) *ret = 0; return 0; } + +#endif /* MCT_D_GCC_H */ diff --git a/src/northbridge/intel/e7501/e7501.h b/src/northbridge/intel/e7501/e7501.h index 1e431b1..20d9f80 100644 --- a/src/northbridge/intel/e7501/e7501.h +++ b/src/northbridge/intel/e7501/e7501.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef E7501_H +#define E7501_H + /* * e7501.h: PCI configuration space for the Intel E7501 memory controller */ @@ -77,3 +80,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* E7501_H */ diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 08b681a..d3a8089 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef E7505_H +#define E7505_H + /* * e7505.h: PCI configuration space for the Intel E7501 memory controller */ @@ -82,3 +85,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* E7505_H */ diff --git a/src/northbridge/intel/e7520/e7520.h b/src/northbridge/intel/e7520/e7520.h index 61401e4..eb35a2c 100644 --- a/src/northbridge/intel/e7520/e7520.h +++ b/src/northbridge/intel/e7520/e7520.h @@ -1,3 +1,6 @@ +#ifndef E7520_H +#define E7520_H + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -37,3 +40,5 @@ #define DEVPRES1_D0F1 (1 << 5) #define DEVPRES1_D8F0 (1 << 1) #define MSCFG 0XF6 + +#endif /* E7520_H */ diff --git a/src/northbridge/intel/e7525/e7525.h b/src/northbridge/intel/e7525/e7525.h index 61401e4..6402c29 100644 --- a/src/northbridge/intel/e7525/e7525.h +++ b/src/northbridge/intel/e7525/e7525.h @@ -1,3 +1,6 @@ +#ifndef E7525_H +#define E7525_H + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -37,3 +40,5 @@ #define DEVPRES1_D0F1 (1 << 5) #define DEVPRES1_D8F0 (1 << 1) #define MSCFG 0XF6 + +#endif /* E7525_H */ diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h index bdf7e51..7474beb 100644 --- a/src/northbridge/intel/i82830/i82830.h +++ b/src/northbridge/intel/i82830/i82830.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I82830_H +#define I82830_H + #define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ #define GCC0 0x50 /* GMCH Control #0 (0xa072) */ #define GCC1 0x52 /* GMCH Control #1 (0x0000) */ @@ -49,3 +52,5 @@ #define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */ #define APSIZE 0xb4 /* Apterture Size (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */ + +#endif /* I82830_H */ diff --git a/src/northbridge/intel/i855/i855.h b/src/northbridge/intel/i855/i855.h index 8786fd7..1d438eb 100644 --- a/src/northbridge/intel/i855/i855.h +++ b/src/northbridge/intel/i855/i855.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I855_H +#define I855_H + /* Host-Hub Interface Bridge */ #define GMC 0x50 /* GMCH Misc. Control (0x0000) */ #define GGC 0x52 /* GMCH Graphics Control (0x0030) */ @@ -74,3 +77,5 @@ #define DRT_TRAS_MIN_7 (1 << 9) #define DRT_TRAS_MIN_6 (2 << 9) #define DRT_TRAS_MIN_5 (3 << 9) + +#endif /* I855_H */ diff --git a/src/northbridge/via/cn400/cn400.h b/src/northbridge/via/cn400/cn400.h index 2df30a6..e593b6f 100644 --- a/src/northbridge/via/cn400/cn400.h +++ b/src/northbridge/via/cn400/cn400.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CN400_H +#define CN400_H + #ifndef __PRE_RAM__ // HACK static inline void cn400_noop(device_t dev) @@ -54,3 +57,5 @@ static inline void cn400_noop(device_t dev) #define RAM_COMMAND_MSR_LOW (const char) 0x03 #define RAM_COMMAND_CBR (const char) 0x04 #define RAM_COMMAND_MSR_HIGH (const char) 0x05 + +#endif /* CN400_H */ diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h index ff1d4b3..178a0e4 100644 --- a/src/northbridge/via/cn700/cn700.h +++ b/src/northbridge/via/cn700/cn700.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CN700_H +#define CN700_H + #if !defined (__PRE_RAM__) // HACK static inline void cn700_noop(device_t dev) @@ -54,3 +57,5 @@ static inline void cn700_noop(device_t dev) #define RAM_COMMAND_PRECHARGE 0x2 #define RAM_COMMAND_MRS 0x3 #define RAM_COMMAND_CBR 0x4 + +#endif /* CN700_H */ diff --git a/src/northbridge/via/cx700/registers.h b/src/northbridge/via/cx700/registers.h index 67c3da4..10b486b 100644 --- a/src/northbridge/via/cx700/registers.h +++ b/src/northbridge/via/cx700/registers.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef REGISTERS_H +#define REGISTERS_H + /* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */ #define SCRATCH_REG_BASE 0xd0 #define SCRATCH_RANK_0 0xd0 @@ -42,3 +45,5 @@ #define DDRII_333 0x2 #define DDRII_266 0x1 #define DDRII_200 0x0 + +#endif /* REGISTERS_H */ diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 00f8f50..03cf1ea 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -1,3 +1,6 @@ +#ifndef AMD8111_SMBUS_H +#define AMD8111_SMBUS_H + #include <device/smbus_def.h> #define SMBGSTATUS 0xe0 @@ -323,3 +326,5 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne } return 0; } + +#endif /* AMD8111_SMBUS_H */ diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index b576cc1..4c17c65 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -1,3 +1,6 @@ +#ifndef I82870_82870_H +#define I82870_82870_H + /* for io apic 1461 */ #define MBAR 0x10 #define ABAR 0x40 @@ -12,3 +15,5 @@ #define STRP_HPCAP 0x0002 // Hot-plug capable (Hx_SLOT zero/nonzero) #define ACNF_SYNCPH 0x0010 // PCI(-X) input clock is synchronous to hub input clock + +#endif /* I82870_82870_H */ diff --git a/src/southbridge/nvidia/ck804/early_setup_ss.h b/src/southbridge/nvidia/ck804/early_setup_ss.h index 9f89595..4945c1b 100644 --- a/src/southbridge/nvidia/ck804/early_setup_ss.h +++ b/src/southbridge/nvidia/ck804/early_setup_ss.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef EARLY_SETUP_SS_H +#define EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -218,3 +221,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* EARLY_SETUP_SS_H */ diff --git a/src/southbridge/nvidia/ck804/early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h index cf25403..c8a52ed 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.h +++ b/src/southbridge/nvidia/ck804/early_smbus.h @@ -1,5 +1,10 @@ +#ifndef EARLY_SMBUS_H +#define EARLY_SMBUS_H + int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned); int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); void enable_smbus(void); int smbus_read_byte(unsigned int, unsigned int); int smbus_write_byte(unsigned int, unsigned int, unsigned char); + +#endif /* EARLY_SMBUS_H */ diff --git a/src/southbridge/nvidia/mcp55/early_setup_ss.h b/src/southbridge/nvidia/mcp55/early_setup_ss.h index 0aadc73..8eb8b34 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_ss.h +++ b/src/southbridge/nvidia/mcp55/early_setup_ss.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef EARLY_SETUP_SS_H +#define EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -219,3 +222,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* EARLY_SETUP_SS_H */ diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 71966a1..5818ed3 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -21,8 +21,10 @@ /* rl5c476 routines and defines*/ -#include <stdint.h> +#ifndef RL5C476_H +#define RL5C476_H +#include <stdint.h> /* the 16 bit control structure for ricoh cardbus bridge */ typedef struct pc16reg { @@ -92,3 +94,5 @@ typedef struct pc16reg { u8 resv9; u8 smpga0; } __attribute__ ((packed)) pc16reg_t; + +#endif /* RL5C476_H */ diff --git a/src/southbridge/sis/sis966/early_setup_ss.h b/src/southbridge/sis/sis966/early_setup_ss.h index b6aa7d7..44c067d 100644 --- a/src/southbridge/sis/sis966/early_setup_ss.h +++ b/src/southbridge/sis/sis966/early_setup_ss.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef EARLY_SETUP_SS_H +#define EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -218,3 +221,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* EARLY_SETUP_SS_H */ diff --git a/src/southbridge/ti/pci7420/pci7420.h b/src/southbridge/ti/pci7420/pci7420.h index f71fe17..6c92ada 100644 --- a/src/southbridge/ti/pci7420/pci7420.h +++ b/src/southbridge/ti/pci7420/pci7420.h @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef PCI7420_H +#define PCI7420_H // 0844d060 (old) #define SYSCTL 0x80 // 08405061 #define RIMUX (1 << 0) @@ -47,3 +49,5 @@ #define INTB 1 #define INTC 2 #define INTD 3 + +#endif /* PCI7420_H */ diff --git a/src/southbridge/via/common/via_early_smbus.h b/src/southbridge/via/common/via_early_smbus.h index aca920b..07c2d52 100644 --- a/src/southbridge/via/common/via_early_smbus.h +++ b/src/southbridge/via/common/via_early_smbus.h @@ -35,6 +35,9 @@ * @endcode */ +#ifndef VIA_EARLY_SMBUS_H +#define VIA_EARLY_SMBUS_H + /** * \brief SMBus IO ports in relation to the base IO port */ @@ -54,3 +57,5 @@ #include <device/early_smbus.h> #include <arch/io.h> + +#endif /* VIA_EARLY_SMBUS_H */ diff --git a/src/southbridge/via/vt82c686/vt82c686.h b/src/southbridge/via/vt82c686/vt82c686.h index 7d2ac52..85cf7b9 100644 --- a/src/southbridge/via/vt82c686/vt82c686.h +++ b/src/southbridge/via/vt82c686/vt82c686.h @@ -25,6 +25,9 @@ * Link: http://www.datasheet4u.com/html/V/T/8/VT82C686B_VIA.pdf.html */ +#ifndef VT82C686_H +#define VT82C686_H + /* Super I/0 Configuration Registers. */ /* Any registers not listed here are reserved. */ #define VT82C686_SIO_DEV_ID 0xe0 /* Super-I/O Device ID */ @@ -53,3 +56,5 @@ PCI_DEVICE_ID_VIA_82C686_4 0x3057 // Function 4, Power Management PCI_DEVICE_ID_VIA_82C686_5 0x3058 // Function 5, AC'97 Codec PCI_DEVICE_ID_VIA_82C686_6 0x3068 // Function 6, MC'97 Codec */ + +#endif /* VT82C686_H */

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Patch set updated for coreboot: bd75915 payloads/external/SeaBIOS: retain the built binary
by Idwer Vollering Aug. 1, 2014

Aug. 1, 2014

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6387 -gerrit commit bd7591505b0ae07e3b26f1a4052c79b2d4ac7205 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Fri Aug 1 15:33:10 2014 +0200 payloads/external/SeaBIOS: retain the built binary Move SeaBIOS' build directory out of build/ Change-Id: I561b209798396d995984c244890e54f31671b5b1 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 36 ++++++++++++++++------------------ src/Kconfig | 2 +- 2 files changed, 18 insertions(+), 20 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 21f933a..487e4a8 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -10,42 +10,40 @@ unexport KCONFIG_NEGATIVES all: build -$(OUT)/seabios: - echo " Cloning SeaBIOS from Git" - git clone http://review.coreboot.org/p/seabios.git $(OUT)/seabios - -fetch: $(OUT)/seabios - cd $(OUT)/seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ +clone: + if [ ! -d seabios ]; then echo " Cloning SeaBIOS from Git"; \ + git clone http://review.coreboot.org/p/seabios.git seabios; fi + cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi -checkout: fetch +checkout: clone echo " Checking out SeaBIOS revision $(TAG-y)" - cd $(OUT)/seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) config: checkout echo " CONFIG SeaBIOS $(TAG-y)" - echo "CONFIG_COREBOOT=y" > $(OUT)/seabios/.config + echo "CONFIG_COREBOOT=y" > seabios/.config ifeq ($(CONFIG_CONSOLE_SERIAL),y) - echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config - echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> $(OUT)/seabios/.config + echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config + echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config else - echo "# CONFIG_DEBUG_SERIAL is not set" >> $(OUT)/seabios/.config + echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) - echo "# CONFIG_THREAD_OPTIONROMS is not set" >> $(OUT)/seabios/.config + echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config - $(MAKE) -C $(OUT)/seabios olddefconfig OUT=$(OUT)/seabios/out/ + #echo "# CONFIG_SMBIOS is not set" >> seabios/.config + $(MAKE) -C seabios olddefconfig OUT=out/ build: config echo " MAKE SeaBIOS $(TAG-y)" - $(MAKE) -C $(OUT)/seabios OUT=$(OUT)/seabios/out/ + $(MAKE) -C seabios OUT=out/ clean: - test -d $(OUT)/seabios && $(MAKE) -C $(OUT)/seabios clean OUT=$(OUT)/seabios/out/ || exit 0 + test -d seabios && $(MAKE) -C seabios clean OUT=out/ || exit 0 distclean: - rm -rf $(OUT)/seabios + rm -rf seabios -.PHONY: checkout config build clean distclean clone fetch +.PHONY: checkout config build clean distclean clone diff --git a/src/Kconfig b/src/Kconfig index af82353..8127315 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -671,7 +671,7 @@ config PAYLOAD_FILE config PAYLOAD_FILE depends on PAYLOAD_SEABIOS - default "$(obj)/seabios/out/bios.bin.elf" + default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" config PAYLOAD_FILE depends on PAYLOAD_FILO

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New patch to review for coreboot: 4ddc1a2 lenovo t520 & x60: Add missing header guards
by HAOUAS Elyes Aug. 1, 2014

Aug. 1, 2014

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6454 -gerrit commit 4ddc1a2161b662a1dbb7289f7a95cc1ea537761e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 15:04:27 2014 +0200 lenovo t520 & x60: Add missing header guards Change-Id: I4fe91c17aa3980ef826cafbb875ab711ad843952 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/lenovo/t520/smi.h | 2 +- src/mainboard/lenovo/x60/i915io.h | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t520/smi.h b/src/mainboard/lenovo/t520/smi.h index f7ffb41..f99fae5 100644 --- a/src/mainboard/lenovo/t520/smi.h +++ b/src/mainboard/lenovo/t520/smi.h @@ -17,4 +17,4 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ \ No newline at end of file + */ diff --git a/src/mainboard/lenovo/x60/i915io.h b/src/mainboard/lenovo/x60/i915io.h index 8f37d9b..e45b1dd 100644 --- a/src/mainboard/lenovo/x60/i915io.h +++ b/src/mainboard/lenovo/x60/i915io.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I915IO_H +#define I915IO_H + #include "i915_reg.h" #include "drm_dp_helper.h" @@ -84,3 +87,5 @@ u32 pack_aux(u32 *src, int src_bytes); void unpack_aux(u32 src, u32 *dst, int dst_bytes); int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, u32 *recv, int recv_size); + +#endif /* I915IO_H */

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New patch to review for coreboot: f1604d7 'chip.h': Add missing header guards
by HAOUAS Elyes Aug. 1, 2014

Aug. 1, 2014

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6453 -gerrit commit f1604d786efaf050a747fd73c3c35879968f4c4c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 14:59:28 2014 +0200 'chip.h': Add missing header guards Change-Id: I286788a7c22e8c49b07e4135457bbbfb39ebc32e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/supermicro/h8scm/chip.h | 4 ++++ src/northbridge/intel/e7520/chip.h | 5 +++++ src/northbridge/intel/e7525/chip.h | 5 +++++ src/northbridge/intel/fsp_sandybridge/chip.h | 5 +++++ src/northbridge/intel/haswell/chip.h | 5 +++++ src/northbridge/intel/i3100/chip.h | 5 +++++ src/northbridge/intel/nehalem/chip.h | 5 +++++ src/northbridge/intel/sandybridge/chip.h | 5 +++++ src/northbridge/via/vx900/chip.h | 5 +++++ src/southbridge/intel/esb6300/chip.h | 5 +++++ src/southbridge/intel/i3100/chip.h | 5 +++++ 11 files changed, 54 insertions(+) diff --git a/src/mainboard/supermicro/h8scm/chip.h b/src/mainboard/supermicro/h8scm/chip.h index df1ae35..5f1a40c 100644 --- a/src/mainboard/supermicro/h8scm/chip.h +++ b/src/mainboard/supermicro/h8scm/chip.h @@ -17,7 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CHIP_H +#define CHIP_H extern struct chip_operations mainboard_ops; struct mainboard_config {}; + +#endif /* CHIP_H */ diff --git a/src/northbridge/intel/e7520/chip.h b/src/northbridge/intel/e7520/chip.h index 2b9e196..b497059 100644 --- a/src/northbridge/intel/e7520/chip.h +++ b/src/northbridge/intel/e7520/chip.h @@ -1,5 +1,10 @@ +#ifndef CHIP_H +#define CHIP_H + struct northbridge_intel_e7520_config { /* Interrupt line connect */ unsigned int intrline; }; + +#endif /* CHIP_H */ diff --git a/src/northbridge/intel/e7525/chip.h b/src/northbridge/intel/e7525/chip.h index c98555c..33e6d94 100644 --- a/src/northbridge/intel/e7525/chip.h +++ b/src/northbridge/intel/e7525/chip.h @@ -1,5 +1,10 @@ +#ifndef CHIP_H +#define CHIP_H + struct northbridge_intel_e7525_config { /* Interrupt line connect */ unsigned int intrline; }; + +#endif /* CHIP_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h index 9b5f605..5916db2 100644 --- a/src/northbridge/intel/fsp_sandybridge/chip.h +++ b/src/northbridge/intel/fsp_sandybridge/chip.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CHIP_H +#define CHIP_H + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,3 +42,5 @@ struct northbridge_intel_fsp_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ }; + +#endif /* CHIP_H */ diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index d60504c..8be50d6 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CHIP_H +#define CHIP_H + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -41,3 +44,5 @@ struct northbridge_intel_haswell_config { }; extern struct chip_operations northbridge_intel_haswell_ops; + +#endif /* CHIP_H */ diff --git a/src/northbridge/intel/i3100/chip.h b/src/northbridge/intel/i3100/chip.h index ca76b02..8034f18 100644 --- a/src/northbridge/intel/i3100/chip.h +++ b/src/northbridge/intel/i3100/chip.h @@ -17,8 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CHIP_H +#define CHIP_H + struct northbridge_intel_i3100_config { /* Interrupt line connect */ u16 intrline; }; + +#endif /* CHIP_H */ diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index e33d108..dea87e7 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CHIP_H +#define CHIP_H + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -44,3 +47,5 @@ struct northbridge_intel_nehalem_config { int gpu_link_frequency_270_mhz; int gpu_lvds_num_lanes; }; + +#endif /* CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index cc32c37..9ef72e2 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CHIP_H +#define CHIP_H + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -44,3 +47,5 @@ struct northbridge_intel_sandybridge_config { int gpu_link_frequency_270_mhz; int gpu_lvds_num_lanes; }; + +#endif /* CHIP_H */ diff --git a/src/northbridge/via/vx900/chip.h b/src/northbridge/via/vx900/chip.h index 6334a8e..fb47582 100644 --- a/src/northbridge/via/vx900/chip.h +++ b/src/northbridge/via/vx900/chip.h @@ -17,6 +17,9 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ +#ifndef CHIP_H +#define CHIP_H + struct northbridge_via_vx900_config { /** * \brief PCIe Lane[3:0] Function Select @@ -50,3 +53,5 @@ struct northbridge_via_vx900_config { */ char ext_int_route_to_pirq; }; + +#endif /* CHIP_H */ diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h index 384a991..6e6b842 100644 --- a/src/southbridge/intel/esb6300/chip.h +++ b/src/southbridge/intel/esb6300/chip.h @@ -1,3 +1,6 @@ +#ifndef CHIP_H +#define CHIP_H + struct southbridge_intel_esb6300_config { #define ESB6300_GPIO_USE_MASK 0x03 @@ -26,3 +29,5 @@ struct southbridge_intel_esb6300_config unsigned int pirq_a_d; unsigned int pirq_e_h; }; + +#endif /* CHIP_H */ diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h index b0f3f32..5fb4d56 100644 --- a/src/southbridge/intel/i3100/chip.h +++ b/src/southbridge/intel/i3100/chip.h @@ -18,6 +18,9 @@ * */ +#ifndef CHIP_H +#define CHIP_H + struct southbridge_intel_i3100_config { #define I3100_GPIO_USE_MASK 0x03 @@ -47,3 +50,5 @@ struct southbridge_intel_i3100_config u32 pirq_a_d; u32 pirq_e_h; }; + +#endif /* CHIP_H */

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New patch to review for coreboot: 6a33acd mainboard/technexion: Add missing header guards
by HAOUAS Elyes Aug. 1, 2014

Aug. 1, 2014

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6452 -gerrit commit 6a33acdde33e8b3edba9b544511807bf17a7e5dd Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 14:48:32 2014 +0200 mainboard/technexion: Add missing header guards Change-Id: Ifec86806510a84047c0579fd410dcc075a3ad973 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/technexion/tim5690/speaker.h | 5 ++++- src/mainboard/technexion/tim5690/tn_post_code.h | 5 +++++ src/mainboard/technexion/tim5690/vgabios.h | 5 +++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/technexion/tim5690/speaker.h b/src/mainboard/technexion/tim5690/speaker.h index e4a5fd0..cd93153 100644 --- a/src/mainboard/technexion/tim5690/speaker.h +++ b/src/mainboard/technexion/tim5690/speaker.h @@ -17,9 +17,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef SPEAKER_H +#define SPEAKER_H void speaker_init(uint8_t time); void speaker_on_nodelay(void); void speaker_off_nodelay(void); void speaker_on_delay(void); void speaker_off_delay(void); + +#endif /* SPEAKER_H */ diff --git a/src/mainboard/technexion/tim5690/tn_post_code.h b/src/mainboard/technexion/tim5690/tn_post_code.h index 46d7382..7f43071 100644 --- a/src/mainboard/technexion/tim5690/tn_post_code.h +++ b/src/mainboard/technexion/tim5690/tn_post_code.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef TN_POST_CODE_H +#define TN_POST_CODE_H + #define LED_MESSAGE_START 0xFF #define LED_MESSAGE_FINISH 0x99 #define LED_MESSAGE_RAM 0x01 @@ -31,3 +34,5 @@ void technexion_post_code_init(void); #endif void technexion_post_code(uint8_t udata8); + +#endif /* TN_POST_CODE_H */ diff --git a/src/mainboard/technexion/tim5690/vgabios.h b/src/mainboard/technexion/tim5690/vgabios.h index a353011..500d536 100644 --- a/src/mainboard/technexion/tim5690/vgabios.h +++ b/src/mainboard/technexion/tim5690/vgabios.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef VGABIOS_H +#define VGABIOS_H + /* AMD Chipset */ #define AMD_RS690_INT15 0x4E08 @@ -35,3 +38,5 @@ typedef struct __rs690_vbios_regs__ /* Initialization VBIOS function */ extern void vgabios_init(rs690_vbios_regs *vbios_regs); + +#endif /* VGABIOS_H */

1 0

New patch to review for coreboot: 0140859 southbridge 'smbus.h': Add missing header guards
by HAOUAS Elyes Aug. 1, 2014

Aug. 1, 2014

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6451 -gerrit commit 014085955854495654e624ad091fb36c8feb0f68 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 14:40:57 2014 +0200 southbridge 'smbus.h': Add missing header guards Change-Id: I20f1a08147544fb951c48c2d9438ba3363adc5a1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/cs5535/smbus.h | 5 +++++ src/southbridge/intel/bd82x6x/smbus.h | 5 +++++ src/southbridge/intel/esb6300/smbus.h | 5 +++++ src/southbridge/intel/fsp_rangeley/smbus.h | 5 +++++ src/southbridge/intel/i3100/smbus.h | 5 +++++ src/southbridge/intel/i82371eb/smbus.h | 5 +++++ src/southbridge/intel/i82801ax/smbus.h | 5 +++++ src/southbridge/intel/i82801bx/smbus.h | 5 +++++ src/southbridge/intel/i82801ex/smbus.h | 5 +++++ src/southbridge/intel/i82801gx/smbus.h | 5 +++++ src/southbridge/intel/i82801ix/smbus.h | 5 +++++ src/southbridge/intel/ibexpeak/smbus.h | 5 +++++ src/southbridge/intel/lynxpoint/smbus.h | 5 +++++ src/southbridge/intel/sch/smbus.h | 5 +++++ src/southbridge/nvidia/ck804/smbus.h | 5 +++++ src/southbridge/nvidia/mcp55/smbus.h | 5 +++++ src/southbridge/sis/sis966/smbus.h | 5 +++++ 17 files changed, 85 insertions(+) diff --git a/src/southbridge/amd/cs5535/smbus.h b/src/southbridge/amd/cs5535/smbus.h index db35f6e..d904295 100644 --- a/src/southbridge/amd/cs5535/smbus.h +++ b/src/southbridge/amd/cs5535/smbus.h @@ -1,3 +1,6 @@ +#ifndef SMBUS_H +#define SMBUS_H + //#include <device/smbus_def.h> #define SMBUS_ERROR -1 #define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2 @@ -44,3 +47,5 @@ #define SMBUS_STATUS_MASK 0xfbff #define SMBUS_IO_BASE 0x6000 + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/bd82x6x/smbus.h b/src/southbridge/intel/bd82x6x/smbus.h index c4b05f6..996ecc7 100644 --- a/src/southbridge/intel/bd82x6x/smbus.h +++ b/src/southbridge/intel/bd82x6x/smbus.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #include "pch.h" @@ -97,3 +100,5 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/esb6300/smbus.h b/src/southbridge/intel/esb6300/smbus.h index 0a944d3..9691849 100644 --- a/src/southbridge/intel/esb6300/smbus.h +++ b/src/southbridge/intel/esb6300/smbus.h @@ -1,3 +1,6 @@ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #define SMBHSTSTAT 0x0 @@ -98,3 +101,5 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/fsp_rangeley/smbus.h b/src/southbridge/intel/fsp_rangeley/smbus.h index 34d2a8c..771859a 100644 --- a/src/southbridge/intel/fsp_rangeley/smbus.h +++ b/src/southbridge/intel/fsp_rangeley/smbus.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #include "soc.h" @@ -97,3 +100,5 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/i3100/smbus.h b/src/southbridge/intel/i3100/smbus.h index b4ed309..1241c45 100644 --- a/src/southbridge/intel/i3100/smbus.h +++ b/src/southbridge/intel/i3100/smbus.h @@ -19,6 +19,9 @@ /* This code is based on src/southbridge/intel/esb6300/esb6300_smbus.h */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #define SMBHSTSTAT 0x0 @@ -153,3 +156,5 @@ static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned a return 0; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/i82371eb/smbus.h b/src/southbridge/intel/i82371eb/smbus.h index 6c7c6f4..c9e624c 100644 --- a/src/southbridge/intel/i82371eb/smbus.h +++ b/src/southbridge/intel/i82371eb/smbus.h @@ -1,3 +1,6 @@ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #include "i82371eb.h" @@ -112,3 +115,5 @@ int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/i82801ax/smbus.h b/src/southbridge/intel/i82801ax/smbus.h index de1e318..79396b1 100644 --- a/src/southbridge/intel/i82801ax/smbus.h +++ b/src/southbridge/intel/i82801ax/smbus.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #include "i82801ax.h" @@ -99,3 +102,5 @@ int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address) } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/i82801bx/smbus.h b/src/southbridge/intel/i82801bx/smbus.h index c23e8fa..79aab0e 100644 --- a/src/southbridge/intel/i82801bx/smbus.h +++ b/src/southbridge/intel/i82801bx/smbus.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> static void smbus_delay(void) @@ -96,3 +99,5 @@ static int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address) } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h index b166797..f056bef 100644 --- a/src/southbridge/intel/i82801ex/smbus.h +++ b/src/southbridge/intel/i82801ex/smbus.h @@ -1,3 +1,6 @@ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #define SMBHSTSTAT 0x0 @@ -102,3 +105,5 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/i82801gx/smbus.h b/src/southbridge/intel/i82801gx/smbus.h index 17804d6..b0a98e8 100644 --- a/src/southbridge/intel/i82801gx/smbus.h +++ b/src/southbridge/intel/i82801gx/smbus.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #include "i82801gx.h" @@ -97,3 +100,5 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/i82801ix/smbus.h b/src/southbridge/intel/i82801ix/smbus.h index f215fb4..7b45f8b 100644 --- a/src/southbridge/intel/i82801ix/smbus.h +++ b/src/southbridge/intel/i82801ix/smbus.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #include "i82801ix.h" @@ -97,3 +100,5 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/ibexpeak/smbus.h b/src/southbridge/intel/ibexpeak/smbus.h index cf57685..52310d8 100644 --- a/src/southbridge/intel/ibexpeak/smbus.h +++ b/src/southbridge/intel/ibexpeak/smbus.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #include "pch.h" @@ -243,3 +246,5 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device, return bytes_read; } #endif + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/lynxpoint/smbus.h b/src/southbridge/intel/lynxpoint/smbus.h index c4b05f6..996ecc7 100644 --- a/src/southbridge/intel/lynxpoint/smbus.h +++ b/src/southbridge/intel/lynxpoint/smbus.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #include "pch.h" @@ -97,3 +100,5 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/intel/sch/smbus.h b/src/southbridge/intel/sch/smbus.h index 058c4b3..3666941 100644 --- a/src/southbridge/intel/sch/smbus.h +++ b/src/southbridge/intel/sch/smbus.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> static void smbus_delay(void) @@ -96,3 +99,5 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, } return byte; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index 3aac3d8..0146a56 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #define SMBHSTSTAT 0x1 @@ -227,3 +230,5 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, return 0; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index 13d7580..62bd13b 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -21,6 +21,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #define SMBHSTSTAT 0x1 @@ -174,3 +177,5 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned } return 0; } + +#endif /* SMBUS_H */ diff --git a/src/southbridge/sis/sis966/smbus.h b/src/southbridge/sis/sis966/smbus.h index 68d17e6..03de567 100644 --- a/src/southbridge/sis/sis966/smbus.h +++ b/src/southbridge/sis/sis966/smbus.h @@ -23,6 +23,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SMBUS_H +#define SMBUS_H + #include <device/smbus_def.h> #define SMBHSTSTAT 0x1 @@ -43,3 +46,5 @@ int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device); int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val); int smbus_read_byte(unsigned device, unsigned address); int smbus_write_byte(unsigned device, unsigned address, unsigned char val); + +#endif /* SMBUS_H */

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New patch to review for coreboot: 0152603 intel 'i440bx.h' & 'i440lx.h': Add missing header guards
by HAOUAS Elyes Aug. 1, 2014

Aug. 1, 2014

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6450 -gerrit commit 0152603927be43045a5c08156db2c2a37280098f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 14:22:26 2014 +0200 intel 'i440bx.h' & 'i440lx.h': Add missing header guards Change-Id: I1ebec4e76505529d514853174e2c00088a2106b4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i440bx/i440bx.h | 5 +++++ src/northbridge/intel/i440lx/i440lx.h | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 149517a..ae4b753 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -33,6 +33,9 @@ * Reserved or Intel Reserved and should not be touched. */ +#ifndef I440BX_H +#define I440BX_H + #define NBXCFG 0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */ #define DRAMC 0x57 /* DRAM Control (00S0_0000b). */ #define DRAMT 0x58 /* DRAM Timing (0x03). */ @@ -86,3 +89,5 @@ #define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */ #define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */ #define BUFFC 0xf0 /* Buffer Control Register (0x0000). */ + +#endif /* I440BX_H */ diff --git a/src/northbridge/intel/i440lx/i440lx.h b/src/northbridge/intel/i440lx/i440lx.h index 47d5b52..76abb47 100644 --- a/src/northbridge/intel/i440lx/i440lx.h +++ b/src/northbridge/intel/i440lx/i440lx.h @@ -35,6 +35,10 @@ * * Reserved or Intel Reserved and should not be touched. */ + +#ifndef I440LX_H +#define I440LX_H + #define APBASE 0x34 /* Aperture Base Address (0x00000008) */ #define PACCFG 0x50 /* 440LX PAC Configuration Register (0s00_s000_0000_0s00b) */ #define DBC 0x53 /* DRAM Row Type Register (0x83) */ @@ -70,3 +74,5 @@ #define PAM4 0x5d #define PAM5 0x5e #define PAM6 0x5f + +#endif /* I440LX_H */

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Patch set updated for coreboot: da6b295 'i915io.h': Add missing header guards
by HAOUAS Elyes Aug. 1, 2014

Aug. 1, 2014

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6444 -gerrit commit da6b2954e10f294f320662e60669e95fdf6cc7b9 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 13:35:15 2014 +0200 'i915io.h': Add missing header guards Change-Id: I2198cdb773c623afee22ecaa79b2f32bfafa0382 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/google/link/i915io.h | 5 +++++ src/mainboard/lenovo/x60/i915io.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/src/mainboard/google/link/i915io.h b/src/mainboard/google/link/i915io.h index 6533c81..ec77f70 100644 --- a/src/mainboard/google/link/i915io.h +++ b/src/mainboard/google/link/i915io.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I915IO_H +#define I915IO_H + #include "i915_reg.h" #include "drm_dp_helper.h" @@ -84,3 +87,5 @@ u32 pack_aux(u32 *src, int src_bytes); void unpack_aux(u32 src, u32 *dst, int dst_bytes); int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, u32 *recv, int recv_size); + +#endif /* I915IO_H */ diff --git a/src/mainboard/lenovo/x60/i915io.h b/src/mainboard/lenovo/x60/i915io.h index 8f37d9b..e45b1dd 100644 --- a/src/mainboard/lenovo/x60/i915io.h +++ b/src/mainboard/lenovo/x60/i915io.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I915IO_H +#define I915IO_H + #include "i915_reg.h" #include "drm_dp_helper.h" @@ -84,3 +87,5 @@ u32 pack_aux(u32 *src, int src_bytes); void unpack_aux(u32 src, u32 *dst, int dst_bytes); int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, u32 *recv, int recv_size); + +#endif /* I915IO_H */

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New patch to review for coreboot: d4094ab intel eagleheights & xe7501devkit 'ioapic.h': Add missing header guards
by HAOUAS Elyes Aug. 1, 2014

Aug. 1, 2014

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6449 -gerrit commit d4094abdbffe7276a76666dd40d8b013ab953414 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 14:12:12 2014 +0200 intel eagleheights & xe7501devkit 'ioapic.h': Add missing header guards Change-Id: I010ce8e66a01367611b822bea7d1907eab166917 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/intel/eagleheights/ioapic.h | 5 +++++ src/mainboard/intel/xe7501devkit/ioapic.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/src/mainboard/intel/eagleheights/ioapic.h b/src/mainboard/intel/eagleheights/ioapic.h index 4ac7d62..971d187 100644 --- a/src/mainboard/intel/eagleheights/ioapic.h +++ b/src/mainboard/intel/eagleheights/ioapic.h @@ -1,2 +1,7 @@ +#ifndef IOAPIC_H +#define IOAPIC_H + #define IOAPIC_I3100 2 #define INTEL_IOAPIC_NUM_INTERRUPTS 24 + +#endif /* IOAPIC_H */ diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h index 9ac2aee..5c15c6a 100644 --- a/src/mainboard/intel/xe7501devkit/ioapic.h +++ b/src/mainboard/intel/xe7501devkit/ioapic.h @@ -1,6 +1,9 @@ // IOAPIC addresses determined by coreboot enumeration. // Someday add functions to get APIC IDs and versions from the chips themselves. +#ifndef IOAPIC_H +#define IOAPIC_H + #define IOAPIC_ICH3 2 #define IOAPIC_P64H2_2_BUS_B 3 // IOAPIC 3 at 01:1c.0 MBAR = fe300000 DataAddr = fe300010 #define IOAPIC_P64H2_2_BUS_A 4 // IOAPIC 4 at 01:1e.0 MBAR = fe301000 DataAddr = fe301010 @@ -9,3 +12,5 @@ #define P64H2_IOAPIC_VERSION 0x20 #define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-3 and P64-H2 + +#endif /* IOAPIC_H */

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New patch to review for coreboot: 49e824e google/snow/exynos5250.h: Add missing header guard
by HAOUAS Elyes Aug. 1, 2014

Aug. 1, 2014

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6448 -gerrit commit 49e824e03fcf80b2a5013968fb3a0ae6d5da1a7f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 14:07:11 2014 +0200 google/snow/exynos5250.h: Add missing header guard Change-Id: I4d87db31239efd70cdec221cdff79aac0a3a76dd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/google/snow/exynos5250.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/snow/exynos5250.h b/src/mainboard/google/snow/exynos5250.h index 0f71a36..4f32c16 100644 --- a/src/mainboard/google/snow/exynos5250.h +++ b/src/mainboard/google/snow/exynos5250.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef EXYNOS5250_H +#define EXYNOS5250_H + /* I2C */ #define I2C_0_SPEED 100000 #define I2C_SLAVE 0 @@ -30,3 +33,5 @@ #define VDD_LDO3_MV 1800 // 1.8V #define VDD_LDO5_MV 1800 // 1.8V #define VDD_LDO10_MV 1800 // 1.8V + +#endif /* EXYNOS5250_H */

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