coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 485c5fc lenovo/t530: Be safe by disabling blink gpio hw with a writeout
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6436 -gerrit commit 485c5fc4828a5f1028817c41b32dbf3ef006a704 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:30:21 2014 +1000 lenovo/t530: Be safe by disabling blink gpio hw with a writeout This disables the blink hardware as it seems to be in the dump. This is safer as it does not rely on 0 as the reset value when '0x00040000' is the default according to the util/inteltool. As seen: gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index fa4356a..da92927 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -186,6 +186,7 @@ void main(unsigned long bist) outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); + outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2);

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Patch set updated for coreboot: 162141d lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header
by Edward O'Callaghan 02 Aug '14

02 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6435 -gerrit commit 162141df66dc34b57a6ac352e05a0c7e2d44477d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:29:40 2014 +1000 lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header Use defines of offsets rather than hard coded values. Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index d65031a..fa4356a 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -182,16 +182,17 @@ void main(unsigned long bist) pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); // setup_pch_gpios(&t530_gpio_map); - outl(0x3962a5ff, DEFAULT_GPIOBASE); - outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); - outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc); - outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); - outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); - outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); - outl(0xffbeff43, DEFAULT_GPIOBASE + 0x38); - outl(0x000000ff, DEFAULT_GPIOBASE + 0x40); - outl(0x00000fff, DEFAULT_GPIOBASE + 0x44); - outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); + /* ICH7 GPIOBASE */ + outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); + outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); + outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); + outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); + outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); + outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); + outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); + outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); + outl(0x00000f4f, DEFAULT_GPIOBASE + GPIO_LVL3); /* Initialize console device(s) */ console_init();

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New patch to review for coreboot: aa7340a chrome ec: Add Methods for new EC events
by Isaac Christensen 02 Aug '14

02 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6458 -gerrit commit aa7340a415b483ffa1b320358e3b478165f3b4ac Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Aug 28 09:54:04 2013 -0700 chrome ec: Add Methods for new EC events The EC recently added events for Thermal and Battery shutdown to provide some sort of notification to the OS that it is about to pull power. Original-Change-Id: Ibbdb5f11b8fa9fc80612a3cc10667c612420b1bb Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167301 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)google.com> (cherry picked from commit 03a53ed5e58caa018d49df193510d95bdf5bed7b) Change-Id: I0cdf89a60b541840029db58d49921340e7ab60eb Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167314 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 16d00848f48da83f6d6c813137a35af45bb05c4b) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/ec/google/chromeec/acpi/ec.asl | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 1cadcc8..1d698a1 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -263,6 +263,20 @@ Device (EC0) Store ("EC: KEY PRESSED", Debug) } + // Thermal Shutdown Imminent + Method (_Q10, 0, NotSerialized) + { + Store ("EC: THERMAL SHUTDOWN", Debug) + Notify (\_TZ, 0x80) + } + + // Battery Shutdown Imminent + Method (_Q11, 0, NotSerialized) + { + Store ("EC: BATTERY SHUTDOWN", Debug) + Notify (BAT0, 0x80) + } + // Throttle Start Method (_Q12, 0, NotSerialized) {

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New patch to review for coreboot: 0c06ace falco: Re-read critical temperatures in ACPI _TMP
by Isaac Christensen 02 Aug '14

02 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6457 -gerrit commit 0c06acef248d15f1047193d53ce2bc534b57cf7c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Aug 26 08:33:56 2013 -0700 falco: Re-read critical temperatures in ACPI _TMP There seem to be a significant number of shutdowns during suspend resume tests related to critical temperatures. It is possible that we are getting a bad reading from PECI and shutting down prematurely in some cases. If we get a reading that is above critical then wait for the EC to re-poll and then re-check the temperature in case it was just a bad reading. Also add some ACPI debug messages when this happens. Original-Change-Id: I0ab7bdcc50d133981c0f36fc696b06d4a1d939a7 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66937 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit a39d7b11dd7b2af37fc2658542d56b32e3966ed4) Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ib612266511d90749ec6507f8467c71523ee8fb95 Reviewed-on: https://chromium-review.googlesource.com/66939 Tested-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit e98da983dca7819490464bddf08b9c53f28d2712) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/falco/acpi/thermal.asl | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/falco/acpi/thermal.asl b/src/mainboard/google/falco/acpi/thermal.asl index 397f3eb..a622d6c 100644 --- a/src/mainboard/google/falco/acpi/thermal.asl +++ b/src/mainboard/google/falco/acpi/thermal.asl @@ -75,7 +75,7 @@ Scope (\_TZ) Return (\PPKG ()) } - Method (_TMP, 0, Serialized) + Method (TCHK, 0, Serialized) { // Get Temperature from TIN# set in NVS Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) @@ -107,5 +107,30 @@ Scope (\_TZ) Multiply (Local0, 10, Local0) Return (Local0) } + + Method (_TMP, 0, Serialized) + { + // Get temperature from EC in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TCRT), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for EC to re-poll + Sleep (1000) + + // Re-read temperature from EC + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } } }

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Patch set updated for coreboot: d6ffa96 payloads/external/SeaBIOS: retain the built binary
by Idwer Vollering 02 Aug '14

02 Aug '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6387 -gerrit commit d6ffa962da0dfa6aaef106c3a0fc591d489b7f4c Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sat Aug 2 00:03:20 2014 +0200 payloads/external/SeaBIOS: retain the built binary build/ is wiped during 'make clean': move SeaBIOS' build directory out of build/ Change-Id: I561b209798396d995984c244890e54f31671b5b1 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 33 +++++++++++++++++---------------- src/Kconfig | 2 +- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 21f933a..8f4be2b 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,3 +1,4 @@ + TAG-$(CONFIG_SEABIOS_MASTER)=origin/master TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 @@ -10,42 +11,42 @@ unexport KCONFIG_NEGATIVES all: build -$(OUT)/seabios: +clone: echo " Cloning SeaBIOS from Git" - git clone http://review.coreboot.org/p/seabios.git $(OUT)/seabios + git clone http://review.coreboot.org/p/seabios.git seabios -fetch: $(OUT)/seabios - cd $(OUT)/seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ +fetch: clone + cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi checkout: fetch echo " Checking out SeaBIOS revision $(TAG-y)" - cd $(OUT)/seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) config: checkout echo " CONFIG SeaBIOS $(TAG-y)" - echo "CONFIG_COREBOOT=y" > $(OUT)/seabios/.config + echo "CONFIG_COREBOOT=y" > seabios/.config ifeq ($(CONFIG_CONSOLE_SERIAL),y) - echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config - echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> $(OUT)/seabios/.config + echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config + echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config else - echo "# CONFIG_DEBUG_SERIAL is not set" >> $(OUT)/seabios/.config + echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) - echo "# CONFIG_THREAD_OPTIONROMS is not set" >> $(OUT)/seabios/.config + echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config - $(MAKE) -C $(OUT)/seabios olddefconfig OUT=$(OUT)/seabios/out/ + #echo "# CONFIG_SMBIOS is not set" >> seabios/.config + $(MAKE) -C seabios olddefconfig OUT=out/ build: config echo " MAKE SeaBIOS $(TAG-y)" - $(MAKE) -C $(OUT)/seabios OUT=$(OUT)/seabios/out/ + $(MAKE) -C seabios OUT=out/ clean: - test -d $(OUT)/seabios && $(MAKE) -C $(OUT)/seabios clean OUT=$(OUT)/seabios/out/ || exit 0 + test -d seabios && $(MAKE) -C seabios OUT=out/ || exit 0 distclean: - rm -rf $(OUT)/seabios + rm -rf seabios -.PHONY: checkout config build clean distclean clone fetch +.PHONY: checkout config build clean distclean fetch diff --git a/src/Kconfig b/src/Kconfig index af82353..8127315 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -671,7 +671,7 @@ config PAYLOAD_FILE config PAYLOAD_FILE depends on PAYLOAD_SEABIOS - default "$(obj)/seabios/out/bios.bin.elf" + default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" config PAYLOAD_FILE depends on PAYLOAD_FILO

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New patch to review for coreboot: b47e667 coreboot_tables: Minor refactoring to reduce redundant data structures
by Isaac Christensen 01 Aug '14

01 Aug '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6456 -gerrit commit b47e667b50d4774d1ace3e1ad0b59c75d200e9c0 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Aug 27 15:38:54 2013 -0700 coreboot_tables: Minor refactoring to reduce redundant data structures There are three Coreboot table tags that all define some kind of memory region, and each has their own homologous struct. I'm about to add a fourth so I'll just clean this up and turn it into a generic struct lb_range instead. Change-Id: Id148b2737d442e0636d2c05e74efa1fdf844a0d3 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167154 (cherry picked from commit 22d82ffa3f5500fbc1b785e343add25e61f4f194) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/arch/armv7/coreboot.c | 12 ++++++------ payloads/libpayload/arch/x86/coreboot.c | 18 ++++++++--------- payloads/libpayload/include/coreboot_tables.h | 28 +++++++-------------------- src/include/boot/coreboot_tables.h | 28 ++++++--------------------- src/lib/coreboot_table.c | 22 ++++++++++----------- 5 files changed, 39 insertions(+), 69 deletions(-) diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/armv7/coreboot.c index bc9b47e..1ee97cc 100644 --- a/payloads/libpayload/arch/armv7/coreboot.c +++ b/payloads/libpayload/arch/armv7/coreboot.c @@ -81,10 +81,10 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info) #ifdef CONFIG_CHROMEOS static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_vbnv *vbnv = (struct cb_vbnv *)ptr; + struct cb_range *vbnv = (struct cb_range *)ptr; - info->vbnv_start = vbnv->vbnv_start; - info->vbnv_size = vbnv->vbnv_size; + info->vbnv_start = vbnv->range_start; + info->vbnv_size = vbnv->range_size; } static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) @@ -101,10 +101,10 @@ static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_vdat *vdat = (struct cb_vdat *) ptr; + struct cb_range *vdat = (struct cb_range *)ptr; - info->vdat_addr = phys_to_virt(vdat->vdat_addr); - info->vdat_size = vdat->vdat_size; + info->vdat_addr = phys_to_virt(vdat->range_start); + info->vdat_size = vdat->range_size; } #endif diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index 43aa970..8995079 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -82,18 +82,18 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info) #ifdef CONFIG_CHROMEOS static void cb_parse_vboot_handoff(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_vboot_handoff *vbho = (struct cb_vboot_handoff *)ptr; + struct cb_range *vbho = (struct cb_range *)ptr; - info->vboot_handoff = (void *)(uintptr_t)vbho->vboot_handoff_addr; - info->vboot_handoff_size = vbho->vboot_handoff_size; + info->vboot_handoff = (void *)(uintptr_t)vbho->range_start; + info->vboot_handoff_size = vbho->range_size; } static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_vbnv *vbnv = (struct cb_vbnv *)ptr; + struct cb_range *vbnv = (struct cb_range *)ptr; - info->vbnv_start = vbnv->vbnv_start; - info->vbnv_size = vbnv->vbnv_size; + info->vbnv_start = vbnv->range_start; + info->vbnv_size = vbnv->range_size; } static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) @@ -110,10 +110,10 @@ static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_vdat *vdat = (struct cb_vdat *) ptr; + struct cb_range *vdat = (struct cb_range *) ptr; - info->vdat_addr = phys_to_virt(vdat->vdat_addr); - info->vdat_size = vdat->vdat_size; + info->vdat_addr = phys_to_virt(vdat->range_start); + info->vdat_size = vdat->range_size; } #endif diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 911157b..0ccc422 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -184,12 +184,14 @@ struct cb_gpios { struct cb_gpio gpios[0]; }; -#define CB_TAG_VDAT 0x0015 -struct cb_vdat { +#define CB_TAG_VDAT 0x0015 +#define CB_TAG_VBNV 0x0019 +#define CB_TAG_VBOOT_HANDOFF 0x0020 +struct cb_range { uint32_t tag; - uint32_t size; /* size of the entire entry */ - uint64_t vdat_addr; - uint32_t vdat_size; + uint32_t size; + uint64_t range_start; + uint32_t range_size; }; #define CB_TAG_TIMESTAMPS 0x0016 @@ -202,22 +204,6 @@ struct cb_cbmem_tab { uint64_t cbmem_tab; }; -#define CB_TAG_VBNV 0x0019 -struct cb_vbnv { - uint32_t tag; - uint32_t size; - uint32_t vbnv_start; - uint32_t vbnv_size; -}; - -#define CB_TAG_VBOOT_HANDOFF 0x0020 -struct cb_vboot_handoff { - uint32_t tag; - uint32_t size; - uint64_t vboot_handoff_addr; - uint32_t vboot_handoff_size; -}; - #define CB_TAG_X86_ROM_MTRR 0x0021 struct cb_x86_rom_mtrr { uint32_t tag; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index f8f8022..3c569a1 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -215,13 +215,15 @@ struct lb_gpios { struct lb_gpio gpios[0]; }; -#define LB_TAG_VDAT 0x0015 -struct lb_vdat { +#define LB_TAG_VDAT 0x0015 +#define LB_TAG_VBNV 0x0019 +#define LB_TAB_VBOOT_HANDOFF 0x0020 +struct lb_range { uint32_t tag; uint32_t size; - uint64_t vdat_addr; - uint32_t vdat_size; + uint64_t range_start; + uint32_t range_size; }; #define LB_TAG_TIMESTAMPS 0x0016 @@ -235,24 +237,6 @@ struct lb_cbmem_ref { uint64_t cbmem_addr; }; -#define LB_TAG_VBNV 0x0019 -struct lb_vbnv { - uint32_t tag; - uint32_t size; - - uint32_t vbnv_start; - uint32_t vbnv_size; -}; - -#define LB_TAB_VBOOT_HANDOFF 0x0020 -struct lb_vboot_handoff { - uint32_t tag; - uint32_t size; - - uint64_t vboot_handoff_addr; - uint32_t vboot_handoff_size; -}; - #define LB_TAG_X86_ROM_MTRR 0x0021 struct lb_x86_rom_mtrr { uint32_t tag; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 1e1ad82..f0ae6c5 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -169,25 +169,25 @@ static void lb_gpios(struct lb_header *header) static void lb_vdat(struct lb_header *header) { #if CONFIG_GENERATE_ACPI_TABLES - struct lb_vdat* vdat; + struct lb_range *vdat; - vdat = (struct lb_vdat *)lb_new_record(header); + vdat = (struct lb_range *)lb_new_record(header); vdat->tag = LB_TAG_VDAT; vdat->size = sizeof(*vdat); - acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size); + acpi_get_vdat_info(&vdat->range_start, &vdat->range_size); #endif } static void lb_vbnv(struct lb_header *header) { #if CONFIG_PC80_SYSTEM - struct lb_vbnv* vbnv; + struct lb_range *vbnv; - vbnv = (struct lb_vbnv *)lb_new_record(header); + vbnv = (struct lb_range *)lb_new_record(header); vbnv->tag = LB_TAG_VBNV; vbnv->size = sizeof(*vbnv); - vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14; - vbnv->vbnv_size = CONFIG_VBNV_SIZE; + vbnv->range_start = CONFIG_VBNV_OFFSET + 14; + vbnv->range_size = CONFIG_VBNV_SIZE; #endif } @@ -196,16 +196,16 @@ static void lb_vboot_handoff(struct lb_header *header) { void *addr; uint32_t size; - struct lb_vboot_handoff* vbho; + struct lb_range *vbho; if (vboot_get_handoff_info(&addr, &size)) return; - vbho = (struct lb_vboot_handoff *)lb_new_record(header); + vbho = (struct lb_range *)lb_new_record(header); vbho->tag = LB_TAB_VBOOT_HANDOFF; vbho->size = sizeof(*vbho); - vbho->vboot_handoff_addr = (intptr_t)addr; - vbho->vboot_handoff_size = size; + vbho->range_start = (intptr_t)addr; + vbho->range_size = size; } #else static inline void lb_vboot_handoff(struct lb_header *header) {}

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Patch merged into coreboot/master: b98ab4a armv7: add wrapper for DCCSW (data cache clean by set/way)
by gerrit＠coreboot.org 01 Aug '14

01 Aug '14

the following patch was just integrated into master: commit b98ab4a893798a5bda9d143943f6930ffaae2b68 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Aug 16 12:17:50 2013 -0700 armv7: add wrapper for DCCSW (data cache clean by set/way) This adds a wrapper for data cache clean (without invalidate) by set/way. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I09ee1563890350a6c1d04f1b96ac5d0c042e2af2 Reviewed-on: https://gerrit.chromium.org/gerrit/66118 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 05bc4f8564c547eacb9cc840a03b916b3c1c6001) armv7: clean but do not invalidate caches between stages This cleans the caches without invalidating them between stages. The dcache content should still be valid when the next stage begins, so we should see a small performance gain. (thanks to gabeblack for pointing this out) Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: Ie18d163f3a78e2786e9fbc7479c8bd896b8ac3aa Reviewed-on: https://gerrit.chromium.org/gerrit/66119 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 619bfe4cf9b93847e38d03d7076beb78fbfa1d1d) armv7: Make coreboot and libpayload cache files the same This merges the difference between the ARM version of cache.c and cache.h for libpayload and coreboot. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I246d2ec98385100304266f4bb15337a8fcf8df93 Reviewed-on: https://gerrit.chromium.org/gerrit/66120 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 0c92f694034f1e94a8aa7811251738c9dc3db2c6) ARM: Fix cache cleaning operation. There was no behavior defined for OP_DCCSW in dcache_op_set_way, so it silently did nothing. Since we started using that to clean the cache between stages and I have a change that enables caches earlier on, this was preventing booting on pit. Old-Change-Id: I3615b6569bf8de195d19d26b62f02932322b7601 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66234 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 99241468cb9dcc86fcca9266ffe72baa88a1f79f) libpayload: Fix data cache cleaning on ARM. A similar fix was made to coreboot where OP_DCCSW was silently not doing anything in dcache_op_set_way. Old-Change-Id: Ia0798aef0cd02da7d1a14b7affa05038a002ab3b Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66236 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 6f6596a182a6780a2e997ac320733722697990c5) Squashed five related commits. Change-Id: I763d42bd5dd9f58734e1e21eb7c8ce3ce2ea56ee Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6418 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6418 for details. -gerrit

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Patch set updated for coreboot: 8b44837 payloads/external/SeaBIOS: retain the built binary
by Idwer Vollering 01 Aug '14

01 Aug '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6387 -gerrit commit 8b44837e5e523d03ac2a0930a154b43334332b9d Author: Idwer Vollering <vidwer(a)gmail.com> Date: Fri Aug 1 15:33:10 2014 +0200 payloads/external/SeaBIOS: retain the built binary build/ is wiped during 'make clean': move SeaBIOS' build directory out of build/ Change-Id: I561b209798396d995984c244890e54f31671b5b1 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 38 +++++++++++++++++----------------- src/Kconfig | 2 +- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 21f933a..c88f251 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -10,42 +10,42 @@ unexport KCONFIG_NEGATIVES all: build -$(OUT)/seabios: - echo " Cloning SeaBIOS from Git" - git clone http://review.coreboot.org/p/seabios.git $(OUT)/seabios - -fetch: $(OUT)/seabios - cd $(OUT)/seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ +clone: + if [ ! -d seabios ]; then echo " Cloning SeaBIOS from Git"; \ + git clone http://review.coreboot.org/p/seabios.git seabios; fi + cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi -checkout: fetch +checkout: clone echo " Checking out SeaBIOS revision $(TAG-y)" - cd $(OUT)/seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) config: checkout echo " CONFIG SeaBIOS $(TAG-y)" - echo "CONFIG_COREBOOT=y" > $(OUT)/seabios/.config + echo "CONFIG_COREBOOT=y" > seabios/.config ifeq ($(CONFIG_CONSOLE_SERIAL),y) - echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config - echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> $(OUT)/seabios/.config + echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config + echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config else - echo "# CONFIG_DEBUG_SERIAL is not set" >> $(OUT)/seabios/.config + echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) - echo "# CONFIG_THREAD_OPTIONROMS is not set" >> $(OUT)/seabios/.config + echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config - $(MAKE) -C $(OUT)/seabios olddefconfig OUT=$(OUT)/seabios/out/ + #echo "# CONFIG_SMBIOS is not set" >> seabios/.config + $(MAKE) -C seabios olddefconfig OUT=out/ build: config echo " MAKE SeaBIOS $(TAG-y)" - $(MAKE) -C $(OUT)/seabios OUT=$(OUT)/seabios/out/ + $(MAKE) -C seabios IASL=$(IASL) OUT=out/ + mkdir $(OUT)/seabios + cp seabios/.config $(OUT)/seabios/seabios-config clean: - test -d $(OUT)/seabios && $(MAKE) -C $(OUT)/seabios clean OUT=$(OUT)/seabios/out/ || exit 0 + test -d seabios && $(MAKE) -C seabios clean OUT=out/ || exit 0 distclean: - rm -rf $(OUT)/seabios + rm -rf seabios -.PHONY: checkout config build clean distclean clone fetch +.PHONY: checkout config build clean distclean clone diff --git a/src/Kconfig b/src/Kconfig index af82353..8127315 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -671,7 +671,7 @@ config PAYLOAD_FILE config PAYLOAD_FILE depends on PAYLOAD_SEABIOS - default "$(obj)/seabios/out/bios.bin.elf" + default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" config PAYLOAD_FILE depends on PAYLOAD_FILO

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Patch merged into coreboot/master: caf1df0 i82801ix: Provide ramstage smbus functions.
by gerrit＠coreboot.org 01 Aug '14

01 Aug '14

the following patch was just integrated into master: commit caf1df0278ef743274b7811e0b4bfb58c122ce4e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Aug 1 02:49:27 2014 +0200 i82801ix: Provide ramstage smbus functions. Change-Id: Idc62e382a4002274abe6c23d76fe0874c62846c5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6433 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6433 for details. -gerrit

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Patch set updated for coreboot: b53422e mainboard/technexion: Add missing header guards
by HAOUAS Elyes 01 Aug '14

01 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6453 -gerrit commit b53422e72df579630290b01802d58e07b05f86e7 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Aug 1 14:48:32 2014 +0200 mainboard/technexion: Add missing header guards Change-Id: Ifec86806510a84047c0579fd410dcc075a3ad973 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> 'chip.h': Add missing header guards Change-Id: I286788a7c22e8c49b07e4135457bbbfb39ebc32e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> lenovo t520 & x60: Add missing header guards Change-Id: I4fe91c17aa3980ef826cafbb875ab711ad843952 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Add missing header guards Change-Id: I065297cdb20dc0f31c1eddc03f0382d5c59ec7e7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> 'chip.h': Add missing header guards Change-Id: I286788a7c22e8c49b07e4135457bbbfb39ebc32e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/lenovo/t520/smi.h | 2 +- src/mainboard/lenovo/x60/i915io.h | 5 +++++ src/mainboard/siemens/sitemp_g1p1/int15_func.h | 5 ++++- src/mainboard/supermicro/h8scm/chip.h | 4 ++++ src/mainboard/technexion/tim5690/speaker.h | 5 ++++- src/mainboard/technexion/tim5690/tn_post_code.h | 5 +++++ src/mainboard/technexion/tim5690/vgabios.h | 5 +++++ src/northbridge/amd/amdfam10/amdfam10.h | 2 +- src/northbridge/amd/amdfam10/nums.h | 3 +-- src/northbridge/amd/amdk8/amdk8.h | 1 - src/northbridge/amd/amdmct/amddefs.h | 5 +++++ src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 4 ++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 4 ++++ src/northbridge/intel/e7501/e7501.h | 5 +++++ src/northbridge/intel/e7505/e7505.h | 5 +++++ src/northbridge/intel/e7520/chip.h | 5 +++++ src/northbridge/intel/e7520/e7520.h | 5 +++++ src/northbridge/intel/e7525/chip.h | 5 +++++ src/northbridge/intel/e7525/e7525.h | 5 +++++ src/northbridge/intel/fsp_sandybridge/chip.h | 5 +++++ src/northbridge/intel/haswell/chip.h | 5 +++++ src/northbridge/intel/i3100/chip.h | 5 +++++ src/northbridge/intel/i82830/i82830.h | 5 +++++ src/northbridge/intel/i855/i855.h | 5 +++++ src/northbridge/intel/nehalem/chip.h | 5 +++++ src/northbridge/intel/sandybridge/chip.h | 5 +++++ src/northbridge/via/cn400/cn400.h | 5 +++++ src/northbridge/via/cn700/cn700.h | 5 +++++ src/northbridge/via/cx700/registers.h | 5 +++++ src/northbridge/via/vx900/chip.h | 5 +++++ src/southbridge/amd/amd8111/amd8111_smbus.h | 5 +++++ src/southbridge/intel/esb6300/chip.h | 5 +++++ src/southbridge/intel/i3100/chip.h | 5 +++++ src/southbridge/intel/i82870/82870.h | 5 +++++ src/southbridge/nvidia/ck804/early_setup_ss.h | 5 +++++ src/southbridge/nvidia/ck804/early_smbus.h | 5 +++++ src/southbridge/nvidia/mcp55/early_setup_ss.h | 5 +++++ src/southbridge/ricoh/rl5c476/rl5c476.h | 6 +++++- src/southbridge/sis/sis966/early_setup_ss.h | 5 +++++ src/southbridge/ti/pci7420/pci7420.h | 4 ++++ src/southbridge/via/common/via_early_smbus.h | 5 +++++ src/southbridge/via/vt82c686/vt82c686.h | 5 +++++ 42 files changed, 187 insertions(+), 8 deletions(-) diff --git a/src/mainboard/lenovo/t520/smi.h b/src/mainboard/lenovo/t520/smi.h index f7ffb41..f99fae5 100644 --- a/src/mainboard/lenovo/t520/smi.h +++ b/src/mainboard/lenovo/t520/smi.h @@ -17,4 +17,4 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ \ No newline at end of file + */ diff --git a/src/mainboard/lenovo/x60/i915io.h b/src/mainboard/lenovo/x60/i915io.h index 8f37d9b..e45b1dd 100644 --- a/src/mainboard/lenovo/x60/i915io.h +++ b/src/mainboard/lenovo/x60/i915io.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I915IO_H +#define I915IO_H + #include "i915_reg.h" #include "drm_dp_helper.h" @@ -84,3 +87,5 @@ u32 pack_aux(u32 *src, int src_bytes); void unpack_aux(u32 src, u32 *dst, int dst_bytes); int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, u32 *recv, int recv_size); + +#endif /* I915IO_H */ diff --git a/src/mainboard/siemens/sitemp_g1p1/int15_func.h b/src/mainboard/siemens/sitemp_g1p1/int15_func.h index 26f679e..32e4284 100644 --- a/src/mainboard/siemens/sitemp_g1p1/int15_func.h +++ b/src/mainboard/siemens/sitemp_g1p1/int15_func.h @@ -20,7 +20,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef INT15_FUNC_H +#define INT15_FUNC_H typedef struct { u8 func00_LCD_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID u8 func02_set_expansion; @@ -33,3 +34,5 @@ typedef struct { }INT15_function_extensions; extern void install_INT15_function_extensions(INT15_function_extensions *); + +#endif /* INT15_FUNC_H */ diff --git a/src/mainboard/supermicro/h8scm/chip.h b/src/mainboard/supermicro/h8scm/chip.h index df1ae35..96d5d07 100644 --- a/src/mainboard/supermicro/h8scm/chip.h +++ b/src/mainboard/supermicro/h8scm/chip.h @@ -17,7 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef H8SCM_CHIP_H +#define H8SCM_CHIP_H extern struct chip_operations mainboard_ops; struct mainboard_config {}; + +#endif /* H8SCM_CHIP_H */ diff --git a/src/mainboard/technexion/tim5690/speaker.h b/src/mainboard/technexion/tim5690/speaker.h index e4a5fd0..cd93153 100644 --- a/src/mainboard/technexion/tim5690/speaker.h +++ b/src/mainboard/technexion/tim5690/speaker.h @@ -17,9 +17,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef SPEAKER_H +#define SPEAKER_H void speaker_init(uint8_t time); void speaker_on_nodelay(void); void speaker_off_nodelay(void); void speaker_on_delay(void); void speaker_off_delay(void); + +#endif /* SPEAKER_H */ diff --git a/src/mainboard/technexion/tim5690/tn_post_code.h b/src/mainboard/technexion/tim5690/tn_post_code.h index 46d7382..7f43071 100644 --- a/src/mainboard/technexion/tim5690/tn_post_code.h +++ b/src/mainboard/technexion/tim5690/tn_post_code.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef TN_POST_CODE_H +#define TN_POST_CODE_H + #define LED_MESSAGE_START 0xFF #define LED_MESSAGE_FINISH 0x99 #define LED_MESSAGE_RAM 0x01 @@ -31,3 +34,5 @@ void technexion_post_code_init(void); #endif void technexion_post_code(uint8_t udata8); + +#endif /* TN_POST_CODE_H */ diff --git a/src/mainboard/technexion/tim5690/vgabios.h b/src/mainboard/technexion/tim5690/vgabios.h index a353011..500d536 100644 --- a/src/mainboard/technexion/tim5690/vgabios.h +++ b/src/mainboard/technexion/tim5690/vgabios.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef VGABIOS_H +#define VGABIOS_H + /* AMD Chipset */ #define AMD_RS690_INT15 0x4E08 @@ -35,3 +38,5 @@ typedef struct __rs690_vbios_regs__ /* Initialization VBIOS function */ extern void vgabios_init(rs690_vbios_regs *vbios_regs); + +#endif /* VGABIOS_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 6e71b4e..c01d182 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -18,8 +18,8 @@ */ #ifndef AMDFAM10_H - #define AMDFAM10_H + /* Definitions of various FAM10 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 diff --git a/src/northbridge/amd/amdfam10/nums.h b/src/northbridge/amd/amdfam10/nums.h index 12bac5d..c1ecf7f 100644 --- a/src/northbridge/amd/amdfam10/nums.h +++ b/src/northbridge/amd/amdfam10/nums.h @@ -18,7 +18,6 @@ */ #ifndef AMDFAM10_NUMS_H - #define AMDFAM10_NUMS_H #if CONFIG_MAX_PHYSICAL_CPUS > 8 @@ -37,4 +36,4 @@ //it could be more bigger #define HC_POSSIBLE_NUM 32 -#endif +#endif /* AMDFAM10_NUMS_H */ diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 05117f7..591244d 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -1,5 +1,4 @@ #ifndef AMDK8_H - #define AMDK8_H #if CONFIG_K8_REV_F_SUPPORT diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 9efc1db..6ac9e64 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef AMDDEFS_H +#define AMDDEFS_H + /* FIXME: this file should be moved to include/cpu/amd/amddefs.h */ /* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ @@ -148,3 +151,5 @@ #define AMD_PKGTYPE_G34 3 #define AMD_PKGTYPE_ASB2 4 #define AMD_PKGTYPE_C32 5 + +#endif /* AMDDEFS_H */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index e989ae3..72b141f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MCT_D_GCC_H +#define MCT_D_GCC_H static inline void _WRMSR(u32 addr, u32 lo, u32 hi) { @@ -376,3 +378,5 @@ static u8 oemNodePresent_D(u8 Node, u8 *ret) *ret = 0; return 0; } + +#endif /* MCT_D_GCC_H */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index abe6e7b..8024075 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef MCT_D_GCC_H +#define MCT_D_GCC_H static inline void _WRMSR(u32 addr, u32 lo, u32 hi) { __asm__ volatile ( @@ -358,3 +360,5 @@ static u8 oemNodePresent_D(u8 Node, u8 *ret) *ret = 0; return 0; } + +#endif /* MCT_D_GCC_H */ diff --git a/src/northbridge/intel/e7501/e7501.h b/src/northbridge/intel/e7501/e7501.h index 1e431b1..20d9f80 100644 --- a/src/northbridge/intel/e7501/e7501.h +++ b/src/northbridge/intel/e7501/e7501.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef E7501_H +#define E7501_H + /* * e7501.h: PCI configuration space for the Intel E7501 memory controller */ @@ -77,3 +80,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* E7501_H */ diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 08b681a..d3a8089 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef E7505_H +#define E7505_H + /* * e7505.h: PCI configuration space for the Intel E7501 memory controller */ @@ -82,3 +85,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* E7505_H */ diff --git a/src/northbridge/intel/e7520/chip.h b/src/northbridge/intel/e7520/chip.h index 2b9e196..831863b 100644 --- a/src/northbridge/intel/e7520/chip.h +++ b/src/northbridge/intel/e7520/chip.h @@ -1,5 +1,10 @@ +#ifndef E7520_CHIP_H +#define E7520_CHIP_H + struct northbridge_intel_e7520_config { /* Interrupt line connect */ unsigned int intrline; }; + +#endif /* E7520_CHIP_H */ diff --git a/src/northbridge/intel/e7520/e7520.h b/src/northbridge/intel/e7520/e7520.h index 61401e4..eb35a2c 100644 --- a/src/northbridge/intel/e7520/e7520.h +++ b/src/northbridge/intel/e7520/e7520.h @@ -1,3 +1,6 @@ +#ifndef E7520_H +#define E7520_H + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -37,3 +40,5 @@ #define DEVPRES1_D0F1 (1 << 5) #define DEVPRES1_D8F0 (1 << 1) #define MSCFG 0XF6 + +#endif /* E7520_H */ diff --git a/src/northbridge/intel/e7525/chip.h b/src/northbridge/intel/e7525/chip.h index c98555c..4b8a4df 100644 --- a/src/northbridge/intel/e7525/chip.h +++ b/src/northbridge/intel/e7525/chip.h @@ -1,5 +1,10 @@ +#ifndef E7525_CHIP_H +#define E7525_CHIP_H + struct northbridge_intel_e7525_config { /* Interrupt line connect */ unsigned int intrline; }; + +#endif /* E7525_CHIP_H */ diff --git a/src/northbridge/intel/e7525/e7525.h b/src/northbridge/intel/e7525/e7525.h index 61401e4..6402c29 100644 --- a/src/northbridge/intel/e7525/e7525.h +++ b/src/northbridge/intel/e7525/e7525.h @@ -1,3 +1,6 @@ +#ifndef E7525_H +#define E7525_H + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -37,3 +40,5 @@ #define DEVPRES1_D0F1 (1 << 5) #define DEVPRES1_D8F0 (1 << 1) #define MSCFG 0XF6 + +#endif /* E7525_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h index 9b5f605..5aa17f7 100644 --- a/src/northbridge/intel/fsp_sandybridge/chip.h +++ b/src/northbridge/intel/fsp_sandybridge/chip.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef FSP_SANDYBRIDGE_CHIP_H +#define FSP_SANDYBRIDGE_CHIP_H + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -39,3 +42,5 @@ struct northbridge_intel_fsp_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ }; + +#endif /* FSP_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index d60504c..82a7777 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef HASWELL_CHIP_H +#define HASWELL_CHIP_H + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -41,3 +44,5 @@ struct northbridge_intel_haswell_config { }; extern struct chip_operations northbridge_intel_haswell_ops; + +#endif /* HASWELL_CHIP_H */ diff --git a/src/northbridge/intel/i3100/chip.h b/src/northbridge/intel/i3100/chip.h index ca76b02..c4488f1 100644 --- a/src/northbridge/intel/i3100/chip.h +++ b/src/northbridge/intel/i3100/chip.h @@ -17,8 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I3100_CHIP_H +#define I3100_CHIP_H + struct northbridge_intel_i3100_config { /* Interrupt line connect */ u16 intrline; }; + +#endif /* I3100_CHIP_H */ diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h index bdf7e51..7474beb 100644 --- a/src/northbridge/intel/i82830/i82830.h +++ b/src/northbridge/intel/i82830/i82830.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I82830_H +#define I82830_H + #define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ #define GCC0 0x50 /* GMCH Control #0 (0xa072) */ #define GCC1 0x52 /* GMCH Control #1 (0x0000) */ @@ -49,3 +52,5 @@ #define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */ #define APSIZE 0xb4 /* Apterture Size (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */ + +#endif /* I82830_H */ diff --git a/src/northbridge/intel/i855/i855.h b/src/northbridge/intel/i855/i855.h index 8786fd7..1d438eb 100644 --- a/src/northbridge/intel/i855/i855.h +++ b/src/northbridge/intel/i855/i855.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I855_H +#define I855_H + /* Host-Hub Interface Bridge */ #define GMC 0x50 /* GMCH Misc. Control (0x0000) */ #define GGC 0x52 /* GMCH Graphics Control (0x0030) */ @@ -74,3 +77,5 @@ #define DRT_TRAS_MIN_7 (1 << 9) #define DRT_TRAS_MIN_6 (2 << 9) #define DRT_TRAS_MIN_5 (3 << 9) + +#endif /* I855_H */ diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index e33d108..e7bd480 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NEHALEM_CHIP_H +#define NEHALEM_CHIP_H + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -44,3 +47,5 @@ struct northbridge_intel_nehalem_config { int gpu_link_frequency_270_mhz; int gpu_lvds_num_lanes; }; + +#endif /* NEHALEM_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index cc32c37..81507c6 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SANDYBRIDGE_CHIP_H +#define SANDYBRIDGE_CHIP_H + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -44,3 +47,5 @@ struct northbridge_intel_sandybridge_config { int gpu_link_frequency_270_mhz; int gpu_lvds_num_lanes; }; + +#endif /* SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/via/cn400/cn400.h b/src/northbridge/via/cn400/cn400.h index 2df30a6..e593b6f 100644 --- a/src/northbridge/via/cn400/cn400.h +++ b/src/northbridge/via/cn400/cn400.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CN400_H +#define CN400_H + #ifndef __PRE_RAM__ // HACK static inline void cn400_noop(device_t dev) @@ -54,3 +57,5 @@ static inline void cn400_noop(device_t dev) #define RAM_COMMAND_MSR_LOW (const char) 0x03 #define RAM_COMMAND_CBR (const char) 0x04 #define RAM_COMMAND_MSR_HIGH (const char) 0x05 + +#endif /* CN400_H */ diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h index ff1d4b3..178a0e4 100644 --- a/src/northbridge/via/cn700/cn700.h +++ b/src/northbridge/via/cn700/cn700.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CN700_H +#define CN700_H + #if !defined (__PRE_RAM__) // HACK static inline void cn700_noop(device_t dev) @@ -54,3 +57,5 @@ static inline void cn700_noop(device_t dev) #define RAM_COMMAND_PRECHARGE 0x2 #define RAM_COMMAND_MRS 0x3 #define RAM_COMMAND_CBR 0x4 + +#endif /* CN700_H */ diff --git a/src/northbridge/via/cx700/registers.h b/src/northbridge/via/cx700/registers.h index 67c3da4..10b486b 100644 --- a/src/northbridge/via/cx700/registers.h +++ b/src/northbridge/via/cx700/registers.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef REGISTERS_H +#define REGISTERS_H + /* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */ #define SCRATCH_REG_BASE 0xd0 #define SCRATCH_RANK_0 0xd0 @@ -42,3 +45,5 @@ #define DDRII_333 0x2 #define DDRII_266 0x1 #define DDRII_200 0x0 + +#endif /* REGISTERS_H */ diff --git a/src/northbridge/via/vx900/chip.h b/src/northbridge/via/vx900/chip.h index 6334a8e..e0873ff 100644 --- a/src/northbridge/via/vx900/chip.h +++ b/src/northbridge/via/vx900/chip.h @@ -17,6 +17,9 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ +#ifndef VX900_CHIP_H +#define VX900_CHIP_H + struct northbridge_via_vx900_config { /** * \brief PCIe Lane[3:0] Function Select @@ -50,3 +53,5 @@ struct northbridge_via_vx900_config { */ char ext_int_route_to_pirq; }; + +#endif /* VX900_CHIP_H */ diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 00f8f50..03cf1ea 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -1,3 +1,6 @@ +#ifndef AMD8111_SMBUS_H +#define AMD8111_SMBUS_H + #include <device/smbus_def.h> #define SMBGSTATUS 0xe0 @@ -323,3 +326,5 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne } return 0; } + +#endif /* AMD8111_SMBUS_H */ diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h index 384a991..1fe3a2f 100644 --- a/src/southbridge/intel/esb6300/chip.h +++ b/src/southbridge/intel/esb6300/chip.h @@ -1,3 +1,6 @@ +#ifndef ESB6300_CHIP_H +#define ESB6300_CHIP_H + struct southbridge_intel_esb6300_config { #define ESB6300_GPIO_USE_MASK 0x03 @@ -26,3 +29,5 @@ struct southbridge_intel_esb6300_config unsigned int pirq_a_d; unsigned int pirq_e_h; }; + +#endif /* ESB6300_CHIP_H */ diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h index b0f3f32..8da7e9b 100644 --- a/src/southbridge/intel/i3100/chip.h +++ b/src/southbridge/intel/i3100/chip.h @@ -18,6 +18,9 @@ * */ +#ifndef I3100_CHIP_H +#define I3100_CHIP_H + struct southbridge_intel_i3100_config { #define I3100_GPIO_USE_MASK 0x03 @@ -47,3 +50,5 @@ struct southbridge_intel_i3100_config u32 pirq_a_d; u32 pirq_e_h; }; + +#endif /* I3100_CHIP_H */ diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index b576cc1..4c17c65 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -1,3 +1,6 @@ +#ifndef I82870_82870_H +#define I82870_82870_H + /* for io apic 1461 */ #define MBAR 0x10 #define ABAR 0x40 @@ -12,3 +15,5 @@ #define STRP_HPCAP 0x0002 // Hot-plug capable (Hx_SLOT zero/nonzero) #define ACNF_SYNCPH 0x0010 // PCI(-X) input clock is synchronous to hub input clock + +#endif /* I82870_82870_H */ diff --git a/src/southbridge/nvidia/ck804/early_setup_ss.h b/src/southbridge/nvidia/ck804/early_setup_ss.h index 9f89595..4945c1b 100644 --- a/src/southbridge/nvidia/ck804/early_setup_ss.h +++ b/src/southbridge/nvidia/ck804/early_setup_ss.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef EARLY_SETUP_SS_H +#define EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -218,3 +221,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* EARLY_SETUP_SS_H */ diff --git a/src/southbridge/nvidia/ck804/early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h index cf25403..c8a52ed 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.h +++ b/src/southbridge/nvidia/ck804/early_smbus.h @@ -1,5 +1,10 @@ +#ifndef EARLY_SMBUS_H +#define EARLY_SMBUS_H + int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned); int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); void enable_smbus(void); int smbus_read_byte(unsigned int, unsigned int); int smbus_write_byte(unsigned int, unsigned int, unsigned char); + +#endif /* EARLY_SMBUS_H */ diff --git a/src/southbridge/nvidia/mcp55/early_setup_ss.h b/src/southbridge/nvidia/mcp55/early_setup_ss.h index 0aadc73..8eb8b34 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_ss.h +++ b/src/southbridge/nvidia/mcp55/early_setup_ss.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef EARLY_SETUP_SS_H +#define EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -219,3 +222,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* EARLY_SETUP_SS_H */ diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 71966a1..5818ed3 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -21,8 +21,10 @@ /* rl5c476 routines and defines*/ -#include <stdint.h> +#ifndef RL5C476_H +#define RL5C476_H +#include <stdint.h> /* the 16 bit control structure for ricoh cardbus bridge */ typedef struct pc16reg { @@ -92,3 +94,5 @@ typedef struct pc16reg { u8 resv9; u8 smpga0; } __attribute__ ((packed)) pc16reg_t; + +#endif /* RL5C476_H */ diff --git a/src/southbridge/sis/sis966/early_setup_ss.h b/src/southbridge/sis/sis966/early_setup_ss.h index b6aa7d7..44c067d 100644 --- a/src/southbridge/sis/sis966/early_setup_ss.h +++ b/src/southbridge/sis/sis966/early_setup_ss.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef EARLY_SETUP_SS_H +#define EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -218,3 +221,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* EARLY_SETUP_SS_H */ diff --git a/src/southbridge/ti/pci7420/pci7420.h b/src/southbridge/ti/pci7420/pci7420.h index f71fe17..6c92ada 100644 --- a/src/southbridge/ti/pci7420/pci7420.h +++ b/src/southbridge/ti/pci7420/pci7420.h @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef PCI7420_H +#define PCI7420_H // 0844d060 (old) #define SYSCTL 0x80 // 08405061 #define RIMUX (1 << 0) @@ -47,3 +49,5 @@ #define INTB 1 #define INTC 2 #define INTD 3 + +#endif /* PCI7420_H */ diff --git a/src/southbridge/via/common/via_early_smbus.h b/src/southbridge/via/common/via_early_smbus.h index aca920b..07c2d52 100644 --- a/src/southbridge/via/common/via_early_smbus.h +++ b/src/southbridge/via/common/via_early_smbus.h @@ -35,6 +35,9 @@ * @endcode */ +#ifndef VIA_EARLY_SMBUS_H +#define VIA_EARLY_SMBUS_H + /** * \brief SMBus IO ports in relation to the base IO port */ @@ -54,3 +57,5 @@ #include <device/early_smbus.h> #include <arch/io.h> + +#endif /* VIA_EARLY_SMBUS_H */ diff --git a/src/southbridge/via/vt82c686/vt82c686.h b/src/southbridge/via/vt82c686/vt82c686.h index 7d2ac52..85cf7b9 100644 --- a/src/southbridge/via/vt82c686/vt82c686.h +++ b/src/southbridge/via/vt82c686/vt82c686.h @@ -25,6 +25,9 @@ * Link: http://www.datasheet4u.com/html/V/T/8/VT82C686B_VIA.pdf.html */ +#ifndef VT82C686_H +#define VT82C686_H + /* Super I/0 Configuration Registers. */ /* Any registers not listed here are reserved. */ #define VT82C686_SIO_DEV_ID 0xe0 /* Super-I/O Device ID */ @@ -53,3 +56,5 @@ PCI_DEVICE_ID_VIA_82C686_4 0x3057 // Function 4, Power Management PCI_DEVICE_ID_VIA_82C686_5 0x3058 // Function 5, AC'97 Codec PCI_DEVICE_ID_VIA_82C686_6 0x3068 // Function 6, MC'97 Codec */ + +#endif /* VT82C686_H */

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coreboot-gerrit August 2014