coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 273d6c1 northbridge/intel: Out of bounds write to array in gma.h
by Edward O'Callaghan 03 Aug '14

03 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6473 -gerrit commit 273d6c13c4f6feef7021a49cb9ef70bc0c0d6661 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Aug 3 18:49:46 2014 +1000 northbridge/intel: Out of bounds write to array in gma.h The signature[] array in the mailboxe struct opregion_header_t has IGD_OPREGION_SIGNATURE written to it with a sizeof(IGD_OPREGION_SIGNATURE) and not a sizeof(signature[]). This resulted in a silent off-by-one out of bounds illegal write. Change-Id: I651620a753c743dd2ed2af51c012c27c14a5ea25 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/fsp_sandybridge/gma.h | 2 +- src/northbridge/intel/haswell/gma.h | 2 +- src/northbridge/intel/nehalem/gma.h | 2 +- src/northbridge/intel/sandybridge/gma.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/fsp_sandybridge/gma.h b/src/northbridge/intel/fsp_sandybridge/gma.h index cdf5d91..5e0acf3 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.h +++ b/src/northbridge/intel/fsp_sandybridge/gma.h @@ -19,7 +19,7 @@ /* mailbox 0: header */ typedef struct { - u8 signature[16]; + u8 signature[17]; u32 size; u32 version; u8 sbios_version[32]; diff --git a/src/northbridge/intel/haswell/gma.h b/src/northbridge/intel/haswell/gma.h index 29281ba..b885d27 100644 --- a/src/northbridge/intel/haswell/gma.h +++ b/src/northbridge/intel/haswell/gma.h @@ -19,7 +19,7 @@ /* mailbox 0: header */ typedef struct { - u8 signature[16]; + u8 signature[17]; u32 size; u32 version; u8 sbios_version[32]; diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h index fdea85a..e3f6012 100644 --- a/src/northbridge/intel/nehalem/gma.h +++ b/src/northbridge/intel/nehalem/gma.h @@ -23,7 +23,7 @@ /* mailbox 0: header */ typedef struct { - u8 signature[16]; + u8 signature[17]; u32 size; u32 version; u8 sbios_version[32]; diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index bc5d986..34bd643 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -19,7 +19,7 @@ /* mailbox 0: header */ typedef struct { - u8 signature[16]; + u8 signature[17]; u32 size; u32 version; u8 sbios_version[32];

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Patch merged into coreboot/master: 96639fb arch/x86/Makefile.inc: trivial: fix indent of informative output about bootblock
by gerrit＠coreboot.org 03 Aug '14

03 Aug '14

the following patch was just integrated into master: commit 96639fb7db099dbaad4e70dd5179cd6f2f636b57 Author: Daniele Forsi <dforsi(a)gmail.com> Date: Sat Aug 2 13:45:17 2014 +0200 arch/x86/Makefile.inc: trivial: fix indent of informative output about bootblock Fixes the 4th line of this sequence: ROMCC generated/bootblock.inc GEN generated/bootblock_inc.S CC generated/bootblock.s CC generated/bootblock.o GEN generated/bootblock.ld Change-Id: Ic0704b83ec9c4191e26a94e0d69cbf4c0486ceed Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> Reviewed-on: http://review.coreboot.org/6466 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6466 for details. -gerrit

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Patch merged into coreboot/master: 9faacba cpu/x86/lapic/lapic.c: trivial: fix comment on #else
by gerrit＠coreboot.org 03 Aug '14

03 Aug '14

the following patch was just integrated into master: commit 9faacba66b9a96398feaecaa14e99fe4a62876e0 Author: Daniele Forsi <dforsi(a)gmail.com> Date: Sat Aug 2 20:55:09 2014 +0200 cpu/x86/lapic/lapic.c: trivial: fix comment on #else The preprocessor symbol has only one "L". Change-Id: I3ec302f18d3bcc81bb45a9d53140f8aedd019317 Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> Reviewed-on: http://review.coreboot.org/6469 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6469 for details. -gerrit

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New patch to review for coreboot: d129a5b northbridge/intel/sandybridge/raminit_native.c: Uninitialized var
by Edward O'Callaghan 03 Aug '14

03 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6472 -gerrit commit d129a5b15b4db5914b3e8f0fbeee686acae39949 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Aug 3 17:53:27 2014 +1000 northbridge/intel/sandybridge/raminit_native.c: Uninitialized var Initialise length before return and give a new line before the if condition as to make clear that it is not part of the for-loop construct. Change-Id: Ia5cee1fd204220adbcfedd9ac3306b8282eb8f90 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/sandybridge/raminit_native.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9b49f11..177fb41 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -1657,10 +1657,12 @@ static struct run get_longest_zero_run(int *seq, int sz) } ls = i + 1; } + if (bl == 0) { ret.middle = sz / 2; ret.start = 0; ret.end = sz; + ret.length = bl; ret.all = 1; return ret; }

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New patch to review for coreboot: 7620e90 emulation qemu-i440fx & qemu-q35: use pci_devfn_t
by HAOUAS Elyes 03 Aug '14

03 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6471 -gerrit commit 7620e90cdf1cccaf96145607287cc1d011d0b98b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 3 08:57:52 2014 +0200 emulation qemu-i440fx & qemu-q35: use pci_devfn_t Change-Id: Iaacec42d753cd15bd59f79f15445d40da664e78a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/emulation/qemu-i440fx/northbridge.c | 2 +- src/mainboard/emulation/qemu-q35/acpi_tables.c | 2 +- src/mainboard/emulation/qemu-q35/mainboard.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index a8a61c4..f776364 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -30,7 +30,7 @@ static const unsigned char qemu_i440fx_irqs[] = { 11, 10, 10, 11, }; -static void qemu_nb_init(device_t dev) +static void qemu_nb_init(pci_devfn_t dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 0f8c0c2..116f4dc 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -46,7 +46,7 @@ static void qemu_reserve_ports(struct device *dev, unsigned int idx, IORESOURCE_ASSIGNED; } -static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(pci_devfn_t dev) { assign_resources(dev->link_list); } diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 4e79b2c..7f62af1 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -200,7 +200,7 @@ unsigned long acpi_fill_slit(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + pci_devfn_t dev; u32 reg; dev = dev_find_device(0x8086, 0x29c0, 0); diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index e991b53..7a8a97c 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -33,7 +33,7 @@ static const unsigned char qemu_q35_irqs[] = { 10, 10, 11, 11, }; -static void qemu_nb_init(device_t dev) +static void qemu_nb_init(pci_devfn_t dev) { /* Map memory at 0xc0000 - 0xfffff */ int i;

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Patch set updated for coreboot: c88b608 sandy/ivybridge: Make UMA size configurable.
by Vladimir Serbinenko 03 Aug '14

03 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6470 -gerrit commit c88b608fa3d99a65988388f4125dd0f8f827435a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 3 01:59:38 2014 +0200 sandy/ivybridge: Make UMA size configurable. Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/cmos.layout | 13 ++++++++++++- src/mainboard/google/link/cmos.layout | 13 ++++++++++++- src/mainboard/google/parrot/cmos.layout | 13 ++++++++++++- src/mainboard/google/stout/cmos.layout | 13 ++++++++++++- src/mainboard/intel/emeraldlake2/cmos.layout | 14 +++++++++++++- src/mainboard/kontron/ktqm77/cmos.layout | 12 +++++++++++- src/mainboard/lenovo/t520/cmos.layout | 12 +++++++++++- src/mainboard/lenovo/t530/cmos.layout | 12 +++++++++++- src/mainboard/lenovo/x230/cmos.layout | 13 ++++++++++++- src/mainboard/samsung/lumpy/cmos.layout | 14 +++++++++++++- src/mainboard/samsung/stumpy/cmos.layout | 13 ++++++++++++- src/northbridge/intel/sandybridge/early_init.c | 9 +++++++-- 12 files changed, 138 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 8270212..da6f114 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -93,7 +93,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 3 e 11 gfx_uma_size + +#547 437 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -137,6 +141,13 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index 2dfa156..1993be7 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -91,7 +91,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 3 e 11 gfx_uma_size + +#547 437 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,13 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index 2dfa156..1993be7 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -91,7 +91,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 3 e 11 gfx_uma_size + +#547 437 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,13 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index 2dfa156..1993be7 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -91,7 +91,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 3 e 11 gfx_uma_size + +#547 437 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,13 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index 2dfa156..711ef4d 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -91,7 +91,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 3 e 11 gfx_uma_size + +#547 437 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,14 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 245b47e..621d958 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -80,7 +80,9 @@ entries # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused +401 3 e 12 gfx_uma_size + +#404 4 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -165,6 +167,14 @@ enumerations 10 4 LM75@9e 11 0 AHCI 11 1 Compatible +12 0 32M +12 1 64M +12 2 96M +12 3 128M +12 4 160M +12 5 192M +12 6 224M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 50aa5f3..825317f 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -100,8 +100,11 @@ entries # coreboot config options: cpu 424 1 e 2 hyper_threading +#425 7 r 0 unused -#425 559 r 0 unused +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -150,6 +153,13 @@ enumerations 10 1 Keyboard only 10 2 Thinklight only 10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 50aa5f3..825317f 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -100,8 +100,11 @@ entries # coreboot config options: cpu 424 1 e 2 hyper_threading +#425 7 r 0 unused -#425 559 r 0 unused +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -150,6 +153,13 @@ enumerations 10 1 Keyboard only 10 2 Thinklight only 10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 50aa5f3..7a2eb01 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -100,8 +100,11 @@ entries # coreboot config options: cpu 424 1 e 2 hyper_threading +#425 7 r 0 unused -#425 559 r 0 unused +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -150,6 +153,14 @@ enumerations 10 1 Keyboard only 10 2 Thinklight only 10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 9f0e9f3..f08b7c2 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -91,7 +91,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 3 e 11 gfx_uma_size + +#547 437 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,14 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index e7b73a2..1f8aee8 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -90,7 +90,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 3 e 11 gfx_uma_size + +#547 437 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,13 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index d688f5b..d1d35db 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <elog.h> +#include <pc80/mc146818rtc.h> #include "sandybridge.h" static void sandybridge_setup_bars(void) @@ -83,6 +84,7 @@ static void sandybridge_setup_graphics(void) u32 reg32; u16 reg16; u8 reg8; + u8 gfxsize; reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID); switch (reg16) { @@ -103,10 +105,13 @@ static void sandybridge_setup_graphics(void) printk(BIOS_DEBUG, "Initializing Graphics...\n"); - /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + gfxsize = 0; + } reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC); reg16 &= ~0x00f8; - reg16 |= 1 << 3; + reg16 |= (gfxsize + 1) << 3; /* Program GTT memory by setting GGC[9:8] = 2MB */ reg16 &= ~0x0300; reg16 |= 2 << 8;

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New patch to review for coreboot: 2d0d654 sandy/ivybridge: Make UMA size configurable.
by Vladimir Serbinenko 03 Aug '14

03 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6470 -gerrit commit 2d0d654ab2c3cf875e88eb330028b78f36733dd7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 3 01:59:38 2014 +0200 sandy/ivybridge: Make UMA size configurable. Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/cmos.layout | 13 ++++++++++++- src/mainboard/google/link/cmos.layout | 13 ++++++++++++- src/mainboard/google/parrot/cmos.layout | 13 ++++++++++++- src/mainboard/google/stout/cmos.layout | 13 ++++++++++++- src/mainboard/intel/emeraldlake2/cmos.layout | 14 +++++++++++++- src/mainboard/kontron/ktqm77/cmos.layout | 12 +++++++++++- src/mainboard/lenovo/t520/cmos.layout | 12 +++++++++++- src/mainboard/lenovo/t530/cmos.layout | 12 +++++++++++- src/mainboard/lenovo/x230/cmos.layout | 13 ++++++++++++- src/mainboard/samsung/lumpy/cmos.layout | 14 +++++++++++++- src/mainboard/samsung/stumpy/cmos.layout | 13 ++++++++++++- src/northbridge/intel/sandybridge/early_init.c | 9 +++++++-- 12 files changed, 138 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 8270212..1445fc6 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -93,7 +93,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 5 e 11 gfx_uma_size + +#549 435 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -137,6 +141,13 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index 2dfa156..cf09f36 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -91,7 +91,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 5 e 11 gfx_uma_size + +#549 435 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,13 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index 2dfa156..cf09f36 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -91,7 +91,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 5 e 11 gfx_uma_size + +#549 435 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,13 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index 2dfa156..cf09f36 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -91,7 +91,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 5 e 11 gfx_uma_size + +#549 435 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,13 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index 2dfa156..0e66b31 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -91,7 +91,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 5 e 11 gfx_uma_size + +#549 435 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,14 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 245b47e..b7807aa 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -80,7 +80,9 @@ entries # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused +401 5 e 12 gfx_uma_size + +#406 2 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -165,6 +167,14 @@ enumerations 10 4 LM75@9e 11 0 AHCI 11 1 Compatible +12 0 32M +12 1 64M +12 2 96M +12 3 128M +12 4 160M +12 5 192M +12 6 224M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 50aa5f3..db842c7 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -100,8 +100,11 @@ entries # coreboot config options: cpu 424 1 e 2 hyper_threading +#425 7 r 0 unused -#425 559 r 0 unused +# coreboot config options: northbridge +432 5 e 11 gfx_uma_size +#437 547 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -150,6 +153,13 @@ enumerations 10 1 Keyboard only 10 2 Thinklight only 10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 50aa5f3..db842c7 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -100,8 +100,11 @@ entries # coreboot config options: cpu 424 1 e 2 hyper_threading +#425 7 r 0 unused -#425 559 r 0 unused +# coreboot config options: northbridge +432 5 e 11 gfx_uma_size +#437 547 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -150,6 +153,13 @@ enumerations 10 1 Keyboard only 10 2 Thinklight only 10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 50aa5f3..98ca932 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -100,8 +100,11 @@ entries # coreboot config options: cpu 424 1 e 2 hyper_threading +#425 7 r 0 unused -#425 559 r 0 unused +# coreboot config options: northbridge +432 5 e 11 gfx_uma_size +#437 547 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -150,6 +153,14 @@ enumerations 10 1 Keyboard only 10 2 Thinklight only 10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 9f0e9f3..440eb2f 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -91,7 +91,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 5 e 11 gfx_uma_size + +#549 435 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,14 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index e7b73a2..55284a5 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -90,7 +90,11 @@ entries # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused + +# coreboot config options: northbridge +544 5 e 11 gfx_uma_size + +#549 435 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -134,6 +138,13 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index d688f5b..d1d35db 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <elog.h> +#include <pc80/mc146818rtc.h> #include "sandybridge.h" static void sandybridge_setup_bars(void) @@ -83,6 +84,7 @@ static void sandybridge_setup_graphics(void) u32 reg32; u16 reg16; u8 reg8; + u8 gfxsize; reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID); switch (reg16) { @@ -103,10 +105,13 @@ static void sandybridge_setup_graphics(void) printk(BIOS_DEBUG, "Initializing Graphics...\n"); - /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + gfxsize = 0; + } reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC); reg16 &= ~0x00f8; - reg16 |= 1 << 3; + reg16 |= (gfxsize + 1) << 3; /* Program GTT memory by setting GGC[9:8] = 2MB */ reg16 &= ~0x0300; reg16 |= 2 << 8;

1 0

Patch set updated for coreboot: 33cee6f bayleybay_fsp: Add bakersport board variant
by Martin Roth 02 Aug '14

02 Aug '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5983 -gerrit commit 33cee6f53a7d3d462a388f5d9c7737d66ef49e5f Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jun 12 12:08:26 2014 -0600 bayleybay_fsp: Add bakersport board variant The Bakersport board is a variant of the Bayley Bay mainboard that uses one ECC DIMM instead of two non-ECC dimms. This commit uses the Bayley Bay mainboard directory and modifies the required pieces to add the Bakersport board variant. It disables the second DIMM, points to an ECC version of the FSP, and sets the board name to be Bakersport instead of Bayley Bay. All of the code is still contained in the bayleybay_fsp directory. It seems like duplicating the whole directory for the one line of code that's actually different between the two platforms. Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/intel/Kconfig | 3 + src/mainboard/intel/bakersport_fsp/Kconfig | 103 ++++++++++++++++++++++ src/mainboard/intel/bakersport_fsp/board_info.txt | 4 + src/mainboard/intel/bakersport_fsp/readme.txt | 5 ++ src/mainboard/intel/bayleybay_fsp/romstage.c | 5 ++ 5 files changed, 120 insertions(+) diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 4f1ff4c..4578dfe 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -3,6 +3,8 @@ if VENDOR_INTEL choice prompt "Mainboard model" +config BOARD_INTEL_BAKERSPORT_FSP + bool "Bakersport FSP-based CRB" config BOARD_INTEL_BAYLEYBAY_FSP bool "Bayley Bay FSP-based CRB" config BOARD_INTEL_COUGAR_CANYON2 @@ -32,6 +34,7 @@ config BOARD_INTEL_WTM2 endchoice +source "src/mainboard/intel/bakersport_fsp/Kconfig" source "src/mainboard/intel/bayleybay_fsp/Kconfig" source "src/mainboard/intel/cougar_canyon2/Kconfig" source "src/mainboard/intel/d810e2cb/Kconfig" diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig new file mode 100644 index 0000000..043e98a --- /dev/null +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -0,0 +1,103 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_INTEL_BAKERSPORT_FSP + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_FSP_BAYTRAIL + select BOARD_ROMSIZE_KB_2048 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select OVERRIDE_MRC_CACHE_LOC + select POST_IO + select INCLUDE_MICROCODE_IN_BUILD if FSP_PACKAGE_DEFAULT + select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT + select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT + select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT + select TSC_MONOTONIC_TIMER + +config MAINBOARD_DIR + string + default "intel/bayleybay_fsp" + +config INCLUDE_ME + bool + default n + +config LOCK_MANAGEMENT_ENGINE + bool + default n + +config MAINBOARD_PART_NUMBER + string + default "Bakersport CRB" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 16 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x800000 + +config FSP_FILE + string + default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP + +config MRC_CACHE_LOC_OVERRIDE + hex + default 0xfff80000 + depends on ENABLE_FSP_FAST_BOOT + +config CBFS_SIZE + hex + default 0x00200000 + +config DRIVERS_PS2_KEYBOARD + bool + default n + +config CONSOLE_POST + bool + default y + +config ENABLE_FSP_FAST_BOOT + bool + depends on HAVE_FSP_BIN + default y + +config VIRTUAL_ROM_SIZE + hex + depends on ENABLE_FSP_FAST_BOOT + default 0x800000 + +config FSP_PACKAGE_DEFAULT + bool "Configure defaults for the Intel FSP package" + default n + +config VGA_BIOS + bool + default y if FSP_PACKAGE_DEFAULT + +endif # BOARD_INTEL_BAKERSPORT_FSP diff --git a/src/mainboard/intel/bakersport_fsp/board_info.txt b/src/mainboard/intel/bakersport_fsp/board_info.txt new file mode 100644 index 0000000..8527d41 --- /dev/null +++ b/src/mainboard/intel/bakersport_fsp/board_info.txt @@ -0,0 +1,4 @@ +Board name: Bakersport +Category: eval +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/intel/bakersport_fsp/readme.txt b/src/mainboard/intel/bakersport_fsp/readme.txt new file mode 100644 index 0000000..b76592c --- /dev/null +++ b/src/mainboard/intel/bakersport_fsp/readme.txt @@ -0,0 +1,5 @@ +The code for the bakersport board is in the bayleybay_fsp directory. + +This directory is just here so so that the bakersport board gets built by +abuild and so that there is a separate entry in the wiki and board-status +tree. diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index 34199bd..ef848fa 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -173,4 +173,9 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) /* Initialize the Azalia Verb Tables to mainboard specific version */ UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; + + /* Disable 2nd DIMM on Bakersport*/ +#if IS_ENABLED(BOARD_INTEL_BAKERSPORT_FSP) + UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */ +#endif }

1 0

New patch to review for coreboot: ba6f1b6 cpu/x86/lapic/lapic.c: trivial: fix comment on #else
by Daniele Forsi 02 Aug '14

02 Aug '14

Daniele Forsi (dforsi(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6469 -gerrit commit ba6f1b6d714924b23a92300e7f947bb19e6ef0f9 Author: Daniele Forsi <dforsi(a)gmail.com> Date: Sat Aug 2 20:55:09 2014 +0200 cpu/x86/lapic/lapic.c: trivial: fix comment on #else The preprocessor symbol has only one "L". Change-Id: I3ec302f18d3bcc81bb45a9d53140f8aedd019317 Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> --- src/cpu/x86/lapic/lapic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index c8f83b0..83a45b0 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -57,7 +57,7 @@ void setup_lapic(void) printk(BIOS_DEBUG, " apic_id: 0x%02lx ", lapicid()); -#else /* !NEED_LLAPIC */ +#else /* !NEED_LAPIC */ /* Only Pentium Pro and later have those MSR stuff */ msr_t msr;

1 0

Patch set updated for coreboot: 1946b22 Fix src/northbridge 'RAMINIT_H' header guards
by HAOUAS Elyes 02 Aug '14

02 Aug '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6464 -gerrit commit 1946b22daba4bb74eb41c50312c980bd19f9c3c9 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Aug 2 12:31:56 2014 +0200 Fix src/northbridge 'RAMINIT_H' header guards Change-Id: I46db08a575a2320f8fe00361ab7d72b95e86eed6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdfam10/raminit.h | 7 +++---- src/northbridge/amd/amdk8/raminit.h | 6 +++--- src/northbridge/amd/gx1/raminit.h | 6 +++--- src/northbridge/amd/gx2/raminit.h | 6 +++--- src/northbridge/amd/lx/raminit.h | 6 +++--- src/northbridge/intel/e7501/raminit.h | 6 +++--- src/northbridge/intel/e7505/raminit.h | 6 +++--- src/northbridge/intel/e7520/raminit.h | 6 +++--- src/northbridge/intel/e7525/raminit.h | 6 +++--- src/northbridge/intel/fsp_sandybridge/raminit.h | 6 +++--- src/northbridge/intel/haswell/raminit.h | 6 +++--- src/northbridge/intel/i440bx/raminit.h | 6 +++--- src/northbridge/intel/i440lx/raminit.h | 6 +++--- src/northbridge/intel/i945/raminit.h | 6 +++--- src/northbridge/intel/nehalem/raminit.h | 6 +++--- src/northbridge/intel/sandybridge/raminit.h | 6 +++--- src/northbridge/intel/sandybridge/raminit_native.h | 6 +++--- src/northbridge/intel/sch/raminit.h | 6 +++--- src/northbridge/via/cn400/raminit.h | 6 +++--- src/northbridge/via/cn700/raminit.h | 6 +++--- src/northbridge/via/cx700/raminit.h | 6 +++--- src/northbridge/via/vt8601/raminit.h | 6 +++--- src/northbridge/via/vt8623/raminit.h | 6 +++--- src/northbridge/via/vx800/raminit.h | 6 +++--- 24 files changed, 72 insertions(+), 73 deletions(-) diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 8ecdac3..55af735 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_AMD_AMDFAM10_RAMINIT_H +#define NORTHBRIDGE_AMD_AMDFAM10_RAMINIT_H #if 0 #if CONFIG_DIMM_SUPPORT==0x0110 @@ -69,5 +69,4 @@ struct mem_controller { //#endif - -#endif +#endif /* NORTHBRIDGE_AMD_AMDFAM10_RAMINIT_H */ diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 9da8417..101ce10 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_AMD_AMDK8_RAMINIT_H +#define NORTHBRIDGE_AMD_AMDK8_RAMINIT_H #define NODE_NUMS 8 @@ -21,4 +21,4 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl, void * void sdram_initialize(int controllers, const struct mem_controller *ctrl); #endif -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_AMD_AMDK8_RAMINIT_H */ diff --git a/src/northbridge/amd/gx1/raminit.h b/src/northbridge/amd/gx1/raminit.h index 6e40683..2d62b0d 100644 --- a/src/northbridge/amd/gx1/raminit.h +++ b/src/northbridge/amd/gx1/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_AMD_GX1_RAMINIT_H +#define NORTHBRIDGE_AMD_GX1_RAMINIT_H #define DIMM_SOCKETS 4 struct mem_controller { @@ -8,4 +8,4 @@ struct mem_controller { }; -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_AMD_GX1_RAMINIT_H */ diff --git a/src/northbridge/amd/gx2/raminit.h b/src/northbridge/amd/gx2/raminit.h index a49bf20..e1e7909 100644 --- a/src/northbridge/amd/gx2/raminit.h +++ b/src/northbridge/amd/gx2/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_AMD_GX2_RAMINIT_H +#define NORTHBRIDGE_AMD_GX2_RAMINIT_H #define DIMM_SOCKETS 2 @@ -9,4 +9,4 @@ struct mem_controller { void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_AMD_GX2_RAMINIT_H */ diff --git a/src/northbridge/amd/lx/raminit.h b/src/northbridge/amd/lx/raminit.h index 01d25e9..0e653c6 100644 --- a/src/northbridge/amd/lx/raminit.h +++ b/src/northbridge/amd/lx/raminit.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_AMD_LX_RAMINIT_H +#define NORTHBRIDGE_AMD_LX_RAMINIT_H #define DIMM_SOCKETS 2 @@ -36,4 +36,4 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl); /* mainboard specific */ int spd_read_byte(unsigned device, unsigned address); -#endif +#endif /* NORTHBRIDGE_AMD_LX_RAMINIT_H */ diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h index 05c3889..7960632 100644 --- a/src/northbridge/intel/e7501/raminit.h +++ b/src/northbridge/intel/e7501/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_E7501_RAMINIT_H +#define NORTHBRIDGE_INTEL_E7501_RAMINIT_H #define MAX_DIMM_SOCKETS_PER_CHANNEL 4 #define MAX_NUM_CHANNELS 2 @@ -17,4 +17,4 @@ struct mem_controller { void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_E7501_RAMINIT_H */ diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index 8eb4990..7b0fb9a 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_E7505_RAMINIT_H +#define NORTHBRIDGE_INTEL_E7505_RAMINIT_H #define MAX_DIMM_SOCKETS_PER_CHANNEL 4 #define MAX_NUM_CHANNELS 2 @@ -24,4 +24,4 @@ int e7505_mch_is_ready(void); /* Mainboard exports this. */ int spd_read_byte(unsigned device, unsigned address); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_E7505_RAMINIT_H */ diff --git a/src/northbridge/intel/e7520/raminit.h b/src/northbridge/intel/e7520/raminit.h index 9fcc380..e9c5d62 100644 --- a/src/northbridge/intel/e7520/raminit.h +++ b/src/northbridge/intel/e7520/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_E7520_RAMINIT_H +#define NORTHBRIDGE_INTEL_E7520_RAMINIT_H #define DIMM_SOCKETS 4 struct mem_controller { @@ -9,4 +9,4 @@ struct mem_controller { u16 channel1[DIMM_SOCKETS]; }; -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_E7520_RAMINIT_H */ diff --git a/src/northbridge/intel/e7525/raminit.h b/src/northbridge/intel/e7525/raminit.h index 183ace8..cf29b09 100644 --- a/src/northbridge/intel/e7525/raminit.h +++ b/src/northbridge/intel/e7525/raminit.h @@ -1,5 +1,5 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_E7525_RAMINIT_H +#define NORTHBRIDGE_INTEL_E7525_RAMINIT_H #define DIMM_SOCKETS 4 struct mem_controller { @@ -9,4 +9,4 @@ struct mem_controller { uint16_t channel1[DIMM_SOCKETS]; }; -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_E7525_RAMINIT_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.h b/src/northbridge/intel/fsp_sandybridge/raminit.h index 73e563f..a5fdb6b 100644 --- a/src/northbridge/intel/fsp_sandybridge/raminit.h +++ b/src/northbridge/intel/fsp_sandybridge/raminit.h @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_RAMINIT_H +#define NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_RAMINIT_H void report_memory_config(void); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_RAMINIT_H */ diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 706c286..135bf46 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H +#define NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H #include "pei_data.h" @@ -27,4 +27,4 @@ int fixup_haswell_errata(void); /* save_mrc_data() must be called after cbmem has been initialized. */ void save_mrc_data(struct pei_data *pei_data); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */ diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index a92c892..3344be4 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_I440BX_RAMINIT_H +#define NORTHBRIDGE_INTEL_I440BX_RAMINIT_H /* The 440BX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4 @@ -36,4 +36,4 @@ void dump_pci_device(unsigned dev); #else #define dump_spd_registers() #endif -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_I440BX_RAMINIT_H */ diff --git a/src/northbridge/intel/i440lx/raminit.h b/src/northbridge/intel/i440lx/raminit.h index 3b906e9..dda7cb0 100644 --- a/src/northbridge/intel/i440lx/raminit.h +++ b/src/northbridge/intel/i440lx/raminit.h @@ -19,10 +19,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_I440LX_RAMINIT_H +#define NORTHBRIDGE_INTEL_I440LX_RAMINIT_H /* The 440LX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4 -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_I440LX_RAMINIT_H */ diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 9eb4193..8e4cc45 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_I945_RAMINIT_H +#define NORTHBRIDGE_INTEL_I945_RAMINIT_H #define DIMM_SOCKETS 2 @@ -75,4 +75,4 @@ void udelay(u32 us); #if CONFIG_DEBUG_RAM_SETUP void sdram_dump_mchbar_registers(void); #endif -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_I945_RAMINIT_H */ diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/nehalem/raminit.h index 0485694..4e17f89 100644 --- a/src/northbridge/intel/nehalem/raminit.h +++ b/src/northbridge/intel/nehalem/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_NEHALEM_RAMINIT_H +#define NORTHBRIDGE_INTEL_NEHALEM_RAMINIT_H #include "nehalem.h" @@ -32,4 +32,4 @@ void chipset_init(const int s3resume); */ void raminit(const int s3resume, const u8 *spd_addrmap); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_NEHALEM_RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index c3b1c2a..fa83f6f 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_RAMINIT_H +#define NORTHBRIDGE_INTEL_SANDYBRIDGE_RAMINIT_H #include "pei_data.h" @@ -33,4 +33,4 @@ void sdram_initialize(struct pei_data *pei_data); void save_mrc_data(struct pei_data *pei_data); int fixup_sandybridge_errata(void); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index 7ed75ff..dd0dd16 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_RAMINIT_NATIVE_H +#define NORTHBRIDGE_INTEL_SANDYBRIDGE_RAMINIT_NATIVE_H #include <device/dram/ddr3.h> @@ -26,4 +26,4 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int s3resume); void read_spd(spd_raw_data *spd, u8 addr); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_RAMINIT_NATIVE_H */ diff --git a/src/northbridge/intel/sch/raminit.h b/src/northbridge/intel/sch/raminit.h index f139490..d6e62e5 100644 --- a/src/northbridge/intel/sch/raminit.h +++ b/src/northbridge/intel/sch/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_SCH_RAMINIT_H +#define NORTHBRIDGE_INTEL_SCH_RAMINIT_H /** * Bit Equates @@ -179,4 +179,4 @@ struct sys_info { void sdram_initialize(int boot_mode); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_SCH_RAMINIT_H */ diff --git a/src/northbridge/via/cn400/raminit.h b/src/northbridge/via/cn400/raminit.h index 89ea0d6..5a532bc 100644 --- a/src/northbridge/via/cn400/raminit.h +++ b/src/northbridge/via/cn400/raminit.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_VIA_CN400_RAMINIT_H +#define NORTHBRIDGE_VIA_CN400_RAMINIT_H #define DIMM_SOCKETS 1 /* Only one works, for now. */ @@ -28,4 +28,4 @@ struct mem_controller { u8 channel0[DIMM_SOCKETS]; }; -#endif +#endif /* NORTHBRIDGE_VIA_CN400_RAMINIT_H */ diff --git a/src/northbridge/via/cn700/raminit.h b/src/northbridge/via/cn700/raminit.h index 89ea0d6..ca1826f 100644 --- a/src/northbridge/via/cn700/raminit.h +++ b/src/northbridge/via/cn700/raminit.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_VIA_CN700_RAMINIT_H +#define NORTHBRIDGE_VIA_CN700_RAMINIT_H #define DIMM_SOCKETS 1 /* Only one works, for now. */ @@ -28,4 +28,4 @@ struct mem_controller { u8 channel0[DIMM_SOCKETS]; }; -#endif +#endif /* NORTHBRIDGE_VIA_CN700_RAMINIT_H */ diff --git a/src/northbridge/via/cx700/raminit.h b/src/northbridge/via/cx700/raminit.h index 98e21f0..1bc2c0f 100644 --- a/src/northbridge/via/cx700/raminit.h +++ b/src/northbridge/via/cx700/raminit.h @@ -17,12 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_VIA_CX700_RAMINIT_H +#define NORTHBRIDGE_VIA_CX700_RAMINIT_H #define DIMM_SOCKETS 2 struct mem_controller { u16 channel0[DIMM_SOCKETS]; }; -#endif +#endif /* NORTHBRIDGE_VIA_CX700_RAMINIT_H */ diff --git a/src/northbridge/via/vt8601/raminit.h b/src/northbridge/via/vt8601/raminit.h index b6d2339..bb47ab6 100644 --- a/src/northbridge/via/vt8601/raminit.h +++ b/src/northbridge/via/vt8601/raminit.h @@ -1,8 +1,8 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_VIA_VT8601_RAMINIT_H +#define NORTHBRIDGE_VIA_VT8601_RAMINIT_H struct mem_controller { int empty; }; -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_VIA_VT8601_RAMINIT_H */ diff --git a/src/northbridge/via/vt8623/raminit.h b/src/northbridge/via/vt8623/raminit.h index b6d2339..981efb8 100644 --- a/src/northbridge/via/vt8623/raminit.h +++ b/src/northbridge/via/vt8623/raminit.h @@ -1,8 +1,8 @@ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_VIA_VT8623_RAMINIT_H +#define NORTHBRIDGE_VIA_VT8623_RAMINIT_H struct mem_controller { int empty; }; -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_VIA_VT8623_RAMINIT_H */ diff --git a/src/northbridge/via/vx800/raminit.h b/src/northbridge/via/vx800/raminit.h index 4c4990c..94c6274 100644 --- a/src/northbridge/via/vx800/raminit.h +++ b/src/northbridge/via/vx800/raminit.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_VIA_VX800_RAMINIT_H +#define NORTHBRIDGE_VIA_VX800_RAMINIT_H #define MEMCTRL PCI_DEV(0,0,3) -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_VIA_VX800_RAMINIT_H */

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coreboot-gerrit August 2014